drm_fourcc.h 32 KB

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  1. /*
  2. * Copyright 2011 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21. * OTHER DEALINGS IN THE SOFTWARE.
  22. */
  23. #ifndef DRM_FOURCC_H
  24. #define DRM_FOURCC_H
  25. #include "drm.h"
  26. #if defined(__cplusplus)
  27. extern "C" {
  28. #endif
  29. /**
  30. * DOC: overview
  31. *
  32. * In the DRM subsystem, framebuffer pixel formats are described using the
  33. * fourcc codes defined in `include/uapi/drm/drm_fourcc.h`. In addition to the
  34. * fourcc code, a Format Modifier may optionally be provided, in order to
  35. * further describe the buffer's format - for example tiling or compression.
  36. *
  37. * Format Modifiers
  38. * ----------------
  39. *
  40. * Format modifiers are used in conjunction with a fourcc code, forming a
  41. * unique fourcc:modifier pair. This format:modifier pair must fully define the
  42. * format and data layout of the buffer, and should be the only way to describe
  43. * that particular buffer.
  44. *
  45. * Having multiple fourcc:modifier pairs which describe the same layout should
  46. * be avoided, as such aliases run the risk of different drivers exposing
  47. * different names for the same data format, forcing userspace to understand
  48. * that they are aliases.
  49. *
  50. * Format modifiers may change any property of the buffer, including the number
  51. * of planes and/or the required allocation size. Format modifiers are
  52. * vendor-namespaced, and as such the relationship between a fourcc code and a
  53. * modifier is specific to the modifer being used. For example, some modifiers
  54. * may preserve meaning - such as number of planes - from the fourcc code,
  55. * whereas others may not.
  56. *
  57. * Vendors should document their modifier usage in as much detail as
  58. * possible, to ensure maximum compatibility across devices, drivers and
  59. * applications.
  60. *
  61. * The authoritative list of format modifier codes is found in
  62. * `include/uapi/drm/drm_fourcc.h`
  63. */
  64. #define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \
  65. ((__u32)(c) << 16) | ((__u32)(d) << 24))
  66. #define DRM_FORMAT_BIG_ENDIAN (1<<31) /* format is big endian instead of little endian */
  67. /* Reserve 0 for the invalid format specifier */
  68. #define DRM_FORMAT_INVALID 0
  69. /* color index */
  70. #define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */
  71. /* 8 bpp Red */
  72. #define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */
  73. /* 16 bpp Red */
  74. #define DRM_FORMAT_R16 fourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */
  75. /* 16 bpp RG */
  76. #define DRM_FORMAT_RG88 fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */
  77. #define DRM_FORMAT_GR88 fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */
  78. /* 32 bpp RG */
  79. #define DRM_FORMAT_RG1616 fourcc_code('R', 'G', '3', '2') /* [31:0] R:G 16:16 little endian */
  80. #define DRM_FORMAT_GR1616 fourcc_code('G', 'R', '3', '2') /* [31:0] G:R 16:16 little endian */
  81. /* 8 bpp RGB */
  82. #define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */
  83. #define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */
  84. /* 16 bpp RGB */
  85. #define DRM_FORMAT_XRGB4444 fourcc_code('X', 'R', '1', '2') /* [15:0] x:R:G:B 4:4:4:4 little endian */
  86. #define DRM_FORMAT_XBGR4444 fourcc_code('X', 'B', '1', '2') /* [15:0] x:B:G:R 4:4:4:4 little endian */
  87. #define DRM_FORMAT_RGBX4444 fourcc_code('R', 'X', '1', '2') /* [15:0] R:G:B:x 4:4:4:4 little endian */
  88. #define DRM_FORMAT_BGRX4444 fourcc_code('B', 'X', '1', '2') /* [15:0] B:G:R:x 4:4:4:4 little endian */
  89. #define DRM_FORMAT_ARGB4444 fourcc_code('A', 'R', '1', '2') /* [15:0] A:R:G:B 4:4:4:4 little endian */
  90. #define DRM_FORMAT_ABGR4444 fourcc_code('A', 'B', '1', '2') /* [15:0] A:B:G:R 4:4:4:4 little endian */
  91. #define DRM_FORMAT_RGBA4444 fourcc_code('R', 'A', '1', '2') /* [15:0] R:G:B:A 4:4:4:4 little endian */
  92. #define DRM_FORMAT_BGRA4444 fourcc_code('B', 'A', '1', '2') /* [15:0] B:G:R:A 4:4:4:4 little endian */
  93. #define DRM_FORMAT_XRGB1555 fourcc_code('X', 'R', '1', '5') /* [15:0] x:R:G:B 1:5:5:5 little endian */
  94. #define DRM_FORMAT_XBGR1555 fourcc_code('X', 'B', '1', '5') /* [15:0] x:B:G:R 1:5:5:5 little endian */
  95. #define DRM_FORMAT_RGBX5551 fourcc_code('R', 'X', '1', '5') /* [15:0] R:G:B:x 5:5:5:1 little endian */
  96. #define DRM_FORMAT_BGRX5551 fourcc_code('B', 'X', '1', '5') /* [15:0] B:G:R:x 5:5:5:1 little endian */
  97. #define DRM_FORMAT_ARGB1555 fourcc_code('A', 'R', '1', '5') /* [15:0] A:R:G:B 1:5:5:5 little endian */
  98. #define DRM_FORMAT_ABGR1555 fourcc_code('A', 'B', '1', '5') /* [15:0] A:B:G:R 1:5:5:5 little endian */
  99. #define DRM_FORMAT_RGBA5551 fourcc_code('R', 'A', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian */
  100. #define DRM_FORMAT_BGRA5551 fourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little endian */
  101. #define DRM_FORMAT_RGB565 fourcc_code('R', 'G', '1', '6') /* [15:0] R:G:B 5:6:5 little endian */
  102. #define DRM_FORMAT_BGR565 fourcc_code('B', 'G', '1', '6') /* [15:0] B:G:R 5:6:5 little endian */
  103. /* 24 bpp RGB */
  104. #define DRM_FORMAT_RGB888 fourcc_code('R', 'G', '2', '4') /* [23:0] R:G:B little endian */
  105. #define DRM_FORMAT_BGR888 fourcc_code('B', 'G', '2', '4') /* [23:0] B:G:R little endian */
  106. /* 32 bpp RGB */
  107. #define DRM_FORMAT_XRGB8888 fourcc_code('X', 'R', '2', '4') /* [31:0] x:R:G:B 8:8:8:8 little endian */
  108. #define DRM_FORMAT_XBGR8888 fourcc_code('X', 'B', '2', '4') /* [31:0] x:B:G:R 8:8:8:8 little endian */
  109. #define DRM_FORMAT_RGBX8888 fourcc_code('R', 'X', '2', '4') /* [31:0] R:G:B:x 8:8:8:8 little endian */
  110. #define DRM_FORMAT_BGRX8888 fourcc_code('B', 'X', '2', '4') /* [31:0] B:G:R:x 8:8:8:8 little endian */
  111. #define DRM_FORMAT_ARGB8888 fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian */
  112. #define DRM_FORMAT_ABGR8888 fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian */
  113. #define DRM_FORMAT_RGBA8888 fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian */
  114. #define DRM_FORMAT_BGRA8888 fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian */
  115. #define DRM_FORMAT_XRGB2101010 fourcc_code('X', 'R', '3', '0') /* [31:0] x:R:G:B 2:10:10:10 little endian */
  116. #define DRM_FORMAT_XBGR2101010 fourcc_code('X', 'B', '3', '0') /* [31:0] x:B:G:R 2:10:10:10 little endian */
  117. #define DRM_FORMAT_RGBX1010102 fourcc_code('R', 'X', '3', '0') /* [31:0] R:G:B:x 10:10:10:2 little endian */
  118. #define DRM_FORMAT_BGRX1010102 fourcc_code('B', 'X', '3', '0') /* [31:0] B:G:R:x 10:10:10:2 little endian */
  119. #define DRM_FORMAT_ARGB2101010 fourcc_code('A', 'R', '3', '0') /* [31:0] A:R:G:B 2:10:10:10 little endian */
  120. #define DRM_FORMAT_ABGR2101010 fourcc_code('A', 'B', '3', '0') /* [31:0] A:B:G:R 2:10:10:10 little endian */
  121. #define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */
  122. #define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */
  123. /*
  124. * Floating point 64bpp RGB
  125. * IEEE 754-2008 binary16 half-precision float
  126. * [15:0] sign:exponent:mantissa 1:5:10
  127. */
  128. #define DRM_FORMAT_XRGB16161616F fourcc_code('X', 'R', '4', 'H') /* [63:0] x:R:G:B 16:16:16:16 little endian */
  129. #define DRM_FORMAT_XBGR16161616F fourcc_code('X', 'B', '4', 'H') /* [63:0] x:B:G:R 16:16:16:16 little endian */
  130. #define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */
  131. #define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */
  132. /* packed YCbCr */
  133. #define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */
  134. #define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */
  135. #define DRM_FORMAT_UYVY fourcc_code('U', 'Y', 'V', 'Y') /* [31:0] Y1:Cr0:Y0:Cb0 8:8:8:8 little endian */
  136. #define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
  137. #define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
  138. #define DRM_FORMAT_XYUV8888 fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */
  139. #define DRM_FORMAT_VUY888 fourcc_code('V', 'U', '2', '4') /* [23:0] Cr:Cb:Y 8:8:8 little endian */
  140. #define DRM_FORMAT_VUY101010 fourcc_code('V', 'U', '3', '0') /* Y followed by U then V, 10:10:10. Non-linear modifier only */
  141. /*
  142. * packed Y2xx indicate for each component, xx valid data occupy msb
  143. * 16-xx padding occupy lsb
  144. */
  145. #define DRM_FORMAT_Y210 fourcc_code('Y', '2', '1', '0') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 10:6:10:6:10:6:10:6 little endian per 2 Y pixels */
  146. #define DRM_FORMAT_Y212 fourcc_code('Y', '2', '1', '2') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 12:4:12:4:12:4:12:4 little endian per 2 Y pixels */
  147. #define DRM_FORMAT_Y216 fourcc_code('Y', '2', '1', '6') /* [63:0] Cr0:Y1:Cb0:Y0 16:16:16:16 little endian per 2 Y pixels */
  148. /*
  149. * packed Y4xx indicate for each component, xx valid data occupy msb
  150. * 16-xx padding occupy lsb except Y410
  151. */
  152. #define DRM_FORMAT_Y410 fourcc_code('Y', '4', '1', '0') /* [31:0] A:Cr:Y:Cb 2:10:10:10 little endian */
  153. #define DRM_FORMAT_Y412 fourcc_code('Y', '4', '1', '2') /* [63:0] A:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */
  154. #define DRM_FORMAT_Y416 fourcc_code('Y', '4', '1', '6') /* [63:0] A:Cr:Y:Cb 16:16:16:16 little endian */
  155. #define DRM_FORMAT_XVYU2101010 fourcc_code('X', 'V', '3', '0') /* [31:0] X:Cr:Y:Cb 2:10:10:10 little endian */
  156. #define DRM_FORMAT_XVYU12_16161616 fourcc_code('X', 'V', '3', '6') /* [63:0] X:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */
  157. #define DRM_FORMAT_XVYU16161616 fourcc_code('X', 'V', '4', '8') /* [63:0] X:Cr:Y:Cb 16:16:16:16 little endian */
  158. /*
  159. * packed YCbCr420 2x2 tiled formats
  160. * first 64 bits will contain Y,Cb,Cr components for a 2x2 tile
  161. */
  162. /* [63:0] A3:A2:Y3:0:Cr0:0:Y2:0:A1:A0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */
  163. #define DRM_FORMAT_Y0L0 fourcc_code('Y', '0', 'L', '0')
  164. /* [63:0] X3:X2:Y3:0:Cr0:0:Y2:0:X1:X0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */
  165. #define DRM_FORMAT_X0L0 fourcc_code('X', '0', 'L', '0')
  166. /* [63:0] A3:A2:Y3:Cr0:Y2:A1:A0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */
  167. #define DRM_FORMAT_Y0L2 fourcc_code('Y', '0', 'L', '2')
  168. /* [63:0] X3:X2:Y3:Cr0:Y2:X1:X0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */
  169. #define DRM_FORMAT_X0L2 fourcc_code('X', '0', 'L', '2')
  170. /*
  171. * 1-plane YUV 4:2:0
  172. * In these formats, the component ordering is specified (Y, followed by U
  173. * then V), but the exact Linear layout is undefined.
  174. * These formats can only be used with a non-Linear modifier.
  175. */
  176. #define DRM_FORMAT_YUV420_8BIT fourcc_code('Y', 'U', '0', '8')
  177. #define DRM_FORMAT_YUV420_10BIT fourcc_code('Y', 'U', '1', '0')
  178. /*
  179. * 2 plane RGB + A
  180. * index 0 = RGB plane, same format as the corresponding non _A8 format has
  181. * index 1 = A plane, [7:0] A
  182. */
  183. #define DRM_FORMAT_XRGB8888_A8 fourcc_code('X', 'R', 'A', '8')
  184. #define DRM_FORMAT_XBGR8888_A8 fourcc_code('X', 'B', 'A', '8')
  185. #define DRM_FORMAT_RGBX8888_A8 fourcc_code('R', 'X', 'A', '8')
  186. #define DRM_FORMAT_BGRX8888_A8 fourcc_code('B', 'X', 'A', '8')
  187. #define DRM_FORMAT_RGB888_A8 fourcc_code('R', '8', 'A', '8')
  188. #define DRM_FORMAT_BGR888_A8 fourcc_code('B', '8', 'A', '8')
  189. #define DRM_FORMAT_RGB565_A8 fourcc_code('R', '5', 'A', '8')
  190. #define DRM_FORMAT_BGR565_A8 fourcc_code('B', '5', 'A', '8')
  191. /*
  192. * 2 plane YCbCr
  193. * index 0 = Y plane, [7:0] Y
  194. * index 1 = Cr:Cb plane, [15:0] Cr:Cb little endian
  195. * or
  196. * index 1 = Cb:Cr plane, [15:0] Cb:Cr little endian
  197. */
  198. #define DRM_FORMAT_NV12 fourcc_code('N', 'V', '1', '2') /* 2x2 subsampled Cr:Cb plane */
  199. #define DRM_FORMAT_NV21 fourcc_code('N', 'V', '2', '1') /* 2x2 subsampled Cb:Cr plane */
  200. #define DRM_FORMAT_NV16 fourcc_code('N', 'V', '1', '6') /* 2x1 subsampled Cr:Cb plane */
  201. #define DRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */
  202. #define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */
  203. #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
  204. /*
  205. * 2 plane YCbCr MSB aligned
  206. * index 0 = Y plane, [15:0] Y:x [10:6] little endian
  207. * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
  208. */
  209. #define DRM_FORMAT_P210 fourcc_code('P', '2', '1', '0') /* 2x1 subsampled Cr:Cb plane, 10 bit per channel */
  210. /*
  211. * 2 plane YCbCr MSB aligned
  212. * index 0 = Y plane, [15:0] Y:x [10:6] little endian
  213. * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
  214. */
  215. #define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel */
  216. /*
  217. * 2 plane YCbCr MSB aligned
  218. * index 0 = Y plane, [15:0] Y:x [12:4] little endian
  219. * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [12:4:12:4] little endian
  220. */
  221. #define DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cr:Cb plane 12 bits per channel */
  222. /*
  223. * 2 plane YCbCr MSB aligned
  224. * index 0 = Y plane, [15:0] Y little endian
  225. * index 1 = Cr:Cb plane, [31:0] Cr:Cb [16:16] little endian
  226. */
  227. #define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */
  228. /*
  229. * 3 plane YCbCr
  230. * index 0: Y plane, [7:0] Y
  231. * index 1: Cb plane, [7:0] Cb
  232. * index 2: Cr plane, [7:0] Cr
  233. * or
  234. * index 1: Cr plane, [7:0] Cr
  235. * index 2: Cb plane, [7:0] Cb
  236. */
  237. #define DRM_FORMAT_YUV410 fourcc_code('Y', 'U', 'V', '9') /* 4x4 subsampled Cb (1) and Cr (2) planes */
  238. #define DRM_FORMAT_YVU410 fourcc_code('Y', 'V', 'U', '9') /* 4x4 subsampled Cr (1) and Cb (2) planes */
  239. #define DRM_FORMAT_YUV411 fourcc_code('Y', 'U', '1', '1') /* 4x1 subsampled Cb (1) and Cr (2) planes */
  240. #define DRM_FORMAT_YVU411 fourcc_code('Y', 'V', '1', '1') /* 4x1 subsampled Cr (1) and Cb (2) planes */
  241. #define DRM_FORMAT_YUV420 fourcc_code('Y', 'U', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes */
  242. #define DRM_FORMAT_YVU420 fourcc_code('Y', 'V', '1', '2') /* 2x2 subsampled Cr (1) and Cb (2) planes */
  243. #define DRM_FORMAT_YUV422 fourcc_code('Y', 'U', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes */
  244. #define DRM_FORMAT_YVU422 fourcc_code('Y', 'V', '1', '6') /* 2x1 subsampled Cr (1) and Cb (2) planes */
  245. #define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */
  246. #define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */
  247. /*
  248. * Format Modifiers:
  249. *
  250. * Format modifiers describe, typically, a re-ordering or modification
  251. * of the data in a plane of an FB. This can be used to express tiled/
  252. * swizzled formats, or compression, or a combination of the two.
  253. *
  254. * The upper 8 bits of the format modifier are a vendor-id as assigned
  255. * below. The lower 56 bits are assigned as vendor sees fit.
  256. */
  257. /* Vendor Ids: */
  258. #define DRM_FORMAT_MOD_NONE 0
  259. #define DRM_FORMAT_MOD_VENDOR_NONE 0
  260. #define DRM_FORMAT_MOD_VENDOR_INTEL 0x01
  261. #define DRM_FORMAT_MOD_VENDOR_AMD 0x02
  262. #define DRM_FORMAT_MOD_VENDOR_NVIDIA 0x03
  263. #define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04
  264. #define DRM_FORMAT_MOD_VENDOR_QCOM 0x05
  265. #define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06
  266. #define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07
  267. #define DRM_FORMAT_MOD_VENDOR_ARM 0x08
  268. #define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09
  269. /* add more to the end as needed */
  270. #define DRM_FORMAT_RESERVED ((1ULL << 56) - 1)
  271. #define fourcc_mod_code(vendor, val) \
  272. ((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | ((val) & 0x00ffffffffffffffULL))
  273. /*
  274. * Format Modifier tokens:
  275. *
  276. * When adding a new token please document the layout with a code comment,
  277. * similar to the fourcc codes above. drm_fourcc.h is considered the
  278. * authoritative source for all of these.
  279. */
  280. /*
  281. * Invalid Modifier
  282. *
  283. * This modifier can be used as a sentinel to terminate the format modifiers
  284. * list, or to initialize a variable with an invalid modifier. It might also be
  285. * used to report an error back to userspace for certain APIs.
  286. */
  287. #define DRM_FORMAT_MOD_INVALID fourcc_mod_code(NONE, DRM_FORMAT_RESERVED)
  288. /*
  289. * Linear Layout
  290. *
  291. * Just plain linear layout. Note that this is different from no specifying any
  292. * modifier (e.g. not setting DRM_MODE_FB_MODIFIERS in the DRM_ADDFB2 ioctl),
  293. * which tells the driver to also take driver-internal information into account
  294. * and so might actually result in a tiled framebuffer.
  295. */
  296. #define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0)
  297. /* Intel framebuffer modifiers */
  298. /*
  299. * Intel X-tiling layout
  300. *
  301. * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
  302. * in row-major layout. Within the tile bytes are laid out row-major, with
  303. * a platform-dependent stride. On top of that the memory can apply
  304. * platform-depending swizzling of some higher address bits into bit6.
  305. *
  306. * This format is highly platforms specific and not useful for cross-driver
  307. * sharing. It exists since on a given platform it does uniquely identify the
  308. * layout in a simple way for i915-specific userspace.
  309. */
  310. #define I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1)
  311. /*
  312. * Intel Y-tiling layout
  313. *
  314. * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
  315. * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes)
  316. * chunks column-major, with a platform-dependent height. On top of that the
  317. * memory can apply platform-depending swizzling of some higher address bits
  318. * into bit6.
  319. *
  320. * This format is highly platforms specific and not useful for cross-driver
  321. * sharing. It exists since on a given platform it does uniquely identify the
  322. * layout in a simple way for i915-specific userspace.
  323. */
  324. #define I915_FORMAT_MOD_Y_TILED fourcc_mod_code(INTEL, 2)
  325. /*
  326. * Intel Yf-tiling layout
  327. *
  328. * This is a tiled layout using 4Kb tiles in row-major layout.
  329. * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which
  330. * are arranged in four groups (two wide, two high) with column-major layout.
  331. * Each group therefore consists out of four 256 byte units, which are also laid
  332. * out as 2x2 column-major.
  333. * 256 byte units are made out of four 64 byte blocks of pixels, producing
  334. * either a square block or a 2:1 unit.
  335. * 64 byte blocks of pixels contain four pixel rows of 16 bytes, where the width
  336. * in pixel depends on the pixel depth.
  337. */
  338. #define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3)
  339. /*
  340. * Intel color control surface (CCS) for render compression
  341. *
  342. * The framebuffer format must be one of the 8:8:8:8 RGB formats.
  343. * The main surface will be plane index 0 and must be Y/Yf-tiled,
  344. * the CCS will be plane index 1.
  345. *
  346. * Each CCS tile matches a 1024x512 pixel area of the main surface.
  347. * To match certain aspects of the 3D hardware the CCS is
  348. * considered to be made up of normal 128Bx32 Y tiles, Thus
  349. * the CCS pitch must be specified in multiples of 128 bytes.
  350. *
  351. * In reality the CCS tile appears to be a 64Bx64 Y tile, composed
  352. * of QWORD (8 bytes) chunks instead of OWORD (16 bytes) chunks.
  353. * But that fact is not relevant unless the memory is accessed
  354. * directly.
  355. */
  356. #define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4)
  357. #define I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5)
  358. /*
  359. * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
  360. *
  361. * Macroblocks are laid in a Z-shape, and each pixel data is following the
  362. * standard NV12 style.
  363. * As for NV12, an image is the result of two frame buffers: one for Y,
  364. * one for the interleaved Cb/Cr components (1/2 the height of the Y buffer).
  365. * Alignment requirements are (for each buffer):
  366. * - multiple of 128 pixels for the width
  367. * - multiple of 32 pixels for the height
  368. *
  369. * For more information: see https://linuxtv.org/downloads/v4l-dvb-apis/re32.html
  370. */
  371. #define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1)
  372. /*
  373. * Tiled, 16 (pixels) x 16 (lines) - sized macroblocks
  374. *
  375. * This is a simple tiled layout using tiles of 16x16 pixels in a row-major
  376. * layout. For YCbCr formats Cb/Cr components are taken in such a way that
  377. * they correspond to their 16x16 luma block.
  378. */
  379. #define DRM_FORMAT_MOD_SAMSUNG_16_16_TILE fourcc_mod_code(SAMSUNG, 2)
  380. /*
  381. * Qualcomm Compressed Format
  382. *
  383. * Refers to a compressed variant of the base format that is compressed.
  384. * Implementation may be platform and base-format specific.
  385. *
  386. * Each macrotile consists of m x n (mostly 4 x 4) tiles.
  387. * Pixel data pitch/stride is aligned with macrotile width.
  388. * Pixel data height is aligned with macrotile height.
  389. * Entire pixel data buffer is aligned with 4k(bytes).
  390. */
  391. #define DRM_FORMAT_MOD_QCOM_COMPRESSED fourcc_mod_code(QCOM, 1)
  392. /* Vivante framebuffer modifiers */
  393. /*
  394. * Vivante 4x4 tiling layout
  395. *
  396. * This is a simple tiled layout using tiles of 4x4 pixels in a row-major
  397. * layout.
  398. */
  399. #define DRM_FORMAT_MOD_VIVANTE_TILED fourcc_mod_code(VIVANTE, 1)
  400. /*
  401. * Vivante 64x64 super-tiling layout
  402. *
  403. * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile
  404. * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row-
  405. * major layout.
  406. *
  407. * For more information: see
  408. * https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling
  409. */
  410. #define DRM_FORMAT_MOD_VIVANTE_SUPER_TILED fourcc_mod_code(VIVANTE, 2)
  411. /*
  412. * Vivante 4x4 tiling layout for dual-pipe
  413. *
  414. * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a
  415. * different base address. Offsets from the base addresses are therefore halved
  416. * compared to the non-split tiled layout.
  417. */
  418. #define DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED fourcc_mod_code(VIVANTE, 3)
  419. /*
  420. * Vivante 64x64 super-tiling layout for dual-pipe
  421. *
  422. * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile
  423. * starts at a different base address. Offsets from the base addresses are
  424. * therefore halved compared to the non-split super-tiled layout.
  425. */
  426. #define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4)
  427. /* NVIDIA frame buffer modifiers */
  428. /*
  429. * Tegra Tiled Layout, used by Tegra 2, 3 and 4.
  430. *
  431. * Pixels are arranged in simple tiles of 16 x 16 bytes.
  432. */
  433. #define DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1)
  434. /*
  435. * 16Bx2 Block Linear layout, used by desktop GPUs, and Tegra K1 and later
  436. *
  437. * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked
  438. * vertically by a power of 2 (1 to 32 GOBs) to form a block.
  439. *
  440. * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape.
  441. *
  442. * Parameter 'v' is the log2 encoding of the number of GOBs stacked vertically.
  443. * Valid values are:
  444. *
  445. * 0 == ONE_GOB
  446. * 1 == TWO_GOBS
  447. * 2 == FOUR_GOBS
  448. * 3 == EIGHT_GOBS
  449. * 4 == SIXTEEN_GOBS
  450. * 5 == THIRTYTWO_GOBS
  451. *
  452. * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format
  453. * in full detail.
  454. */
  455. #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(v) \
  456. fourcc_mod_code(NVIDIA, 0x10 | ((v) & 0xf))
  457. #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB \
  458. fourcc_mod_code(NVIDIA, 0x10)
  459. #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB \
  460. fourcc_mod_code(NVIDIA, 0x11)
  461. #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB \
  462. fourcc_mod_code(NVIDIA, 0x12)
  463. #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB \
  464. fourcc_mod_code(NVIDIA, 0x13)
  465. #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB \
  466. fourcc_mod_code(NVIDIA, 0x14)
  467. #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB \
  468. fourcc_mod_code(NVIDIA, 0x15)
  469. /*
  470. * Some Broadcom modifiers take parameters, for example the number of
  471. * vertical lines in the image. Reserve the lower 32 bits for modifier
  472. * type, and the next 24 bits for parameters. Top 8 bits are the
  473. * vendor code.
  474. */
  475. #define __fourcc_mod_broadcom_param_shift 8
  476. #define __fourcc_mod_broadcom_param_bits 48
  477. #define fourcc_mod_broadcom_code(val, params) \
  478. fourcc_mod_code(BROADCOM, ((((__u64)params) << __fourcc_mod_broadcom_param_shift) | val))
  479. #define fourcc_mod_broadcom_param(m) \
  480. ((int)(((m) >> __fourcc_mod_broadcom_param_shift) & \
  481. ((1ULL << __fourcc_mod_broadcom_param_bits) - 1)))
  482. #define fourcc_mod_broadcom_mod(m) \
  483. ((m) & ~(((1ULL << __fourcc_mod_broadcom_param_bits) - 1) << \
  484. __fourcc_mod_broadcom_param_shift))
  485. /*
  486. * Broadcom VC4 "T" format
  487. *
  488. * This is the primary layout that the V3D GPU can texture from (it
  489. * can't do linear). The T format has:
  490. *
  491. * - 64b utiles of pixels in a raster-order grid according to cpp. It's 4x4
  492. * pixels at 32 bit depth.
  493. *
  494. * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually
  495. * 16x16 pixels).
  496. *
  497. * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels). On
  498. * even 4k tile rows, they're arranged as (BL, TL, TR, BR), and on odd rows
  499. * they're (TR, BR, BL, TL), where bottom left is start of memory.
  500. *
  501. * - an image made of 4k tiles in rows either left-to-right (even rows of 4k
  502. * tiles) or right-to-left (odd rows of 4k tiles).
  503. */
  504. #define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1)
  505. /*
  506. * Broadcom SAND format
  507. *
  508. * This is the native format that the H.264 codec block uses. For VC4
  509. * HVS, it is only valid for H.264 (NV12/21) and RGBA modes.
  510. *
  511. * The image can be considered to be split into columns, and the
  512. * columns are placed consecutively into memory. The width of those
  513. * columns can be either 32, 64, 128, or 256 pixels, but in practice
  514. * only 128 pixel columns are used.
  515. *
  516. * The pitch between the start of each column is set to optimally
  517. * switch between SDRAM banks. This is passed as the number of lines
  518. * of column width in the modifier (we can't use the stride value due
  519. * to various core checks that look at it , so you should set the
  520. * stride to width*cpp).
  521. *
  522. * Note that the column height for this format modifier is the same
  523. * for all of the planes, assuming that each column contains both Y
  524. * and UV. Some SAND-using hardware stores UV in a separate tiled
  525. * image from Y to reduce the column height, which is not supported
  526. * with these modifiers.
  527. */
  528. #define DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(v) \
  529. fourcc_mod_broadcom_code(2, v)
  530. #define DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(v) \
  531. fourcc_mod_broadcom_code(3, v)
  532. #define DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(v) \
  533. fourcc_mod_broadcom_code(4, v)
  534. #define DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(v) \
  535. fourcc_mod_broadcom_code(5, v)
  536. #define DRM_FORMAT_MOD_BROADCOM_SAND32 \
  537. DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(0)
  538. #define DRM_FORMAT_MOD_BROADCOM_SAND64 \
  539. DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(0)
  540. #define DRM_FORMAT_MOD_BROADCOM_SAND128 \
  541. DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(0)
  542. #define DRM_FORMAT_MOD_BROADCOM_SAND256 \
  543. DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(0)
  544. /* Broadcom UIF format
  545. *
  546. * This is the common format for the current Broadcom multimedia
  547. * blocks, including V3D 3.x and newer, newer video codecs, and
  548. * displays.
  549. *
  550. * The image consists of utiles (64b blocks), UIF blocks (2x2 utiles),
  551. * and macroblocks (4x4 UIF blocks). Those 4x4 UIF block groups are
  552. * stored in columns, with padding between the columns to ensure that
  553. * moving from one column to the next doesn't hit the same SDRAM page
  554. * bank.
  555. *
  556. * To calculate the padding, it is assumed that each hardware block
  557. * and the software driving it knows the platform's SDRAM page size,
  558. * number of banks, and XOR address, and that it's identical between
  559. * all blocks using the format. This tiling modifier will use XOR as
  560. * necessary to reduce the padding. If a hardware block can't do XOR,
  561. * the assumption is that a no-XOR tiling modifier will be created.
  562. */
  563. #define DRM_FORMAT_MOD_BROADCOM_UIF fourcc_mod_code(BROADCOM, 6)
  564. /*
  565. * Arm Framebuffer Compression (AFBC) modifiers
  566. *
  567. * AFBC is a proprietary lossless image compression protocol and format.
  568. * It provides fine-grained random access and minimizes the amount of data
  569. * transferred between IP blocks.
  570. *
  571. * AFBC has several features which may be supported and/or used, which are
  572. * represented using bits in the modifier. Not all combinations are valid,
  573. * and different devices or use-cases may support different combinations.
  574. *
  575. * Further information on the use of AFBC modifiers can be found in
  576. * Documentation/gpu/afbc.rst
  577. */
  578. #define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) fourcc_mod_code(ARM, __afbc_mode)
  579. /*
  580. * AFBC superblock size
  581. *
  582. * Indicates the superblock size(s) used for the AFBC buffer. The buffer
  583. * size (in pixels) must be aligned to a multiple of the superblock size.
  584. * Four lowest significant bits(LSBs) are reserved for block size.
  585. *
  586. * Where one superblock size is specified, it applies to all planes of the
  587. * buffer (e.g. 16x16, 32x8). When multiple superblock sizes are specified,
  588. * the first applies to the Luma plane and the second applies to the Chroma
  589. * plane(s). e.g. (32x8_64x4 means 32x8 Luma, with 64x4 Chroma).
  590. * Multiple superblock sizes are only valid for multi-plane YCbCr formats.
  591. */
  592. #define AFBC_FORMAT_MOD_BLOCK_SIZE_MASK 0xf
  593. #define AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 (1ULL)
  594. #define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 (2ULL)
  595. #define AFBC_FORMAT_MOD_BLOCK_SIZE_64x4 (3ULL)
  596. #define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8_64x4 (4ULL)
  597. /*
  598. * AFBC lossless colorspace transform
  599. *
  600. * Indicates that the buffer makes use of the AFBC lossless colorspace
  601. * transform.
  602. */
  603. #define AFBC_FORMAT_MOD_YTR (1ULL << 4)
  604. /*
  605. * AFBC block-split
  606. *
  607. * Indicates that the payload of each superblock is split. The second
  608. * half of the payload is positioned at a predefined offset from the start
  609. * of the superblock payload.
  610. */
  611. #define AFBC_FORMAT_MOD_SPLIT (1ULL << 5)
  612. /*
  613. * AFBC sparse layout
  614. *
  615. * This flag indicates that the payload of each superblock must be stored at a
  616. * predefined position relative to the other superblocks in the same AFBC
  617. * buffer. This order is the same order used by the header buffer. In this mode
  618. * each superblock is given the same amount of space as an uncompressed
  619. * superblock of the particular format would require, rounding up to the next
  620. * multiple of 128 bytes in size.
  621. */
  622. #define AFBC_FORMAT_MOD_SPARSE (1ULL << 6)
  623. /*
  624. * AFBC copy-block restrict
  625. *
  626. * Buffers with this flag must obey the copy-block restriction. The restriction
  627. * is such that there are no copy-blocks referring across the border of 8x8
  628. * blocks. For the subsampled data the 8x8 limitation is also subsampled.
  629. */
  630. #define AFBC_FORMAT_MOD_CBR (1ULL << 7)
  631. /*
  632. * AFBC tiled layout
  633. *
  634. * The tiled layout groups superblocks in 8x8 or 4x4 tiles, where all
  635. * superblocks inside a tile are stored together in memory. 8x8 tiles are used
  636. * for pixel formats up to and including 32 bpp while 4x4 tiles are used for
  637. * larger bpp formats. The order between the tiles is scan line.
  638. * When the tiled layout is used, the buffer size (in pixels) must be aligned
  639. * to the tile size.
  640. */
  641. #define AFBC_FORMAT_MOD_TILED (1ULL << 8)
  642. /*
  643. * AFBC solid color blocks
  644. *
  645. * Indicates that the buffer makes use of solid-color blocks, whereby bandwidth
  646. * can be reduced if a whole superblock is a single color.
  647. */
  648. #define AFBC_FORMAT_MOD_SC (1ULL << 9)
  649. /*
  650. * AFBC double-buffer
  651. *
  652. * Indicates that the buffer is allocated in a layout safe for front-buffer
  653. * rendering.
  654. */
  655. #define AFBC_FORMAT_MOD_DB (1ULL << 10)
  656. /*
  657. * AFBC buffer content hints
  658. *
  659. * Indicates that the buffer includes per-superblock content hints.
  660. */
  661. #define AFBC_FORMAT_MOD_BCH (1ULL << 11)
  662. /*
  663. * Allwinner tiled modifier
  664. *
  665. * This tiling mode is implemented by the VPU found on all Allwinner platforms,
  666. * codenamed sunxi. It is associated with a YUV format that uses either 2 or 3
  667. * planes.
  668. *
  669. * With this tiling, the luminance samples are disposed in tiles representing
  670. * 32x32 pixels and the chrominance samples in tiles representing 32x64 pixels.
  671. * The pixel order in each tile is linear and the tiles are disposed linearly,
  672. * both in row-major order.
  673. */
  674. #define DRM_FORMAT_MOD_ALLWINNER_TILED fourcc_mod_code(ALLWINNER, 1)
  675. #if defined(__cplusplus)
  676. }
  677. #endif
  678. #endif /* DRM_FOURCC_H */