drm.h 32 KB

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  1. /**
  2. * \file drm.h
  3. * Header for the Direct Rendering Manager
  4. *
  5. * \author Rickard E. (Rik) Faith <faith@valinux.com>
  6. *
  7. * \par Acknowledgments:
  8. * Dec 1999, Richard Henderson <rth@twiddle.net>, move to generic \c cmpxchg.
  9. */
  10. /*
  11. * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
  12. * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
  13. * All rights reserved.
  14. *
  15. * Permission is hereby granted, free of charge, to any person obtaining a
  16. * copy of this software and associated documentation files (the "Software"),
  17. * to deal in the Software without restriction, including without limitation
  18. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  19. * and/or sell copies of the Software, and to permit persons to whom the
  20. * Software is furnished to do so, subject to the following conditions:
  21. *
  22. * The above copyright notice and this permission notice (including the next
  23. * paragraph) shall be included in all copies or substantial portions of the
  24. * Software.
  25. *
  26. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  27. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  28. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  29. * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  30. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  31. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  32. * OTHER DEALINGS IN THE SOFTWARE.
  33. */
  34. #ifndef _DRM_H_
  35. #define _DRM_H_
  36. #if defined(__linux__)
  37. #include <linux/types.h>
  38. #include <asm/ioctl.h>
  39. typedef unsigned int drm_handle_t;
  40. #else /* One of the BSDs */
  41. #include <stdint.h>
  42. #include <sys/ioccom.h>
  43. #include <sys/types.h>
  44. typedef int8_t __s8;
  45. typedef uint8_t __u8;
  46. typedef int16_t __s16;
  47. typedef uint16_t __u16;
  48. typedef int32_t __s32;
  49. typedef uint32_t __u32;
  50. typedef int64_t __s64;
  51. typedef uint64_t __u64;
  52. typedef size_t __kernel_size_t;
  53. typedef unsigned long drm_handle_t;
  54. #endif
  55. #if defined(__cplusplus)
  56. extern "C" {
  57. #endif
  58. #define DRM_NAME "drm" /**< Name in kernel, /dev, and /proc */
  59. #define DRM_MIN_ORDER 5 /**< At least 2^5 bytes = 32 bytes */
  60. #define DRM_MAX_ORDER 22 /**< Up to 2^22 bytes = 4MB */
  61. #define DRM_RAM_PERCENT 10 /**< How much system ram can we lock? */
  62. #define _DRM_LOCK_HELD 0x80000000U /**< Hardware lock is held */
  63. #define _DRM_LOCK_CONT 0x40000000U /**< Hardware lock is contended */
  64. #define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD)
  65. #define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT)
  66. #define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT))
  67. typedef unsigned int drm_context_t;
  68. typedef unsigned int drm_drawable_t;
  69. typedef unsigned int drm_magic_t;
  70. /**
  71. * Cliprect.
  72. *
  73. * \warning: If you change this structure, make sure you change
  74. * XF86DRIClipRectRec in the server as well
  75. *
  76. * \note KW: Actually it's illegal to change either for
  77. * backwards-compatibility reasons.
  78. */
  79. struct drm_clip_rect {
  80. unsigned short x1;
  81. unsigned short y1;
  82. unsigned short x2;
  83. unsigned short y2;
  84. };
  85. /**
  86. * Drawable information.
  87. */
  88. struct drm_drawable_info {
  89. unsigned int num_rects;
  90. struct drm_clip_rect *rects;
  91. };
  92. /**
  93. * Texture region,
  94. */
  95. struct drm_tex_region {
  96. unsigned char next;
  97. unsigned char prev;
  98. unsigned char in_use;
  99. unsigned char padding;
  100. unsigned int age;
  101. };
  102. /**
  103. * Hardware lock.
  104. *
  105. * The lock structure is a simple cache-line aligned integer. To avoid
  106. * processor bus contention on a multiprocessor system, there should not be any
  107. * other data stored in the same cache line.
  108. */
  109. struct drm_hw_lock {
  110. __volatile__ unsigned int lock; /**< lock variable */
  111. char padding[60]; /**< Pad to cache line */
  112. };
  113. /**
  114. * DRM_IOCTL_VERSION ioctl argument type.
  115. *
  116. * \sa drmGetVersion().
  117. */
  118. struct drm_version {
  119. int version_major; /**< Major version */
  120. int version_minor; /**< Minor version */
  121. int version_patchlevel; /**< Patch level */
  122. __kernel_size_t name_len; /**< Length of name buffer */
  123. char *name; /**< Name of driver */
  124. __kernel_size_t date_len; /**< Length of date buffer */
  125. char *date; /**< User-space buffer to hold date */
  126. __kernel_size_t desc_len; /**< Length of desc buffer */
  127. char *desc; /**< User-space buffer to hold desc */
  128. };
  129. /**
  130. * DRM_IOCTL_GET_UNIQUE ioctl argument type.
  131. *
  132. * \sa drmGetBusid() and drmSetBusId().
  133. */
  134. struct drm_unique {
  135. __kernel_size_t unique_len; /**< Length of unique */
  136. char *unique; /**< Unique name for driver instantiation */
  137. };
  138. struct drm_list {
  139. int count; /**< Length of user-space structures */
  140. struct drm_version *version;
  141. };
  142. struct drm_block {
  143. int unused;
  144. };
  145. /**
  146. * DRM_IOCTL_CONTROL ioctl argument type.
  147. *
  148. * \sa drmCtlInstHandler() and drmCtlUninstHandler().
  149. */
  150. struct drm_control {
  151. enum {
  152. DRM_ADD_COMMAND,
  153. DRM_RM_COMMAND,
  154. DRM_INST_HANDLER,
  155. DRM_UNINST_HANDLER
  156. } func;
  157. int irq;
  158. };
  159. /**
  160. * Type of memory to map.
  161. */
  162. enum drm_map_type {
  163. _DRM_FRAME_BUFFER = 0, /**< WC (no caching), no core dump */
  164. _DRM_REGISTERS = 1, /**< no caching, no core dump */
  165. _DRM_SHM = 2, /**< shared, cached */
  166. _DRM_AGP = 3, /**< AGP/GART */
  167. _DRM_SCATTER_GATHER = 4, /**< Scatter/gather memory for PCI DMA */
  168. _DRM_CONSISTENT = 5 /**< Consistent memory for PCI DMA */
  169. };
  170. /**
  171. * Memory mapping flags.
  172. */
  173. enum drm_map_flags {
  174. _DRM_RESTRICTED = 0x01, /**< Cannot be mapped to user-virtual */
  175. _DRM_READ_ONLY = 0x02,
  176. _DRM_LOCKED = 0x04, /**< shared, cached, locked */
  177. _DRM_KERNEL = 0x08, /**< kernel requires access */
  178. _DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */
  179. _DRM_CONTAINS_LOCK = 0x20, /**< SHM page that contains lock */
  180. _DRM_REMOVABLE = 0x40, /**< Removable mapping */
  181. _DRM_DRIVER = 0x80 /**< Managed by driver */
  182. };
  183. struct drm_ctx_priv_map {
  184. unsigned int ctx_id; /**< Context requesting private mapping */
  185. void *handle; /**< Handle of map */
  186. };
  187. /**
  188. * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls
  189. * argument type.
  190. *
  191. * \sa drmAddMap().
  192. */
  193. struct drm_map {
  194. unsigned long offset; /**< Requested physical address (0 for SAREA)*/
  195. unsigned long size; /**< Requested physical size (bytes) */
  196. enum drm_map_type type; /**< Type of memory to map */
  197. enum drm_map_flags flags; /**< Flags */
  198. void *handle; /**< User-space: "Handle" to pass to mmap() */
  199. /**< Kernel-space: kernel-virtual address */
  200. int mtrr; /**< MTRR slot used */
  201. /* Private data */
  202. };
  203. /**
  204. * DRM_IOCTL_GET_CLIENT ioctl argument type.
  205. */
  206. struct drm_client {
  207. int idx; /**< Which client desired? */
  208. int auth; /**< Is client authenticated? */
  209. unsigned long pid; /**< Process ID */
  210. unsigned long uid; /**< User ID */
  211. unsigned long magic; /**< Magic */
  212. unsigned long iocs; /**< Ioctl count */
  213. };
  214. enum drm_stat_type {
  215. _DRM_STAT_LOCK,
  216. _DRM_STAT_OPENS,
  217. _DRM_STAT_CLOSES,
  218. _DRM_STAT_IOCTLS,
  219. _DRM_STAT_LOCKS,
  220. _DRM_STAT_UNLOCKS,
  221. _DRM_STAT_VALUE, /**< Generic value */
  222. _DRM_STAT_BYTE, /**< Generic byte counter (1024bytes/K) */
  223. _DRM_STAT_COUNT, /**< Generic non-byte counter (1000/k) */
  224. _DRM_STAT_IRQ, /**< IRQ */
  225. _DRM_STAT_PRIMARY, /**< Primary DMA bytes */
  226. _DRM_STAT_SECONDARY, /**< Secondary DMA bytes */
  227. _DRM_STAT_DMA, /**< DMA */
  228. _DRM_STAT_SPECIAL, /**< Special DMA (e.g., priority or polled) */
  229. _DRM_STAT_MISSED /**< Missed DMA opportunity */
  230. /* Add to the *END* of the list */
  231. };
  232. /**
  233. * DRM_IOCTL_GET_STATS ioctl argument type.
  234. */
  235. struct drm_stats {
  236. unsigned long count;
  237. struct {
  238. unsigned long value;
  239. enum drm_stat_type type;
  240. } data[15];
  241. };
  242. /**
  243. * Hardware locking flags.
  244. */
  245. enum drm_lock_flags {
  246. _DRM_LOCK_READY = 0x01, /**< Wait until hardware is ready for DMA */
  247. _DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */
  248. _DRM_LOCK_FLUSH = 0x04, /**< Flush this context's DMA queue first */
  249. _DRM_LOCK_FLUSH_ALL = 0x08, /**< Flush all DMA queues first */
  250. /* These *HALT* flags aren't supported yet
  251. -- they will be used to support the
  252. full-screen DGA-like mode. */
  253. _DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */
  254. _DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */
  255. };
  256. /**
  257. * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type.
  258. *
  259. * \sa drmGetLock() and drmUnlock().
  260. */
  261. struct drm_lock {
  262. int context;
  263. enum drm_lock_flags flags;
  264. };
  265. /**
  266. * DMA flags
  267. *
  268. * \warning
  269. * These values \e must match xf86drm.h.
  270. *
  271. * \sa drm_dma.
  272. */
  273. enum drm_dma_flags {
  274. /* Flags for DMA buffer dispatch */
  275. _DRM_DMA_BLOCK = 0x01, /**<
  276. * Block until buffer dispatched.
  277. *
  278. * \note The buffer may not yet have
  279. * been processed by the hardware --
  280. * getting a hardware lock with the
  281. * hardware quiescent will ensure
  282. * that the buffer has been
  283. * processed.
  284. */
  285. _DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */
  286. _DRM_DMA_PRIORITY = 0x04, /**< High priority dispatch */
  287. /* Flags for DMA buffer request */
  288. _DRM_DMA_WAIT = 0x10, /**< Wait for free buffers */
  289. _DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */
  290. _DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */
  291. };
  292. /**
  293. * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type.
  294. *
  295. * \sa drmAddBufs().
  296. */
  297. struct drm_buf_desc {
  298. int count; /**< Number of buffers of this size */
  299. int size; /**< Size in bytes */
  300. int low_mark; /**< Low water mark */
  301. int high_mark; /**< High water mark */
  302. enum {
  303. _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */
  304. _DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */
  305. _DRM_SG_BUFFER = 0x04, /**< Scatter/gather memory buffer */
  306. _DRM_FB_BUFFER = 0x08, /**< Buffer is in frame buffer */
  307. _DRM_PCI_BUFFER_RO = 0x10 /**< Map PCI DMA buffer read-only */
  308. } flags;
  309. unsigned long agp_start; /**<
  310. * Start address of where the AGP buffers are
  311. * in the AGP aperture
  312. */
  313. };
  314. /**
  315. * DRM_IOCTL_INFO_BUFS ioctl argument type.
  316. */
  317. struct drm_buf_info {
  318. int count; /**< Entries in list */
  319. struct drm_buf_desc *list;
  320. };
  321. /**
  322. * DRM_IOCTL_FREE_BUFS ioctl argument type.
  323. */
  324. struct drm_buf_free {
  325. int count;
  326. int *list;
  327. };
  328. /**
  329. * Buffer information
  330. *
  331. * \sa drm_buf_map.
  332. */
  333. struct drm_buf_pub {
  334. int idx; /**< Index into the master buffer list */
  335. int total; /**< Buffer size */
  336. int used; /**< Amount of buffer in use (for DMA) */
  337. void *address; /**< Address of buffer */
  338. };
  339. /**
  340. * DRM_IOCTL_MAP_BUFS ioctl argument type.
  341. */
  342. struct drm_buf_map {
  343. int count; /**< Length of the buffer list */
  344. #ifdef __cplusplus
  345. void *virt;
  346. #else
  347. void *virtual; /**< Mmap'd area in user-virtual */
  348. #endif
  349. struct drm_buf_pub *list; /**< Buffer information */
  350. };
  351. /**
  352. * DRM_IOCTL_DMA ioctl argument type.
  353. *
  354. * Indices here refer to the offset into the buffer list in drm_buf_get.
  355. *
  356. * \sa drmDMA().
  357. */
  358. struct drm_dma {
  359. int context; /**< Context handle */
  360. int send_count; /**< Number of buffers to send */
  361. int *send_indices; /**< List of handles to buffers */
  362. int *send_sizes; /**< Lengths of data to send */
  363. enum drm_dma_flags flags; /**< Flags */
  364. int request_count; /**< Number of buffers requested */
  365. int request_size; /**< Desired size for buffers */
  366. int *request_indices; /**< Buffer information */
  367. int *request_sizes;
  368. int granted_count; /**< Number of buffers granted */
  369. };
  370. enum drm_ctx_flags {
  371. _DRM_CONTEXT_PRESERVED = 0x01,
  372. _DRM_CONTEXT_2DONLY = 0x02
  373. };
  374. /**
  375. * DRM_IOCTL_ADD_CTX ioctl argument type.
  376. *
  377. * \sa drmCreateContext() and drmDestroyContext().
  378. */
  379. struct drm_ctx {
  380. drm_context_t handle;
  381. enum drm_ctx_flags flags;
  382. };
  383. /**
  384. * DRM_IOCTL_RES_CTX ioctl argument type.
  385. */
  386. struct drm_ctx_res {
  387. int count;
  388. struct drm_ctx *contexts;
  389. };
  390. /**
  391. * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type.
  392. */
  393. struct drm_draw {
  394. drm_drawable_t handle;
  395. };
  396. /**
  397. * DRM_IOCTL_UPDATE_DRAW ioctl argument type.
  398. */
  399. typedef enum {
  400. DRM_DRAWABLE_CLIPRECTS
  401. } drm_drawable_info_type_t;
  402. struct drm_update_draw {
  403. drm_drawable_t handle;
  404. unsigned int type;
  405. unsigned int num;
  406. unsigned long long data;
  407. };
  408. /**
  409. * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type.
  410. */
  411. struct drm_auth {
  412. drm_magic_t magic;
  413. };
  414. /**
  415. * DRM_IOCTL_IRQ_BUSID ioctl argument type.
  416. *
  417. * \sa drmGetInterruptFromBusID().
  418. */
  419. struct drm_irq_busid {
  420. int irq; /**< IRQ number */
  421. int busnum; /**< bus number */
  422. int devnum; /**< device number */
  423. int funcnum; /**< function number */
  424. };
  425. enum drm_vblank_seq_type {
  426. _DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */
  427. _DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */
  428. /* bits 1-6 are reserved for high crtcs */
  429. _DRM_VBLANK_HIGH_CRTC_MASK = 0x0000003e,
  430. _DRM_VBLANK_EVENT = 0x4000000, /**< Send event instead of blocking */
  431. _DRM_VBLANK_FLIP = 0x8000000, /**< Scheduled buffer swap should flip */
  432. _DRM_VBLANK_NEXTONMISS = 0x10000000, /**< If missed, wait for next vblank */
  433. _DRM_VBLANK_SECONDARY = 0x20000000, /**< Secondary display controller */
  434. _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking, unsupported */
  435. };
  436. #define _DRM_VBLANK_HIGH_CRTC_SHIFT 1
  437. #define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE)
  438. #define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_EVENT | _DRM_VBLANK_SIGNAL | \
  439. _DRM_VBLANK_SECONDARY | _DRM_VBLANK_NEXTONMISS)
  440. struct drm_wait_vblank_request {
  441. enum drm_vblank_seq_type type;
  442. unsigned int sequence;
  443. unsigned long signal;
  444. };
  445. struct drm_wait_vblank_reply {
  446. enum drm_vblank_seq_type type;
  447. unsigned int sequence;
  448. long tval_sec;
  449. long tval_usec;
  450. };
  451. /**
  452. * DRM_IOCTL_WAIT_VBLANK ioctl argument type.
  453. *
  454. * \sa drmWaitVBlank().
  455. */
  456. union drm_wait_vblank {
  457. struct drm_wait_vblank_request request;
  458. struct drm_wait_vblank_reply reply;
  459. };
  460. #define _DRM_PRE_MODESET 1
  461. #define _DRM_POST_MODESET 2
  462. /**
  463. * DRM_IOCTL_MODESET_CTL ioctl argument type
  464. *
  465. * \sa drmModesetCtl().
  466. */
  467. struct drm_modeset_ctl {
  468. __u32 crtc;
  469. __u32 cmd;
  470. };
  471. /**
  472. * DRM_IOCTL_AGP_ENABLE ioctl argument type.
  473. *
  474. * \sa drmAgpEnable().
  475. */
  476. struct drm_agp_mode {
  477. unsigned long mode; /**< AGP mode */
  478. };
  479. /**
  480. * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type.
  481. *
  482. * \sa drmAgpAlloc() and drmAgpFree().
  483. */
  484. struct drm_agp_buffer {
  485. unsigned long size; /**< In bytes -- will round to page boundary */
  486. unsigned long handle; /**< Used for binding / unbinding */
  487. unsigned long type; /**< Type of memory to allocate */
  488. unsigned long physical; /**< Physical used by i810 */
  489. };
  490. /**
  491. * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type.
  492. *
  493. * \sa drmAgpBind() and drmAgpUnbind().
  494. */
  495. struct drm_agp_binding {
  496. unsigned long handle; /**< From drm_agp_buffer */
  497. unsigned long offset; /**< In bytes -- will round to page boundary */
  498. };
  499. /**
  500. * DRM_IOCTL_AGP_INFO ioctl argument type.
  501. *
  502. * \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(),
  503. * drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(),
  504. * drmAgpVendorId() and drmAgpDeviceId().
  505. */
  506. struct drm_agp_info {
  507. int agp_version_major;
  508. int agp_version_minor;
  509. unsigned long mode;
  510. unsigned long aperture_base; /* physical address */
  511. unsigned long aperture_size; /* bytes */
  512. unsigned long memory_allowed; /* bytes */
  513. unsigned long memory_used;
  514. /* PCI information */
  515. unsigned short id_vendor;
  516. unsigned short id_device;
  517. };
  518. /**
  519. * DRM_IOCTL_SG_ALLOC ioctl argument type.
  520. */
  521. struct drm_scatter_gather {
  522. unsigned long size; /**< In bytes -- will round to page boundary */
  523. unsigned long handle; /**< Used for mapping / unmapping */
  524. };
  525. /**
  526. * DRM_IOCTL_SET_VERSION ioctl argument type.
  527. */
  528. struct drm_set_version {
  529. int drm_di_major;
  530. int drm_di_minor;
  531. int drm_dd_major;
  532. int drm_dd_minor;
  533. };
  534. /** DRM_IOCTL_GEM_CLOSE ioctl argument type */
  535. struct drm_gem_close {
  536. /** Handle of the object to be closed. */
  537. __u32 handle;
  538. __u32 pad;
  539. };
  540. /** DRM_IOCTL_GEM_FLINK ioctl argument type */
  541. struct drm_gem_flink {
  542. /** Handle for the object being named */
  543. __u32 handle;
  544. /** Returned global name */
  545. __u32 name;
  546. };
  547. /** DRM_IOCTL_GEM_OPEN ioctl argument type */
  548. struct drm_gem_open {
  549. /** Name of object being opened */
  550. __u32 name;
  551. /** Returned handle for the object */
  552. __u32 handle;
  553. /** Returned size of the object */
  554. __u64 size;
  555. };
  556. #define DRM_CAP_DUMB_BUFFER 0x1
  557. #define DRM_CAP_VBLANK_HIGH_CRTC 0x2
  558. #define DRM_CAP_DUMB_PREFERRED_DEPTH 0x3
  559. #define DRM_CAP_DUMB_PREFER_SHADOW 0x4
  560. #define DRM_CAP_PRIME 0x5
  561. #define DRM_PRIME_CAP_IMPORT 0x1
  562. #define DRM_PRIME_CAP_EXPORT 0x2
  563. #define DRM_CAP_TIMESTAMP_MONOTONIC 0x6
  564. #define DRM_CAP_ASYNC_PAGE_FLIP 0x7
  565. /*
  566. * The CURSOR_WIDTH and CURSOR_HEIGHT capabilities return a valid widthxheight
  567. * combination for the hardware cursor. The intention is that a hardware
  568. * agnostic userspace can query a cursor plane size to use.
  569. *
  570. * Note that the cross-driver contract is to merely return a valid size;
  571. * drivers are free to attach another meaning on top, eg. i915 returns the
  572. * maximum plane size.
  573. */
  574. #define DRM_CAP_CURSOR_WIDTH 0x8
  575. #define DRM_CAP_CURSOR_HEIGHT 0x9
  576. #define DRM_CAP_ADDFB2_MODIFIERS 0x10
  577. #define DRM_CAP_PAGE_FLIP_TARGET 0x11
  578. #define DRM_CAP_CRTC_IN_VBLANK_EVENT 0x12
  579. #define DRM_CAP_SYNCOBJ 0x13
  580. #define DRM_CAP_SYNCOBJ_TIMELINE 0x14
  581. /** DRM_IOCTL_GET_CAP ioctl argument type */
  582. struct drm_get_cap {
  583. __u64 capability;
  584. __u64 value;
  585. };
  586. /**
  587. * DRM_CLIENT_CAP_STEREO_3D
  588. *
  589. * if set to 1, the DRM core will expose the stereo 3D capabilities of the
  590. * monitor by advertising the supported 3D layouts in the flags of struct
  591. * drm_mode_modeinfo.
  592. */
  593. #define DRM_CLIENT_CAP_STEREO_3D 1
  594. /**
  595. * DRM_CLIENT_CAP_UNIVERSAL_PLANES
  596. *
  597. * If set to 1, the DRM core will expose all planes (overlay, primary, and
  598. * cursor) to userspace.
  599. */
  600. #define DRM_CLIENT_CAP_UNIVERSAL_PLANES 2
  601. /**
  602. * DRM_CLIENT_CAP_ATOMIC
  603. *
  604. * If set to 1, the DRM core will expose atomic properties to userspace
  605. */
  606. #define DRM_CLIENT_CAP_ATOMIC 3
  607. /**
  608. * DRM_CLIENT_CAP_ASPECT_RATIO
  609. *
  610. * If set to 1, the DRM core will provide aspect ratio information in modes.
  611. */
  612. #define DRM_CLIENT_CAP_ASPECT_RATIO 4
  613. /**
  614. * DRM_CLIENT_CAP_WRITEBACK_CONNECTORS
  615. *
  616. * If set to 1, the DRM core will expose special connectors to be used for
  617. * writing back to memory the scene setup in the commit. Depends on client
  618. * also supporting DRM_CLIENT_CAP_ATOMIC
  619. */
  620. #define DRM_CLIENT_CAP_WRITEBACK_CONNECTORS 5
  621. /** DRM_IOCTL_SET_CLIENT_CAP ioctl argument type */
  622. struct drm_set_client_cap {
  623. __u64 capability;
  624. __u64 value;
  625. };
  626. #define DRM_RDWR O_RDWR
  627. #define DRM_CLOEXEC O_CLOEXEC
  628. struct drm_prime_handle {
  629. __u32 handle;
  630. /** Flags.. only applicable for handle->fd */
  631. __u32 flags;
  632. /** Returned dmabuf file descriptor */
  633. __s32 fd;
  634. };
  635. struct drm_syncobj_create {
  636. __u32 handle;
  637. #define DRM_SYNCOBJ_CREATE_SIGNALED (1 << 0)
  638. __u32 flags;
  639. };
  640. struct drm_syncobj_destroy {
  641. __u32 handle;
  642. __u32 pad;
  643. };
  644. #define DRM_SYNCOBJ_FD_TO_HANDLE_FLAGS_IMPORT_SYNC_FILE (1 << 0)
  645. #define DRM_SYNCOBJ_HANDLE_TO_FD_FLAGS_EXPORT_SYNC_FILE (1 << 0)
  646. struct drm_syncobj_handle {
  647. __u32 handle;
  648. __u32 flags;
  649. __s32 fd;
  650. __u32 pad;
  651. };
  652. struct drm_syncobj_transfer {
  653. __u32 src_handle;
  654. __u32 dst_handle;
  655. __u64 src_point;
  656. __u64 dst_point;
  657. __u32 flags;
  658. __u32 pad;
  659. };
  660. #define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL (1 << 0)
  661. #define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT (1 << 1)
  662. #define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_AVAILABLE (1 << 2) /* wait for time point to become available */
  663. struct drm_syncobj_wait {
  664. __u64 handles;
  665. /* absolute timeout */
  666. __s64 timeout_nsec;
  667. __u32 count_handles;
  668. __u32 flags;
  669. __u32 first_signaled; /* only valid when not waiting all */
  670. __u32 pad;
  671. };
  672. struct drm_syncobj_timeline_wait {
  673. __u64 handles;
  674. /* wait on specific timeline point for every handles*/
  675. __u64 points;
  676. /* absolute timeout */
  677. __s64 timeout_nsec;
  678. __u32 count_handles;
  679. __u32 flags;
  680. __u32 first_signaled; /* only valid when not waiting all */
  681. __u32 pad;
  682. };
  683. struct drm_syncobj_array {
  684. __u64 handles;
  685. __u32 count_handles;
  686. __u32 pad;
  687. };
  688. #define DRM_SYNCOBJ_QUERY_FLAGS_LAST_SUBMITTED (1 << 0) /* last available point on timeline syncobj */
  689. struct drm_syncobj_timeline_array {
  690. __u64 handles;
  691. __u64 points;
  692. __u32 count_handles;
  693. __u32 flags;
  694. };
  695. /* Query current scanout sequence number */
  696. struct drm_crtc_get_sequence {
  697. __u32 crtc_id; /* requested crtc_id */
  698. __u32 active; /* return: crtc output is active */
  699. __u64 sequence; /* return: most recent vblank sequence */
  700. __s64 sequence_ns; /* return: most recent time of first pixel out */
  701. };
  702. /* Queue event to be delivered at specified sequence. Time stamp marks
  703. * when the first pixel of the refresh cycle leaves the display engine
  704. * for the display
  705. */
  706. #define DRM_CRTC_SEQUENCE_RELATIVE 0x00000001 /* sequence is relative to current */
  707. #define DRM_CRTC_SEQUENCE_NEXT_ON_MISS 0x00000002 /* Use next sequence if we've missed */
  708. struct drm_crtc_queue_sequence {
  709. __u32 crtc_id;
  710. __u32 flags;
  711. __u64 sequence; /* on input, target sequence. on output, actual sequence */
  712. __u64 user_data; /* user data passed to event */
  713. };
  714. #if defined(__cplusplus)
  715. }
  716. #endif
  717. #include "drm_mode.h"
  718. #if defined(__cplusplus)
  719. extern "C" {
  720. #endif
  721. #define DRM_IOCTL_BASE 'd'
  722. #define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr)
  723. #define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type)
  724. #define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type)
  725. #define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type)
  726. #define DRM_IOCTL_VERSION DRM_IOWR(0x00, struct drm_version)
  727. #define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, struct drm_unique)
  728. #define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, struct drm_auth)
  729. #define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, struct drm_irq_busid)
  730. #define DRM_IOCTL_GET_MAP DRM_IOWR(0x04, struct drm_map)
  731. #define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, struct drm_client)
  732. #define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, struct drm_stats)
  733. #define DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, struct drm_set_version)
  734. #define DRM_IOCTL_MODESET_CTL DRM_IOW(0x08, struct drm_modeset_ctl)
  735. #define DRM_IOCTL_GEM_CLOSE DRM_IOW (0x09, struct drm_gem_close)
  736. #define DRM_IOCTL_GEM_FLINK DRM_IOWR(0x0a, struct drm_gem_flink)
  737. #define DRM_IOCTL_GEM_OPEN DRM_IOWR(0x0b, struct drm_gem_open)
  738. #define DRM_IOCTL_GET_CAP DRM_IOWR(0x0c, struct drm_get_cap)
  739. #define DRM_IOCTL_SET_CLIENT_CAP DRM_IOW( 0x0d, struct drm_set_client_cap)
  740. #define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, struct drm_unique)
  741. #define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, struct drm_auth)
  742. #define DRM_IOCTL_BLOCK DRM_IOWR(0x12, struct drm_block)
  743. #define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, struct drm_block)
  744. #define DRM_IOCTL_CONTROL DRM_IOW( 0x14, struct drm_control)
  745. #define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, struct drm_map)
  746. #define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, struct drm_buf_desc)
  747. #define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, struct drm_buf_desc)
  748. #define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, struct drm_buf_info)
  749. #define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, struct drm_buf_map)
  750. #define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, struct drm_buf_free)
  751. #define DRM_IOCTL_RM_MAP DRM_IOW( 0x1b, struct drm_map)
  752. #define DRM_IOCTL_SET_SAREA_CTX DRM_IOW( 0x1c, struct drm_ctx_priv_map)
  753. #define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, struct drm_ctx_priv_map)
  754. #define DRM_IOCTL_SET_MASTER DRM_IO(0x1e)
  755. #define DRM_IOCTL_DROP_MASTER DRM_IO(0x1f)
  756. #define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, struct drm_ctx)
  757. #define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, struct drm_ctx)
  758. #define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, struct drm_ctx)
  759. #define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, struct drm_ctx)
  760. #define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, struct drm_ctx)
  761. #define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, struct drm_ctx)
  762. #define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, struct drm_ctx_res)
  763. #define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, struct drm_draw)
  764. #define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, struct drm_draw)
  765. #define DRM_IOCTL_DMA DRM_IOWR(0x29, struct drm_dma)
  766. #define DRM_IOCTL_LOCK DRM_IOW( 0x2a, struct drm_lock)
  767. #define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, struct drm_lock)
  768. #define DRM_IOCTL_FINISH DRM_IOW( 0x2c, struct drm_lock)
  769. #define DRM_IOCTL_PRIME_HANDLE_TO_FD DRM_IOWR(0x2d, struct drm_prime_handle)
  770. #define DRM_IOCTL_PRIME_FD_TO_HANDLE DRM_IOWR(0x2e, struct drm_prime_handle)
  771. #define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30)
  772. #define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31)
  773. #define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, struct drm_agp_mode)
  774. #define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, struct drm_agp_info)
  775. #define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, struct drm_agp_buffer)
  776. #define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, struct drm_agp_buffer)
  777. #define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, struct drm_agp_binding)
  778. #define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, struct drm_agp_binding)
  779. #define DRM_IOCTL_SG_ALLOC DRM_IOWR(0x38, struct drm_scatter_gather)
  780. #define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, struct drm_scatter_gather)
  781. #define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, union drm_wait_vblank)
  782. #define DRM_IOCTL_CRTC_GET_SEQUENCE DRM_IOWR(0x3b, struct drm_crtc_get_sequence)
  783. #define DRM_IOCTL_CRTC_QUEUE_SEQUENCE DRM_IOWR(0x3c, struct drm_crtc_queue_sequence)
  784. #define DRM_IOCTL_UPDATE_DRAW DRM_IOW(0x3f, struct drm_update_draw)
  785. #define DRM_IOCTL_MODE_GETRESOURCES DRM_IOWR(0xA0, struct drm_mode_card_res)
  786. #define DRM_IOCTL_MODE_GETCRTC DRM_IOWR(0xA1, struct drm_mode_crtc)
  787. #define DRM_IOCTL_MODE_SETCRTC DRM_IOWR(0xA2, struct drm_mode_crtc)
  788. #define DRM_IOCTL_MODE_CURSOR DRM_IOWR(0xA3, struct drm_mode_cursor)
  789. #define DRM_IOCTL_MODE_GETGAMMA DRM_IOWR(0xA4, struct drm_mode_crtc_lut)
  790. #define DRM_IOCTL_MODE_SETGAMMA DRM_IOWR(0xA5, struct drm_mode_crtc_lut)
  791. #define DRM_IOCTL_MODE_GETENCODER DRM_IOWR(0xA6, struct drm_mode_get_encoder)
  792. #define DRM_IOCTL_MODE_GETCONNECTOR DRM_IOWR(0xA7, struct drm_mode_get_connector)
  793. #define DRM_IOCTL_MODE_ATTACHMODE DRM_IOWR(0xA8, struct drm_mode_mode_cmd) /* deprecated (never worked) */
  794. #define DRM_IOCTL_MODE_DETACHMODE DRM_IOWR(0xA9, struct drm_mode_mode_cmd) /* deprecated (never worked) */
  795. #define DRM_IOCTL_MODE_GETPROPERTY DRM_IOWR(0xAA, struct drm_mode_get_property)
  796. #define DRM_IOCTL_MODE_SETPROPERTY DRM_IOWR(0xAB, struct drm_mode_connector_set_property)
  797. #define DRM_IOCTL_MODE_GETPROPBLOB DRM_IOWR(0xAC, struct drm_mode_get_blob)
  798. #define DRM_IOCTL_MODE_GETFB DRM_IOWR(0xAD, struct drm_mode_fb_cmd)
  799. #define DRM_IOCTL_MODE_ADDFB DRM_IOWR(0xAE, struct drm_mode_fb_cmd)
  800. #define DRM_IOCTL_MODE_RMFB DRM_IOWR(0xAF, unsigned int)
  801. #define DRM_IOCTL_MODE_PAGE_FLIP DRM_IOWR(0xB0, struct drm_mode_crtc_page_flip)
  802. #define DRM_IOCTL_MODE_DIRTYFB DRM_IOWR(0xB1, struct drm_mode_fb_dirty_cmd)
  803. #define DRM_IOCTL_MODE_CREATE_DUMB DRM_IOWR(0xB2, struct drm_mode_create_dumb)
  804. #define DRM_IOCTL_MODE_MAP_DUMB DRM_IOWR(0xB3, struct drm_mode_map_dumb)
  805. #define DRM_IOCTL_MODE_DESTROY_DUMB DRM_IOWR(0xB4, struct drm_mode_destroy_dumb)
  806. #define DRM_IOCTL_MODE_GETPLANERESOURCES DRM_IOWR(0xB5, struct drm_mode_get_plane_res)
  807. #define DRM_IOCTL_MODE_GETPLANE DRM_IOWR(0xB6, struct drm_mode_get_plane)
  808. #define DRM_IOCTL_MODE_SETPLANE DRM_IOWR(0xB7, struct drm_mode_set_plane)
  809. #define DRM_IOCTL_MODE_ADDFB2 DRM_IOWR(0xB8, struct drm_mode_fb_cmd2)
  810. #define DRM_IOCTL_MODE_OBJ_GETPROPERTIES DRM_IOWR(0xB9, struct drm_mode_obj_get_properties)
  811. #define DRM_IOCTL_MODE_OBJ_SETPROPERTY DRM_IOWR(0xBA, struct drm_mode_obj_set_property)
  812. #define DRM_IOCTL_MODE_CURSOR2 DRM_IOWR(0xBB, struct drm_mode_cursor2)
  813. #define DRM_IOCTL_MODE_ATOMIC DRM_IOWR(0xBC, struct drm_mode_atomic)
  814. #define DRM_IOCTL_MODE_CREATEPROPBLOB DRM_IOWR(0xBD, struct drm_mode_create_blob)
  815. #define DRM_IOCTL_MODE_DESTROYPROPBLOB DRM_IOWR(0xBE, struct drm_mode_destroy_blob)
  816. #define DRM_IOCTL_SYNCOBJ_CREATE DRM_IOWR(0xBF, struct drm_syncobj_create)
  817. #define DRM_IOCTL_SYNCOBJ_DESTROY DRM_IOWR(0xC0, struct drm_syncobj_destroy)
  818. #define DRM_IOCTL_SYNCOBJ_HANDLE_TO_FD DRM_IOWR(0xC1, struct drm_syncobj_handle)
  819. #define DRM_IOCTL_SYNCOBJ_FD_TO_HANDLE DRM_IOWR(0xC2, struct drm_syncobj_handle)
  820. #define DRM_IOCTL_SYNCOBJ_WAIT DRM_IOWR(0xC3, struct drm_syncobj_wait)
  821. #define DRM_IOCTL_SYNCOBJ_RESET DRM_IOWR(0xC4, struct drm_syncobj_array)
  822. #define DRM_IOCTL_SYNCOBJ_SIGNAL DRM_IOWR(0xC5, struct drm_syncobj_array)
  823. #define DRM_IOCTL_MODE_CREATE_LEASE DRM_IOWR(0xC6, struct drm_mode_create_lease)
  824. #define DRM_IOCTL_MODE_LIST_LESSEES DRM_IOWR(0xC7, struct drm_mode_list_lessees)
  825. #define DRM_IOCTL_MODE_GET_LEASE DRM_IOWR(0xC8, struct drm_mode_get_lease)
  826. #define DRM_IOCTL_MODE_REVOKE_LEASE DRM_IOWR(0xC9, struct drm_mode_revoke_lease)
  827. #define DRM_IOCTL_SYNCOBJ_TIMELINE_WAIT DRM_IOWR(0xCA, struct drm_syncobj_timeline_wait)
  828. #define DRM_IOCTL_SYNCOBJ_QUERY DRM_IOWR(0xCB, struct drm_syncobj_timeline_array)
  829. #define DRM_IOCTL_SYNCOBJ_TRANSFER DRM_IOWR(0xCC, struct drm_syncobj_transfer)
  830. #define DRM_IOCTL_SYNCOBJ_TIMELINE_SIGNAL DRM_IOWR(0xCD, struct drm_syncobj_timeline_array)
  831. #define DRM_IOCTL_MODE_GETFB2 DRM_IOWR(0xCE, struct drm_mode_fb_cmd2)
  832. /**
  833. * Device specific ioctls should only be in their respective headers
  834. * The device specific ioctl range is from 0x40 to 0x9f.
  835. * Generic IOCTLS restart at 0xA0.
  836. *
  837. * \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and
  838. * drmCommandReadWrite().
  839. */
  840. #define DRM_COMMAND_BASE 0x40
  841. #define DRM_COMMAND_END 0xA0
  842. /**
  843. * Header for events written back to userspace on the drm fd. The
  844. * type defines the type of event, the length specifies the total
  845. * length of the event (including the header), and user_data is
  846. * typically a 64 bit value passed with the ioctl that triggered the
  847. * event. A read on the drm fd will always only return complete
  848. * events, that is, if for example the read buffer is 100 bytes, and
  849. * there are two 64 byte events pending, only one will be returned.
  850. *
  851. * Event types 0 - 0x7fffffff are generic drm events, 0x80000000 and
  852. * up are chipset specific.
  853. */
  854. struct drm_event {
  855. __u32 type;
  856. __u32 length;
  857. };
  858. #define DRM_EVENT_VBLANK 0x01
  859. #define DRM_EVENT_FLIP_COMPLETE 0x02
  860. #define DRM_EVENT_CRTC_SEQUENCE 0x03
  861. struct drm_event_vblank {
  862. struct drm_event base;
  863. __u64 user_data;
  864. __u32 tv_sec;
  865. __u32 tv_usec;
  866. __u32 sequence;
  867. __u32 crtc_id; /* 0 on older kernels that do not support this */
  868. };
  869. /* Event delivered at sequence. Time stamp marks when the first pixel
  870. * of the refresh cycle leaves the display engine for the display
  871. */
  872. struct drm_event_crtc_sequence {
  873. struct drm_event base;
  874. __u64 user_data;
  875. __s64 time_ns;
  876. __u64 sequence;
  877. };
  878. /* typedef area */
  879. typedef struct drm_clip_rect drm_clip_rect_t;
  880. typedef struct drm_drawable_info drm_drawable_info_t;
  881. typedef struct drm_tex_region drm_tex_region_t;
  882. typedef struct drm_hw_lock drm_hw_lock_t;
  883. typedef struct drm_version drm_version_t;
  884. typedef struct drm_unique drm_unique_t;
  885. typedef struct drm_list drm_list_t;
  886. typedef struct drm_block drm_block_t;
  887. typedef struct drm_control drm_control_t;
  888. typedef enum drm_map_type drm_map_type_t;
  889. typedef enum drm_map_flags drm_map_flags_t;
  890. typedef struct drm_ctx_priv_map drm_ctx_priv_map_t;
  891. typedef struct drm_map drm_map_t;
  892. typedef struct drm_client drm_client_t;
  893. typedef enum drm_stat_type drm_stat_type_t;
  894. typedef struct drm_stats drm_stats_t;
  895. typedef enum drm_lock_flags drm_lock_flags_t;
  896. typedef struct drm_lock drm_lock_t;
  897. typedef enum drm_dma_flags drm_dma_flags_t;
  898. typedef struct drm_buf_desc drm_buf_desc_t;
  899. typedef struct drm_buf_info drm_buf_info_t;
  900. typedef struct drm_buf_free drm_buf_free_t;
  901. typedef struct drm_buf_pub drm_buf_pub_t;
  902. typedef struct drm_buf_map drm_buf_map_t;
  903. typedef struct drm_dma drm_dma_t;
  904. typedef union drm_wait_vblank drm_wait_vblank_t;
  905. typedef struct drm_agp_mode drm_agp_mode_t;
  906. typedef enum drm_ctx_flags drm_ctx_flags_t;
  907. typedef struct drm_ctx drm_ctx_t;
  908. typedef struct drm_ctx_res drm_ctx_res_t;
  909. typedef struct drm_draw drm_draw_t;
  910. typedef struct drm_update_draw drm_update_draw_t;
  911. typedef struct drm_auth drm_auth_t;
  912. typedef struct drm_irq_busid drm_irq_busid_t;
  913. typedef enum drm_vblank_seq_type drm_vblank_seq_type_t;
  914. typedef struct drm_agp_buffer drm_agp_buffer_t;
  915. typedef struct drm_agp_binding drm_agp_binding_t;
  916. typedef struct drm_agp_info drm_agp_info_t;
  917. typedef struct drm_scatter_gather drm_scatter_gather_t;
  918. typedef struct drm_set_version drm_set_version_t;
  919. #if defined(__cplusplus)
  920. }
  921. #endif
  922. #endif