platform.c 5.1 KB

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  1. /*
  2. * SPDX-License-Identifier: BSD-2-Clause
  3. *
  4. * Copyright (c) Nuclei Corporation or its affiliates.
  5. *
  6. * Authors:
  7. * lujun <lujun@nucleisys.com>
  8. * hqfang <578567190@qq.com>
  9. */
  10. #include <libfdt.h>
  11. #include <sbi/riscv_asm.h>
  12. #include <sbi/riscv_io.h>
  13. #include <sbi/riscv_encoding.h>
  14. #include <sbi/sbi_console.h>
  15. #include <sbi/sbi_const.h>
  16. #include <sbi/sbi_platform.h>
  17. #include <sbi/sbi_system.h>
  18. #include <sbi_utils/fdt/fdt_fixup.h>
  19. #include <sbi_utils/irqchip/plic.h>
  20. #include <sbi_utils/serial/sifive-uart.h>
  21. #include <sbi_utils/sys/clint.h>
  22. /* clang-format off */
  23. #define UX600_HART_COUNT 1
  24. #define UX600_TIMER_FREQ 32768
  25. /* Nuclei timer base address */
  26. #define UX600_NUCLEI_TIMER_ADDR 0x2000000
  27. #define UX600_NUCLEI_TIMER_MSFTRST_OFS 0xFF0
  28. #define UX600_NUCLEI_TIMER_MSFTRST_KEY 0x80000A5F
  29. /* The clint compatiable timer offset is 0x1000 against nuclei timer */
  30. #define UX600_CLINT_TIMER_ADDR (UX600_NUCLEI_TIMER_ADDR + 0x1000)
  31. #define UX600_PLIC_ADDR 0x8000000
  32. #define UX600_PLIC_NUM_SOURCES 0x35
  33. #define UX600_PLIC_NUM_PRIORITIES 7
  34. #define UX600_UART0_ADDR 0x10013000
  35. #define UX600_UART1_ADDR 0x10023000
  36. #define UX600_DEBUG_UART UX600_UART0_ADDR
  37. #ifndef UX600_UART_BAUDRATE
  38. #define UX600_UART_BAUDRATE 57600
  39. #endif
  40. #define UX600_GPIO_ADDR 0x10012000
  41. #define UX600_GPIO_IOF_EN_OFS 0x38
  42. #define UX600_GPIO_IOF_SEL_OFS 0x3C
  43. #define UX600_GPIO_IOF_UART0_MASK 0x00030000
  44. #define UX600_TIMER_VALUE() readl((void *)UX600_NUCLEI_TIMER_ADDR)
  45. /* clang-format on */
  46. static u32 ux600_clk_freq = 8000000;
  47. static struct plic_data plic = {
  48. .addr = UX600_PLIC_ADDR,
  49. .num_src = UX600_PLIC_NUM_SOURCES,
  50. };
  51. static struct clint_data clint = {
  52. .addr = UX600_CLINT_TIMER_ADDR,
  53. .first_hartid = 0,
  54. .hart_count = UX600_HART_COUNT,
  55. .has_64bit_mmio = TRUE,
  56. };
  57. static u32 measure_cpu_freq(u32 n)
  58. {
  59. u32 start_mtime, delta_mtime;
  60. u32 mtime_freq = UX600_TIMER_FREQ;
  61. u32 tmp = (u32)UX600_TIMER_VALUE();
  62. u32 start_mcycle, delta_mcycle, freq;
  63. /* Don't start measuring until we see an mtime tick */
  64. do {
  65. start_mtime = (u32)UX600_TIMER_VALUE();
  66. } while (start_mtime == tmp);
  67. start_mcycle = csr_read(mcycle);
  68. do {
  69. delta_mtime = (u32)UX600_TIMER_VALUE() - start_mtime;
  70. } while (delta_mtime < n);
  71. delta_mcycle = csr_read(mcycle) - start_mcycle;
  72. freq = (delta_mcycle / delta_mtime) * mtime_freq
  73. + ((delta_mcycle % delta_mtime) * mtime_freq) / delta_mtime;
  74. return freq;
  75. }
  76. static u32 ux600_get_clk_freq(void)
  77. {
  78. u32 cpu_freq;
  79. /* warm up */
  80. measure_cpu_freq(1);
  81. /* measure for real */
  82. cpu_freq = measure_cpu_freq(100);
  83. return cpu_freq;
  84. }
  85. static int ux600_system_reset_check(u32 type, u32 reason)
  86. {
  87. return 1;
  88. }
  89. static void ux600_system_reset(u32 type, u32 reason)
  90. {
  91. /* Reset system using MSFTRST register in Nuclei Timer. */
  92. writel(UX600_NUCLEI_TIMER_MSFTRST_KEY, (void *)(UX600_NUCLEI_TIMER_ADDR
  93. + UX600_NUCLEI_TIMER_MSFTRST_OFS));
  94. while(1);
  95. }
  96. static struct sbi_system_reset_device ux600_reset = {
  97. .name = "nuclei_ux600_reset",
  98. .system_reset_check = ux600_system_reset_check,
  99. .system_reset = ux600_system_reset
  100. };
  101. static int ux600_early_init(bool cold_boot)
  102. {
  103. u32 regval;
  104. if (cold_boot)
  105. sbi_system_reset_set_device(&ux600_reset);
  106. /* Measure CPU Frequency using Timer */
  107. ux600_clk_freq = ux600_get_clk_freq();
  108. /* Init GPIO UART pinmux */
  109. regval = readl((void *)(UX600_GPIO_ADDR + UX600_GPIO_IOF_SEL_OFS)) &
  110. ~UX600_GPIO_IOF_UART0_MASK;
  111. writel(regval, (void *)(UX600_GPIO_ADDR + UX600_GPIO_IOF_SEL_OFS));
  112. regval = readl((void *)(UX600_GPIO_ADDR + UX600_GPIO_IOF_EN_OFS)) |
  113. UX600_GPIO_IOF_UART0_MASK;
  114. writel(regval, (void *)(UX600_GPIO_ADDR + UX600_GPIO_IOF_EN_OFS));
  115. return 0;
  116. }
  117. static void ux600_modify_dt(void *fdt)
  118. {
  119. fdt_fixups(fdt);
  120. }
  121. static int ux600_final_init(bool cold_boot)
  122. {
  123. void *fdt;
  124. if (!cold_boot)
  125. return 0;
  126. fdt = sbi_scratch_thishart_arg1_ptr();
  127. ux600_modify_dt(fdt);
  128. return 0;
  129. }
  130. static int ux600_console_init(void)
  131. {
  132. return sifive_uart_init(UX600_DEBUG_UART, ux600_clk_freq,
  133. UX600_UART_BAUDRATE);
  134. }
  135. static int ux600_irqchip_init(bool cold_boot)
  136. {
  137. int rc;
  138. u32 hartid = current_hartid();
  139. if (cold_boot) {
  140. rc = plic_cold_irqchip_init(&plic);
  141. if (rc)
  142. return rc;
  143. }
  144. return plic_warm_irqchip_init(&plic, (hartid) ? (2 * hartid - 1) : 0,
  145. (hartid) ? (2 * hartid) : -1);
  146. }
  147. static int ux600_ipi_init(bool cold_boot)
  148. {
  149. int rc;
  150. if (cold_boot) {
  151. rc = clint_cold_ipi_init(&clint);
  152. if (rc)
  153. return rc;
  154. }
  155. return clint_warm_ipi_init();
  156. }
  157. static int ux600_timer_init(bool cold_boot)
  158. {
  159. int rc;
  160. if (cold_boot) {
  161. rc = clint_cold_timer_init(&clint, NULL);
  162. if (rc)
  163. return rc;
  164. }
  165. return clint_warm_timer_init();
  166. }
  167. const struct sbi_platform_operations platform_ops = {
  168. .early_init = ux600_early_init,
  169. .final_init = ux600_final_init,
  170. .console_init = ux600_console_init,
  171. .irqchip_init = ux600_irqchip_init,
  172. .ipi_init = ux600_ipi_init,
  173. .timer_init = ux600_timer_init,
  174. };
  175. const struct sbi_platform platform = {
  176. .opensbi_version = OPENSBI_VERSION,
  177. .platform_version = SBI_PLATFORM_VERSION(0x0U, 0x01U),
  178. .name = "Nuclei UX600",
  179. .features = SBI_PLATFORM_DEFAULT_FEATURES,
  180. .hart_count = UX600_HART_COUNT,
  181. .hart_stack_size = SBI_PLATFORM_DEFAULT_HART_STACK_SIZE,
  182. .platform_ops_addr = (unsigned long)&platform_ops
  183. };