sbi_expected_trap.S 1.4 KB

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  1. /*
  2. * SPDX-License-Identifier: BSD-2-Clause
  3. *
  4. * Copyright (c) 2020 Western Digital Corporation or its affiliates.
  5. *
  6. * Authors:
  7. * Anup Patel <anup.patel@wdc.com>
  8. */
  9. #include <sbi/riscv_asm.h>
  10. #include <sbi/sbi_trap.h>
  11. /*
  12. * We assume that faulting instruction is is 4-byte long and blindly
  13. * increment SEPC by 4.
  14. *
  15. * The trap info will be saved as follows:
  16. * A3 <- pointer struct sbi_trap_info
  17. * A4 <- temporary
  18. */
  19. .align 3
  20. .global __sbi_expected_trap
  21. __sbi_expected_trap:
  22. /* Without H-extension so, MTVAL2 and MTINST CSRs not available */
  23. csrr a4, CSR_MEPC
  24. REG_S a4, SBI_TRAP_INFO_OFFSET(epc)(a3)
  25. csrr a4, CSR_MCAUSE
  26. REG_S a4, SBI_TRAP_INFO_OFFSET(cause)(a3)
  27. csrr a4, CSR_MTVAL
  28. REG_S a4, SBI_TRAP_INFO_OFFSET(tval)(a3)
  29. REG_S zero, SBI_TRAP_INFO_OFFSET(tval2)(a3)
  30. REG_S zero, SBI_TRAP_INFO_OFFSET(tinst)(a3)
  31. csrr a4, CSR_MEPC
  32. addi a4, a4, 4
  33. csrw CSR_MEPC, a4
  34. mret
  35. .align 3
  36. .global __sbi_expected_trap_hext
  37. __sbi_expected_trap_hext:
  38. /* With H-extension so, MTVAL2 and MTINST CSRs available */
  39. csrr a4, CSR_MEPC
  40. REG_S a4, SBI_TRAP_INFO_OFFSET(epc)(a3)
  41. csrr a4, CSR_MCAUSE
  42. REG_S a4, SBI_TRAP_INFO_OFFSET(cause)(a3)
  43. csrr a4, CSR_MTVAL
  44. REG_S a4, SBI_TRAP_INFO_OFFSET(tval)(a3)
  45. csrr a4, CSR_MTVAL2
  46. REG_S a4, SBI_TRAP_INFO_OFFSET(tval2)(a3)
  47. csrr a4, CSR_MTINST
  48. REG_S a4, SBI_TRAP_INFO_OFFSET(tinst)(a3)
  49. csrr a4, CSR_MEPC
  50. addi a4, a4, 4
  51. csrw CSR_MEPC, a4
  52. mret