sbi_csr_detect.h 1.6 KB

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  1. /*
  2. * SPDX-License-Identifier: BSD-2-Clause
  3. *
  4. * Copyright (c) 2020 Western Digital Corporation or its affiliates.
  5. *
  6. * Authors:
  7. * Atish Patra <atish.patra@wdc.com>
  8. */
  9. #ifndef __SBI_CSR_DETECT__H
  10. #define __SBI_CSR_DETECT__H
  11. #include <sbi/riscv_encoding.h>
  12. #include <sbi/sbi_hart.h>
  13. #include <sbi/sbi_trap.h>
  14. #define csr_read_allowed(csr_num, trap) \
  15. ({ \
  16. register ulong tinfo asm("a3") = (ulong)trap; \
  17. register ulong ttmp asm("a4"); \
  18. register ulong mtvec = sbi_hart_expected_trap_addr(); \
  19. register ulong ret = 0; \
  20. ((struct sbi_trap_info *)(trap))->cause = 0; \
  21. asm volatile( \
  22. "add %[ttmp], %[tinfo], zero\n" \
  23. "csrrw %[mtvec], " STR(CSR_MTVEC) ", %[mtvec]\n" \
  24. "csrr %[ret], %[csr]\n" \
  25. "csrw " STR(CSR_MTVEC) ", %[mtvec]" \
  26. : [mtvec] "+&r"(mtvec), [tinfo] "+&r"(tinfo), \
  27. [ttmp] "+&r"(ttmp), [ret] "=&r" (ret) \
  28. : [csr] "i" (csr_num) \
  29. : "memory"); \
  30. ret; \
  31. }) \
  32. #define csr_write_allowed(csr_num, trap, value) \
  33. ({ \
  34. register ulong tinfo asm("a3") = (ulong)trap; \
  35. register ulong ttmp asm("a4"); \
  36. register ulong mtvec = sbi_hart_expected_trap_addr(); \
  37. ((struct sbi_trap_info *)(trap))->cause = 0; \
  38. asm volatile( \
  39. "add %[ttmp], %[tinfo], zero\n" \
  40. "csrrw %[mtvec], " STR(CSR_MTVEC) ", %[mtvec]\n" \
  41. "csrw %[csr], %[val]\n" \
  42. "csrw " STR(CSR_MTVEC) ", %[mtvec]" \
  43. : [mtvec] "+&r"(mtvec), \
  44. [tinfo] "+&r"(tinfo), [ttmp] "+&r"(ttmp) \
  45. : [csr] "i" (csr_num), [val] "r" (value) \
  46. : "memory"); \
  47. }) \
  48. #endif