riscv_io.h 3.1 KB

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  1. /*
  2. * SPDX-License-Identifier: BSD-2-Clause
  3. *
  4. * Copyright (c) 2019 Western Digital Corporation or its affiliates.
  5. *
  6. * Authors:
  7. * Anup Patel <anup.patel@wdc.com>
  8. */
  9. #ifndef __RISCV_IO_H__
  10. #define __RISCV_IO_H__
  11. #include <sbi/riscv_barrier.h>
  12. #include <sbi/sbi_types.h>
  13. static inline void __raw_writeb(u8 val, volatile void *addr)
  14. {
  15. asm volatile("sb %0, 0(%1)" : : "r"(val), "r"(addr));
  16. }
  17. static inline void __raw_writew(u16 val, volatile void *addr)
  18. {
  19. asm volatile("sh %0, 0(%1)" : : "r"(val), "r"(addr));
  20. }
  21. static inline void __raw_writel(u32 val, volatile void *addr)
  22. {
  23. asm volatile("sw %0, 0(%1)" : : "r"(val), "r"(addr));
  24. }
  25. #if __riscv_xlen != 32
  26. static inline void __raw_writeq(u64 val, volatile void *addr)
  27. {
  28. asm volatile("sd %0, 0(%1)" : : "r"(val), "r"(addr));
  29. }
  30. #endif
  31. static inline u8 __raw_readb(const volatile void *addr)
  32. {
  33. u8 val;
  34. asm volatile("lb %0, 0(%1)" : "=r"(val) : "r"(addr));
  35. return val;
  36. }
  37. static inline u16 __raw_readw(const volatile void *addr)
  38. {
  39. u16 val;
  40. asm volatile("lh %0, 0(%1)" : "=r"(val) : "r"(addr));
  41. return val;
  42. }
  43. static inline u32 __raw_readl(const volatile void *addr)
  44. {
  45. u32 val;
  46. asm volatile("lw %0, 0(%1)" : "=r"(val) : "r"(addr));
  47. return val;
  48. }
  49. #if __riscv_xlen != 32
  50. static inline u64 __raw_readq(const volatile void *addr)
  51. {
  52. u64 val;
  53. asm volatile("ld %0, 0(%1)" : "=r"(val) : "r"(addr));
  54. return val;
  55. }
  56. #endif
  57. /* FIXME: These are now the same as asm-generic */
  58. /* clang-format off */
  59. #define __io_rbr() do {} while (0)
  60. #define __io_rar() do {} while (0)
  61. #define __io_rbw() do {} while (0)
  62. #define __io_raw() do {} while (0)
  63. #define readb_relaxed(c) ({ u8 __v; __io_rbr(); __v = __raw_readb(c); __io_rar(); __v; })
  64. #define readw_relaxed(c) ({ u16 __v; __io_rbr(); __v = __raw_readw(c); __io_rar(); __v; })
  65. #define readl_relaxed(c) ({ u32 __v; __io_rbr(); __v = __raw_readl(c); __io_rar(); __v; })
  66. #define writeb_relaxed(v,c) ({ __io_rbw(); __raw_writeb((v),(c)); __io_raw(); })
  67. #define writew_relaxed(v,c) ({ __io_rbw(); __raw_writew((v),(c)); __io_raw(); })
  68. #define writel_relaxed(v,c) ({ __io_rbw(); __raw_writel((v),(c)); __io_raw(); })
  69. #if __riscv_xlen != 32
  70. #define readq_relaxed(c) ({ u64 __v; __io_rbr(); __v = __raw_readq(c); __io_rar(); __v; })
  71. #define writeq_relaxed(v,c) ({ __io_rbw(); __raw_writeq((v),(c)); __io_raw(); })
  72. #endif
  73. #define __io_br() do {} while (0)
  74. #define __io_ar() __asm__ __volatile__ ("fence i,r" : : : "memory");
  75. #define __io_bw() __asm__ __volatile__ ("fence w,o" : : : "memory");
  76. #define __io_aw() do {} while (0)
  77. #define readb(c) ({ u8 __v; __io_br(); __v = __raw_readb(c); __io_ar(); __v; })
  78. #define readw(c) ({ u16 __v; __io_br(); __v = __raw_readw(c); __io_ar(); __v; })
  79. #define readl(c) ({ u32 __v; __io_br(); __v = __raw_readl(c); __io_ar(); __v; })
  80. #define writeb(v,c) ({ __io_bw(); __raw_writeb((v),(c)); __io_aw(); })
  81. #define writew(v,c) ({ __io_bw(); __raw_writew((v),(c)); __io_aw(); })
  82. #define writel(v,c) ({ __io_bw(); __raw_writel((v),(c)); __io_aw(); })
  83. #if __riscv_xlen != 32
  84. #define readq(c) ({ u64 __v; __io_br(); __v = __raw_readq(c); __io_ar(); __v; })
  85. #define writeq(v,c) ({ __io_bw(); __raw_writeq((v),(c)); __io_aw(); })
  86. #endif
  87. /* clang-format on */
  88. #endif