riscv_barrier.h 1.3 KB

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  1. /*
  2. * SPDX-License-Identifier: BSD-2-Clause
  3. *
  4. * Copyright (c) 2019 Western Digital Corporation or its affiliates.
  5. *
  6. * Authors:
  7. * Anup Patel <anup.patel@wdc.com>
  8. */
  9. #ifndef __RISCV_BARRIER_H__
  10. #define __RISCV_BARRIER_H__
  11. /* clang-format off */
  12. #define RISCV_ACQUIRE_BARRIER "\tfence r , rw\n"
  13. #define RISCV_RELEASE_BARRIER "\tfence rw, w\n"
  14. #define RISCV_FENCE(p, s) \
  15. __asm__ __volatile__ ("fence " #p "," #s : : : "memory")
  16. #define RISCV_FENCE_I \
  17. __asm__ __volatile__ ("fence.i" : : : "memory")
  18. /* Read & Write Memory barrier */
  19. #define mb() RISCV_FENCE(iorw,iorw)
  20. /* Read Memory barrier */
  21. #define rmb() RISCV_FENCE(ir,ir)
  22. /* Write Memory barrier */
  23. #define wmb() RISCV_FENCE(ow,ow)
  24. /* SMP Read & Write Memory barrier */
  25. #define smp_mb() RISCV_FENCE(rw,rw)
  26. /* SMP Read Memory barrier */
  27. #define smp_rmb() RISCV_FENCE(r,r)
  28. /* SMP Write Memory barrier */
  29. #define smp_wmb() RISCV_FENCE(w,w)
  30. /* CPU relax for busy loop */
  31. #define cpu_relax() asm volatile ("" : : : "memory")
  32. /* clang-format on */
  33. #define __smp_store_release(p, v) \
  34. do { \
  35. RISCV_FENCE(rw, w); \
  36. *(p) = (v); \
  37. } while (0)
  38. #define __smp_load_acquire(p) \
  39. ({ \
  40. typeof(*p) ___p1 = *(p); \
  41. RISCV_FENCE(r, rw); \
  42. ___p1; \
  43. })
  44. #endif