test_head.S 1.5 KB

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  1. /*
  2. * SPDX-License-Identifier: BSD-2-Clause
  3. *
  4. * Copyright (c) 2019 Western Digital Corporation or its affiliates.
  5. *
  6. * Authors:
  7. * Anup Patel <anup.patel@wdc.com>
  8. */
  9. #include <sbi/riscv_encoding.h>
  10. #define __ASM_STR(x) x
  11. #if __riscv_xlen == 64
  12. #define __REG_SEL(a, b) __ASM_STR(a)
  13. #define RISCV_PTR .dword
  14. #elif __riscv_xlen == 32
  15. #define __REG_SEL(a, b) __ASM_STR(b)
  16. #define RISCV_PTR .word
  17. #else
  18. #error "Unexpected __riscv_xlen"
  19. #endif
  20. #define REG_L __REG_SEL(ld, lw)
  21. #define REG_S __REG_SEL(sd, sw)
  22. .section .entry, "ax", %progbits
  23. .align 3
  24. .globl _start
  25. _start:
  26. /* Pick one hart to run the main boot sequence */
  27. lla a3, _hart_lottery
  28. li a2, 1
  29. amoadd.w a3, a2, (a3)
  30. bnez a3, _start_hang
  31. /* Save a0 and a1 */
  32. lla a3, _boot_a0
  33. REG_S a0, 0(a3)
  34. lla a3, _boot_a1
  35. REG_S a1, 0(a3)
  36. /* Zero-out BSS */
  37. lla a4, _bss_start
  38. lla a5, _bss_end
  39. _bss_zero:
  40. REG_S zero, (a4)
  41. add a4, a4, __SIZEOF_POINTER__
  42. blt a4, a5, _bss_zero
  43. _start_warm:
  44. /* Disable and clear all interrupts */
  45. csrw CSR_SIE, zero
  46. csrw CSR_SIP, zero
  47. /* Setup exception vectors */
  48. lla a3, _start_hang
  49. csrw CSR_STVEC, a3
  50. /* Setup stack */
  51. lla a3, _payload_end
  52. li a4, 0x2000
  53. add sp, a3, a4
  54. /* Jump to C main */
  55. lla a3, _boot_a0
  56. REG_L a0, 0(a3)
  57. lla a3, _boot_a1
  58. REG_L a1, 0(a3)
  59. call test_main
  60. /* We don't expect to reach here hence just hang */
  61. j _start_hang
  62. .section .entry, "ax", %progbits
  63. .align 3
  64. .globl _start_hang
  65. _start_hang:
  66. wfi
  67. j _start_hang
  68. .section .entry, "ax", %progbits
  69. .align 3
  70. _hart_lottery:
  71. RISCV_PTR 0
  72. _boot_a0:
  73. RISCV_PTR 0
  74. _boot_a1:
  75. RISCV_PTR 0