fw_base.S 18 KB

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  1. /*
  2. * SPDX-License-Identifier: BSD-2-Clause
  3. *
  4. * Copyright (c) 2019 Western Digital Corporation or its affiliates.
  5. *
  6. * Authors:
  7. * Anup Patel <anup.patel@wdc.com>
  8. */
  9. #include <sbi/riscv_asm.h>
  10. #include <sbi/riscv_encoding.h>
  11. #include <sbi/riscv_elf.h>
  12. #include <sbi/sbi_platform.h>
  13. #include <sbi/sbi_scratch.h>
  14. #include <sbi/sbi_trap.h>
  15. #define BOOT_STATUS_RELOCATE_DONE 1
  16. #define BOOT_STATUS_BOOT_HART_DONE 2
  17. .macro MOV_3R __d0, __s0, __d1, __s1, __d2, __s2
  18. add \__d0, \__s0, zero
  19. add \__d1, \__s1, zero
  20. add \__d2, \__s2, zero
  21. .endm
  22. .macro MOV_5R __d0, __s0, __d1, __s1, __d2, __s2, __d3, __s3, __d4, __s4
  23. add \__d0, \__s0, zero
  24. add \__d1, \__s1, zero
  25. add \__d2, \__s2, zero
  26. add \__d3, \__s3, zero
  27. add \__d4, \__s4, zero
  28. .endm
  29. /*
  30. * If __start_reg <= __check_reg and __check_reg < __end_reg then
  31. * jump to __pass
  32. */
  33. .macro BRANGE __start_reg, __end_reg, __check_reg, __jump_lable
  34. blt \__check_reg, \__start_reg, 999f
  35. bge \__check_reg, \__end_reg, 999f
  36. j \__jump_lable
  37. 999:
  38. .endm
  39. .section .entry, "ax", %progbits
  40. .align 3
  41. .globl _start
  42. .globl _start_warm
  43. _start:
  44. /* Find preferred boot HART id */
  45. MOV_3R s0, a0, s1, a1, s2, a2
  46. call fw_boot_hart
  47. add a6, a0, zero
  48. MOV_3R a0, s0, a1, s1, a2, s2
  49. li a7, -1
  50. beq a6, a7, _try_lottery
  51. /* Jump to relocation wait loop if we are not boot hart */
  52. bne a0, a6, _wait_relocate_copy_done
  53. _try_lottery:
  54. /* Jump to relocation wait loop if we don't get relocation lottery */
  55. lla a6, _relocate_lottery
  56. li a7, 1
  57. amoadd.w a6, a7, (a6)
  58. bnez a6, _wait_relocate_copy_done
  59. /* Save load address */
  60. lla t0, _load_start
  61. lla t1, _start
  62. REG_S t1, 0(t0)
  63. #ifdef FW_PIC
  64. /* relocate the global table content */
  65. lla t0, _link_start
  66. REG_L t0, 0(t0)
  67. /* t1 shall has the address of _start */
  68. sub t2, t1, t0
  69. lla t3, _runtime_offset
  70. REG_S t2, (t3)
  71. lla t0, __rel_dyn_start
  72. lla t1, __rel_dyn_end
  73. beq t0, t1, _relocate_done
  74. j 5f
  75. 2:
  76. REG_L t5, -(REGBYTES*2)(t0) /* t5 <-- relocation info:type */
  77. li t3, R_RISCV_RELATIVE /* reloc type R_RISCV_RELATIVE */
  78. bne t5, t3, 3f
  79. REG_L t3, -(REGBYTES*3)(t0)
  80. REG_L t5, -(REGBYTES)(t0) /* t5 <-- addend */
  81. add t5, t5, t2
  82. add t3, t3, t2
  83. REG_S t5, 0(t3) /* store runtime address to the GOT entry */
  84. j 5f
  85. 3:
  86. lla t4, __dyn_sym_start
  87. 4:
  88. REG_L t5, -(REGBYTES*2)(t0) /* t5 <-- relocation info:type */
  89. srli t6, t5, SYM_INDEX /* t6 <--- sym table index */
  90. andi t5, t5, 0xFF /* t5 <--- relocation type */
  91. li t3, RELOC_TYPE
  92. bne t5, t3, 5f
  93. /* address R_RISCV_64 or R_RISCV_32 cases*/
  94. REG_L t3, -(REGBYTES*3)(t0)
  95. li t5, SYM_SIZE
  96. mul t6, t6, t5
  97. add s5, t4, t6
  98. REG_L t6, -(REGBYTES)(t0) /* t0 <-- addend */
  99. REG_L t5, REGBYTES(s5)
  100. add t5, t5, t6
  101. add t5, t5, t2 /* t5 <-- location to fix up in RAM */
  102. add t3, t3, t2 /* t3 <-- location to fix up in RAM */
  103. REG_S t5, 0(t3) /* store runtime address to the variable */
  104. 5:
  105. addi t0, t0, (REGBYTES*3)
  106. ble t0, t1, 2b
  107. j _relocate_done
  108. _wait_relocate_copy_done:
  109. j _wait_for_boot_hart
  110. #else
  111. /* Relocate if load address != link address */
  112. _relocate:
  113. lla t0, _link_start
  114. REG_L t0, 0(t0)
  115. lla t1, _link_end
  116. REG_L t1, 0(t1)
  117. lla t2, _load_start
  118. REG_L t2, 0(t2)
  119. sub t3, t1, t0
  120. add t3, t3, t2
  121. beq t0, t2, _relocate_done
  122. lla t4, _relocate_done
  123. sub t4, t4, t2
  124. add t4, t4, t0
  125. blt t2, t0, _relocate_copy_to_upper
  126. _relocate_copy_to_lower:
  127. ble t1, t2, _relocate_copy_to_lower_loop
  128. lla t3, _relocate_lottery
  129. BRANGE t2, t1, t3, _start_hang
  130. lla t3, _boot_status
  131. BRANGE t2, t1, t3, _start_hang
  132. lla t3, _relocate
  133. lla t5, _relocate_done
  134. BRANGE t2, t1, t3, _start_hang
  135. BRANGE t2, t1, t5, _start_hang
  136. BRANGE t3, t5, t2, _start_hang
  137. _relocate_copy_to_lower_loop:
  138. REG_L t3, 0(t2)
  139. REG_S t3, 0(t0)
  140. add t0, t0, __SIZEOF_POINTER__
  141. add t2, t2, __SIZEOF_POINTER__
  142. blt t0, t1, _relocate_copy_to_lower_loop
  143. jr t4
  144. _relocate_copy_to_upper:
  145. ble t3, t0, _relocate_copy_to_upper_loop
  146. lla t2, _relocate_lottery
  147. BRANGE t0, t3, t2, _start_hang
  148. lla t2, _boot_status
  149. BRANGE t0, t3, t2, _start_hang
  150. lla t2, _relocate
  151. lla t5, _relocate_done
  152. BRANGE t0, t3, t2, _start_hang
  153. BRANGE t0, t3, t5, _start_hang
  154. BRANGE t2, t5, t0, _start_hang
  155. _relocate_copy_to_upper_loop:
  156. add t3, t3, -__SIZEOF_POINTER__
  157. add t1, t1, -__SIZEOF_POINTER__
  158. REG_L t2, 0(t3)
  159. REG_S t2, 0(t1)
  160. blt t0, t1, _relocate_copy_to_upper_loop
  161. jr t4
  162. _wait_relocate_copy_done:
  163. lla t0, _start
  164. lla t1, _link_start
  165. REG_L t1, 0(t1)
  166. beq t0, t1, _wait_for_boot_hart
  167. lla t2, _boot_status
  168. lla t3, _wait_for_boot_hart
  169. sub t3, t3, t0
  170. add t3, t3, t1
  171. 1:
  172. /* waitting for relocate copy done (_boot_status == 1) */
  173. li t4, BOOT_STATUS_RELOCATE_DONE
  174. REG_L t5, 0(t2)
  175. /* Reduce the bus traffic so that boot hart may proceed faster */
  176. nop
  177. nop
  178. nop
  179. bgt t4, t5, 1b
  180. jr t3
  181. #endif
  182. _relocate_done:
  183. /*
  184. * Mark relocate copy done
  185. * Use _boot_status copy relative to the load address
  186. */
  187. lla t0, _boot_status
  188. #ifndef FW_PIC
  189. lla t1, _link_start
  190. REG_L t1, 0(t1)
  191. lla t2, _load_start
  192. REG_L t2, 0(t2)
  193. sub t0, t0, t1
  194. add t0, t0, t2
  195. #endif
  196. li t1, BOOT_STATUS_RELOCATE_DONE
  197. REG_S t1, 0(t0)
  198. fence rw, rw
  199. /* At this point we are running from link address */
  200. /* Reset all registers for boot HART */
  201. li ra, 0
  202. call _reset_regs
  203. /* Zero-out BSS */
  204. lla s4, _bss_start
  205. lla s5, _bss_end
  206. _bss_zero:
  207. REG_S zero, (s4)
  208. add s4, s4, __SIZEOF_POINTER__
  209. blt s4, s5, _bss_zero
  210. /* Setup temporary trap handler */
  211. lla s4, _start_hang
  212. csrw CSR_MTVEC, s4
  213. /* Setup temporary stack */
  214. lla s4, _fw_end
  215. li s5, (SBI_SCRATCH_SIZE * 2)
  216. add sp, s4, s5
  217. /* Allow main firmware to save info */
  218. MOV_5R s0, a0, s1, a1, s2, a2, s3, a3, s4, a4
  219. call fw_save_info
  220. MOV_5R a0, s0, a1, s1, a2, s2, a3, s3, a4, s4
  221. #ifdef FW_FDT_PATH
  222. /* Override previous arg1 */
  223. lla a1, fw_fdt_bin
  224. #endif
  225. /*
  226. * Initialize platform
  227. * Note: The a0 to a4 registers passed to the
  228. * firmware are parameters to this function.
  229. */
  230. MOV_5R s0, a0, s1, a1, s2, a2, s3, a3, s4, a4
  231. call fw_platform_init
  232. add t0, a0, zero
  233. MOV_5R a0, s0, a1, s1, a2, s2, a3, s3, a4, s4
  234. add a1, t0, zero
  235. /* Preload HART details
  236. * s7 -> HART Count
  237. * s8 -> HART Stack Size
  238. */
  239. lla a4, platform
  240. #if __riscv_xlen == 64
  241. lwu s7, SBI_PLATFORM_HART_COUNT_OFFSET(a4)
  242. lwu s8, SBI_PLATFORM_HART_STACK_SIZE_OFFSET(a4)
  243. #else
  244. lw s7, SBI_PLATFORM_HART_COUNT_OFFSET(a4)
  245. lw s8, SBI_PLATFORM_HART_STACK_SIZE_OFFSET(a4)
  246. #endif
  247. /* Setup scratch space for all the HARTs*/
  248. lla tp, _fw_end
  249. mul a5, s7, s8
  250. add tp, tp, a5
  251. /* Keep a copy of tp */
  252. add t3, tp, zero
  253. /* Counter */
  254. li t2, 1
  255. /* hartid 0 is mandated by ISA */
  256. li t1, 0
  257. _scratch_init:
  258. add tp, t3, zero
  259. mul a5, s8, t1
  260. sub tp, tp, a5
  261. li a5, SBI_SCRATCH_SIZE
  262. sub tp, tp, a5
  263. /* Initialize scratch space */
  264. /* Store fw_start and fw_size in scratch space */
  265. lla a4, _fw_start
  266. lla a5, _fw_end
  267. mul t0, s7, s8
  268. add a5, a5, t0
  269. sub a5, a5, a4
  270. REG_S a4, SBI_SCRATCH_FW_START_OFFSET(tp)
  271. REG_S a5, SBI_SCRATCH_FW_SIZE_OFFSET(tp)
  272. /* Store next arg1 in scratch space */
  273. MOV_3R s0, a0, s1, a1, s2, a2
  274. call fw_next_arg1
  275. REG_S a0, SBI_SCRATCH_NEXT_ARG1_OFFSET(tp)
  276. MOV_3R a0, s0, a1, s1, a2, s2
  277. /* Store next address in scratch space */
  278. MOV_3R s0, a0, s1, a1, s2, a2
  279. call fw_next_addr
  280. REG_S a0, SBI_SCRATCH_NEXT_ADDR_OFFSET(tp)
  281. MOV_3R a0, s0, a1, s1, a2, s2
  282. /* Store next mode in scratch space */
  283. MOV_3R s0, a0, s1, a1, s2, a2
  284. call fw_next_mode
  285. REG_S a0, SBI_SCRATCH_NEXT_MODE_OFFSET(tp)
  286. MOV_3R a0, s0, a1, s1, a2, s2
  287. /* Store warm_boot address in scratch space */
  288. lla a4, _start_warm
  289. REG_S a4, SBI_SCRATCH_WARMBOOT_ADDR_OFFSET(tp)
  290. /* Store platform address in scratch space */
  291. lla a4, platform
  292. REG_S a4, SBI_SCRATCH_PLATFORM_ADDR_OFFSET(tp)
  293. /* Store hartid-to-scratch function address in scratch space */
  294. lla a4, _hartid_to_scratch
  295. REG_S a4, SBI_SCRATCH_HARTID_TO_SCRATCH_OFFSET(tp)
  296. /* Store trap-exit function address in scratch space */
  297. lla a4, _trap_exit
  298. REG_S a4, SBI_SCRATCH_TRAP_EXIT_OFFSET(tp)
  299. /* Clear tmp0 in scratch space */
  300. REG_S zero, SBI_SCRATCH_TMP0_OFFSET(tp)
  301. /* Store firmware options in scratch space */
  302. MOV_3R s0, a0, s1, a1, s2, a2
  303. #ifdef FW_OPTIONS
  304. li a0, FW_OPTIONS
  305. #else
  306. call fw_options
  307. #endif
  308. REG_S a0, SBI_SCRATCH_OPTIONS_OFFSET(tp)
  309. MOV_3R a0, s0, a1, s1, a2, s2
  310. /* Move to next scratch space */
  311. add t1, t1, t2
  312. blt t1, s7, _scratch_init
  313. /*
  314. * Relocate Flatened Device Tree (FDT)
  315. * source FDT address = previous arg1
  316. * destination FDT address = next arg1
  317. *
  318. * Note: We will preserve a0 and a1 passed by
  319. * previous booting stage.
  320. */
  321. beqz a1, _fdt_reloc_done
  322. /* Mask values in a3 and a4 */
  323. li a3, ~(__SIZEOF_POINTER__ - 1)
  324. li a4, 0xff
  325. /* t1 = destination FDT start address */
  326. MOV_3R s0, a0, s1, a1, s2, a2
  327. call fw_next_arg1
  328. add t1, a0, zero
  329. MOV_3R a0, s0, a1, s1, a2, s2
  330. beqz t1, _fdt_reloc_done
  331. beq t1, a1, _fdt_reloc_done
  332. and t1, t1, a3
  333. /* t0 = source FDT start address */
  334. add t0, a1, zero
  335. and t0, t0, a3
  336. /* t2 = source FDT size in big-endian */
  337. #if __riscv_xlen == 64
  338. lwu t2, 4(t0)
  339. #else
  340. lw t2, 4(t0)
  341. #endif
  342. /* t3 = bit[15:8] of FDT size */
  343. add t3, t2, zero
  344. srli t3, t3, 16
  345. and t3, t3, a4
  346. slli t3, t3, 8
  347. /* t4 = bit[23:16] of FDT size */
  348. add t4, t2, zero
  349. srli t4, t4, 8
  350. and t4, t4, a4
  351. slli t4, t4, 16
  352. /* t5 = bit[31:24] of FDT size */
  353. add t5, t2, zero
  354. and t5, t5, a4
  355. slli t5, t5, 24
  356. /* t2 = bit[7:0] of FDT size */
  357. srli t2, t2, 24
  358. and t2, t2, a4
  359. /* t2 = FDT size in little-endian */
  360. or t2, t2, t3
  361. or t2, t2, t4
  362. or t2, t2, t5
  363. /* t2 = destination FDT end address */
  364. add t2, t1, t2
  365. /* FDT copy loop */
  366. ble t2, t1, _fdt_reloc_done
  367. _fdt_reloc_again:
  368. REG_L t3, 0(t0)
  369. REG_S t3, 0(t1)
  370. add t0, t0, __SIZEOF_POINTER__
  371. add t1, t1, __SIZEOF_POINTER__
  372. blt t1, t2, _fdt_reloc_again
  373. _fdt_reloc_done:
  374. /* mark boot hart done */
  375. li t0, BOOT_STATUS_BOOT_HART_DONE
  376. lla t1, _boot_status
  377. REG_S t0, 0(t1)
  378. fence rw, rw
  379. j _start_warm
  380. /* waiting for boot hart to be done (_boot_status == 2) */
  381. _wait_for_boot_hart:
  382. li t0, BOOT_STATUS_BOOT_HART_DONE
  383. lla t1, _boot_status
  384. REG_L t1, 0(t1)
  385. /* Reduce the bus traffic so that boot hart may proceed faster */
  386. nop
  387. nop
  388. nop
  389. bne t0, t1, _wait_for_boot_hart
  390. _start_warm:
  391. /* Reset all registers for non-boot HARTs */
  392. li ra, 0
  393. call _reset_regs
  394. /* Disable and clear all interrupts */
  395. csrw CSR_MIE, zero
  396. csrw CSR_MIP, zero
  397. /* Find HART count and HART stack size */
  398. lla a4, platform
  399. #if __riscv_xlen == 64
  400. lwu s7, SBI_PLATFORM_HART_COUNT_OFFSET(a4)
  401. lwu s8, SBI_PLATFORM_HART_STACK_SIZE_OFFSET(a4)
  402. #else
  403. lw s7, SBI_PLATFORM_HART_COUNT_OFFSET(a4)
  404. lw s8, SBI_PLATFORM_HART_STACK_SIZE_OFFSET(a4)
  405. #endif
  406. REG_L s9, SBI_PLATFORM_HART_INDEX2ID_OFFSET(a4)
  407. /* Find HART id */
  408. csrr s6, CSR_MHARTID
  409. /* Find HART index */
  410. beqz s9, 3f
  411. li a4, 0
  412. 1:
  413. #if __riscv_xlen == 64
  414. lwu a5, (s9)
  415. #else
  416. lw a5, (s9)
  417. #endif
  418. beq a5, s6, 2f
  419. add s9, s9, 4
  420. add a4, a4, 1
  421. blt a4, s7, 1b
  422. li a4, -1
  423. 2: add s6, a4, zero
  424. 3: bge s6, s7, _start_hang
  425. /* Find the scratch space based on HART index */
  426. lla tp, _fw_end
  427. mul a5, s7, s8
  428. add tp, tp, a5
  429. mul a5, s8, s6
  430. sub tp, tp, a5
  431. li a5, SBI_SCRATCH_SIZE
  432. sub tp, tp, a5
  433. /* update the mscratch */
  434. csrw CSR_MSCRATCH, tp
  435. /* Setup stack */
  436. add sp, tp, zero
  437. /* Setup trap handler */
  438. lla a4, _trap_handler
  439. #if __riscv_xlen == 32
  440. csrr a5, CSR_MISA
  441. srli a5, a5, ('H' - 'A')
  442. andi a5, a5, 0x1
  443. beq a5, zero, _skip_trap_handler_rv32_hyp
  444. lla a4, _trap_handler_rv32_hyp
  445. _skip_trap_handler_rv32_hyp:
  446. #endif
  447. csrw CSR_MTVEC, a4
  448. #if __riscv_xlen == 32
  449. /* Override trap exit for H-extension */
  450. csrr a5, CSR_MISA
  451. srli a5, a5, ('H' - 'A')
  452. andi a5, a5, 0x1
  453. beq a5, zero, _skip_trap_exit_rv32_hyp
  454. lla a4, _trap_exit_rv32_hyp
  455. csrr a5, CSR_MSCRATCH
  456. REG_S a4, SBI_SCRATCH_TRAP_EXIT_OFFSET(a5)
  457. _skip_trap_exit_rv32_hyp:
  458. #endif
  459. /* Initialize SBI runtime */
  460. csrr a0, CSR_MSCRATCH
  461. call sbi_init
  462. /* We don't expect to reach here hence just hang */
  463. j _start_hang
  464. .align 3
  465. #ifdef FW_PIC
  466. _runtime_offset:
  467. RISCV_PTR 0
  468. #endif
  469. _relocate_lottery:
  470. RISCV_PTR 0
  471. _boot_status:
  472. RISCV_PTR 0
  473. _load_start:
  474. RISCV_PTR _fw_start
  475. _link_start:
  476. RISCV_PTR FW_TEXT_START
  477. _link_end:
  478. RISCV_PTR _fw_reloc_end
  479. .section .entry, "ax", %progbits
  480. .align 3
  481. .globl _hartid_to_scratch
  482. _hartid_to_scratch:
  483. /*
  484. * a0 -> HART ID (passed by caller)
  485. * a1 -> HART Index (passed by caller)
  486. * t0 -> HART Stack Size
  487. * t1 -> HART Stack End
  488. * t2 -> Temporary
  489. */
  490. lla t2, platform
  491. #if __riscv_xlen == 64
  492. lwu t0, SBI_PLATFORM_HART_STACK_SIZE_OFFSET(t2)
  493. lwu t2, SBI_PLATFORM_HART_COUNT_OFFSET(t2)
  494. #else
  495. lw t0, SBI_PLATFORM_HART_STACK_SIZE_OFFSET(t2)
  496. lw t2, SBI_PLATFORM_HART_COUNT_OFFSET(t2)
  497. #endif
  498. sub t2, t2, a1
  499. mul t2, t2, t0
  500. lla t1, _fw_end
  501. add t1, t1, t2
  502. li t2, SBI_SCRATCH_SIZE
  503. sub a0, t1, t2
  504. ret
  505. .section .entry, "ax", %progbits
  506. .align 3
  507. .globl _start_hang
  508. _start_hang:
  509. wfi
  510. j _start_hang
  511. .section .entry, "ax", %progbits
  512. .align 3
  513. .globl fw_platform_init
  514. .weak fw_platform_init
  515. fw_platform_init:
  516. add a0, a1, zero
  517. ret
  518. .macro TRAP_SAVE_AND_SETUP_SP_T0
  519. /* Swap TP and MSCRATCH */
  520. csrrw tp, CSR_MSCRATCH, tp
  521. /* Save T0 in scratch space */
  522. REG_S t0, SBI_SCRATCH_TMP0_OFFSET(tp)
  523. /*
  524. * Set T0 to appropriate exception stack
  525. *
  526. * Came_From_M_Mode = ((MSTATUS.MPP < PRV_M) ? 1 : 0) - 1;
  527. * Exception_Stack = TP ^ (Came_From_M_Mode & (SP ^ TP))
  528. *
  529. * Came_From_M_Mode = 0 ==> Exception_Stack = TP
  530. * Came_From_M_Mode = -1 ==> Exception_Stack = SP
  531. */
  532. csrr t0, CSR_MSTATUS
  533. srl t0, t0, MSTATUS_MPP_SHIFT
  534. and t0, t0, PRV_M
  535. slti t0, t0, PRV_M
  536. add t0, t0, -1
  537. xor sp, sp, tp
  538. and t0, t0, sp
  539. xor sp, sp, tp
  540. xor t0, tp, t0
  541. /* Save original SP on exception stack */
  542. REG_S sp, (SBI_TRAP_REGS_OFFSET(sp) - SBI_TRAP_REGS_SIZE)(t0)
  543. /* Set SP to exception stack and make room for trap registers */
  544. add sp, t0, -(SBI_TRAP_REGS_SIZE)
  545. /* Restore T0 from scratch space */
  546. REG_L t0, SBI_SCRATCH_TMP0_OFFSET(tp)
  547. /* Save T0 on stack */
  548. REG_S t0, SBI_TRAP_REGS_OFFSET(t0)(sp)
  549. /* Swap TP and MSCRATCH */
  550. csrrw tp, CSR_MSCRATCH, tp
  551. .endm
  552. .macro TRAP_SAVE_MEPC_MSTATUS have_mstatush
  553. /* Save MEPC and MSTATUS CSRs */
  554. csrr t0, CSR_MEPC
  555. REG_S t0, SBI_TRAP_REGS_OFFSET(mepc)(sp)
  556. csrr t0, CSR_MSTATUS
  557. REG_S t0, SBI_TRAP_REGS_OFFSET(mstatus)(sp)
  558. .if \have_mstatush
  559. csrr t0, CSR_MSTATUSH
  560. REG_S t0, SBI_TRAP_REGS_OFFSET(mstatusH)(sp)
  561. .else
  562. REG_S zero, SBI_TRAP_REGS_OFFSET(mstatusH)(sp)
  563. .endif
  564. .endm
  565. .macro TRAP_SAVE_GENERAL_REGS_EXCEPT_SP_T0
  566. /* Save all general regisers except SP and T0 */
  567. REG_S zero, SBI_TRAP_REGS_OFFSET(zero)(sp)
  568. REG_S ra, SBI_TRAP_REGS_OFFSET(ra)(sp)
  569. REG_S gp, SBI_TRAP_REGS_OFFSET(gp)(sp)
  570. REG_S tp, SBI_TRAP_REGS_OFFSET(tp)(sp)
  571. REG_S t1, SBI_TRAP_REGS_OFFSET(t1)(sp)
  572. REG_S t2, SBI_TRAP_REGS_OFFSET(t2)(sp)
  573. REG_S s0, SBI_TRAP_REGS_OFFSET(s0)(sp)
  574. REG_S s1, SBI_TRAP_REGS_OFFSET(s1)(sp)
  575. REG_S a0, SBI_TRAP_REGS_OFFSET(a0)(sp)
  576. REG_S a1, SBI_TRAP_REGS_OFFSET(a1)(sp)
  577. REG_S a2, SBI_TRAP_REGS_OFFSET(a2)(sp)
  578. REG_S a3, SBI_TRAP_REGS_OFFSET(a3)(sp)
  579. REG_S a4, SBI_TRAP_REGS_OFFSET(a4)(sp)
  580. REG_S a5, SBI_TRAP_REGS_OFFSET(a5)(sp)
  581. REG_S a6, SBI_TRAP_REGS_OFFSET(a6)(sp)
  582. REG_S a7, SBI_TRAP_REGS_OFFSET(a7)(sp)
  583. REG_S s2, SBI_TRAP_REGS_OFFSET(s2)(sp)
  584. REG_S s3, SBI_TRAP_REGS_OFFSET(s3)(sp)
  585. REG_S s4, SBI_TRAP_REGS_OFFSET(s4)(sp)
  586. REG_S s5, SBI_TRAP_REGS_OFFSET(s5)(sp)
  587. REG_S s6, SBI_TRAP_REGS_OFFSET(s6)(sp)
  588. REG_S s7, SBI_TRAP_REGS_OFFSET(s7)(sp)
  589. REG_S s8, SBI_TRAP_REGS_OFFSET(s8)(sp)
  590. REG_S s9, SBI_TRAP_REGS_OFFSET(s9)(sp)
  591. REG_S s10, SBI_TRAP_REGS_OFFSET(s10)(sp)
  592. REG_S s11, SBI_TRAP_REGS_OFFSET(s11)(sp)
  593. REG_S t3, SBI_TRAP_REGS_OFFSET(t3)(sp)
  594. REG_S t4, SBI_TRAP_REGS_OFFSET(t4)(sp)
  595. REG_S t5, SBI_TRAP_REGS_OFFSET(t5)(sp)
  596. REG_S t6, SBI_TRAP_REGS_OFFSET(t6)(sp)
  597. .endm
  598. .macro TRAP_CALL_C_ROUTINE
  599. /* Call C routine */
  600. add a0, sp, zero
  601. call sbi_trap_handler
  602. .endm
  603. .macro TRAP_RESTORE_GENERAL_REGS_EXCEPT_A0_T0
  604. /* Restore all general regisers except A0 and T0 */
  605. REG_L ra, SBI_TRAP_REGS_OFFSET(ra)(a0)
  606. REG_L sp, SBI_TRAP_REGS_OFFSET(sp)(a0)
  607. REG_L gp, SBI_TRAP_REGS_OFFSET(gp)(a0)
  608. REG_L tp, SBI_TRAP_REGS_OFFSET(tp)(a0)
  609. REG_L t1, SBI_TRAP_REGS_OFFSET(t1)(a0)
  610. REG_L t2, SBI_TRAP_REGS_OFFSET(t2)(a0)
  611. REG_L s0, SBI_TRAP_REGS_OFFSET(s0)(a0)
  612. REG_L s1, SBI_TRAP_REGS_OFFSET(s1)(a0)
  613. REG_L a1, SBI_TRAP_REGS_OFFSET(a1)(a0)
  614. REG_L a2, SBI_TRAP_REGS_OFFSET(a2)(a0)
  615. REG_L a3, SBI_TRAP_REGS_OFFSET(a3)(a0)
  616. REG_L a4, SBI_TRAP_REGS_OFFSET(a4)(a0)
  617. REG_L a5, SBI_TRAP_REGS_OFFSET(a5)(a0)
  618. REG_L a6, SBI_TRAP_REGS_OFFSET(a6)(a0)
  619. REG_L a7, SBI_TRAP_REGS_OFFSET(a7)(a0)
  620. REG_L s2, SBI_TRAP_REGS_OFFSET(s2)(a0)
  621. REG_L s3, SBI_TRAP_REGS_OFFSET(s3)(a0)
  622. REG_L s4, SBI_TRAP_REGS_OFFSET(s4)(a0)
  623. REG_L s5, SBI_TRAP_REGS_OFFSET(s5)(a0)
  624. REG_L s6, SBI_TRAP_REGS_OFFSET(s6)(a0)
  625. REG_L s7, SBI_TRAP_REGS_OFFSET(s7)(a0)
  626. REG_L s8, SBI_TRAP_REGS_OFFSET(s8)(a0)
  627. REG_L s9, SBI_TRAP_REGS_OFFSET(s9)(a0)
  628. REG_L s10, SBI_TRAP_REGS_OFFSET(s10)(a0)
  629. REG_L s11, SBI_TRAP_REGS_OFFSET(s11)(a0)
  630. REG_L t3, SBI_TRAP_REGS_OFFSET(t3)(a0)
  631. REG_L t4, SBI_TRAP_REGS_OFFSET(t4)(a0)
  632. REG_L t5, SBI_TRAP_REGS_OFFSET(t5)(a0)
  633. REG_L t6, SBI_TRAP_REGS_OFFSET(t6)(a0)
  634. .endm
  635. .macro TRAP_RESTORE_MEPC_MSTATUS have_mstatush
  636. /* Restore MEPC and MSTATUS CSRs */
  637. REG_L t0, SBI_TRAP_REGS_OFFSET(mepc)(a0)
  638. csrw CSR_MEPC, t0
  639. REG_L t0, SBI_TRAP_REGS_OFFSET(mstatus)(a0)
  640. csrw CSR_MSTATUS, t0
  641. .if \have_mstatush
  642. REG_L t0, SBI_TRAP_REGS_OFFSET(mstatusH)(a0)
  643. csrw CSR_MSTATUSH, t0
  644. .endif
  645. .endm
  646. .macro TRAP_RESTORE_A0_T0
  647. /* Restore T0 */
  648. REG_L t0, SBI_TRAP_REGS_OFFSET(t0)(a0)
  649. /* Restore A0 */
  650. REG_L a0, SBI_TRAP_REGS_OFFSET(a0)(a0)
  651. .endm
  652. .section .entry, "ax", %progbits
  653. .align 3
  654. .globl _trap_handler
  655. .globl _trap_exit
  656. _trap_handler:
  657. TRAP_SAVE_AND_SETUP_SP_T0
  658. TRAP_SAVE_MEPC_MSTATUS 0
  659. TRAP_SAVE_GENERAL_REGS_EXCEPT_SP_T0
  660. TRAP_CALL_C_ROUTINE
  661. _trap_exit:
  662. TRAP_RESTORE_GENERAL_REGS_EXCEPT_A0_T0
  663. TRAP_RESTORE_MEPC_MSTATUS 0
  664. TRAP_RESTORE_A0_T0
  665. mret
  666. #if __riscv_xlen == 32
  667. .section .entry, "ax", %progbits
  668. .align 3
  669. .globl _trap_handler_rv32_hyp
  670. .globl _trap_exit_rv32_hyp
  671. _trap_handler_rv32_hyp:
  672. TRAP_SAVE_AND_SETUP_SP_T0
  673. TRAP_SAVE_MEPC_MSTATUS 1
  674. TRAP_SAVE_GENERAL_REGS_EXCEPT_SP_T0
  675. TRAP_CALL_C_ROUTINE
  676. _trap_exit_rv32_hyp:
  677. TRAP_RESTORE_GENERAL_REGS_EXCEPT_A0_T0
  678. TRAP_RESTORE_MEPC_MSTATUS 1
  679. TRAP_RESTORE_A0_T0
  680. mret
  681. #endif
  682. .section .entry, "ax", %progbits
  683. .align 3
  684. .globl _reset_regs
  685. _reset_regs:
  686. /* flush the instruction cache */
  687. fence.i
  688. /* Reset all registers except ra, a0, a1 and a2 */
  689. li sp, 0
  690. li gp, 0
  691. li tp, 0
  692. li t0, 0
  693. li t1, 0
  694. li t2, 0
  695. li s0, 0
  696. li s1, 0
  697. li a3, 0
  698. li a4, 0
  699. li a5, 0
  700. li a6, 0
  701. li a7, 0
  702. li s2, 0
  703. li s3, 0
  704. li s4, 0
  705. li s5, 0
  706. li s6, 0
  707. li s7, 0
  708. li s8, 0
  709. li s9, 0
  710. li s10, 0
  711. li s11, 0
  712. li t3, 0
  713. li t4, 0
  714. li t5, 0
  715. li t6, 0
  716. csrw CSR_MSCRATCH, 0
  717. ret
  718. #ifdef FW_FDT_PATH
  719. .section .rodata
  720. .align 4
  721. .globl fw_fdt_bin
  722. fw_fdt_bin:
  723. .incbin FW_FDT_PATH
  724. #ifdef FW_FDT_PADDING
  725. .fill FW_FDT_PADDING, 1, 0
  726. #endif
  727. #endif