vha_dev_ax3.c 7.6 KB

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  1. /*
  2. *****************************************************************************
  3. * Copyright (c) Imagination Technologies Ltd.
  4. *
  5. * The contents of this file are subject to the MIT license as set out below.
  6. *
  7. * Permission is hereby granted, free of charge, to any person obtaining a
  8. * copy of this software and associated documentation files (the "Software"),
  9. * to deal in the Software without restriction, including without limitation
  10. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11. * and/or sell copies of the Software, and to permit persons to whom the
  12. * Software is furnished to do so, subject to the following conditions:
  13. *
  14. * The above copyright notice and this permission notice shall be included in
  15. * all copies or substantial portions of the Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  20. * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22. * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23. * THE SOFTWARE.
  24. *
  25. * Alternatively, the contents of this file may be used under the terms of the
  26. * GNU General Public License Version 2 ("GPL")in which case the provisions of
  27. * GPL are applicable instead of those above.
  28. *
  29. * If you wish to allow use of your version of this file only under the terms
  30. * of GPL, and not to allow others to use your version of this file under the
  31. * terms of the MIT license, indicate your decision by deleting the provisions
  32. * above and replace them with the notice and other provisions required by GPL
  33. * as set out in the file called "GPLHEADER" included in this distribution. If
  34. * you do not delete the provisions above, a recipient may use your version of
  35. * this file under the terms of either the MIT license or GPL.
  36. *
  37. * This License is also included in this distribution in the file called
  38. * "MIT_COPYING".
  39. *
  40. *****************************************************************************/
  41. #include <linux/device.h>
  42. #include <linux/moduleparam.h>
  43. #include "vha_common.h"
  44. #include "vha_plat.h"
  45. #include "vha_regs.h"
  46. static uint32_t os_priority = _OSID_;
  47. module_param(os_priority, uint, 0444);
  48. MODULE_PARM_DESC(os_priority, "Kick priority for this driver instance: <0,3>");
  49. static uint32_t prio_limits;
  50. module_param(prio_limits, uint, 0444);
  51. MODULE_PARM_DESC(prio_limits, "Priority limits. Valid for OS0 only. See TRM");
  52. static uint32_t hl_wdt_cycles = VHA_CORE_WDT_CYCLES;
  53. module_param(hl_wdt_cycles, uint, 0444);
  54. MODULE_PARM_DESC(hl_wdt_cycles, "High level watchdog cycles");
  55. static uint32_t hl_wdt_mode = 1;
  56. module_param(hl_wdt_mode, uint, 0444);
  57. MODULE_PARM_DESC(hl_wdt_mode, "High level watchdog mode: 1-pass; 2-layer group. See TRM");
  58. void vha_dev_mh_setup(struct vha_dev *vha, int ctx_id, struct vha_mh_config_regs *regs)
  59. {
  60. uint64_t val64 = 0;
  61. val64 |= VHA_CR_SETBITS_OS(CNN_PRELOAD_CONTROL, CBUF_N_REQS,
  62. VHA_CR_CNN_PRELOAD_CTRL_N_64);
  63. /* Setup preload for MMM */
  64. val64 |= VHA_CR_SETBITS_OS(CNN_PRELOAD_CONTROL, MMM_RD_N_REQS, VHA_CR_CNN_PRELOAD_CTRL_N_256);
  65. val64 |= VHA_CR_SETBITS_OS(CNN_PRELOAD_CONTROL, MMM_WR_N_REQS, VHA_CR_CNN_PRELOAD_CTRL_N_256);
  66. IOWRITE64_PDUMP(val64, VHA_CR_OS(CNN_PRELOAD_CONTROL));
  67. }
  68. void vha_dev_hwwdt_setup(struct vha_dev *vha, uint64_t cycles, uint64_t mode)
  69. {
  70. img_pdump_printf("-- Setup High level watchdog\n");
  71. IOWRITE64_PDUMP((cycles & VHA_CR_CNN_HL_WDT_COMPAREMATCH_MASKFULL),
  72. VHA_CR_CNN_HL_WDT_COMPAREMATCH);
  73. IOWRITE64_PDUMP(hl_wdt_mode,
  74. VHA_CR_CNN_HL_WDT_CTRL);
  75. IOWRITE64_PDUMP(0, VHA_CR_CNN_HL_WDT_TIMER);
  76. /* Setup memory watchdog */
  77. IOWRITE64(vha->reg_base, VHA_CR_CNN_MEM_WDT_COMPAREMATCH, VHA_CORE_MEM_WDT_CYCLES);
  78. IOWRITE64(vha->reg_base, VHA_CR_CNN_MEM_WDT_CTRL,
  79. VHA_CR_CNN_MEM_WDT_CTRL_CNN_MEM_WDT_CTRL_KICK_PASS);
  80. IOWRITE64(vha->reg_base, VHA_CR_CNN_MEM_WDT_TIMER, 0);
  81. }
  82. int vha_dev_hwwdt_calculate(struct vha_dev *vha, struct vha_cmd *cmd,
  83. uint64_t *cycles, uint64_t *mode)
  84. {
  85. if (!cycles || !mode)
  86. return -EINVAL;
  87. return -EIO;
  88. }
  89. int vha_dev_prepare(struct vha_dev *vha)
  90. {
  91. /* Enable core events */
  92. img_pdump_printf("-- Enable CORE events\n");
  93. IOWRITE64_PDUMP(VHA_CORE_EVNTS, VHA_CR_OS(VHA_EVENT_ENABLE));
  94. img_pdump_printf("-- Clear CORE events\n");
  95. IOWRITE64_PDUMP(VHA_CORE_EVNTS, VHA_CR_OS(VHA_EVENT_CLEAR));
  96. return 0;
  97. }
  98. void vha_dev_setup(struct vha_dev *vha)
  99. {
  100. uint64_t val64;
  101. vha_dev_hwwdt_setup(vha, hl_wdt_cycles, 0);
  102. if (prio_limits) {
  103. img_pdump_printf("-- Set priority limits\n");
  104. IOWRITE64_PDUMP(prio_limits, VHA_CR_CNN_CMD_PRIORITY_LIMITS);
  105. }
  106. img_pdump_printf("-- MMU set virtual address range0:%#llx-%#llx\n",
  107. IMG_MEM_VA_HEAP1_BASE, IMG_MEM_VA_HEAP1_SIZE);
  108. val64 = (uint64_t)vha->mmu_page_size <<
  109. VHA_CR_MMU_PAGE_SIZE_RANGE_ONE_PAGE_SIZE_SHIFT;
  110. val64 |= VHA_CR_ALIGN_SETBITS(MMU_PAGE_SIZE_RANGE_ONE,
  111. BASE_ADDR, IMG_MEM_VA_HEAP1_BASE);
  112. val64 |= VHA_CR_ALIGN_SETBITS(MMU_PAGE_SIZE_RANGE_ONE,
  113. END_ADDR, (IMG_MEM_VA_HEAP1_BASE + IMG_MEM_VA_HEAP1_SIZE));
  114. IOWRITE64_PDUMP(val64, VHA_CR_MMU_PAGE_SIZE_RANGE_ONE);
  115. img_pdump_printf("-- MMU set virtual address range1:%#llx-%#llx\n",
  116. IMG_MEM_VA_HEAP2_BASE, IMG_MEM_VA_HEAP2_SIZE);
  117. val64 = (uint64_t)vha->mmu_page_size <<
  118. VHA_CR_MMU_PAGE_SIZE_RANGE_TWO_PAGE_SIZE_SHIFT ;
  119. val64 |= VHA_CR_ALIGN_SETBITS(MMU_PAGE_SIZE_RANGE_TWO,
  120. BASE_ADDR, IMG_MEM_VA_HEAP2_BASE);
  121. val64 |= VHA_CR_ALIGN_SETBITS(MMU_PAGE_SIZE_RANGE_TWO,
  122. END_ADDR, (IMG_MEM_VA_HEAP2_BASE + IMG_MEM_VA_HEAP2_SIZE));
  123. IOWRITE64_PDUMP(val64, VHA_CR_MMU_PAGE_SIZE_RANGE_TWO);
  124. }
  125. void vha_dev_wait(struct vha_dev *vha)
  126. {
  127. uint32_t ready_val = VHA_CR_OS(VHA_EVENT_STATUS_VHA_READY_EN);
  128. uint32_t ready_mask = 0xffffffff;
  129. /* Ignore PARITY when waiting for status change */
  130. uint32_t status_mask = VHA_CR_OS(VHA_EVENT_STATUS_PARITY_CLRMSK);
  131. #ifdef VHA_SCF
  132. if (vha->hw_props.supported.parity &&
  133. !vha->parity_disable) {
  134. /* If READY bit is set then parity bit must be set as well ! */
  135. ready_val |= VHA_CR_OS(VHA_EVENT_STATUS_PARITY_EN);
  136. }
  137. #else
  138. /* Ignore PARITY, so that non-SCF pdump may work with SC CSIM */
  139. ready_mask &= VHA_CR_OS(VHA_EVENT_STATUS_PARITY_CLRMSK);
  140. #endif
  141. /* Wait for READY interrupt as well
  142. * pdump POL for any status flag:
  143. * count=100, delay=100cycles
  144. */
  145. img_pdump_printf("-- Wait for any CORE status change\n"
  146. "POL :REG:%#x 0 %#x 3 1000 1000\n",
  147. VHA_CR_OS(VHA_EVENT_STATUS), status_mask);
  148. /* quick pdump POL for the status READY flag only:
  149. * count=1, delay=10cycles
  150. */
  151. img_pdump_printf("-- Check for READY flag only\n"
  152. "POL :REG:%#x %#x %#x 0 1 10\n",
  153. VHA_CR_OS(VHA_EVENT_STATUS),
  154. ready_val, ready_mask);
  155. /* We do clear interrupts in the irq handler,
  156. * but this is not recorded into pdump because
  157. * of the irq context, so do it here */
  158. img_pdump_printf("-- Clear CORE events\n"
  159. "WRW64 :REG:%#x %#x\n",
  160. VHA_CR_OS(VHA_EVENT_CLEAR),
  161. VHA_CR_OS(VHA_EVENT_CLEAR_VHA_READY_EN) |
  162. VHA_CR_OS(VHA_EVENT_CLEAR_VHA_ERROR_EN) |
  163. VHA_CR_OS(VHA_EVENT_CLEAR_VHA_HL_WDT_EN));
  164. }
  165. uint32_t vha_dev_kick_prepare(struct vha_dev *vha,
  166. struct vha_cmd *cmd, int ctx_id)
  167. {
  168. /* write to the START bit */
  169. uint32_t val32 = (min(2048U, cmd->stream_size)/32-1)
  170. << VHA_CR_OS(CNN_CONTROL_CMD_SIZE_MIN1_SHIFT);
  171. val32 |= VHA_CR_OS(CNN_CONTROL_START_EN);
  172. /* This is odd, hw uses two contexts, we provide the base one,
  173. * but the other is always used in pair */
  174. img_pdump_printf("-- CNN setup CTXT_PASID:%d PRIO:%d\n",
  175. ctx_id, os_priority);
  176. val32 |= VHA_CR_SETBITS_OS(CNN_CONTROL,
  177. CTXT_PASID, ctx_id);
  178. val32 |= VHA_CR_SETBITS_OS(CNN_CONTROL,
  179. PRIORITY, os_priority);
  180. return val32;
  181. }