vha_dev_ax2.c 7.0 KB

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  1. /*
  2. *****************************************************************************
  3. * Copyright (c) Imagination Technologies Ltd.
  4. *
  5. * The contents of this file are subject to the MIT license as set out below.
  6. *
  7. * Permission is hereby granted, free of charge, to any person obtaining a
  8. * copy of this software and associated documentation files (the "Software"),
  9. * to deal in the Software without restriction, including without limitation
  10. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11. * and/or sell copies of the Software, and to permit persons to whom the
  12. * Software is furnished to do so, subject to the following conditions:
  13. *
  14. * The above copyright notice and this permission notice shall be included in
  15. * all copies or substantial portions of the Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  20. * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22. * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23. * THE SOFTWARE.
  24. *
  25. * Alternatively, the contents of this file may be used under the terms of the
  26. * GNU General Public License Version 2 ("GPL")in which case the provisions of
  27. * GPL are applicable instead of those above.
  28. *
  29. * If you wish to allow use of your version of this file only under the terms
  30. * of GPL, and not to allow others to use your version of this file under the
  31. * terms of the MIT license, indicate your decision by deleting the provisions
  32. * above and replace them with the notice and other provisions required by GPL
  33. * as set out in the file called "GPLHEADER" included in this distribution. If
  34. * you do not delete the provisions above, a recipient may use your version of
  35. * this file under the terms of either the MIT license or GPL.
  36. *
  37. * This License is also included in this distribution in the file called
  38. * "MIT_COPYING".
  39. *
  40. *****************************************************************************/
  41. #include <linux/device.h>
  42. #include <linux/moduleparam.h>
  43. #include "vha_common.h"
  44. #include "vha_plat.h"
  45. #include "vha_regs.h"
  46. static long cnn_wdt_cycles = VHA_CORE_WDT_CYCLES;
  47. module_param(cnn_wdt_cycles, long, 0444);
  48. MODULE_PARM_DESC(cnn_wdt_cycles,
  49. "CNN hw watchdog expiration cycles, -1=use estimated cycles, 0=disable watchdog, >0=predefined");
  50. static uint32_t cnn_wdt_cycles_margin = 40;
  51. module_param(cnn_wdt_cycles_margin, uint, 0444);
  52. MODULE_PARM_DESC(cnn_wdt_cycles_margin,
  53. "CNN estimated hw watchdog percentage overhead. default:40% additional margin added");
  54. void vha_dev_mh_setup(struct vha_dev *vha, int ctx_id, struct vha_mh_config_regs *regs)
  55. {
  56. uint64_t val64 = 0;
  57. uint8_t burst = ilog2(VHA_CORE_MH_MAX_BURST_LENGTH/32);
  58. WARN_ON(burst & ~VHA_CR_MH_CONTROL_MAX_BURST_LENGTH_MASK);
  59. val64 |= VHA_CR_SETBITS(CNN_CMD_MH_CONTROL,
  60. MAX_BURST_LENGTH, burst);
  61. val64 |= VHA_CR_SETBITS(CNN_CMD_MH_CONTROL,
  62. GPU_PIPE_COHERENT, VHA_CORE_MH_GPU_PIPE_COHERENT_TYPE);
  63. val64 |= VHA_CR_SETBITS(CNN_CMD_MH_CONTROL,
  64. SLC_CACHE_POLICY, VHA_CORE_MH_SLC_CACHE_POLICY_TYPE);
  65. val64 |= VHA_CR_SETBITS(CNN_CMD_MH_CONTROL,
  66. PERSISTENCE, VHA_CORE_MH_PERSISTENCE_PRIO);
  67. img_pdump_printf("-- CNN mem hierarchy setup CTXT_PASID:%d\n", ctx_id);
  68. val64 |= VHA_CR_SETBITS(CNN_CMD_MH_CONTROL,
  69. CTXT_PASID, ctx_id);
  70. /* Note: CMD reg has different layout than IBUF,CBUF,ABUFF,OUPACK */
  71. IOWRITE64_PDUMP(val64, VHA_CR_CNN_CMD_MH_CONTROL);
  72. val64 = 0;
  73. val64 |= VHA_CR_SETBITS(CNN_IBUF_MH_CONTROL,
  74. MAX_BURST_LENGTH, burst);
  75. val64 |= VHA_CR_SETBITS(CNN_IBUF_MH_CONTROL,
  76. GPU_PIPE_COHERENT, VHA_CORE_MH_GPU_PIPE_COHERENT_TYPE);
  77. val64 |= VHA_CR_SETBITS(CNN_IBUF_MH_CONTROL,
  78. PERSISTENCE, VHA_CORE_MH_PERSISTENCE_PRIO);
  79. IOWRITE64_PDUMP(val64, VHA_CR_CNN_IBUF_MH_CONTROL);
  80. IOWRITE64_PDUMP(val64, VHA_CR_CNN_CBUF_MH_CONTROL);
  81. IOWRITE64_PDUMP(val64, VHA_CR_CNN_ABUF_MH_CONTROL);
  82. IOWRITE64_PDUMP(val64, VHA_CR_CNN_OUTPACK_MH_CONTROL);
  83. IOWRITE64_PDUMP(val64, VHA_CR_CNN_ELEMENTOPS_MH_CONTROL);
  84. }
  85. void vha_dev_hwwdt_setup(struct vha_dev *vha, uint64_t cycles, uint64_t mode)
  86. {
  87. if (!mode)
  88. mode = VHA_CR_CNN_WDT_CTRL_CNN_WDT_CTRL_KICK_PASS;
  89. dev_dbg(vha->dev, "%s: cycles:%llx mode:%llx\n", __func__, cycles, mode);
  90. /* Note: Do not pdump the main watchdog as it may trigger
  91. * during memory latency/stalling testing */
  92. if (cycles) {
  93. IOWRITE64(vha->reg_base, VHA_CR_CNN_WDT_COMPAREMATCH,
  94. cycles & VHA_CR_CNN_WDT_COMPAREMATCH_MASKFULL);
  95. IOWRITE64(vha->reg_base, VHA_CR_CNN_WDT_CTRL,
  96. mode & VHA_CR_CNN_WDT_CTRL_CNN_WDT_CTRL_MASK);
  97. } else {
  98. IOWRITE64(vha->reg_base, VHA_CR_CNN_WDT_CTRL,
  99. VHA_CR_CNN_WDT_CTRL_CNN_WDT_CTRL_NONE);
  100. }
  101. /* Clear timer value just for sanity */
  102. IOWRITE64(vha->reg_base, VHA_CR_CNN_WDT_TIMER, 0);
  103. /* Note: We are not enabling MEM_WDT because it will not detect
  104. * issues due to the BIF/MMU or the customers memory fabric.
  105. * We could in theory enable this in customer systems,
  106. * but there is always a risk that it would result in false negatives
  107. * if there memory latency went very high temporarily.
  108. * HW team set this watchdog externally */
  109. #if 0
  110. IOWRITE64(vha->reg_base, VHA_CR_CNN_MEM_WDT_COMPAREMATCH, 0xfffff);
  111. IOWRITE64(vha->reg_base, VHA_CR_CNN_MEM_WDT_CTRL,
  112. VHA_CR_CNN_MEM_WDT_CTRL_CNN_MEM_WDT_CTRL_KICK_PASS);
  113. /* Clear timer value */
  114. IOWRITE64(vha->reg_base + VHA_CR_CNN_MEM_WDT_TIMER, 0);
  115. #endif
  116. }
  117. int vha_dev_hwwdt_calculate(struct vha_dev *vha, struct vha_cmd *cmd,
  118. uint64_t *cycles, uint64_t *mode)
  119. {
  120. const struct vha_user_cnn_submit_cmd *user_cmd =
  121. (struct vha_user_cnn_submit_cmd *)&cmd->user_cmd;
  122. if (!cycles || !mode)
  123. return -EINVAL;
  124. if (user_cmd && user_cmd->estimated_cycles && cnn_wdt_cycles == -1) {
  125. /* allow 40%, by default, above the estimated cycle count.
  126. * Clamp at uint32_t maximum */
  127. uint64_t wdt_cycles = user_cmd->estimated_cycles;
  128. uint64_t margin = wdt_cycles * cnn_wdt_cycles_margin;
  129. do_div(margin, 100UL);
  130. dev_dbg(vha->dev,
  131. "%s: estimated wdt cycles:%llx + margin:%llx\n",
  132. __func__, wdt_cycles, margin);
  133. wdt_cycles += margin;
  134. if (wdt_cycles > 0xffffffff)
  135. wdt_cycles = 0xffffffff;
  136. /* estimated cycle is per segment */
  137. *cycles = wdt_cycles;
  138. *mode = VHA_CR_CNN_WDT_CTRL_CNN_WDT_CTRL_KICK;
  139. } else {
  140. /* default value is per pass.
  141. * If default is 0 cycles it disables the watchdog */
  142. *cycles = cnn_wdt_cycles;
  143. *mode = VHA_CR_CNN_WDT_CTRL_CNN_WDT_CTRL_KICK_PASS;
  144. }
  145. vha->wdt_mode = *mode;
  146. return 0;
  147. }
  148. int vha_dev_prepare(struct vha_dev *vha)
  149. {
  150. /* Nothing to do */
  151. return 0;
  152. }
  153. void vha_dev_setup(struct vha_dev *vha)
  154. {
  155. vha->is_ready = true;
  156. }
  157. void vha_dev_wait(struct vha_dev *vha)
  158. {
  159. /* Nothing to do */
  160. }
  161. uint32_t vha_dev_kick_prepare(struct vha_dev *vha,
  162. struct vha_cmd *cmd, int ctx_id)
  163. {
  164. /* write to the START bit */
  165. uint32_t val = (min(2048U, cmd->stream_size)/32-1)
  166. << VHA_CR_OS(CNN_CONTROL_CMD_SIZE_MIN1_SHIFT);
  167. val |= VHA_CR_OS(CNN_CONTROL_START_EN);
  168. return val;
  169. }