vha_plat_param_thead_light_fpga_c910.h 1.3 KB

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  1. /*!
  2. *****************************************************************************
  3. *
  4. * @File vha_plat_param_thead_light_fpga_c910.h
  5. * ---------------------------------------------------------------------------
  6. *
  7. * Copyright (C) 2020 Alibaba Group Holding Limited
  8. *
  9. *****************************************************************************/
  10. #ifndef VHA_PLAT_PARAM_THEAD_LIGHT_FPGA_C910_H
  11. #define VHA_PLAT_PARAM_THEAD_LIGHT_FPGA_C910_H
  12. /* Core clock frequency: default 30MHz */
  13. #define VHA_CORE_CLOCK_MHZ 1000
  14. /* Core watchdog cycles default value */
  15. /* MMM can transfer any number of bytes at cost of higher cycles, setting it to ~100ms @800MHz */
  16. #define VHA_CORE_WDT_CYCLES (0x4ffffff*VHA_CORE_CLOCK_MHZ/800)
  17. /* Memory watchdog is set ~1ms @800MHz which is very safe value to avoid any false interrupts */
  18. #define VHA_MEM_WDT_CYCLES (0xfffff*VHA_CORE_CLOCK_MHZ/800)
  19. /* Memory burst size */
  20. #define VHA_CORE_MH_MAX_BURST_LENGTH 128
  21. /* SLC cache policy type (0-use cache, 1-bypass cache) */
  22. #define VHA_CORE_MH_SLC_CACHE_POLICY_TYPE 1
  23. /* GPU pipe coherent type */
  24. #define VHA_CORE_MH_GPU_PIPE_COHERENT_TYPE 1
  25. /* Persistence priority 0-lowest,3-highest */
  26. #define VHA_CORE_MH_PERSISTENCE_PRIO 0
  27. /* Suspend delay in ms after which the
  28. * runtime suspend callback is called */
  29. #define VHA_CORE_SUSPEND_DELAY 10
  30. #endif /* VHA_PLAT_PARAM_THEAD_LIGHT_FPGA_C910_H */