vha_plat_emu.c 17 KB

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  1. /*!
  2. *****************************************************************************
  3. *
  4. * @File vha_plat_emu.c
  5. * ---------------------------------------------------------------------------
  6. *
  7. * Copyright (c) Imagination Technologies Ltd.
  8. *
  9. * The contents of this file are subject to the MIT license as set out below.
  10. *
  11. * Permission is hereby granted, free of charge, to any person obtaining a
  12. * copy of this software and associated documentation files (the "Software"),
  13. * to deal in the Software without restriction, including without limitation
  14. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  15. * and/or sell copies of the Software, and to permit persons to whom the
  16. * Software is furnished to do so, subject to the following conditions:
  17. *
  18. * The above copyright notice and this permission notice shall be included in
  19. * all copies or substantial portions of the Software.
  20. *
  21. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  22. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  23. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  24. * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  25. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  26. * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  27. * THE SOFTWARE.
  28. *
  29. * Alternatively, the contents of this file may be used under the terms of the
  30. * GNU General Public License Version 2 ("GPL")in which case the provisions of
  31. * GPL are applicable instead of those above.
  32. *
  33. * If you wish to allow use of your version of this file only under the terms
  34. * of GPL, and not to allow others to use your version of this file under the
  35. * terms of the MIT license, indicate your decision by deleting the provisions
  36. * above and replace them with the notice and other provisions required by GPL
  37. * as set out in the file called "GPLHEADER" included in this distribution. If
  38. * you do not delete the provisions above, a recipient may use your version of
  39. * this file under the terms of either the MIT license or GPL.
  40. *
  41. * This License is also included in this distribution in the file called
  42. * "MIT_COPYING".
  43. *
  44. *****************************************************************************/
  45. #include <linux/delay.h>
  46. #include <linux/interrupt.h>
  47. #include <linux/module.h>
  48. #include <linux/device.h>
  49. #include <linux/gfp.h>
  50. #include <linux/dma-mapping.h>
  51. #include <linux/pci.h>
  52. #include <linux/pm.h>
  53. #include <linux/mod_devicetable.h>
  54. #include "uapi/version.h"
  55. #include "vha_common.h"
  56. #include "vha_plat.h"
  57. #define DEVICE_NAME "vha"
  58. /*
  59. * Spec:
  60. * Emulator PCIe In-Circuit Interface Card.Technical
  61. * Reference Manual.1.0.24.External PSTDRW.External
  62. */
  63. /* Emulator address range 0x4000-0x4FFF */
  64. #define PCI_EMU_SYS_CTRL_REGS_BAR (0)
  65. /* Offset of INTERRUPT_ENABLE */
  66. #define PCI_EMU_INTERRUPT_ENABLE_OFS (0x4048)
  67. /* master interrupt enable - default high */
  68. #define PCI_EMU_IRQ_ENABLE (1<<0)
  69. #define PCI_EMU_IRQ_HIGH (1<<1)
  70. /* Emulator reset offset */
  71. #define PCI_EMU_RESET_OFS (0x4000)
  72. /* Emulator reset bits */
  73. #define PCI_EMU_RESET_LOGIC (1<<0)
  74. #define PCI_EMU_RESET_DUT (1<<1)
  75. #define PCI_EMU_VENDOR_ID (0x1010)
  76. #define PCI_EMU_DEVICE_ID (0x1CE3)
  77. #define NUM_EMU_BARS 3
  78. #define EMU_REG_BAR PCI_EMU_SYS_CTRL_REGS_BAR
  79. #define NNA_REG_BAR 1
  80. #define NNA_MEM_BAR 2
  81. /* Number of core cycles used to measure the core clock frequency */
  82. #define FREQ_MEASURE_CYCLES 0x7fffff
  83. static unsigned long pci_size;
  84. module_param(pci_size, ulong, 0444);
  85. MODULE_PARM_DESC(pci_size, "physical size in bytes. when 0 (the default), use all memory in the PCI bar");
  86. static unsigned long pci_offset;
  87. module_param(pci_offset, ulong, 0444);
  88. MODULE_PARM_DESC(pci_offset, "offset from PCI bar start. (default: 0)");
  89. static unsigned short pool_alloc_order;
  90. module_param(pool_alloc_order, ushort, 0444);
  91. MODULE_PARM_DESC(pool_alloc_order,
  92. "Carveout pool allocation order, depends on PAGE_SIZE, \
  93. for CPU PAGE_SIZE=4kB, 0-4kB, 1-8kB, 2-16kB, 3-32kB, 4-64kB");
  94. static unsigned long poll_interrupts = 1; /* Enabled by default */
  95. module_param(poll_interrupts, ulong, 0444);
  96. MODULE_PARM_DESC(poll_interrupts, "Poll for interrupts? 0: No, 1: Yes");
  97. static unsigned long irq_poll_delay_us = 10000; /* 10 ms */
  98. module_param(irq_poll_delay_us, ulong, 0444);
  99. MODULE_PARM_DESC(irq_poll_delay_us, "Delay in us between each interrupt poll");
  100. static bool mem_static_kptr = true;
  101. module_param(mem_static_kptr, bool, 0444);
  102. MODULE_PARM_DESC(mem_static_kptr,
  103. "Creates static kernel mapping for fpga memory");
  104. static struct heap_config vha_plat_emu_heap_configs[] = {
  105. #ifdef CONFIG_GENERIC_ALLOCATOR
  106. {
  107. .type = IMG_MEM_HEAP_TYPE_CARVEOUT,
  108. /* .options.carveout to be filled at run time */
  109. /* .to_dev_addr to be filled at run time */
  110. /* .to_host_addr to be filled at run time */
  111. },
  112. #else
  113. #error CONFIG_GENERIC_ALLOCATOR was not defined
  114. #endif
  115. #if CONFIG_DMA_SHARED_BUFFER
  116. {
  117. .type = IMG_MEM_HEAP_TYPE_DMABUF,
  118. .to_dev_addr = NULL,
  119. .options.dmabuf = {
  120. .use_sg_dma = true,
  121. },
  122. },
  123. #else
  124. #warning "Memory importing not supported!"
  125. #endif
  126. };
  127. static const int vha_plat_emu_heaps =
  128. sizeof(vha_plat_emu_heap_configs)/sizeof(*vha_plat_emu_heap_configs);
  129. static const struct pci_device_id pci_pci_ids[] = {
  130. { PCI_DEVICE(PCI_EMU_VENDOR_ID, PCI_EMU_DEVICE_ID) },
  131. { 0, }
  132. };
  133. MODULE_DEVICE_TABLE(pci, pci_pci_ids);
  134. struct imgpci_prvdata {
  135. int irq;
  136. struct {
  137. unsigned long addr;
  138. unsigned long size;
  139. void __iomem *km_addr;
  140. } memmap[NUM_EMU_BARS];
  141. struct pci_dev *pci_dev;
  142. int irq_poll;
  143. struct delayed_work irq_work;
  144. };
  145. struct img_pci_driver {
  146. struct pci_dev *pci_dev;
  147. struct pci_driver pci_driver;
  148. };
  149. static int vha_plat_probe(struct pci_dev *pci_dev,
  150. const struct pci_device_id *id);
  151. static void vha_plat_remove(struct pci_dev *dev);
  152. static int vha_plat_suspend(struct device *dev);
  153. static int vha_plat_resume(struct device *dev);
  154. static SIMPLE_DEV_PM_OPS(vha_pm_plat_ops,
  155. vha_plat_suspend, vha_plat_resume);
  156. static ssize_t info_show(struct device_driver *drv, char *buf)
  157. {
  158. return sprintf(buf, "VHA EMU driver version : " VERSION_STRING "\n");
  159. }
  160. static DRIVER_ATTR_RO(info);
  161. static struct attribute *drv_attrs[] = {
  162. &driver_attr_info.attr,
  163. NULL
  164. };
  165. ATTRIBUTE_GROUPS(drv);
  166. static struct img_pci_driver vha_pci_drv = {
  167. .pci_driver = {
  168. .name = "vha_pci",
  169. .id_table = pci_pci_ids,
  170. .probe = vha_plat_probe,
  171. .remove = vha_plat_remove,
  172. .driver = {
  173. .groups = drv_groups,
  174. .pm = &vha_pm_plat_ops,
  175. }
  176. },
  177. };
  178. static ulong maxmapsizeMB = (sizeof(void *) == 4) ? 400 : 1024;
  179. #if 0
  180. static unsigned int emu_readreg32(struct imgpci_prvdata *data,
  181. int bar, unsigned long offset
  182. )
  183. {
  184. void __iomem *reg =
  185. (void __iomem *)(data->memmap[bar].km_addr + offset);
  186. return ioread32(reg);
  187. }
  188. #endif
  189. static void emu_writereg32(struct imgpci_prvdata *data,
  190. int bar, unsigned long offset, int val)
  191. {
  192. void __iomem *reg =
  193. (void __iomem *)(data->memmap[bar].km_addr + offset);
  194. iowrite32(val, reg);
  195. }
  196. static void reset_emu(struct pci_dev *dev,
  197. struct imgpci_prvdata *data)
  198. {
  199. if (!dev)
  200. return;
  201. emu_writereg32(data, PCI_EMU_SYS_CTRL_REGS_BAR,
  202. PCI_EMU_RESET_OFS,
  203. ~(PCI_EMU_RESET_LOGIC|PCI_EMU_RESET_DUT));
  204. mdelay(100);
  205. emu_writereg32(data, PCI_EMU_SYS_CTRL_REGS_BAR,
  206. PCI_EMU_RESET_OFS,
  207. PCI_EMU_RESET_LOGIC|PCI_EMU_RESET_DUT);
  208. }
  209. static irqreturn_t pci_thread_irq(int irq, void *dev_id)
  210. {
  211. struct pci_dev *dev = (struct pci_dev *)dev_id;
  212. return vha_handle_thread_irq(&dev->dev);
  213. }
  214. static irqreturn_t pci_handle_irq(int irq, void *dev_id)
  215. {
  216. struct pci_dev *dev = (struct pci_dev *)dev_id;
  217. struct imgpci_prvdata *data = vha_get_plat_data(&dev->dev);
  218. irqreturn_t ret = IRQ_NONE;
  219. if (data == NULL || dev_id == NULL) {
  220. /* spurious interrupt: not yet initialised. */
  221. goto exit;
  222. }
  223. ret = vha_handle_irq(&dev->dev);
  224. exit:
  225. return ret;
  226. }
  227. /* Interrupt polling function */
  228. static void pci_poll_interrupt(struct work_struct *work)
  229. {
  230. struct imgpci_prvdata *data = container_of(work,
  231. struct imgpci_prvdata, irq_work.work);
  232. struct pci_dev *dev = data->pci_dev;
  233. int ret;
  234. if (!data->irq_poll)
  235. return;
  236. preempt_disable();
  237. ret = vha_handle_irq(&dev->dev);
  238. preempt_enable();
  239. if (ret == IRQ_WAKE_THREAD)
  240. vha_handle_thread_irq(&dev->dev);
  241. /* retrigger */
  242. schedule_delayed_work(&data->irq_work,
  243. usecs_to_jiffies(irq_poll_delay_us));
  244. }
  245. /*
  246. * IO hooks.
  247. * NOTE: customer may want to use spinlock to avoid
  248. * problems with multi threaded IO access
  249. */
  250. static DEFINE_SPINLOCK(io_irq_lock);
  251. static unsigned long io_irq_flags;
  252. uint64_t vha_plat_read64(void *addr)
  253. {
  254. u64 val;
  255. spin_lock_irqsave(&io_irq_lock, io_irq_flags);
  256. val =(uint64_t)readl((const volatile void __iomem *)addr) |
  257. ((uint64_t)readl((const volatile void __iomem *)addr + 4) << 32);
  258. spin_unlock_irqrestore(&io_irq_lock, io_irq_flags);
  259. return val;
  260. }
  261. void vha_plat_write64(void *addr, uint64_t val)
  262. {
  263. spin_lock_irqsave(&io_irq_lock, io_irq_flags);
  264. writel((uint32_t)(val & 0xffffffff), (volatile void __iomem *)addr);
  265. writel((uint32_t)(val >> 32), (volatile void __iomem *)addr + 4);
  266. spin_unlock_irqrestore(&io_irq_lock, io_irq_flags);
  267. }
  268. int vha_plat_deinit(void)
  269. {
  270. struct pci_dev *dev = vha_pci_drv.pci_dev;
  271. int ret;
  272. if (dev) {
  273. struct imgpci_prvdata *data = vha_get_plat_data(&dev->dev);
  274. if (data) {
  275. if (poll_interrupts) {
  276. data->irq_poll = 0;
  277. cancel_delayed_work_sync(&data->irq_work);
  278. }
  279. /* reset the emulator */
  280. reset_emu(data->pci_dev, data);
  281. emu_writereg32(data,
  282. PCI_EMU_SYS_CTRL_REGS_BAR,
  283. PCI_EMU_INTERRUPT_ENABLE_OFS,
  284. ~PCI_EMU_IRQ_ENABLE);
  285. } else {
  286. dev_dbg(&dev->dev,
  287. "%s: prv data not found, HW reset omitted\n",
  288. __func__);
  289. }
  290. } else {
  291. pr_debug("%s: dev missing, HW reset omitted\n", __func__);
  292. }
  293. /* Unregister the driver from the OS */
  294. pci_unregister_driver(&(vha_pci_drv.pci_driver));
  295. ret = vha_deinit();
  296. if (ret)
  297. pr_err("VHA driver deinit failed\n");
  298. return ret;
  299. }
  300. #ifdef CONFIG_GENERIC_ALLOCATOR
  301. static phys_addr_t carveout_to_dev_addr(union heap_options *options,
  302. phys_addr_t addr)
  303. {
  304. phys_addr_t base = options->carveout.phys;
  305. size_t size = options->carveout.size;
  306. unsigned long offset = options->carveout.offs;
  307. if (addr - offset >= base && addr < base + size - offset)
  308. return addr - base;
  309. pr_err("%s: unexpected addr! base 0x%llx size %zu offs %zu addr 0x%llx\n",
  310. __func__, base, size, offset, addr);
  311. WARN_ON(1);
  312. return addr;
  313. }
  314. static phys_addr_t carveout_to_host_addr(union heap_options *options,
  315. phys_addr_t addr)
  316. {
  317. phys_addr_t base = options->carveout.phys;
  318. size_t size = options->carveout.size;
  319. unsigned long offset = options->carveout.offs;
  320. if (addr < size - offset)
  321. return base + addr;
  322. pr_err("%s: unexpected addr! base %llx size %zu offs %zu addr %#llx\n",
  323. __func__, base, size, offset, addr);
  324. WARN_ON(1);
  325. return addr;
  326. }
  327. static void *carveout_get_kptr(phys_addr_t addr,
  328. size_t size, enum img_mem_attr mattr)
  329. {
  330. /*
  331. * Device memory is I/O memory and as a rule, it cannot
  332. * be dereferenced safely without memory barriers, that
  333. * is why it is guarded by __iomem (return of ioremap)
  334. * and checked by sparse. It is accessed only through
  335. * ioread32(), iowrit32(), etc.
  336. *
  337. * In x86 this memory can be dereferenced and safely
  338. * accessed, i.e. a * __iomem pointer can be casted to
  339. * a regular void* * pointer. We cast this here
  340. * assuming FPGA is x86 and add __force to silence the
  341. * sparse warning
  342. *
  343. * Note: System memory carveout can be used with cached turned on.
  344. * */
  345. void *kptr = NULL;
  346. if (mattr & IMG_MEM_ATTR_UNCACHED)
  347. #if LINUX_VERSION_CODE < KERNEL_VERSION(5, 6, 0)
  348. kptr = (void * __force *)ioremap_nocache(addr, size);
  349. #else
  350. kptr = (void * __force *)ioremap(addr, size);
  351. #endif
  352. else if (mattr & IMG_MEM_ATTR_CACHED)
  353. kptr = (void * __force *)ioremap_cache(addr, size);
  354. else if (mattr & IMG_MEM_ATTR_WRITECOMBINE)
  355. kptr = (void * __force *)ioremap_wc(addr, size);
  356. return kptr;
  357. }
  358. static int carveout_put_kptr(void *addr)
  359. {
  360. iounmap((volatile void __iomem *)addr);
  361. return 0;
  362. }
  363. #endif
  364. static int vha_plat_probe(struct pci_dev *pci_dev,
  365. const struct pci_device_id *id)
  366. {
  367. int bar, ret = 0;
  368. struct imgpci_prvdata *data;
  369. size_t maxmapsize = maxmapsizeMB * 1024 * 1024;
  370. struct device *dev = &pci_dev->dev;
  371. #ifdef CONFIG_GENERIC_ALLOCATOR
  372. int heap;
  373. #endif
  374. dev_dbg(dev, "probing device, pci_dev: %p\n", dev);
  375. /* Enable the device */
  376. if (pci_enable_device(pci_dev))
  377. goto out_free;
  378. dev_info(dev, "%s dma_get_mask : %#llx\n", __func__, dma_get_mask(dev));
  379. if (dev->dma_mask) {
  380. dev_info(dev, "%s dev->dma_mask : %p : %#llx\n",
  381. __func__, dev->dma_mask, *dev->dma_mask);
  382. } else {
  383. dev_info(dev, "%s mask unset, setting coherent\n", __func__);
  384. dev->dma_mask = &dev->coherent_dma_mask;
  385. }
  386. dev_info(dev, "%s dma_set_mask %#llx\n", __func__, dma_get_mask(dev));
  387. ret = dma_set_mask(dev, dma_get_mask(dev));
  388. if (ret) {
  389. dev_err(dev, "%s failed to set dma mask\n", __func__);
  390. goto out_disable;
  391. }
  392. /* Reserve PCI I/O and memory resources */
  393. if (pci_request_regions(pci_dev, "imgpci"))
  394. goto out_disable;
  395. /* Create a kernel space mapping for each of the bars */
  396. data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
  397. dev_dbg(dev, "allocated imgpci_prvdata @ %p\n", data);
  398. memset(data, 0, sizeof(*data));
  399. for (bar = 0; bar < NUM_EMU_BARS; bar++) {
  400. data->memmap[bar].addr = pci_resource_start(pci_dev, bar);
  401. data->memmap[bar].size = pci_resource_len(pci_dev, bar);
  402. if (data->memmap[bar].size > maxmapsize) {
  403. /*
  404. * We avoid mapping too big regions: we do not need
  405. * such a big amount of memory and some times we do
  406. * not have enough contiguous 'vmallocable' memory.
  407. */
  408. dev_warn(dev, "not mapping all mem for bar %u\n", bar);
  409. data->memmap[bar].size = maxmapsize;
  410. }
  411. if (bar == NNA_MEM_BAR) {
  412. /* Change memory size according to module parameter */
  413. if (pci_size)
  414. data->memmap[bar].size = pci_size;
  415. /* ioremap fpga memory only when static mode is used */
  416. if (!mem_static_kptr)
  417. continue;
  418. }
  419. #if LINUX_VERSION_CODE < KERNEL_VERSION(5, 6, 0)
  420. data->memmap[bar].km_addr = devm_ioremap_nocache(dev,
  421. pci_resource_start(pci_dev, bar),
  422. data->memmap[bar].size);
  423. #else
  424. data->memmap[bar].km_addr = devm_ioremap(dev,
  425. pci_resource_start(pci_dev, bar),
  426. data->memmap[bar].size);
  427. #endif
  428. dev_dbg(dev, "[bar %u] addr: 0x%lx size: 0x%lx km: 0x%p\n",
  429. bar, data->memmap[bar].addr,
  430. data->memmap[bar].size,
  431. data->memmap[bar].km_addr);
  432. }
  433. /* Get the IRQ...*/
  434. data->irq = pci_dev->irq;
  435. data->pci_dev = pci_dev;
  436. vha_pci_drv.pci_dev = pci_dev;
  437. reset_emu(pci_dev, data);
  438. if (!poll_interrupts) {
  439. /* Enable interrupts */
  440. emu_writereg32(data, PCI_EMU_SYS_CTRL_REGS_BAR,
  441. PCI_EMU_INTERRUPT_ENABLE_OFS,
  442. PCI_EMU_IRQ_ENABLE | PCI_EMU_IRQ_HIGH);
  443. }
  444. /* patch heap config with PCI memory addresses */
  445. for (heap = 0; heap < vha_plat_emu_heaps; heap++) {
  446. struct heap_config *cfg = &vha_plat_emu_heap_configs[heap];
  447. #ifdef CONFIG_GENERIC_ALLOCATOR
  448. if (cfg->type == IMG_MEM_HEAP_TYPE_CARVEOUT) {
  449. cfg->options.carveout.phys = data->memmap[NNA_MEM_BAR].addr;
  450. if (mem_static_kptr)
  451. cfg->options.carveout.kptr =
  452. data->memmap[NNA_MEM_BAR].km_addr;
  453. cfg->options.carveout.size = data->memmap[NNA_MEM_BAR].size;
  454. cfg->options.carveout.offs = pci_offset;
  455. cfg->to_dev_addr = carveout_to_dev_addr;
  456. cfg->to_host_addr = carveout_to_host_addr;
  457. /* IO memory access callbacks */
  458. if (!mem_static_kptr) {
  459. /* Dynamic kernel memory mapping */
  460. cfg->options.carveout.get_kptr = carveout_get_kptr;
  461. cfg->options.carveout.put_kptr = carveout_put_kptr;
  462. }
  463. /* Allocation order */
  464. cfg->options.carveout.pool_order = pool_alloc_order;
  465. break;
  466. }
  467. #endif
  468. }
  469. ret = vha_add_dev(dev, vha_plat_emu_heap_configs,
  470. vha_plat_emu_heaps, data,
  471. data->memmap[NNA_REG_BAR].km_addr, data->memmap[NNA_REG_BAR].size);
  472. if (ret) {
  473. dev_err(dev, "failed to intialize driver core!\n");
  474. goto out_release;
  475. }
  476. if (!poll_interrupts) {
  477. /* Install the ISR callback...*/
  478. ret = devm_request_threaded_irq(dev, data->irq, &pci_handle_irq,
  479. &pci_thread_irq, IRQF_SHARED, DEVICE_NAME,
  480. (void *)pci_dev);
  481. if (ret) {
  482. dev_err(dev, "failed to request irq!\n");
  483. goto out_rm_dev;
  484. }
  485. dev_dbg(dev, "registered irq %d\n", data->irq);
  486. } else {
  487. INIT_DELAYED_WORK(&data->irq_work, pci_poll_interrupt);
  488. data->irq_poll = 1;
  489. /* Start the interrupt poll */
  490. schedule_delayed_work(&data->irq_work,
  491. usecs_to_jiffies(irq_poll_delay_us));
  492. }
  493. /* Try to calibrate the core if needed */
  494. ret = vha_dev_calibrate(dev, FREQ_MEASURE_CYCLES);
  495. if (ret) {
  496. dev_err(dev, "%s: Failed to start clock calibration!\n", __func__);
  497. goto out_rm_dev;
  498. }
  499. return ret;
  500. out_rm_dev:
  501. vha_rm_dev(dev);
  502. out_release:
  503. pci_release_regions(pci_dev);
  504. out_disable:
  505. pci_disable_device(pci_dev);
  506. out_free:
  507. return ret;
  508. }
  509. static void vha_plat_remove(struct pci_dev *dev)
  510. {
  511. dev_dbg(&dev->dev, "removing device\n");
  512. pci_release_regions(dev);
  513. pci_disable_device(dev);
  514. vha_rm_dev(&dev->dev);
  515. }
  516. #ifdef CONFIG_PM
  517. static int vha_plat_suspend(struct device *dev)
  518. {
  519. return vha_suspend_dev(dev);
  520. }
  521. static int vha_plat_resume(struct device *dev)
  522. {
  523. return vha_resume_dev(dev);
  524. }
  525. #endif
  526. int vha_plat_init(void)
  527. {
  528. int ret;
  529. ret = pci_register_driver(&vha_pci_drv.pci_driver);
  530. if (ret) {
  531. pr_err("failed to register PCI driver!\n");
  532. return ret;
  533. }
  534. /* pci_dev should be set in probe */
  535. if (!vha_pci_drv.pci_dev) {
  536. pr_err("failed to find VHA PCI dev!\n");
  537. pci_unregister_driver(&vha_pci_drv.pci_driver);
  538. return -ENODEV;
  539. }
  540. return 0;
  541. }
  542. /*
  543. * coding style for emacs
  544. *
  545. * Local variables:
  546. * indent-tabs-mode: t
  547. * tab-width: 8
  548. * c-basic-offset: 8
  549. * End:
  550. */