vha_regs.h 14 KB

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  1. /*!
  2. *****************************************************************************
  3. * Copyright (c) Imagination Technologies Ltd.
  4. *
  5. * The contents of this file are subject to the MIT license as set out below.
  6. *
  7. * Permission is hereby granted, free of charge, to any person obtaining a
  8. * copy of this software and associated documentation files (the "Software"),
  9. * to deal in the Software without restriction, including without limitation
  10. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11. * and/or sell copies of the Software, and to permit persons to whom the
  12. * Software is furnished to do so, subject to the following conditions:
  13. *
  14. * The above copyright notice and this permission notice shall be included in
  15. * all copies or substantial portions of the Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  20. * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22. * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23. * THE SOFTWARE.
  24. *
  25. * Alternatively, the contents of this file may be used under the terms of the
  26. * GNU General Public License Version 2 ("GPL")in which case the provisions of
  27. * GPL are applicable instead of those above.
  28. *
  29. * If you wish to allow use of your version of this file only under the terms
  30. * of GPL, and not to allow others to use your version of this file under the
  31. * terms of the MIT license, indicate your decision by deleting the provisions
  32. * above and replace them with the notice and other provisions required by GPL
  33. * as set out in the file called "GPLHEADER" included in this distribution. If
  34. * you do not delete the provisions above, a recipient may use your version of
  35. * this file under the terms of either the MIT license or GPL.
  36. *
  37. * This License is also included in this distribution in the file called
  38. * "MIT_COPYING".
  39. *
  40. *****************************************************************************/
  41. #ifndef VHA_REGS_H
  42. #define VHA_REGS_H
  43. #include "../vha_io.h"
  44. #if defined(HW_AX3)
  45. #include <hwdefs/vha_cr_magna.h>
  46. #else
  47. #error "No HW layout defined"
  48. #endif
  49. #if defined(CFG_SYS_MAGNA)
  50. #include <hwdefs/magna_system.h>
  51. #endif
  52. #define HW_SERIES (28U)
  53. /* General register macros */
  54. #define VHA_GET_FIELD_FULL_MASK(reg, field) \
  55. (VHA_CR_BITMASK(reg, field) >> VHA_CR_##reg##_##field##_SHIFT)
  56. #define VHA_SET_FIELD_SIMPLE_VAL(reg, field, type) \
  57. (VHA_CR_##reg##_##field##_##type)
  58. #define VHA_SET_FIELD_SIMPLE_FULL(reg, field) \
  59. VHA_CR_BITMASK(reg, field)
  60. #define VHA_WM_ID_TO_MASK(i) (1 << i)
  61. #define VHA_CORE_ID_TO_MASK(i) (1 << i)
  62. #define VHA_WM_MASK_TO_ID(m) ({ \
  63. uint8_t _ret_ = m; \
  64. WARN_ON(!_ret_); \
  65. do { \
  66. if (!_ret_) break; \
  67. _ret_ = ffs(_ret_) - 1; \
  68. } while (0); \
  69. _ret_; \
  70. })
  71. #define VHA_CORE_MASK_TO_ID(m) VHA_WM_MASK_TO_ID(m)
  72. #define VHA_CORE_MASK_TO_NUM(m) ({ \
  73. uint8_t _ret_ = m; \
  74. WARN_ON(!_ret_); \
  75. do { \
  76. if (!_ret_) break; \
  77. _ret_ = _ret_ - ((_ret_ >> 1) & 0x55); \
  78. _ret_ = (_ret_ & 0x33) + ((_ret_ >> 2) & 0x33); \
  79. _ret_ = (((_ret_ + (_ret_ >> 4)) & 0x0F) * 0x01); \
  80. } while (0); \
  81. _ret_; \
  82. })
  83. #if defined(CONFIG_VHA_DUMMY)
  84. #define VHA_LOCK_WM()
  85. #define VHA_UNLOCK_WM()
  86. #else
  87. #define VHA_LOCK_WM() spin_lock_irq(&vha->irq_lock)
  88. #define VHA_UNLOCK_WM() spin_unlock(&vha->irq_lock)
  89. #endif
  90. #define VHA_SELECT_WM(wm) ({ \
  91. uint64_t reg = 0;\
  92. uint8_t c = 10;\
  93. IOWRITE64_CR_PDUMP(VHA_CR_SETBITS(TLC_WM_INDIRECT, ADDRESS, (uint64_t)wm), \
  94. TLC_WM_INDIRECT); \
  95. do { \
  96. reg = IOREAD64_CR_REGIO(TLC_WM_INDIRECT); \
  97. c--;\
  98. } while ((reg != wm) && c > 0); \
  99. WARN_ON(c == 0); \
  100. })
  101. /* Clock calibration defines. */
  102. #define VHA_CALIBRATION_WM_ID 0
  103. #define VHA_CALIBRATION_CORE_ID 0
  104. #define VHA_CALIBRATION_CORE_MASK (1 << VHA_CALIBRATION_CORE_ID)
  105. /* Event macro definitions */
  106. #define VHA_SYS_EVENT_TYPE(name) \
  107. VHA_CR_BITMASK(SYS_EVENT_TYPE, name)
  108. #define VHA_WM_EVENT_TYPE(name) \
  109. VHA_CR_BITMASK(WM_EVENT_TYPE, name)
  110. #define VHA_CORE_EVENT_TYPE(name) \
  111. VHA_CR_BITMASK(CORE_EVENT_TYPE, name)
  112. #define VHA_IC_EVENT_TYPE(name) \
  113. VHA_CR_BITMASK(INTERCONNECT_EVENT_TYPE, name)
  114. #define VHA_SYS_EVENTS ( \
  115. VHA_SYS_EVENT_TYPE(RAM_INIT_DONE ) | \
  116. VHA_SYS_EVENT_TYPE(MEMBUS_RESET_DONE))
  117. #ifdef VHA_SCF
  118. #define VHA_SYS_SCF_ERR_EVENTS ( \
  119. VHA_SYS_EVENT_TYPE(LOGIC_ERROR ) | \
  120. VHA_SYS_EVENT_TYPE(RAM_CORRECTION ) | \
  121. VHA_SYS_EVENT_TYPE(RAM_DETECTION ) | \
  122. VHA_SYS_EVENT_TYPE(MMU_PARITY_ERROR) | \
  123. VHA_SYS_EVENT_TYPE(AXI_MEMORY_PARITY_ERROR))
  124. #else
  125. #define VHA_SYS_SCF_ERR_EVENTS (0)
  126. #endif
  127. #define VHA_SYS_ERR_EVENTS ( \
  128. VHA_SYS_SCF_ERR_EVENTS | \
  129. VHA_SYS_EVENT_TYPE(LSYNC_INV_REQ ) | \
  130. VHA_SYS_EVENT_TYPE(SYS_MEM_WDT ) | \
  131. VHA_SYS_EVENT_TYPE(MMU_PAGE_FAULT ) | \
  132. VHA_SYS_EVENT_TYPE(AXI_ERROR ))
  133. #define VHA_SYS_EVENTS_DEFAULT ( \
  134. VHA_SYS_EVENTS | \
  135. VHA_SYS_ERR_EVENTS)
  136. #define VHA_WM_EVENTS ( \
  137. VHA_WM_EVENT_TYPE(RESPONSE_FIFO_READY))
  138. #ifdef VHA_SCF
  139. #define VHA_WM_SCF_ERR_EVENTS ( \
  140. VHA_WM_EVENT_TYPE(LOGIC_FAULT ))
  141. #else
  142. #define VHA_WM_SCF_ERR_EVENTS (0)
  143. #endif
  144. #define VHA_WM_ERR_EVENTS ( \
  145. VHA_WM_SCF_ERR_EVENTS | \
  146. VHA_WM_EVENT_TYPE(WM_WL_WDT ) | \
  147. VHA_WM_EVENT_TYPE(WM_WL_IDLE_WDT) | \
  148. VHA_WM_EVENT_TYPE(WM_SOCIF_WDT ))
  149. #define VHA_WM_EVENTS_DEFAULT ( \
  150. VHA_WM_EVENTS | \
  151. VHA_WM_ERR_EVENTS)
  152. #define VHA_CORE_EVENTS ( \
  153. VHA_CORE_EVENT_TYPE(CNN_COMPLETE ))
  154. #ifdef VHA_SCF
  155. #define VHA_CORE_SCF_ERR_EVENTS ( \
  156. VHA_CORE_EVENT_TYPE(RAM_CORRECTION ) | \
  157. VHA_CORE_EVENT_TYPE(RAM_DETECTION ) | \
  158. VHA_CORE_EVENT_TYPE(LOGIC_ERROR ))
  159. #else
  160. #define VHA_CORE_SCF_ERR_EVENTS (0)
  161. #endif
  162. #define VHA_CORE_ERR_EVENTS ( \
  163. VHA_CORE_SCF_ERR_EVENTS | \
  164. VHA_CORE_EVENT_TYPE(CNN_ERROR ) | \
  165. VHA_CORE_EVENT_TYPE(CORE_SYNC_ERROR ) | \
  166. VHA_CORE_EVENT_TYPE(CORE_WDT ) | \
  167. VHA_CORE_EVENT_TYPE(CORE_MEM_WDT ))
  168. #define VHA_CORE_EVENTS_DEFAULT ( \
  169. VHA_CORE_EVENTS | \
  170. VHA_CORE_ERR_EVENTS)
  171. #define VHA_IC_EVENTS (0)
  172. #ifdef VHA_SCF
  173. #define VHA_IC_SCF_ERR_EVENTS ( \
  174. VHA_IC_EVENT_TYPE(LOGIC_ERROR ))
  175. #else
  176. #define VHA_IC_SCF_ERR_EVENTS (0)
  177. #endif
  178. #define VHA_IC_ERR_EVENTS ( \
  179. VHA_IC_SCF_ERR_EVENTS | \
  180. VHA_IC_EVENT_TYPE(LOCKSTEP_ERROR) | \
  181. VHA_IC_EVENT_TYPE(SOCIF_READ_MISMATCH) | \
  182. VHA_IC_EVENT_TYPE(SOCIF_READ_UNRESPONSIVE))
  183. #define VHA_IC_EVENTS_DEFAULT ( \
  184. VHA_IC_EVENTS | \
  185. VHA_IC_ERR_EVENTS)
  186. /* Clock macro definitions */
  187. #define VHA_CLOCKS_MULTI_ALL 0xff
  188. #define VHA_SPREAD_MASK(m) \
  189. (((m * 0x0101010101010101ULL & 0x8040201008040201ULL) * \
  190. 0x0102040810204081ULL >> 49) & 0x5555)
  191. #define VHA_SET_CLOCKS(mask, mode) \
  192. (VHA_SPREAD_MASK(mask) * VHA_CR_SYS_CLK_CTRL0_MODE_##mode)
  193. /* As REGBANK is a NOTOFF register, define its OFF to be AUTO by default. */
  194. #define VHA_CR_SYS_CLK_CTRL0_REGBANK_OFF \
  195. VHA_CR_SYS_CLK_CTRL0_REGBANK_AUTO
  196. #define VHA_SYS_CLOCK_MODE(name, mode) \
  197. VHA_CR_SYS_CLK_CTRL0_##name##_##mode
  198. #define VHA_SYS_CLOCK_MODE_MULTI(name, mode, mask) \
  199. (VHA_SET_CLOCKS(mask, mode) << VHA_CR_SYS_CLK_CTRL0_##name##0_SHIFT)
  200. #define VHA_SYS_CLOCK_MODE_MULTI_ALL(name, mode) \
  201. (VHA_SET_CLOCKS(VHA_CLOCKS_MULTI_ALL, mode) << \
  202. VHA_CR_SYS_CLK_CTRL0_##name##0_SHIFT)
  203. #define VHA_SYS_CLOCKS_DEFAULT(mode) ( (\
  204. VHA_SYS_CLOCK_MODE(REGBANK, mode) | \
  205. VHA_SYS_CLOCK_MODE(SOCM, mode) | \
  206. VHA_SYS_CLOCK_MODE(LSYNC, mode) | \
  207. VHA_SYS_CLOCK_MODE(SLC, mode) | \
  208. VHA_SYS_CLOCK_MODE(AXI, mode) | \
  209. VHA_SYS_CLOCK_MODE(INTERCONNECT, mode) | \
  210. VHA_SYS_CLOCK_MODE_MULTI_ALL(WM, mode) | \
  211. VHA_SYS_CLOCK_MODE_MULTI_ALL(NOC, mode) | \
  212. VHA_SYS_CLOCK_MODE_MULTI_ALL(CORE, mode) \
  213. ) & VHA_CR_SYS_CLK_CTRL0_MASKFULL)
  214. #define VHA_SYS_CLOCKS_RESET(mode) ( (\
  215. VHA_SYS_CLOCK_MODE(REGBANK, mode) | \
  216. VHA_SYS_CLOCK_MODE(SOCM, mode) | \
  217. VHA_SYS_CLOCK_MODE(LSYNC, mode) | \
  218. VHA_SYS_CLOCK_MODE(SLC, mode) | \
  219. VHA_SYS_CLOCK_MODE(AXI, mode) | \
  220. VHA_SYS_CLOCK_MODE(INTERCONNECT, mode) | \
  221. VHA_SYS_CLOCK_MODE_MULTI_ALL(WM, mode) | \
  222. VHA_SYS_CLOCK_MODE_MULTI_ALL(NOC, mode) \
  223. ) & VHA_CR_SYS_CLK_CTRL0_MASKFULL)
  224. #define VHA_SYS_CLOCKS_CORE_FULL_MASK ( \
  225. ~(VHA_CR_SYS_CLK_CTRL0_CORE7_CLRMSK) | \
  226. ~(VHA_CR_SYS_CLK_CTRL0_CORE6_CLRMSK) | \
  227. ~(VHA_CR_SYS_CLK_CTRL0_CORE5_CLRMSK) | \
  228. ~(VHA_CR_SYS_CLK_CTRL0_CORE4_CLRMSK) | \
  229. ~(VHA_CR_SYS_CLK_CTRL0_CORE3_CLRMSK) | \
  230. ~(VHA_CR_SYS_CLK_CTRL0_CORE2_CLRMSK) | \
  231. ~(VHA_CR_SYS_CLK_CTRL0_CORE1_CLRMSK) | \
  232. ~(VHA_CR_SYS_CLK_CTRL0_CORE0_CLRMSK))
  233. #define VHA_MAIN_CLOCK_MODE(name, mode) \
  234. VHA_CR_CLK_CTRL0_##name##_##mode \
  235. #define VHA_MAIN_CLOCKS_DEFAULT(mode) ( (\
  236. VHA_MAIN_CLOCK_MODE(CNN_CORE_XBAR, mode) | \
  237. VHA_MAIN_CLOCK_MODE(CNN_MMM, mode) | \
  238. VHA_MAIN_CLOCK_MODE(CNN_EWO, mode) | \
  239. VHA_MAIN_CLOCK_MODE(CNN_PACK, mode) | \
  240. VHA_MAIN_CLOCK_MODE(CNN_OIN, mode) | \
  241. VHA_MAIN_CLOCK_MODE(CNN_POOL, mode) | \
  242. VHA_MAIN_CLOCK_MODE(CNN_SB, mode) | \
  243. VHA_MAIN_CLOCK_MODE(CNN_XBAR, mode) | \
  244. VHA_MAIN_CLOCK_MODE(CNN_NORM, mode) | \
  245. VHA_MAIN_CLOCK_MODE(CNN_ACT, mode) | \
  246. VHA_MAIN_CLOCK_MODE(CNN_ACCUM, mode) | \
  247. VHA_MAIN_CLOCK_MODE(CNN_CNV, mode) | \
  248. VHA_MAIN_CLOCK_MODE(CNN_CBUF, mode) | \
  249. VHA_MAIN_CLOCK_MODE(CNN_IBUF, mode) | \
  250. VHA_MAIN_CLOCK_MODE(CNN_CMD, mode) | \
  251. VHA_MAIN_CLOCK_MODE(CNN, mode) | \
  252. VHA_MAIN_CLOCK_MODE(CNN_TRS_A, mode) | \
  253. VHA_MAIN_CLOCK_MODE(CNN_TRS_B, mode) | \
  254. VHA_MAIN_CLOCK_MODE(MEMBUS_RESET, mode) | \
  255. VHA_MAIN_CLOCK_MODE(BWM, mode) | \
  256. VHA_MAIN_CLOCK_MODE(LOCM, mode) | \
  257. VHA_MAIN_CLOCK_MODE(NOC, mode) | \
  258. VHA_MAIN_CLOCK_MODE(ARB, mode) | \
  259. VHA_MAIN_CLOCK_MODE(BIF, mode) \
  260. ) & VHA_CR_CLK_CTRL0_MASKFULL)
  261. /* Response status macro definitions. */
  262. #define VHA_WM_RESPONSE_STATUS(name) \
  263. VHA_CR_BITMASK(WM_RESPONSE_FIFO_WL_STATUS, name)
  264. #define VHA_WM_RESPONSE_SUCCESS ( \
  265. VHA_WM_RESPONSE_STATUS(SUCCESS))
  266. #define VHA_WM_RESPONSE_ERROR_CODE(name) \
  267. (VHA_CR_WM_RESPONSE_FIFO_WL_STATUS_WL_ERROR_CODE_##name)
  268. #define VHA_WM_RESPONSE_GET_ERROR_CODE(s) \
  269. VHA_CR_GETBITS(WM_RESPONSE_FIFO_WL_STATUS, ERROR_CODE, s)
  270. #define VHA_WM_RESPONSE_GET_FAILED_CORE_IDX(s) \
  271. VHA_CR_GETBITS(WM_RESPONSE_FIFO_WL_STATUS, FAILED_CORE_IDX, s)
  272. /* Core status macro definitions. */
  273. #define VHA_CORE_STATUS(name) \
  274. VHA_CR_BITMASK(CORE_EVENT_HOST_STATUS, name)
  275. /* IC status macro definitions. */
  276. #define VHA_IC_STATUS(name) \
  277. VHA_CR_BITMASK(INTERCONNECT_EVENT_HOST_STATUS, name)
  278. /* Confirmation writes error indication. */
  279. /* There is a fake error bit set in the VHA_CR_WM_RESPONSE_FIFO_WL_STATUS reg
  280. * to indicate confirmation writes error detected with software. */
  281. #define VHA_REG_CONF_ERROR_SHIFT (63)
  282. #define VHA_REG_CONF_ERROR_CLRMSK (0x7fffffffffffffffULL)
  283. #define VHA_REG_CONF_ERROR_EN (0x8000000000000000ULL)
  284. #define VHA_REG_SET_CONF_ERROR(r) \
  285. (r |= VHA_REG_CONF_ERROR_EN)
  286. #define VHA_REG_CLR_CONF_ERROR(r) \
  287. (r &= VHA_REG_CONF_ERROR_CLRMSK)
  288. #define VHA_REG_GET_CONF_ERROR(r) \
  289. ((r & VHA_REG_CONF_ERROR_EN) >> VHA_REG_CONF_ERROR_SHIFT)
  290. /* Parity error indication. */
  291. /* As not all regs with PARITY bit have LOGIC_ERROR bit to identify parity
  292. * error, there's a fake parity bit set in these regs to indicate parity
  293. * errors detected with software. */
  294. #define VHA_REG_PARITY_ERROR_SHIFT (62)
  295. #define VHA_REG_PARITY_ERROR_CLRMSK (0xBfffffffffffffffULL)
  296. #define VHA_REG_PARITY_ERROR_EN (0x4000000000000000ULL)
  297. #define VHA_REG_SET_PARITY_ERROR(r) \
  298. (r |= VHA_REG_PARITY_ERROR_EN)
  299. #define VHA_REG_CLR_PARITY_ERROR(r) \
  300. (r &= VHA_REG_PARITY_ERROR_CLRMSK)
  301. #define VHA_REG_GET_PARITY_ERROR(r) \
  302. ((r & VHA_REG_PARITY_ERROR_EN) >> VHA_REG_PARITY_ERROR_SHIFT)
  303. /* Workload id mismatch indication. */
  304. /* There is a fake error bit set in the VHA_CR_WM_RESPONSE_FIFO_WL_STATUS reg
  305. * to indicate workload id mismatch error detected with software. */
  306. #define VHA_REG_WL_ID_MISMATCH_ERROR_SHIFT (61)
  307. #define VHA_REG_WL_ID_MISMATCH_ERROR_CLRMSK (0xDfffffffffffffffULL)
  308. #define VHA_REG_WL_ID_MISMATCH_ERROR_EN (0x2000000000000000ULL)
  309. #define VHA_REG_SET_WL_ID_MISMATCH_ERROR(r) \
  310. (r |= VHA_REG_WL_ID_MISMATCH_ERROR_EN)
  311. #define VHA_REG_CLR_WL_ID_MISMATCH_ERROR(r) \
  312. (r &= VHA_REG_WL_ID_MISMATCH_ERROR_CLRMSK)
  313. #define VHA_REG_GET_WL_ID_MISMATCH_ERROR(r) \
  314. ((r & VHA_REG_WL_ID_MISMATCH_ERROR_EN) >> VHA_REG_WL_ID_MISMATCH_ERROR_SHIFT)
  315. /* CRC mismatch indication. */
  316. /* There is a fake error bit set in the VHA_CR_WM_RESPONSE_FIFO_WL_STATUS reg
  317. * to indicate workload id mismatch error detected with software. */
  318. #define VHA_REG_COMBINED_CRC_ERROR_SHIFT (60)
  319. #define VHA_REG_COMBINED_CRC_ERROR_CLRMSK (0xEFFFFFFFFFFFFFFFULL)
  320. #define VHA_REG_COMBINED_CRC_ERROR_EN (0x1000000000000000ULL)
  321. #define VHA_REG_SET_COMBINED_CRC_ERROR(r) \
  322. (r |= VHA_REG_COMBINED_CRC_ERROR_EN)
  323. #define VHA_REG_CLR_COMBINED_CRC_ERROR(r) \
  324. (r &= VHA_REG_COMBINED_CRC_ERROR_CLRMSK)
  325. #define VHA_REG_GET_COMBINED_CRC_ERROR(r) \
  326. ((r & VHA_REG_COMBINED_CRC_ERROR_EN) >> VHA_REG_COMBINED_CRC_ERROR_SHIFT)
  327. /* General core error indication. */
  328. /* There is a fake error bit set in the VHA_CR_WM_EVENT_STATUS reg
  329. * to indicate that core error was detected for one of the assigned cores. */
  330. #define VHA_REG_WM_CORE_ERROR_SHIFT (24)
  331. #define VHA_REG_WM_CORE_ERROR_CLRMSK (0xfffffffffeffffffULL)
  332. #define VHA_REG_WM_CORE_ERROR_EN (0x0000000001000000ULL)
  333. #define VHA_REG_SET_WM_CORE_ERROR(r) \
  334. (r |= VHA_REG_WM_CORE_ERROR_EN)
  335. #define VHA_REG_CLR_WM_CORE_ERROR(r) \
  336. (r &= VHA_REG_WM_CORE_ERROR_CLRMSK)
  337. #define VHA_REG_GET_WM_CORE_ERROR(r) \
  338. ((r & VHA_REG_WM_CORE_ERROR_EN) >> VHA_REG_WM_CORE_ERROR_SHIFT)
  339. /* General interconnect error indication. */
  340. /* There is a fake error bit set in the VHA_CR_WM_EVENT_STATUS reg
  341. * to indicate that interconnect error was detected for one of the assigned ones. */
  342. #define VHA_REG_WM_IC_ERROR_SHIFT (25)
  343. #define VHA_REG_WM_IC_ERROR_CLRMSK (0xfffffffffdffffffULL)
  344. #define VHA_REG_WM_IC_ERROR_EN (0x0000000002000000ULL)
  345. #define VHA_REG_SET_WM_IC_ERROR(r) \
  346. (r |= VHA_REG_WM_IC_ERROR_EN)
  347. #define VHA_REG_CLR_WM_IC_ERROR(r) \
  348. (r &= VHA_REG_WM_IC_ERROR_CLRMSK)
  349. #define VHA_REG_GET_WM_IC_ERROR(r) \
  350. ((r & VHA_REG_WM_IC_ERROR_EN) >> VHA_REG_WM_IC_ERROR_SHIFT)
  351. #endif /* VHA_REGS_H */