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- /*************************************************************************/ /*!
- @Title Hardware definition file vha_cr_magna.h
- @Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved
- */ /**************************************************************************/
- /* **** Autogenerated C -- do not edit **** */
- /*
- */
- #ifndef _VHA_CR_MAGNA_H_
- #define _VHA_CR_MAGNA_H_
- #define VHA_CR_MAGNA_REVISION 1
- /*
- Register VHA_CR_TLC_WM_INDIRECT
- */
- #define VHA_CR_TLC_WM_INDIRECT (0x0908U)
- #define VHA_CR_TLC_WM_INDIRECT_MASKFULL (IMG_UINT64_C(0x0000000000000007))
- #define VHA_CR_TLC_WM_INDIRECT_ADDRESS_SHIFT (0U)
- #define VHA_CR_TLC_WM_INDIRECT_ADDRESS_CLRMSK (0XFFFFFFF8U)
- /*
- Register VHA_CR_TLC_MH_CORE_INDIRECT
- */
- #define VHA_CR_TLC_MH_CORE_INDIRECT (0x0900U)
- #define VHA_CR_TLC_MH_CORE_INDIRECT_MASKFULL (IMG_UINT64_C(0x00000000000000FF))
- #define VHA_CR_TLC_MH_CORE_INDIRECT_MASK_SHIFT (0U)
- #define VHA_CR_TLC_MH_CORE_INDIRECT_MASK_CLRMSK (0XFFFFFF00U)
- /*
- Register VHA_CR_IC_CORE_INDIRECT
- */
- #define VHA_CR_IC_CORE_INDIRECT (0x0900U)
- #define VHA_CR_IC_CORE_INDIRECT_MASKFULL (IMG_UINT64_C(0x00000000000000FF))
- #define VHA_CR_IC_CORE_INDIRECT_MASK_SHIFT (0U)
- #define VHA_CR_IC_CORE_INDIRECT_MASK_CLRMSK (0XFFFFFF00U)
- /*
- Register VHA_CR_CORE_CTRL_INDIRECT
- */
- #define VHA_CR_CORE_CTRL_INDIRECT (0x0900U)
- #define VHA_CR_CORE_CTRL_INDIRECT_MASKFULL (IMG_UINT64_C(0x00000000000000FF))
- #define VHA_CR_CORE_CTRL_INDIRECT_MASK_SHIFT (0U)
- #define VHA_CR_CORE_CTRL_INDIRECT_MASK_CLRMSK (0XFFFFFF00U)
- /*
- Register VHA_CR_CORE_MH_INDIRECT
- */
- #define VHA_CR_CORE_MH_INDIRECT (0x0900U)
- #define VHA_CR_CORE_MH_INDIRECT_MASKFULL (IMG_UINT64_C(0x00000000000000FF))
- #define VHA_CR_CORE_MH_INDIRECT_MASK_SHIFT (0U)
- #define VHA_CR_CORE_MH_INDIRECT_MASK_CLRMSK (0XFFFFFF00U)
- /*
- Register VHA_CR_CNN_TOP_INDIRECT
- */
- #define VHA_CR_CNN_TOP_INDIRECT (0x0900U)
- #define VHA_CR_CNN_TOP_INDIRECT_MASKFULL (IMG_UINT64_C(0x00000000000000FF))
- #define VHA_CR_CNN_TOP_INDIRECT_MASK_SHIFT (0U)
- #define VHA_CR_CNN_TOP_INDIRECT_MASK_CLRMSK (0XFFFFFF00U)
- /*
- Register VHA_CR_CNN_FE_INDIRECT
- */
- #define VHA_CR_CNN_FE_INDIRECT (0x0900U)
- #define VHA_CR_CNN_FE_INDIRECT_MASKFULL (IMG_UINT64_C(0x00000000000000FF))
- #define VHA_CR_CNN_FE_INDIRECT_MASK_SHIFT (0U)
- #define VHA_CR_CNN_FE_INDIRECT_MASK_CLRMSK (0XFFFFFF00U)
- /*
- Register VHA_CR_CNN_BE_INDIRECT
- */
- #define VHA_CR_CNN_BE_INDIRECT (0x0900U)
- #define VHA_CR_CNN_BE_INDIRECT_MASKFULL (IMG_UINT64_C(0x00000000000000FF))
- #define VHA_CR_CNN_BE_INDIRECT_MASK_SHIFT (0U)
- #define VHA_CR_CNN_BE_INDIRECT_MASK_CLRMSK (0XFFFFFF00U)
- #define VHA_CR_DOMAINSPLIT_TYPE_MASK (0x0000FFFFU)
- #define VHA_CR_DOMAINSPLIT_TYPE_RESERVED_SHIFT (9U)
- #define VHA_CR_DOMAINSPLIT_TYPE_RESERVED_CLRMSK (0XFFFF01FFU)
- #define VHA_CR_DOMAINSPLIT_TYPE_CORE7_SHIFT (8U)
- #define VHA_CR_DOMAINSPLIT_TYPE_CORE7_CLRMSK (0XFFFFFEFFU)
- #define VHA_CR_DOMAINSPLIT_TYPE_CORE7_EN (0X00000100U)
- #define VHA_CR_DOMAINSPLIT_TYPE_CORE6_SHIFT (7U)
- #define VHA_CR_DOMAINSPLIT_TYPE_CORE6_CLRMSK (0XFFFFFF7FU)
- #define VHA_CR_DOMAINSPLIT_TYPE_CORE6_EN (0X00000080U)
- #define VHA_CR_DOMAINSPLIT_TYPE_CORE5_SHIFT (6U)
- #define VHA_CR_DOMAINSPLIT_TYPE_CORE5_CLRMSK (0XFFFFFFBFU)
- #define VHA_CR_DOMAINSPLIT_TYPE_CORE5_EN (0X00000040U)
- #define VHA_CR_DOMAINSPLIT_TYPE_CORE4_SHIFT (5U)
- #define VHA_CR_DOMAINSPLIT_TYPE_CORE4_CLRMSK (0XFFFFFFDFU)
- #define VHA_CR_DOMAINSPLIT_TYPE_CORE4_EN (0X00000020U)
- #define VHA_CR_DOMAINSPLIT_TYPE_CORE3_SHIFT (4U)
- #define VHA_CR_DOMAINSPLIT_TYPE_CORE3_CLRMSK (0XFFFFFFEFU)
- #define VHA_CR_DOMAINSPLIT_TYPE_CORE3_EN (0X00000010U)
- #define VHA_CR_DOMAINSPLIT_TYPE_CORE2_SHIFT (3U)
- #define VHA_CR_DOMAINSPLIT_TYPE_CORE2_CLRMSK (0XFFFFFFF7U)
- #define VHA_CR_DOMAINSPLIT_TYPE_CORE2_EN (0X00000008U)
- #define VHA_CR_DOMAINSPLIT_TYPE_CORE1_SHIFT (2U)
- #define VHA_CR_DOMAINSPLIT_TYPE_CORE1_CLRMSK (0XFFFFFFFBU)
- #define VHA_CR_DOMAINSPLIT_TYPE_CORE1_EN (0X00000004U)
- #define VHA_CR_DOMAINSPLIT_TYPE_CORE0_SHIFT (1U)
- #define VHA_CR_DOMAINSPLIT_TYPE_CORE0_CLRMSK (0XFFFFFFFDU)
- #define VHA_CR_DOMAINSPLIT_TYPE_CORE0_EN (0X00000002U)
- #define VHA_CR_DOMAINSPLIT_TYPE_TLC_SHIFT (0U)
- #define VHA_CR_DOMAINSPLIT_TYPE_TLC_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_DOMAINSPLIT_TYPE_TLC_EN (0X00000001U)
- /*
- Register VHA_CR_PRODUCT_ID
- */
- #define VHA_CR_PRODUCT_ID (0x0018U)
- #define VHA_CR_PRODUCT_ID_MASKFULL (IMG_UINT64_C(0x00000000FFFF0000))
- #define VHA_CR_PRODUCT_ID_IMG_PRODUCT_ID_SHIFT (16U)
- #define VHA_CR_PRODUCT_ID_IMG_PRODUCT_ID_CLRMSK (IMG_UINT64_C(0XFFFFFFFF0000FFFF))
- /*
- Register VHA_CR_CORE_ID
- */
- #define VHA_CR_CORE_ID (0x0020U)
- #define VHA_CR_CORE_ID_MASKFULL (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
- #define VHA_CR_CORE_ID_BRANCH_ID_SHIFT (48U)
- #define VHA_CR_CORE_ID_BRANCH_ID_CLRMSK (IMG_UINT64_C(0X0000FFFFFFFFFFFF))
- #define VHA_CR_CORE_ID_VERSION_ID_SHIFT (32U)
- #define VHA_CR_CORE_ID_VERSION_ID_CLRMSK (IMG_UINT64_C(0XFFFF0000FFFFFFFF))
- #define VHA_CR_CORE_ID_NUMBER_OF_SCALABLE_UNITS_SHIFT (16U)
- #define VHA_CR_CORE_ID_NUMBER_OF_SCALABLE_UNITS_CLRMSK (IMG_UINT64_C(0XFFFFFFFF0000FFFF))
- #define VHA_CR_CORE_ID_CONFIG_ID_SHIFT (0U)
- #define VHA_CR_CORE_ID_CONFIG_ID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF0000))
- /*
- Register VHA_CR_CORE_IP_INTEGRATOR_ID
- */
- #define VHA_CR_CORE_IP_INTEGRATOR_ID (0x0028U)
- #define VHA_CR_CORE_IP_INTEGRATOR_ID_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_CORE_IP_INTEGRATOR_ID_VALUE_SHIFT (0U)
- #define VHA_CR_CORE_IP_INTEGRATOR_ID_VALUE_CLRMSK (IMG_UINT64_C(0XFFFFFFFF00000000))
- /*
- Register VHA_CR_CORE_IP_CHANGELIST
- */
- #define VHA_CR_CORE_IP_CHANGELIST (0x0030U)
- #define VHA_CR_CORE_IP_CHANGELIST_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_CORE_IP_CHANGELIST_VALUE_SHIFT (0U)
- #define VHA_CR_CORE_IP_CHANGELIST_VALUE_CLRMSK (IMG_UINT64_C(0XFFFFFFFF00000000))
- /*
- Register VHA_CR_CORE_IP_CONFIG
- */
- #define VHA_CR_CORE_IP_CONFIG (0x0038U)
- #define VHA_CR_CORE_IP_CONFIG_MASKFULL (IMG_UINT64_C(0x00000000000FFF01))
- #define VHA_CR_CORE_IP_CONFIG_SIGNATURES_SUPPORTED_SAFETY_SHIFT (19U)
- #define VHA_CR_CORE_IP_CONFIG_SIGNATURES_SUPPORTED_SAFETY_CLRMSK (0XFFF7FFFFU)
- #define VHA_CR_CORE_IP_CONFIG_SIGNATURES_SUPPORTED_SAFETY_EN (0X00080000U)
- #define VHA_CR_CORE_IP_CONFIG_OCM_SECURITY_SHIFT (18U)
- #define VHA_CR_CORE_IP_CONFIG_OCM_SECURITY_CLRMSK (0XFFFBFFFFU)
- #define VHA_CR_CORE_IP_CONFIG_OCM_SECURITY_EN (0X00040000U)
- #define VHA_CR_CORE_IP_CONFIG_ECC_RAMS_SHIFT (16U)
- #define VHA_CR_CORE_IP_CONFIG_ECC_RAMS_CLRMSK (0XFFFCFFFFU)
- #define VHA_CR_CORE_IP_CONFIG_PARITY_REGISTERS_SHIFT (15U)
- #define VHA_CR_CORE_IP_CONFIG_PARITY_REGISTERS_CLRMSK (0XFFFF7FFFU)
- #define VHA_CR_CORE_IP_CONFIG_PARITY_REGISTERS_EN (0X00008000U)
- #define VHA_CR_CORE_IP_CONFIG_MMU_VERSION_SHIFT (12U)
- #define VHA_CR_CORE_IP_CONFIG_MMU_VERSION_CLRMSK (0XFFFF8FFFU)
- #define VHA_CR_CORE_IP_CONFIG_SIGNATURES_SUPPORTED_SUBSET_SHIFT (11U)
- #define VHA_CR_CORE_IP_CONFIG_SIGNATURES_SUPPORTED_SUBSET_CLRMSK (0XFFFFF7FFU)
- #define VHA_CR_CORE_IP_CONFIG_SIGNATURES_SUPPORTED_SUBSET_EN (0X00000800U)
- #define VHA_CR_CORE_IP_CONFIG_SIGNATURES_SUPPORTED_ALL_SHIFT (10U)
- #define VHA_CR_CORE_IP_CONFIG_SIGNATURES_SUPPORTED_ALL_CLRMSK (0XFFFFFBFFU)
- #define VHA_CR_CORE_IP_CONFIG_SIGNATURES_SUPPORTED_ALL_EN (0X00000400U)
- #define VHA_CR_CORE_IP_CONFIG_RANDOM_STALLERS_SUPPORTED_SHIFT (9U)
- #define VHA_CR_CORE_IP_CONFIG_RANDOM_STALLERS_SUPPORTED_CLRMSK (0XFFFFFDFFU)
- #define VHA_CR_CORE_IP_CONFIG_RANDOM_STALLERS_SUPPORTED_EN (0X00000200U)
- #define VHA_CR_CORE_IP_CONFIG_RTM_SUPPORTED_SHIFT (8U)
- #define VHA_CR_CORE_IP_CONFIG_RTM_SUPPORTED_CLRMSK (0XFFFFFEFFU)
- #define VHA_CR_CORE_IP_CONFIG_RTM_SUPPORTED_EN (0X00000100U)
- #define VHA_CR_CORE_IP_CONFIG_CNN_SUPPORTED_SHIFT (0U)
- #define VHA_CR_CORE_IP_CONFIG_CNN_SUPPORTED_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_CORE_IP_CONFIG_CNN_SUPPORTED_EN (0X00000001U)
- #define VHA_CR_CORE_IP_CONFIG1_BUS_WIDTH_MASK (0x00000007U)
- /*
- 8-byte memory interface */
- #define VHA_CR_CORE_IP_CONFIG1_BUS_WIDTH_MEM_WORD_8_BYTES (0x00000000U)
- /*
- 16-byte memory interface */
- #define VHA_CR_CORE_IP_CONFIG1_BUS_WIDTH_MEM_WORD_16_BYTES (0x00000001U)
- /*
- 32-byte memory interface */
- #define VHA_CR_CORE_IP_CONFIG1_BUS_WIDTH_MEM_WORD_32_BYTES (0x00000002U)
- /*
- 64-byte memory interface */
- #define VHA_CR_CORE_IP_CONFIG1_BUS_WIDTH_MEM_WORD_64_BYTES (0x00000003U)
- /*
- 128-byte memory interface */
- #define VHA_CR_CORE_IP_CONFIG1_BUS_WIDTH_MEM_WORD_128_BYTES (0x00000004U)
- /*
- Register VHA_CR_CORE_IP_CONFIG1
- */
- #define VHA_CR_CORE_IP_CONFIG1 (0x0040U)
- #define VHA_CR_CORE_IP_CONFIG1_MASKFULL (IMG_UINT64_C(0x00001FFFCFFF9FFF))
- #define VHA_CR_CORE_IP_CONFIG1_EXT_MEM_BUS_WIDTH_SHIFT (42U)
- #define VHA_CR_CORE_IP_CONFIG1_EXT_MEM_BUS_WIDTH_CLRMSK (IMG_UINT64_C(0XFFFFE3FFFFFFFFFF))
- #define VHA_CR_CORE_IP_CONFIG1_EXT_MEM_BUS_WIDTH_MEM_WORD_8_BYTES (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_CORE_IP_CONFIG1_EXT_MEM_BUS_WIDTH_MEM_WORD_16_BYTES (IMG_UINT64_C(0x0000040000000000))
- #define VHA_CR_CORE_IP_CONFIG1_EXT_MEM_BUS_WIDTH_MEM_WORD_32_BYTES (IMG_UINT64_C(0x0000080000000000))
- #define VHA_CR_CORE_IP_CONFIG1_EXT_MEM_BUS_WIDTH_MEM_WORD_64_BYTES (IMG_UINT64_C(0x00000c0000000000))
- #define VHA_CR_CORE_IP_CONFIG1_EXT_MEM_BUS_WIDTH_MEM_WORD_128_BYTES (IMG_UINT64_C(0x0000100000000000))
- #define VHA_CR_CORE_IP_CONFIG1_SYS_OCM_NUM_SUBBANKS_LOG2_SHIFT (39U)
- #define VHA_CR_CORE_IP_CONFIG1_SYS_OCM_NUM_SUBBANKS_LOG2_CLRMSK (IMG_UINT64_C(0XFFFFFC7FFFFFFFFF))
- #define VHA_CR_CORE_IP_CONFIG1_SYS_OCM_NUM_BANK_ARRAYS_MIN1_SHIFT (36U)
- #define VHA_CR_CORE_IP_CONFIG1_SYS_OCM_NUM_BANK_ARRAYS_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFF8FFFFFFFFF))
- #define VHA_CR_CORE_IP_CONFIG1_SYS_OCM_NUM_BANK_GROUPS_MIN1_SHIFT (33U)
- #define VHA_CR_CORE_IP_CONFIG1_SYS_OCM_NUM_BANK_GROUPS_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFF1FFFFFFFF))
- #define VHA_CR_CORE_IP_CONFIG1_NUM_CORES_MIN1_SHIFT (30U)
- #define VHA_CR_CORE_IP_CONFIG1_NUM_CORES_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFE3FFFFFFF))
- #define VHA_CR_CORE_IP_CONFIG1_CORE_OCM_RAM_SIZE_4KB_SHIFT (15U)
- #define VHA_CR_CORE_IP_CONFIG1_CORE_OCM_RAM_SIZE_4KB_CLRMSK (IMG_UINT64_C(0XFFFFFFFFF0007FFF))
- #define VHA_CR_CORE_IP_CONFIG1_SYS_OCM_RAM_SIZE_4KB_SHIFT (0U)
- #define VHA_CR_CORE_IP_CONFIG1_SYS_OCM_RAM_SIZE_4KB_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFE000))
- /*
- Register VHA_CR_CNN_IP_CONFIG0
- */
- #define VHA_CR_CNN_IP_CONFIG0 (0x0068U)
- #define VHA_CR_CNN_IP_CONFIG0_MASKFULL (IMG_UINT64_C(0x000000001FFFFFFF))
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_CMD_CRC_FOOTER_SHIFT (28U)
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_CMD_CRC_FOOTER_CLRMSK (IMG_UINT64_C(0XFFFFFFFFEFFFFFFF))
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_CMD_CRC_FOOTER_EN (IMG_UINT64_C(0X0000000010000000))
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_MEM_REQ_PRIORITISATION_SHIFT (27U)
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_MEM_REQ_PRIORITISATION_CLRMSK (IMG_UINT64_C(0XFFFFFFFFF7FFFFFF))
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_MEM_REQ_PRIORITISATION_EN (IMG_UINT64_C(0X0000000008000000))
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_PIPELINE_ORDER_XBAR_SHIFT (26U)
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_PIPELINE_ORDER_XBAR_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFBFFFFFF))
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_PIPELINE_ORDER_XBAR_EN (IMG_UINT64_C(0X0000000004000000))
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DEPTHWISE_POOLING_ENGINE_SHIFT (25U)
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DEPTHWISE_POOLING_ENGINE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFDFFFFFF))
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DEPTHWISE_POOLING_ENGINE_EN (IMG_UINT64_C(0X0000000002000000))
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_PARALLEL_MMM_SUPPORTED_SHIFT (24U)
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_PARALLEL_MMM_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFEFFFFFF))
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_PARALLEL_MMM_SUPPORTED_EN (IMG_UINT64_C(0X0000000001000000))
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_MMU_PRELOADS_SHIFT (23U)
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_MMU_PRELOADS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF7FFFFF))
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_MMU_PRELOADS_EN (IMG_UINT64_C(0X0000000000800000))
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_MMM_SUPPORTED_SHIFT (22U)
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_MMM_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFBFFFFF))
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_MMM_SUPPORTED_EN (IMG_UINT64_C(0X0000000000400000))
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_SCHEDULING_SUPPORTED_SHIFT (21U)
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_SCHEDULING_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFDFFFFF))
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_SCHEDULING_SUPPORTED_EN (IMG_UINT64_C(0X0000000000200000))
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_SECURITY_SHIFT (20U)
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_SECURITY_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFEFFFFF))
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_SECURITY_EN (IMG_UINT64_C(0X0000000000100000))
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_CBUF_DECOMPRESSION_SUPPORTED_SHIFT (19U)
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_CBUF_DECOMPRESSION_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF7FFFF))
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_CBUF_DECOMPRESSION_SUPPORTED_EN (IMG_UINT64_C(0X0000000000080000))
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_POOL_MIN_SUPPORTED_SHIFT (18U)
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_POOL_MIN_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFBFFFF))
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_POOL_MIN_SUPPORTED_EN (IMG_UINT64_C(0X0000000000040000))
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_UNSIGNED_SUPPORTED_SHIFT (17U)
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_UNSIGNED_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFDFFFF))
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_UNSIGNED_SUPPORTED_EN (IMG_UINT64_C(0X0000000000020000))
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_MIRROR_PADDING_SUPPORTED_SHIFT (16U)
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_MIRROR_PADDING_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFEFFFF))
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_MIRROR_PADDING_SUPPORTED_EN (IMG_UINT64_C(0X0000000000010000))
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_EWO_BROADCAST_SUPPORTED_SHIFT (15U)
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_EWO_BROADCAST_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF7FFF))
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_EWO_BROADCAST_SUPPORTED_EN (IMG_UINT64_C(0X0000000000008000))
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_HALF_16BIT_CONV_SUPPORTED_SHIFT (14U)
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_HALF_16BIT_CONV_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFBFFF))
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_HALF_16BIT_CONV_SUPPORTED_EN (IMG_UINT64_C(0X0000000000004000))
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_OUTPUT_FIXTOFIX_SUPPORTED_SHIFT (13U)
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_OUTPUT_FIXTOFIX_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFDFFF))
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_OUTPUT_FIXTOFIX_SUPPORTED_EN (IMG_UINT64_C(0X0000000000002000))
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DUAL_8BIT_CONV_SUPPORTED_SHIFT (12U)
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DUAL_8BIT_CONV_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFEFFF))
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DUAL_8BIT_CONV_SUPPORTED_EN (IMG_UINT64_C(0X0000000000001000))
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DATA_DECOMPRESSION_SUPPORTED_SHIFT (11U)
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DATA_DECOMPRESSION_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF7FF))
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DATA_DECOMPRESSION_SUPPORTED_EN (IMG_UINT64_C(0X0000000000000800))
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DATA_COMPRESSION_SUPPORTED_SHIFT (10U)
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DATA_COMPRESSION_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFBFF))
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DATA_COMPRESSION_SUPPORTED_EN (IMG_UINT64_C(0X0000000000000400))
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_ELEMENT_OPS_CALC_SUPPORTED_SHIFT (9U)
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_ELEMENT_OPS_CALC_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFDFF))
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_ELEMENT_OPS_CALC_SUPPORTED_EN (IMG_UINT64_C(0X0000000000000200))
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_ELEMENT_OPS_FETCH_SUPPORTED_SHIFT (8U)
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_ELEMENT_OPS_FETCH_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFEFF))
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_ELEMENT_OPS_FETCH_SUPPORTED_EN (IMG_UINT64_C(0X0000000000000100))
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_ELEMENT_OPS_SUPPORTED_SHIFT (7U)
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_ELEMENT_OPS_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFF7F))
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_ELEMENT_OPS_SUPPORTED_EN (IMG_UINT64_C(0X0000000000000080))
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_POOL_AVG_SUPPORTED_SHIFT (6U)
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_POOL_AVG_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFBF))
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_POOL_AVG_SUPPORTED_EN (IMG_UINT64_C(0X0000000000000040))
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_POOL_MAX_SUPPORTED_SHIFT (5U)
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_POOL_MAX_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFDF))
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_POOL_MAX_SUPPORTED_EN (IMG_UINT64_C(0X0000000000000020))
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_NORM_ICN_SUPPORTED_SHIFT (4U)
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_NORM_ICN_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFEF))
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_NORM_ICN_SUPPORTED_EN (IMG_UINT64_C(0X0000000000000010))
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_NORM_ACN_SUPPORTED_SHIFT (3U)
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_NORM_ACN_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF7))
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_NORM_ACN_SUPPORTED_EN (IMG_UINT64_C(0X0000000000000008))
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_ACT_LUT_SUPPORTED_SHIFT (2U)
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_ACT_LUT_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFB))
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_ACT_LUT_SUPPORTED_EN (IMG_UINT64_C(0X0000000000000004))
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DECONV_SUPPORTED_SHIFT (1U)
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DECONV_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFD))
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DECONV_SUPPORTED_EN (IMG_UINT64_C(0X0000000000000002))
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_CONV_SUPPORTED_SHIFT (0U)
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_CONV_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
- #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_CONV_SUPPORTED_EN (IMG_UINT64_C(0X0000000000000001))
- /*
- Register VHA_CR_CNN_IP_CONFIG1
- */
- #define VHA_CR_CNN_IP_CONFIG1 (0x0070U)
- #define VHA_CR_CNN_IP_CONFIG1_MASKFULL (IMG_UINT64_C(0xFFFFFFFF3F0FFFFF))
- #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_ADDRESS_ALIGNMENT_BYTES_LOG2_SHIFT (60U)
- #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_ADDRESS_ALIGNMENT_BYTES_LOG2_CLRMSK (IMG_UINT64_C(0X0FFFFFFFFFFFFFFF))
- #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_MAX_FILTERS_PER_SET_MIN1_SHIFT (52U)
- #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_MAX_FILTERS_PER_SET_MIN1_CLRMSK (IMG_UINT64_C(0XF00FFFFFFFFFFFFF))
- #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_MAX_FILTERS_MIN1_SHIFT (39U)
- #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_MAX_FILTERS_MIN1_CLRMSK (IMG_UINT64_C(0XFFF0007FFFFFFFFF))
- #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_SCHEDULING_NUM_PRIORITY_MIN1_SHIFT (37U)
- #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_SCHEDULING_NUM_PRIORITY_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFF9FFFFFFFFF))
- #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_CONV_ENGINE_CALC_BLOCKS_MIN1_SHIFT (32U)
- #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_CONV_ENGINE_CALC_BLOCKS_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFE0FFFFFFFF))
- #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_WEIGHT_DATA_WIDTH_MIN1_SHIFT (24U)
- #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_WEIGHT_DATA_WIDTH_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFC0FFFFFF))
- #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_ACTIVATION_DATA_WIDTH_MIN1_SHIFT (16U)
- #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_ACTIVATION_DATA_WIDTH_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF0FFFF))
- #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_CONV_ENGINE_NUM_FILTERS_MIN1_SHIFT (12U)
- #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_CONV_ENGINE_NUM_FILTERS_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF0FFF))
- #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_CONV_ENGINE_NUM_COEFFS_MIN1_SHIFT (4U)
- #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_CONV_ENGINE_NUM_COEFFS_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF00F))
- #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_SCHEDULING_NUM_HOSTS_MIN1_SHIFT (0U)
- #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_SCHEDULING_NUM_HOSTS_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF0))
- /*
- Register VHA_CR_CNN_IP_CONFIG2
- */
- #define VHA_CR_CNN_IP_CONFIG2 (0x0078U)
- #define VHA_CR_CNN_IP_CONFIG2_MASKFULL (IMG_UINT64_C(0x00FFFFFFFFFFFFFF))
- #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_TENSOR_CONCAT_MIN1_SHIFT (51U)
- #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_TENSOR_CONCAT_MIN1_CLRMSK (IMG_UINT64_C(0XFF07FFFFFFFFFFFF))
- #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_TENSOR_SPLIT_MIN1_SHIFT (48U)
- #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_TENSOR_SPLIT_MIN1_CLRMSK (IMG_UINT64_C(0XFFF8FFFFFFFFFFFF))
- #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_SHARED_BUFFER_BANKS_MIN1_SHIFT (44U)
- #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_SHARED_BUFFER_BANKS_MIN1_CLRMSK (IMG_UINT64_C(0XFFFF0FFFFFFFFFFF))
- #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_MAX_FILTERS_WITH_BIAS_MIN1_SHIFT (34U)
- #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_MAX_FILTERS_WITH_BIAS_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFF003FFFFFFFF))
- #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_NORM_UNITS_MIN1_SHIFT (28U)
- #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_NORM_UNITS_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFC0FFFFFFF))
- #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_SHARED_BUFFER_SIZE_MIN1_SHIFT (20U)
- #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_SHARED_BUFFER_SIZE_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFF00FFFFF))
- #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_COEFF_BUFFER_SIZE_MIN1_SHIFT (4U)
- #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_COEFF_BUFFER_SIZE_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF0000F))
- #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_COEFF_BUFFER_BANKS_MIN1_SHIFT (0U)
- #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_COEFF_BUFFER_BANKS_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF0))
- /*
- Register VHA_CR_CNN_IP_CONFIG3
- */
- #define VHA_CR_CNN_IP_CONFIG3 (0x0080U)
- #define VHA_CR_CNN_IP_CONFIG3_MASKFULL (IMG_UINT64_C(0x000001FFFFFFFFFF))
- #define VHA_CR_CNN_IP_CONFIG3_VHA_CNN_MMM_PARALLELISM_L1_MIN1_SHIFT (38U)
- #define VHA_CR_CNN_IP_CONFIG3_VHA_CNN_MMM_PARALLELISM_L1_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFE3FFFFFFFFF))
- #define VHA_CR_CNN_IP_CONFIG3_VHA_CNN_MMM_PARALLELISM_L0_MIN1_SHIFT (34U)
- #define VHA_CR_CNN_IP_CONFIG3_VHA_CNN_MMM_PARALLELISM_L0_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFC3FFFFFFFF))
- #define VHA_CR_CNN_IP_CONFIG3_VHA_CNN_MMM_BUFFER_SIZE_MIN1_SHIFT (29U)
- #define VHA_CR_CNN_IP_CONFIG3_VHA_CNN_MMM_BUFFER_SIZE_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFC1FFFFFFF))
- #define VHA_CR_CNN_IP_CONFIG3_VHA_CNN_MMM_BUFFER_BANKS_MIN1_SHIFT (24U)
- #define VHA_CR_CNN_IP_CONFIG3_VHA_CNN_MMM_BUFFER_BANKS_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFE0FFFFFF))
- #define VHA_CR_CNN_IP_CONFIG3_VHA_CNN_ACT_LUT_SIZE_MIN1_SHIFT (16U)
- #define VHA_CR_CNN_IP_CONFIG3_VHA_CNN_ACT_LUT_SIZE_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF00FFFF))
- #define VHA_CR_CNN_IP_CONFIG3_VHA_CNN_INPUT_BUFFER_SIZE_MIN1_SHIFT (8U)
- #define VHA_CR_CNN_IP_CONFIG3_VHA_CNN_INPUT_BUFFER_SIZE_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF00FF))
- #define VHA_CR_CNN_IP_CONFIG3_VHA_CNN_INPUT_BUFFER_BANKS_MIN1_SHIFT (0U)
- #define VHA_CR_CNN_IP_CONFIG3_VHA_CNN_INPUT_BUFFER_BANKS_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFF00))
- #define VHA_CR_SYS_CLK_CTRL0_MODE_MASK (0x00000003U)
- /*
- The domain clock is forced off */
- #define VHA_CR_SYS_CLK_CTRL0_MODE_OFF (0x00000000U)
- /*
- The domain clock is forced on */
- #define VHA_CR_SYS_CLK_CTRL0_MODE_ON (0x00000001U)
- /*
- Automatic clock gating is active, the domain clock is only on whilst data is being processed */
- #define VHA_CR_SYS_CLK_CTRL0_MODE_AUTO (0x00000002U)
- #define VHA_CR_SYS_CLK_CTRL0_MODE_NOTOFF_MASK (0x00000003U)
- /*
- The domain clock is forced on */
- #define VHA_CR_SYS_CLK_CTRL0_MODE_NOTOFF_ON (0x00000001U)
- /*
- Automatic clock gating is active, the domain clock is only on whilst data is being processed */
- #define VHA_CR_SYS_CLK_CTRL0_MODE_NOTOFF_AUTO (0x00000002U)
- /*
- Register VHA_CR_SYS_CLK_CTRL0
- */
- #define VHA_CR_SYS_CLK_CTRL0 (0x0200U)
- #define VHA_CR_SYS_CLK_CTRL0_MASKFULL (IMG_UINT64_C(0xFFFFFFFFFFFF0FFF))
- #define VHA_CR_SYS_CLK_CTRL0_CORE7_SHIFT (62U)
- #define VHA_CR_SYS_CLK_CTRL0_CORE7_CLRMSK (IMG_UINT64_C(0X3FFFFFFFFFFFFFFF))
- #define VHA_CR_SYS_CLK_CTRL0_CORE7_OFF (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_SYS_CLK_CTRL0_CORE7_ON (IMG_UINT64_C(0x4000000000000000))
- #define VHA_CR_SYS_CLK_CTRL0_CORE7_AUTO (IMG_UINT64_C(0x8000000000000000))
- #define VHA_CR_SYS_CLK_CTRL0_CORE6_SHIFT (60U)
- #define VHA_CR_SYS_CLK_CTRL0_CORE6_CLRMSK (IMG_UINT64_C(0XCFFFFFFFFFFFFFFF))
- #define VHA_CR_SYS_CLK_CTRL0_CORE6_OFF (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_SYS_CLK_CTRL0_CORE6_ON (IMG_UINT64_C(0x1000000000000000))
- #define VHA_CR_SYS_CLK_CTRL0_CORE6_AUTO (IMG_UINT64_C(0x2000000000000000))
- #define VHA_CR_SYS_CLK_CTRL0_CORE5_SHIFT (58U)
- #define VHA_CR_SYS_CLK_CTRL0_CORE5_CLRMSK (IMG_UINT64_C(0XF3FFFFFFFFFFFFFF))
- #define VHA_CR_SYS_CLK_CTRL0_CORE5_OFF (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_SYS_CLK_CTRL0_CORE5_ON (IMG_UINT64_C(0x0400000000000000))
- #define VHA_CR_SYS_CLK_CTRL0_CORE5_AUTO (IMG_UINT64_C(0x0800000000000000))
- #define VHA_CR_SYS_CLK_CTRL0_CORE4_SHIFT (56U)
- #define VHA_CR_SYS_CLK_CTRL0_CORE4_CLRMSK (IMG_UINT64_C(0XFCFFFFFFFFFFFFFF))
- #define VHA_CR_SYS_CLK_CTRL0_CORE4_OFF (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_SYS_CLK_CTRL0_CORE4_ON (IMG_UINT64_C(0x0100000000000000))
- #define VHA_CR_SYS_CLK_CTRL0_CORE4_AUTO (IMG_UINT64_C(0x0200000000000000))
- #define VHA_CR_SYS_CLK_CTRL0_CORE3_SHIFT (54U)
- #define VHA_CR_SYS_CLK_CTRL0_CORE3_CLRMSK (IMG_UINT64_C(0XFF3FFFFFFFFFFFFF))
- #define VHA_CR_SYS_CLK_CTRL0_CORE3_OFF (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_SYS_CLK_CTRL0_CORE3_ON (IMG_UINT64_C(0x0040000000000000))
- #define VHA_CR_SYS_CLK_CTRL0_CORE3_AUTO (IMG_UINT64_C(0x0080000000000000))
- #define VHA_CR_SYS_CLK_CTRL0_CORE2_SHIFT (52U)
- #define VHA_CR_SYS_CLK_CTRL0_CORE2_CLRMSK (IMG_UINT64_C(0XFFCFFFFFFFFFFFFF))
- #define VHA_CR_SYS_CLK_CTRL0_CORE2_OFF (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_SYS_CLK_CTRL0_CORE2_ON (IMG_UINT64_C(0x0010000000000000))
- #define VHA_CR_SYS_CLK_CTRL0_CORE2_AUTO (IMG_UINT64_C(0x0020000000000000))
- #define VHA_CR_SYS_CLK_CTRL0_CORE1_SHIFT (50U)
- #define VHA_CR_SYS_CLK_CTRL0_CORE1_CLRMSK (IMG_UINT64_C(0XFFF3FFFFFFFFFFFF))
- #define VHA_CR_SYS_CLK_CTRL0_CORE1_OFF (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_SYS_CLK_CTRL0_CORE1_ON (IMG_UINT64_C(0x0004000000000000))
- #define VHA_CR_SYS_CLK_CTRL0_CORE1_AUTO (IMG_UINT64_C(0x0008000000000000))
- #define VHA_CR_SYS_CLK_CTRL0_CORE0_SHIFT (48U)
- #define VHA_CR_SYS_CLK_CTRL0_CORE0_CLRMSK (IMG_UINT64_C(0XFFFCFFFFFFFFFFFF))
- #define VHA_CR_SYS_CLK_CTRL0_CORE0_OFF (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_SYS_CLK_CTRL0_CORE0_ON (IMG_UINT64_C(0x0001000000000000))
- #define VHA_CR_SYS_CLK_CTRL0_CORE0_AUTO (IMG_UINT64_C(0x0002000000000000))
- #define VHA_CR_SYS_CLK_CTRL0_NOC7_SHIFT (46U)
- #define VHA_CR_SYS_CLK_CTRL0_NOC7_CLRMSK (IMG_UINT64_C(0XFFFF3FFFFFFFFFFF))
- #define VHA_CR_SYS_CLK_CTRL0_NOC7_OFF (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_SYS_CLK_CTRL0_NOC7_ON (IMG_UINT64_C(0x0000400000000000))
- #define VHA_CR_SYS_CLK_CTRL0_NOC7_AUTO (IMG_UINT64_C(0x0000800000000000))
- #define VHA_CR_SYS_CLK_CTRL0_NOC6_SHIFT (44U)
- #define VHA_CR_SYS_CLK_CTRL0_NOC6_CLRMSK (IMG_UINT64_C(0XFFFFCFFFFFFFFFFF))
- #define VHA_CR_SYS_CLK_CTRL0_NOC6_OFF (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_SYS_CLK_CTRL0_NOC6_ON (IMG_UINT64_C(0x0000100000000000))
- #define VHA_CR_SYS_CLK_CTRL0_NOC6_AUTO (IMG_UINT64_C(0x0000200000000000))
- #define VHA_CR_SYS_CLK_CTRL0_NOC5_SHIFT (42U)
- #define VHA_CR_SYS_CLK_CTRL0_NOC5_CLRMSK (IMG_UINT64_C(0XFFFFF3FFFFFFFFFF))
- #define VHA_CR_SYS_CLK_CTRL0_NOC5_OFF (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_SYS_CLK_CTRL0_NOC5_ON (IMG_UINT64_C(0x0000040000000000))
- #define VHA_CR_SYS_CLK_CTRL0_NOC5_AUTO (IMG_UINT64_C(0x0000080000000000))
- #define VHA_CR_SYS_CLK_CTRL0_NOC4_SHIFT (40U)
- #define VHA_CR_SYS_CLK_CTRL0_NOC4_CLRMSK (IMG_UINT64_C(0XFFFFFCFFFFFFFFFF))
- #define VHA_CR_SYS_CLK_CTRL0_NOC4_OFF (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_SYS_CLK_CTRL0_NOC4_ON (IMG_UINT64_C(0x0000010000000000))
- #define VHA_CR_SYS_CLK_CTRL0_NOC4_AUTO (IMG_UINT64_C(0x0000020000000000))
- #define VHA_CR_SYS_CLK_CTRL0_NOC3_SHIFT (38U)
- #define VHA_CR_SYS_CLK_CTRL0_NOC3_CLRMSK (IMG_UINT64_C(0XFFFFFF3FFFFFFFFF))
- #define VHA_CR_SYS_CLK_CTRL0_NOC3_OFF (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_SYS_CLK_CTRL0_NOC3_ON (IMG_UINT64_C(0x0000004000000000))
- #define VHA_CR_SYS_CLK_CTRL0_NOC3_AUTO (IMG_UINT64_C(0x0000008000000000))
- #define VHA_CR_SYS_CLK_CTRL0_NOC2_SHIFT (36U)
- #define VHA_CR_SYS_CLK_CTRL0_NOC2_CLRMSK (IMG_UINT64_C(0XFFFFFFCFFFFFFFFF))
- #define VHA_CR_SYS_CLK_CTRL0_NOC2_OFF (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_SYS_CLK_CTRL0_NOC2_ON (IMG_UINT64_C(0x0000001000000000))
- #define VHA_CR_SYS_CLK_CTRL0_NOC2_AUTO (IMG_UINT64_C(0x0000002000000000))
- #define VHA_CR_SYS_CLK_CTRL0_NOC1_SHIFT (34U)
- #define VHA_CR_SYS_CLK_CTRL0_NOC1_CLRMSK (IMG_UINT64_C(0XFFFFFFF3FFFFFFFF))
- #define VHA_CR_SYS_CLK_CTRL0_NOC1_OFF (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_SYS_CLK_CTRL0_NOC1_ON (IMG_UINT64_C(0x0000000400000000))
- #define VHA_CR_SYS_CLK_CTRL0_NOC1_AUTO (IMG_UINT64_C(0x0000000800000000))
- #define VHA_CR_SYS_CLK_CTRL0_NOC0_SHIFT (32U)
- #define VHA_CR_SYS_CLK_CTRL0_NOC0_CLRMSK (IMG_UINT64_C(0XFFFFFFFCFFFFFFFF))
- #define VHA_CR_SYS_CLK_CTRL0_NOC0_OFF (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_SYS_CLK_CTRL0_NOC0_ON (IMG_UINT64_C(0x0000000100000000))
- #define VHA_CR_SYS_CLK_CTRL0_NOC0_AUTO (IMG_UINT64_C(0x0000000200000000))
- #define VHA_CR_SYS_CLK_CTRL0_WM7_SHIFT (30U)
- #define VHA_CR_SYS_CLK_CTRL0_WM7_CLRMSK (IMG_UINT64_C(0XFFFFFFFF3FFFFFFF))
- #define VHA_CR_SYS_CLK_CTRL0_WM7_OFF (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_SYS_CLK_CTRL0_WM7_ON (IMG_UINT64_C(0x0000000040000000))
- #define VHA_CR_SYS_CLK_CTRL0_WM7_AUTO (IMG_UINT64_C(0x0000000080000000))
- #define VHA_CR_SYS_CLK_CTRL0_WM6_SHIFT (28U)
- #define VHA_CR_SYS_CLK_CTRL0_WM6_CLRMSK (IMG_UINT64_C(0XFFFFFFFFCFFFFFFF))
- #define VHA_CR_SYS_CLK_CTRL0_WM6_OFF (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_SYS_CLK_CTRL0_WM6_ON (IMG_UINT64_C(0x0000000010000000))
- #define VHA_CR_SYS_CLK_CTRL0_WM6_AUTO (IMG_UINT64_C(0x0000000020000000))
- #define VHA_CR_SYS_CLK_CTRL0_WM5_SHIFT (26U)
- #define VHA_CR_SYS_CLK_CTRL0_WM5_CLRMSK (IMG_UINT64_C(0XFFFFFFFFF3FFFFFF))
- #define VHA_CR_SYS_CLK_CTRL0_WM5_OFF (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_SYS_CLK_CTRL0_WM5_ON (IMG_UINT64_C(0x0000000004000000))
- #define VHA_CR_SYS_CLK_CTRL0_WM5_AUTO (IMG_UINT64_C(0x0000000008000000))
- #define VHA_CR_SYS_CLK_CTRL0_WM4_SHIFT (24U)
- #define VHA_CR_SYS_CLK_CTRL0_WM4_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFCFFFFFF))
- #define VHA_CR_SYS_CLK_CTRL0_WM4_OFF (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_SYS_CLK_CTRL0_WM4_ON (IMG_UINT64_C(0x0000000001000000))
- #define VHA_CR_SYS_CLK_CTRL0_WM4_AUTO (IMG_UINT64_C(0x0000000002000000))
- #define VHA_CR_SYS_CLK_CTRL0_WM3_SHIFT (22U)
- #define VHA_CR_SYS_CLK_CTRL0_WM3_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF3FFFFF))
- #define VHA_CR_SYS_CLK_CTRL0_WM3_OFF (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_SYS_CLK_CTRL0_WM3_ON (IMG_UINT64_C(0x0000000000400000))
- #define VHA_CR_SYS_CLK_CTRL0_WM3_AUTO (IMG_UINT64_C(0x0000000000800000))
- #define VHA_CR_SYS_CLK_CTRL0_WM2_SHIFT (20U)
- #define VHA_CR_SYS_CLK_CTRL0_WM2_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFCFFFFF))
- #define VHA_CR_SYS_CLK_CTRL0_WM2_OFF (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_SYS_CLK_CTRL0_WM2_ON (IMG_UINT64_C(0x0000000000100000))
- #define VHA_CR_SYS_CLK_CTRL0_WM2_AUTO (IMG_UINT64_C(0x0000000000200000))
- #define VHA_CR_SYS_CLK_CTRL0_WM1_SHIFT (18U)
- #define VHA_CR_SYS_CLK_CTRL0_WM1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF3FFFF))
- #define VHA_CR_SYS_CLK_CTRL0_WM1_OFF (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_SYS_CLK_CTRL0_WM1_ON (IMG_UINT64_C(0x0000000000040000))
- #define VHA_CR_SYS_CLK_CTRL0_WM1_AUTO (IMG_UINT64_C(0x0000000000080000))
- #define VHA_CR_SYS_CLK_CTRL0_WM0_SHIFT (16U)
- #define VHA_CR_SYS_CLK_CTRL0_WM0_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFCFFFF))
- #define VHA_CR_SYS_CLK_CTRL0_WM0_OFF (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_SYS_CLK_CTRL0_WM0_ON (IMG_UINT64_C(0x0000000000010000))
- #define VHA_CR_SYS_CLK_CTRL0_WM0_AUTO (IMG_UINT64_C(0x0000000000020000))
- #define VHA_CR_SYS_CLK_CTRL0_INTERCONNECT_SHIFT (10U)
- #define VHA_CR_SYS_CLK_CTRL0_INTERCONNECT_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF3FF))
- #define VHA_CR_SYS_CLK_CTRL0_INTERCONNECT_OFF (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_SYS_CLK_CTRL0_INTERCONNECT_ON (IMG_UINT64_C(0x0000000000000400))
- #define VHA_CR_SYS_CLK_CTRL0_INTERCONNECT_AUTO (IMG_UINT64_C(0x0000000000000800))
- #define VHA_CR_SYS_CLK_CTRL0_AXI_SHIFT (8U)
- #define VHA_CR_SYS_CLK_CTRL0_AXI_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFCFF))
- #define VHA_CR_SYS_CLK_CTRL0_AXI_OFF (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_SYS_CLK_CTRL0_AXI_ON (IMG_UINT64_C(0x0000000000000100))
- #define VHA_CR_SYS_CLK_CTRL0_AXI_AUTO (IMG_UINT64_C(0x0000000000000200))
- #define VHA_CR_SYS_CLK_CTRL0_SLC_SHIFT (6U)
- #define VHA_CR_SYS_CLK_CTRL0_SLC_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFF3F))
- #define VHA_CR_SYS_CLK_CTRL0_SLC_OFF (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_SYS_CLK_CTRL0_SLC_ON (IMG_UINT64_C(0x0000000000000040))
- #define VHA_CR_SYS_CLK_CTRL0_SLC_AUTO (IMG_UINT64_C(0x0000000000000080))
- #define VHA_CR_SYS_CLK_CTRL0_LSYNC_SHIFT (4U)
- #define VHA_CR_SYS_CLK_CTRL0_LSYNC_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFCF))
- #define VHA_CR_SYS_CLK_CTRL0_LSYNC_OFF (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_SYS_CLK_CTRL0_LSYNC_ON (IMG_UINT64_C(0x0000000000000010))
- #define VHA_CR_SYS_CLK_CTRL0_LSYNC_AUTO (IMG_UINT64_C(0x0000000000000020))
- #define VHA_CR_SYS_CLK_CTRL0_SOCM_SHIFT (2U)
- #define VHA_CR_SYS_CLK_CTRL0_SOCM_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF3))
- #define VHA_CR_SYS_CLK_CTRL0_SOCM_OFF (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_SYS_CLK_CTRL0_SOCM_ON (IMG_UINT64_C(0x0000000000000004))
- #define VHA_CR_SYS_CLK_CTRL0_SOCM_AUTO (IMG_UINT64_C(0x0000000000000008))
- #define VHA_CR_SYS_CLK_CTRL0_REGBANK_SHIFT (0U)
- #define VHA_CR_SYS_CLK_CTRL0_REGBANK_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFC))
- #define VHA_CR_SYS_CLK_CTRL0_REGBANK_ON (IMG_UINT64_C(0x0000000000000001))
- #define VHA_CR_SYS_CLK_CTRL0_REGBANK_AUTO (IMG_UINT64_C(0x0000000000000002))
- /*
- Clock is gated and the module is inactive */
- #define VHA_CR_SYS_CLK_STATUS0_MODE_GATED (0x00000000U)
- /*
- Clock is running */
- #define VHA_CR_SYS_CLK_STATUS0_MODE_RUNNING (0x00000001U)
- /*
- Register VHA_CR_SYS_CLK_STATUS0
- */
- #define VHA_CR_SYS_CLK_STATUS0 (0x0208U)
- #define VHA_CR_SYS_CLK_STATUS0_MASKFULL (IMG_UINT64_C(0x00000000FFFFFF3F))
- #define VHA_CR_SYS_CLK_STATUS0_CORE7_SHIFT (31U)
- #define VHA_CR_SYS_CLK_STATUS0_CORE7_CLRMSK (IMG_UINT64_C(0XFFFFFFFF7FFFFFFF))
- #define VHA_CR_SYS_CLK_STATUS0_CORE7_GATED (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_SYS_CLK_STATUS0_CORE7_RUNNING (IMG_UINT64_C(0x0000000080000000))
- #define VHA_CR_SYS_CLK_STATUS0_CORE6_SHIFT (30U)
- #define VHA_CR_SYS_CLK_STATUS0_CORE6_CLRMSK (IMG_UINT64_C(0XFFFFFFFFBFFFFFFF))
- #define VHA_CR_SYS_CLK_STATUS0_CORE6_GATED (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_SYS_CLK_STATUS0_CORE6_RUNNING (IMG_UINT64_C(0x0000000040000000))
- #define VHA_CR_SYS_CLK_STATUS0_CORE5_SHIFT (29U)
- #define VHA_CR_SYS_CLK_STATUS0_CORE5_CLRMSK (IMG_UINT64_C(0XFFFFFFFFDFFFFFFF))
- #define VHA_CR_SYS_CLK_STATUS0_CORE5_GATED (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_SYS_CLK_STATUS0_CORE5_RUNNING (IMG_UINT64_C(0x0000000020000000))
- #define VHA_CR_SYS_CLK_STATUS0_CORE4_SHIFT (28U)
- #define VHA_CR_SYS_CLK_STATUS0_CORE4_CLRMSK (IMG_UINT64_C(0XFFFFFFFFEFFFFFFF))
- #define VHA_CR_SYS_CLK_STATUS0_CORE4_GATED (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_SYS_CLK_STATUS0_CORE4_RUNNING (IMG_UINT64_C(0x0000000010000000))
- #define VHA_CR_SYS_CLK_STATUS0_CORE3_SHIFT (27U)
- #define VHA_CR_SYS_CLK_STATUS0_CORE3_CLRMSK (IMG_UINT64_C(0XFFFFFFFFF7FFFFFF))
- #define VHA_CR_SYS_CLK_STATUS0_CORE3_GATED (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_SYS_CLK_STATUS0_CORE3_RUNNING (IMG_UINT64_C(0x0000000008000000))
- #define VHA_CR_SYS_CLK_STATUS0_CORE2_SHIFT (26U)
- #define VHA_CR_SYS_CLK_STATUS0_CORE2_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFBFFFFFF))
- #define VHA_CR_SYS_CLK_STATUS0_CORE2_GATED (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_SYS_CLK_STATUS0_CORE2_RUNNING (IMG_UINT64_C(0x0000000004000000))
- #define VHA_CR_SYS_CLK_STATUS0_CORE1_SHIFT (25U)
- #define VHA_CR_SYS_CLK_STATUS0_CORE1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFDFFFFFF))
- #define VHA_CR_SYS_CLK_STATUS0_CORE1_GATED (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_SYS_CLK_STATUS0_CORE1_RUNNING (IMG_UINT64_C(0x0000000002000000))
- #define VHA_CR_SYS_CLK_STATUS0_CORE0_SHIFT (24U)
- #define VHA_CR_SYS_CLK_STATUS0_CORE0_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFEFFFFFF))
- #define VHA_CR_SYS_CLK_STATUS0_CORE0_GATED (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_SYS_CLK_STATUS0_CORE0_RUNNING (IMG_UINT64_C(0x0000000001000000))
- #define VHA_CR_SYS_CLK_STATUS0_NOC7_SHIFT (23U)
- #define VHA_CR_SYS_CLK_STATUS0_NOC7_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF7FFFFF))
- #define VHA_CR_SYS_CLK_STATUS0_NOC7_GATED (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_SYS_CLK_STATUS0_NOC7_RUNNING (IMG_UINT64_C(0x0000000000800000))
- #define VHA_CR_SYS_CLK_STATUS0_NOC6_SHIFT (22U)
- #define VHA_CR_SYS_CLK_STATUS0_NOC6_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFBFFFFF))
- #define VHA_CR_SYS_CLK_STATUS0_NOC6_GATED (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_SYS_CLK_STATUS0_NOC6_RUNNING (IMG_UINT64_C(0x0000000000400000))
- #define VHA_CR_SYS_CLK_STATUS0_NOC5_SHIFT (21U)
- #define VHA_CR_SYS_CLK_STATUS0_NOC5_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFDFFFFF))
- #define VHA_CR_SYS_CLK_STATUS0_NOC5_GATED (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_SYS_CLK_STATUS0_NOC5_RUNNING (IMG_UINT64_C(0x0000000000200000))
- #define VHA_CR_SYS_CLK_STATUS0_NOC4_SHIFT (20U)
- #define VHA_CR_SYS_CLK_STATUS0_NOC4_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFEFFFFF))
- #define VHA_CR_SYS_CLK_STATUS0_NOC4_GATED (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_SYS_CLK_STATUS0_NOC4_RUNNING (IMG_UINT64_C(0x0000000000100000))
- #define VHA_CR_SYS_CLK_STATUS0_NOC3_SHIFT (19U)
- #define VHA_CR_SYS_CLK_STATUS0_NOC3_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF7FFFF))
- #define VHA_CR_SYS_CLK_STATUS0_NOC3_GATED (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_SYS_CLK_STATUS0_NOC3_RUNNING (IMG_UINT64_C(0x0000000000080000))
- #define VHA_CR_SYS_CLK_STATUS0_NOC2_SHIFT (18U)
- #define VHA_CR_SYS_CLK_STATUS0_NOC2_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFBFFFF))
- #define VHA_CR_SYS_CLK_STATUS0_NOC2_GATED (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_SYS_CLK_STATUS0_NOC2_RUNNING (IMG_UINT64_C(0x0000000000040000))
- #define VHA_CR_SYS_CLK_STATUS0_NOC1_SHIFT (17U)
- #define VHA_CR_SYS_CLK_STATUS0_NOC1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFDFFFF))
- #define VHA_CR_SYS_CLK_STATUS0_NOC1_GATED (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_SYS_CLK_STATUS0_NOC1_RUNNING (IMG_UINT64_C(0x0000000000020000))
- #define VHA_CR_SYS_CLK_STATUS0_NOC0_SHIFT (16U)
- #define VHA_CR_SYS_CLK_STATUS0_NOC0_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFEFFFF))
- #define VHA_CR_SYS_CLK_STATUS0_NOC0_GATED (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_SYS_CLK_STATUS0_NOC0_RUNNING (IMG_UINT64_C(0x0000000000010000))
- #define VHA_CR_SYS_CLK_STATUS0_WM7_SHIFT (15U)
- #define VHA_CR_SYS_CLK_STATUS0_WM7_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF7FFF))
- #define VHA_CR_SYS_CLK_STATUS0_WM7_GATED (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_SYS_CLK_STATUS0_WM7_RUNNING (IMG_UINT64_C(0x0000000000008000))
- #define VHA_CR_SYS_CLK_STATUS0_WM6_SHIFT (14U)
- #define VHA_CR_SYS_CLK_STATUS0_WM6_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFBFFF))
- #define VHA_CR_SYS_CLK_STATUS0_WM6_GATED (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_SYS_CLK_STATUS0_WM6_RUNNING (IMG_UINT64_C(0x0000000000004000))
- #define VHA_CR_SYS_CLK_STATUS0_WM5_SHIFT (13U)
- #define VHA_CR_SYS_CLK_STATUS0_WM5_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFDFFF))
- #define VHA_CR_SYS_CLK_STATUS0_WM5_GATED (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_SYS_CLK_STATUS0_WM5_RUNNING (IMG_UINT64_C(0x0000000000002000))
- #define VHA_CR_SYS_CLK_STATUS0_WM4_SHIFT (12U)
- #define VHA_CR_SYS_CLK_STATUS0_WM4_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFEFFF))
- #define VHA_CR_SYS_CLK_STATUS0_WM4_GATED (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_SYS_CLK_STATUS0_WM4_RUNNING (IMG_UINT64_C(0x0000000000001000))
- #define VHA_CR_SYS_CLK_STATUS0_WM3_SHIFT (11U)
- #define VHA_CR_SYS_CLK_STATUS0_WM3_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF7FF))
- #define VHA_CR_SYS_CLK_STATUS0_WM3_GATED (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_SYS_CLK_STATUS0_WM3_RUNNING (IMG_UINT64_C(0x0000000000000800))
- #define VHA_CR_SYS_CLK_STATUS0_WM2_SHIFT (10U)
- #define VHA_CR_SYS_CLK_STATUS0_WM2_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFBFF))
- #define VHA_CR_SYS_CLK_STATUS0_WM2_GATED (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_SYS_CLK_STATUS0_WM2_RUNNING (IMG_UINT64_C(0x0000000000000400))
- #define VHA_CR_SYS_CLK_STATUS0_WM1_SHIFT (9U)
- #define VHA_CR_SYS_CLK_STATUS0_WM1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFDFF))
- #define VHA_CR_SYS_CLK_STATUS0_WM1_GATED (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_SYS_CLK_STATUS0_WM1_RUNNING (IMG_UINT64_C(0x0000000000000200))
- #define VHA_CR_SYS_CLK_STATUS0_WM0_SHIFT (8U)
- #define VHA_CR_SYS_CLK_STATUS0_WM0_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFEFF))
- #define VHA_CR_SYS_CLK_STATUS0_WM0_GATED (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_SYS_CLK_STATUS0_WM0_RUNNING (IMG_UINT64_C(0x0000000000000100))
- #define VHA_CR_SYS_CLK_STATUS0_INTERCONNECT_SHIFT (5U)
- #define VHA_CR_SYS_CLK_STATUS0_INTERCONNECT_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFDF))
- #define VHA_CR_SYS_CLK_STATUS0_INTERCONNECT_GATED (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_SYS_CLK_STATUS0_INTERCONNECT_RUNNING (IMG_UINT64_C(0x0000000000000020))
- #define VHA_CR_SYS_CLK_STATUS0_AXI_SHIFT (4U)
- #define VHA_CR_SYS_CLK_STATUS0_AXI_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFEF))
- #define VHA_CR_SYS_CLK_STATUS0_AXI_GATED (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_SYS_CLK_STATUS0_AXI_RUNNING (IMG_UINT64_C(0x0000000000000010))
- #define VHA_CR_SYS_CLK_STATUS0_SLC_SHIFT (3U)
- #define VHA_CR_SYS_CLK_STATUS0_SLC_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF7))
- #define VHA_CR_SYS_CLK_STATUS0_SLC_GATED (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_SYS_CLK_STATUS0_SLC_RUNNING (IMG_UINT64_C(0x0000000000000008))
- #define VHA_CR_SYS_CLK_STATUS0_LSYNC_SHIFT (2U)
- #define VHA_CR_SYS_CLK_STATUS0_LSYNC_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFB))
- #define VHA_CR_SYS_CLK_STATUS0_LSYNC_GATED (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_SYS_CLK_STATUS0_LSYNC_RUNNING (IMG_UINT64_C(0x0000000000000004))
- #define VHA_CR_SYS_CLK_STATUS0_SOCM_SHIFT (1U)
- #define VHA_CR_SYS_CLK_STATUS0_SOCM_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFD))
- #define VHA_CR_SYS_CLK_STATUS0_SOCM_GATED (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_SYS_CLK_STATUS0_SOCM_RUNNING (IMG_UINT64_C(0x0000000000000002))
- #define VHA_CR_SYS_CLK_STATUS0_REGBANK_SHIFT (0U)
- #define VHA_CR_SYS_CLK_STATUS0_REGBANK_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
- #define VHA_CR_SYS_CLK_STATUS0_REGBANK_GATED (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_SYS_CLK_STATUS0_REGBANK_RUNNING (IMG_UINT64_C(0x0000000000000001))
- /*
- Register VHA_CR_SYS_RESET_CTRL
- */
- #define VHA_CR_SYS_RESET_CTRL (0x0210U)
- #define VHA_CR_SYS_RESET_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000FFFF1E))
- #define VHA_CR_SYS_RESET_CTRL_CORE_SHIFT (16U)
- #define VHA_CR_SYS_RESET_CTRL_CORE_CLRMSK (0XFF00FFFFU)
- #define VHA_CR_SYS_RESET_CTRL_WM_SHIFT (8U)
- #define VHA_CR_SYS_RESET_CTRL_WM_CLRMSK (0XFFFF00FFU)
- #define VHA_CR_SYS_RESET_CTRL_INTERCONNECT_SHIFT (4U)
- #define VHA_CR_SYS_RESET_CTRL_INTERCONNECT_CLRMSK (0XFFFFFFEFU)
- #define VHA_CR_SYS_RESET_CTRL_INTERCONNECT_EN (0X00000010U)
- #define VHA_CR_SYS_RESET_CTRL_SLC_SHIFT (3U)
- #define VHA_CR_SYS_RESET_CTRL_SLC_CLRMSK (0XFFFFFFF7U)
- #define VHA_CR_SYS_RESET_CTRL_SLC_EN (0X00000008U)
- #define VHA_CR_SYS_RESET_CTRL_MH_SHIFT (2U)
- #define VHA_CR_SYS_RESET_CTRL_MH_CLRMSK (0XFFFFFFFBU)
- #define VHA_CR_SYS_RESET_CTRL_MH_EN (0X00000004U)
- #define VHA_CR_SYS_RESET_CTRL_REGBANK_SHIFT (1U)
- #define VHA_CR_SYS_RESET_CTRL_REGBANK_CLRMSK (0XFFFFFFFDU)
- #define VHA_CR_SYS_RESET_CTRL_REGBANK_EN (0X00000002U)
- /*
- Register VHA_CR_HOST_EVENT_SOURCE
- */
- #define VHA_CR_HOST_EVENT_SOURCE (0x0218U)
- #define VHA_CR_HOST_EVENT_SOURCE_MASKFULL (IMG_UINT64_C(0x00000000FFFFFF01))
- #define VHA_CR_HOST_EVENT_SOURCE_IC_SHIFT (24U)
- #define VHA_CR_HOST_EVENT_SOURCE_IC_CLRMSK (0X00FFFFFFU)
- #define VHA_CR_HOST_EVENT_SOURCE_CORE_SHIFT (16U)
- #define VHA_CR_HOST_EVENT_SOURCE_CORE_CLRMSK (0XFF00FFFFU)
- #define VHA_CR_HOST_EVENT_SOURCE_WM_SHIFT (8U)
- #define VHA_CR_HOST_EVENT_SOURCE_WM_CLRMSK (0XFFFF00FFU)
- #define VHA_CR_HOST_EVENT_SOURCE_SYS_SHIFT (0U)
- #define VHA_CR_HOST_EVENT_SOURCE_SYS_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_HOST_EVENT_SOURCE_SYS_EN (0X00000001U)
- #define VHA_CR_SYS_EVENT_TYPE_LOGIC_ERROR_SHIFT (30U)
- #define VHA_CR_SYS_EVENT_TYPE_LOGIC_ERROR_CLRMSK (0XBFFFFFFFU)
- #define VHA_CR_SYS_EVENT_TYPE_LOGIC_ERROR_EN (0X40000000U)
- #define VHA_CR_SYS_EVENT_TYPE_RAM_CORRECTION_SHIFT (29U)
- #define VHA_CR_SYS_EVENT_TYPE_RAM_CORRECTION_CLRMSK (0XDFFFFFFFU)
- #define VHA_CR_SYS_EVENT_TYPE_RAM_CORRECTION_EN (0X20000000U)
- #define VHA_CR_SYS_EVENT_TYPE_RAM_DETECTION_SHIFT (28U)
- #define VHA_CR_SYS_EVENT_TYPE_RAM_DETECTION_CLRMSK (0XEFFFFFFFU)
- #define VHA_CR_SYS_EVENT_TYPE_RAM_DETECTION_EN (0X10000000U)
- #define VHA_CR_SYS_EVENT_TYPE_LSYNC_INV_REQ_SHIFT (27U)
- #define VHA_CR_SYS_EVENT_TYPE_LSYNC_INV_REQ_CLRMSK (0XF7FFFFFFU)
- #define VHA_CR_SYS_EVENT_TYPE_LSYNC_INV_REQ_EN (0X08000000U)
- #define VHA_CR_SYS_EVENT_TYPE_SOCM_SCRUB_DONE_SHIFT (26U)
- #define VHA_CR_SYS_EVENT_TYPE_SOCM_SCRUB_DONE_CLRMSK (0XFBFFFFFFU)
- #define VHA_CR_SYS_EVENT_TYPE_SOCM_SCRUB_DONE_EN (0X04000000U)
- #define VHA_CR_SYS_EVENT_TYPE_AXI_MEMORY_PARITY_ERROR_SHIFT (21U)
- #define VHA_CR_SYS_EVENT_TYPE_AXI_MEMORY_PARITY_ERROR_CLRMSK (0XFE1FFFFFU)
- #define VHA_CR_SYS_EVENT_TYPE_SYS_MEM_WDT_SHIFT (20U)
- #define VHA_CR_SYS_EVENT_TYPE_SYS_MEM_WDT_CLRMSK (0XFFEFFFFFU)
- #define VHA_CR_SYS_EVENT_TYPE_SYS_MEM_WDT_EN (0X00100000U)
- #define VHA_CR_SYS_EVENT_TYPE_MMU_PARITY_ERROR_SHIFT (16U)
- #define VHA_CR_SYS_EVENT_TYPE_MMU_PARITY_ERROR_CLRMSK (0XFFF0FFFFU)
- #define VHA_CR_SYS_EVENT_TYPE_MMU_PAGE_FAULT_SHIFT (8U)
- #define VHA_CR_SYS_EVENT_TYPE_MMU_PAGE_FAULT_CLRMSK (0XFFFF00FFU)
- #define VHA_CR_SYS_EVENT_TYPE_AXI_ERROR_SHIFT (4U)
- #define VHA_CR_SYS_EVENT_TYPE_AXI_ERROR_CLRMSK (0XFFFFFF0FU)
- #define VHA_CR_SYS_EVENT_TYPE_RAM_INIT_DONE_SHIFT (3U)
- #define VHA_CR_SYS_EVENT_TYPE_RAM_INIT_DONE_CLRMSK (0XFFFFFFF7U)
- #define VHA_CR_SYS_EVENT_TYPE_RAM_INIT_DONE_EN (0X00000008U)
- #define VHA_CR_SYS_EVENT_TYPE_MEMBUS_RESET_DONE_SHIFT (2U)
- #define VHA_CR_SYS_EVENT_TYPE_MEMBUS_RESET_DONE_CLRMSK (0XFFFFFFFBU)
- #define VHA_CR_SYS_EVENT_TYPE_MEMBUS_RESET_DONE_EN (0X00000004U)
- #define VHA_CR_SYS_EVENT_TYPE_POWER_ABORT_SHIFT (1U)
- #define VHA_CR_SYS_EVENT_TYPE_POWER_ABORT_CLRMSK (0XFFFFFFFDU)
- #define VHA_CR_SYS_EVENT_TYPE_POWER_ABORT_EN (0X00000002U)
- #define VHA_CR_SYS_EVENT_TYPE_POWER_COMPLETE_SHIFT (0U)
- #define VHA_CR_SYS_EVENT_TYPE_POWER_COMPLETE_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_SYS_EVENT_TYPE_POWER_COMPLETE_EN (0X00000001U)
- #define VHA_CR_SYS_EVENT_STATUS_TYPE_PARITY_SHIFT (31U)
- #define VHA_CR_SYS_EVENT_STATUS_TYPE_PARITY_CLRMSK (0X7FFFFFFFU)
- #define VHA_CR_SYS_EVENT_STATUS_TYPE_PARITY_EN (0X80000000U)
- #define VHA_CR_SYS_EVENT_STATUS_TYPE_LOGIC_ERROR_SHIFT (30U)
- #define VHA_CR_SYS_EVENT_STATUS_TYPE_LOGIC_ERROR_CLRMSK (0XBFFFFFFFU)
- #define VHA_CR_SYS_EVENT_STATUS_TYPE_LOGIC_ERROR_EN (0X40000000U)
- #define VHA_CR_SYS_EVENT_STATUS_TYPE_RAM_CORRECTION_SHIFT (29U)
- #define VHA_CR_SYS_EVENT_STATUS_TYPE_RAM_CORRECTION_CLRMSK (0XDFFFFFFFU)
- #define VHA_CR_SYS_EVENT_STATUS_TYPE_RAM_CORRECTION_EN (0X20000000U)
- #define VHA_CR_SYS_EVENT_STATUS_TYPE_RAM_DETECTION_SHIFT (28U)
- #define VHA_CR_SYS_EVENT_STATUS_TYPE_RAM_DETECTION_CLRMSK (0XEFFFFFFFU)
- #define VHA_CR_SYS_EVENT_STATUS_TYPE_RAM_DETECTION_EN (0X10000000U)
- #define VHA_CR_SYS_EVENT_STATUS_TYPE_LSYNC_INV_REQ_SHIFT (27U)
- #define VHA_CR_SYS_EVENT_STATUS_TYPE_LSYNC_INV_REQ_CLRMSK (0XF7FFFFFFU)
- #define VHA_CR_SYS_EVENT_STATUS_TYPE_LSYNC_INV_REQ_EN (0X08000000U)
- #define VHA_CR_SYS_EVENT_STATUS_TYPE_SOCM_SCRUB_DONE_SHIFT (26U)
- #define VHA_CR_SYS_EVENT_STATUS_TYPE_SOCM_SCRUB_DONE_CLRMSK (0XFBFFFFFFU)
- #define VHA_CR_SYS_EVENT_STATUS_TYPE_SOCM_SCRUB_DONE_EN (0X04000000U)
- #define VHA_CR_SYS_EVENT_STATUS_TYPE_AXI_MEMORY_PARITY_ERROR_SHIFT (21U)
- #define VHA_CR_SYS_EVENT_STATUS_TYPE_AXI_MEMORY_PARITY_ERROR_CLRMSK (0XFE1FFFFFU)
- #define VHA_CR_SYS_EVENT_STATUS_TYPE_SYS_MEM_WDT_SHIFT (20U)
- #define VHA_CR_SYS_EVENT_STATUS_TYPE_SYS_MEM_WDT_CLRMSK (0XFFEFFFFFU)
- #define VHA_CR_SYS_EVENT_STATUS_TYPE_SYS_MEM_WDT_EN (0X00100000U)
- #define VHA_CR_SYS_EVENT_STATUS_TYPE_MMU_PARITY_ERROR_SHIFT (16U)
- #define VHA_CR_SYS_EVENT_STATUS_TYPE_MMU_PARITY_ERROR_CLRMSK (0XFFF0FFFFU)
- #define VHA_CR_SYS_EVENT_STATUS_TYPE_MMU_PAGE_FAULT_SHIFT (8U)
- #define VHA_CR_SYS_EVENT_STATUS_TYPE_MMU_PAGE_FAULT_CLRMSK (0XFFFF00FFU)
- #define VHA_CR_SYS_EVENT_STATUS_TYPE_AXI_ERROR_SHIFT (4U)
- #define VHA_CR_SYS_EVENT_STATUS_TYPE_AXI_ERROR_CLRMSK (0XFFFFFF0FU)
- #define VHA_CR_SYS_EVENT_STATUS_TYPE_RAM_INIT_DONE_SHIFT (3U)
- #define VHA_CR_SYS_EVENT_STATUS_TYPE_RAM_INIT_DONE_CLRMSK (0XFFFFFFF7U)
- #define VHA_CR_SYS_EVENT_STATUS_TYPE_RAM_INIT_DONE_EN (0X00000008U)
- #define VHA_CR_SYS_EVENT_STATUS_TYPE_MEMBUS_RESET_DONE_SHIFT (2U)
- #define VHA_CR_SYS_EVENT_STATUS_TYPE_MEMBUS_RESET_DONE_CLRMSK (0XFFFFFFFBU)
- #define VHA_CR_SYS_EVENT_STATUS_TYPE_MEMBUS_RESET_DONE_EN (0X00000004U)
- #define VHA_CR_SYS_EVENT_STATUS_TYPE_POWER_ABORT_SHIFT (1U)
- #define VHA_CR_SYS_EVENT_STATUS_TYPE_POWER_ABORT_CLRMSK (0XFFFFFFFDU)
- #define VHA_CR_SYS_EVENT_STATUS_TYPE_POWER_ABORT_EN (0X00000002U)
- #define VHA_CR_SYS_EVENT_STATUS_TYPE_POWER_COMPLETE_SHIFT (0U)
- #define VHA_CR_SYS_EVENT_STATUS_TYPE_POWER_COMPLETE_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_SYS_EVENT_STATUS_TYPE_POWER_COMPLETE_EN (0X00000001U)
- /*
- Register VHA_CR_SYS_EVENT_ENABLE
- */
- #define VHA_CR_SYS_EVENT_ENABLE (0x0220U)
- #define VHA_CR_SYS_EVENT_ENABLE_MASKFULL (IMG_UINT64_C(0x000000007DFFFFFF))
- #define VHA_CR_SYS_EVENT_ENABLE_LOGIC_ERROR_SHIFT (30U)
- #define VHA_CR_SYS_EVENT_ENABLE_LOGIC_ERROR_CLRMSK (0XBFFFFFFFU)
- #define VHA_CR_SYS_EVENT_ENABLE_LOGIC_ERROR_EN (0X40000000U)
- #define VHA_CR_SYS_EVENT_ENABLE_RAM_CORRECTION_SHIFT (29U)
- #define VHA_CR_SYS_EVENT_ENABLE_RAM_CORRECTION_CLRMSK (0XDFFFFFFFU)
- #define VHA_CR_SYS_EVENT_ENABLE_RAM_CORRECTION_EN (0X20000000U)
- #define VHA_CR_SYS_EVENT_ENABLE_RAM_DETECTION_SHIFT (28U)
- #define VHA_CR_SYS_EVENT_ENABLE_RAM_DETECTION_CLRMSK (0XEFFFFFFFU)
- #define VHA_CR_SYS_EVENT_ENABLE_RAM_DETECTION_EN (0X10000000U)
- #define VHA_CR_SYS_EVENT_ENABLE_LSYNC_INV_REQ_SHIFT (27U)
- #define VHA_CR_SYS_EVENT_ENABLE_LSYNC_INV_REQ_CLRMSK (0XF7FFFFFFU)
- #define VHA_CR_SYS_EVENT_ENABLE_LSYNC_INV_REQ_EN (0X08000000U)
- #define VHA_CR_SYS_EVENT_ENABLE_SOCM_SCRUB_DONE_SHIFT (26U)
- #define VHA_CR_SYS_EVENT_ENABLE_SOCM_SCRUB_DONE_CLRMSK (0XFBFFFFFFU)
- #define VHA_CR_SYS_EVENT_ENABLE_SOCM_SCRUB_DONE_EN (0X04000000U)
- #define VHA_CR_SYS_EVENT_ENABLE_AXI_MEMORY_PARITY_ERROR_SHIFT (21U)
- #define VHA_CR_SYS_EVENT_ENABLE_AXI_MEMORY_PARITY_ERROR_CLRMSK (0XFE1FFFFFU)
- #define VHA_CR_SYS_EVENT_ENABLE_SYS_MEM_WDT_SHIFT (20U)
- #define VHA_CR_SYS_EVENT_ENABLE_SYS_MEM_WDT_CLRMSK (0XFFEFFFFFU)
- #define VHA_CR_SYS_EVENT_ENABLE_SYS_MEM_WDT_EN (0X00100000U)
- #define VHA_CR_SYS_EVENT_ENABLE_MMU_PARITY_ERROR_SHIFT (16U)
- #define VHA_CR_SYS_EVENT_ENABLE_MMU_PARITY_ERROR_CLRMSK (0XFFF0FFFFU)
- #define VHA_CR_SYS_EVENT_ENABLE_MMU_PAGE_FAULT_SHIFT (8U)
- #define VHA_CR_SYS_EVENT_ENABLE_MMU_PAGE_FAULT_CLRMSK (0XFFFF00FFU)
- #define VHA_CR_SYS_EVENT_ENABLE_AXI_ERROR_SHIFT (4U)
- #define VHA_CR_SYS_EVENT_ENABLE_AXI_ERROR_CLRMSK (0XFFFFFF0FU)
- #define VHA_CR_SYS_EVENT_ENABLE_RAM_INIT_DONE_SHIFT (3U)
- #define VHA_CR_SYS_EVENT_ENABLE_RAM_INIT_DONE_CLRMSK (0XFFFFFFF7U)
- #define VHA_CR_SYS_EVENT_ENABLE_RAM_INIT_DONE_EN (0X00000008U)
- #define VHA_CR_SYS_EVENT_ENABLE_MEMBUS_RESET_DONE_SHIFT (2U)
- #define VHA_CR_SYS_EVENT_ENABLE_MEMBUS_RESET_DONE_CLRMSK (0XFFFFFFFBU)
- #define VHA_CR_SYS_EVENT_ENABLE_MEMBUS_RESET_DONE_EN (0X00000004U)
- #define VHA_CR_SYS_EVENT_ENABLE_POWER_ABORT_SHIFT (1U)
- #define VHA_CR_SYS_EVENT_ENABLE_POWER_ABORT_CLRMSK (0XFFFFFFFDU)
- #define VHA_CR_SYS_EVENT_ENABLE_POWER_ABORT_EN (0X00000002U)
- #define VHA_CR_SYS_EVENT_ENABLE_POWER_COMPLETE_SHIFT (0U)
- #define VHA_CR_SYS_EVENT_ENABLE_POWER_COMPLETE_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_SYS_EVENT_ENABLE_POWER_COMPLETE_EN (0X00000001U)
- /*
- Register VHA_CR_SYS_EVENT_STATUS
- */
- #define VHA_CR_SYS_EVENT_STATUS (0x0228U)
- #define VHA_CR_SYS_EVENT_STATUS_MASKFULL (IMG_UINT64_C(0x00000000FDFFFFFF))
- #define VHA_CR_SYS_EVENT_STATUS_PARITY_SHIFT (31U)
- #define VHA_CR_SYS_EVENT_STATUS_PARITY_CLRMSK (0X7FFFFFFFU)
- #define VHA_CR_SYS_EVENT_STATUS_PARITY_EN (0X80000000U)
- #define VHA_CR_SYS_EVENT_STATUS_LOGIC_ERROR_SHIFT (30U)
- #define VHA_CR_SYS_EVENT_STATUS_LOGIC_ERROR_CLRMSK (0XBFFFFFFFU)
- #define VHA_CR_SYS_EVENT_STATUS_LOGIC_ERROR_EN (0X40000000U)
- #define VHA_CR_SYS_EVENT_STATUS_RAM_CORRECTION_SHIFT (29U)
- #define VHA_CR_SYS_EVENT_STATUS_RAM_CORRECTION_CLRMSK (0XDFFFFFFFU)
- #define VHA_CR_SYS_EVENT_STATUS_RAM_CORRECTION_EN (0X20000000U)
- #define VHA_CR_SYS_EVENT_STATUS_RAM_DETECTION_SHIFT (28U)
- #define VHA_CR_SYS_EVENT_STATUS_RAM_DETECTION_CLRMSK (0XEFFFFFFFU)
- #define VHA_CR_SYS_EVENT_STATUS_RAM_DETECTION_EN (0X10000000U)
- #define VHA_CR_SYS_EVENT_STATUS_LSYNC_INV_REQ_SHIFT (27U)
- #define VHA_CR_SYS_EVENT_STATUS_LSYNC_INV_REQ_CLRMSK (0XF7FFFFFFU)
- #define VHA_CR_SYS_EVENT_STATUS_LSYNC_INV_REQ_EN (0X08000000U)
- #define VHA_CR_SYS_EVENT_STATUS_SOCM_SCRUB_DONE_SHIFT (26U)
- #define VHA_CR_SYS_EVENT_STATUS_SOCM_SCRUB_DONE_CLRMSK (0XFBFFFFFFU)
- #define VHA_CR_SYS_EVENT_STATUS_SOCM_SCRUB_DONE_EN (0X04000000U)
- #define VHA_CR_SYS_EVENT_STATUS_AXI_MEMORY_PARITY_ERROR_SHIFT (21U)
- #define VHA_CR_SYS_EVENT_STATUS_AXI_MEMORY_PARITY_ERROR_CLRMSK (0XFE1FFFFFU)
- #define VHA_CR_SYS_EVENT_STATUS_SYS_MEM_WDT_SHIFT (20U)
- #define VHA_CR_SYS_EVENT_STATUS_SYS_MEM_WDT_CLRMSK (0XFFEFFFFFU)
- #define VHA_CR_SYS_EVENT_STATUS_SYS_MEM_WDT_EN (0X00100000U)
- #define VHA_CR_SYS_EVENT_STATUS_MMU_PARITY_ERROR_SHIFT (16U)
- #define VHA_CR_SYS_EVENT_STATUS_MMU_PARITY_ERROR_CLRMSK (0XFFF0FFFFU)
- #define VHA_CR_SYS_EVENT_STATUS_MMU_PAGE_FAULT_SHIFT (8U)
- #define VHA_CR_SYS_EVENT_STATUS_MMU_PAGE_FAULT_CLRMSK (0XFFFF00FFU)
- #define VHA_CR_SYS_EVENT_STATUS_AXI_ERROR_SHIFT (4U)
- #define VHA_CR_SYS_EVENT_STATUS_AXI_ERROR_CLRMSK (0XFFFFFF0FU)
- #define VHA_CR_SYS_EVENT_STATUS_RAM_INIT_DONE_SHIFT (3U)
- #define VHA_CR_SYS_EVENT_STATUS_RAM_INIT_DONE_CLRMSK (0XFFFFFFF7U)
- #define VHA_CR_SYS_EVENT_STATUS_RAM_INIT_DONE_EN (0X00000008U)
- #define VHA_CR_SYS_EVENT_STATUS_MEMBUS_RESET_DONE_SHIFT (2U)
- #define VHA_CR_SYS_EVENT_STATUS_MEMBUS_RESET_DONE_CLRMSK (0XFFFFFFFBU)
- #define VHA_CR_SYS_EVENT_STATUS_MEMBUS_RESET_DONE_EN (0X00000004U)
- #define VHA_CR_SYS_EVENT_STATUS_POWER_ABORT_SHIFT (1U)
- #define VHA_CR_SYS_EVENT_STATUS_POWER_ABORT_CLRMSK (0XFFFFFFFDU)
- #define VHA_CR_SYS_EVENT_STATUS_POWER_ABORT_EN (0X00000002U)
- #define VHA_CR_SYS_EVENT_STATUS_POWER_COMPLETE_SHIFT (0U)
- #define VHA_CR_SYS_EVENT_STATUS_POWER_COMPLETE_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_SYS_EVENT_STATUS_POWER_COMPLETE_EN (0X00000001U)
- /*
- Register VHA_CR_SYS_EVENT_STATUS_DISABLE
- */
- #define VHA_CR_SYS_EVENT_STATUS_DISABLE (0x0290U)
- #define VHA_CR_SYS_EVENT_STATUS_DISABLE_MASKFULL (IMG_UINT64_C(0x000000007DFFFFFF))
- #define VHA_CR_SYS_EVENT_STATUS_DISABLE_LOGIC_ERROR_SHIFT (30U)
- #define VHA_CR_SYS_EVENT_STATUS_DISABLE_LOGIC_ERROR_CLRMSK (0XBFFFFFFFU)
- #define VHA_CR_SYS_EVENT_STATUS_DISABLE_LOGIC_ERROR_EN (0X40000000U)
- #define VHA_CR_SYS_EVENT_STATUS_DISABLE_RAM_CORRECTION_SHIFT (29U)
- #define VHA_CR_SYS_EVENT_STATUS_DISABLE_RAM_CORRECTION_CLRMSK (0XDFFFFFFFU)
- #define VHA_CR_SYS_EVENT_STATUS_DISABLE_RAM_CORRECTION_EN (0X20000000U)
- #define VHA_CR_SYS_EVENT_STATUS_DISABLE_RAM_DETECTION_SHIFT (28U)
- #define VHA_CR_SYS_EVENT_STATUS_DISABLE_RAM_DETECTION_CLRMSK (0XEFFFFFFFU)
- #define VHA_CR_SYS_EVENT_STATUS_DISABLE_RAM_DETECTION_EN (0X10000000U)
- #define VHA_CR_SYS_EVENT_STATUS_DISABLE_LSYNC_INV_REQ_SHIFT (27U)
- #define VHA_CR_SYS_EVENT_STATUS_DISABLE_LSYNC_INV_REQ_CLRMSK (0XF7FFFFFFU)
- #define VHA_CR_SYS_EVENT_STATUS_DISABLE_LSYNC_INV_REQ_EN (0X08000000U)
- #define VHA_CR_SYS_EVENT_STATUS_DISABLE_SOCM_SCRUB_DONE_SHIFT (26U)
- #define VHA_CR_SYS_EVENT_STATUS_DISABLE_SOCM_SCRUB_DONE_CLRMSK (0XFBFFFFFFU)
- #define VHA_CR_SYS_EVENT_STATUS_DISABLE_SOCM_SCRUB_DONE_EN (0X04000000U)
- #define VHA_CR_SYS_EVENT_STATUS_DISABLE_AXI_MEMORY_PARITY_ERROR_SHIFT (21U)
- #define VHA_CR_SYS_EVENT_STATUS_DISABLE_AXI_MEMORY_PARITY_ERROR_CLRMSK (0XFE1FFFFFU)
- #define VHA_CR_SYS_EVENT_STATUS_DISABLE_SYS_MEM_WDT_SHIFT (20U)
- #define VHA_CR_SYS_EVENT_STATUS_DISABLE_SYS_MEM_WDT_CLRMSK (0XFFEFFFFFU)
- #define VHA_CR_SYS_EVENT_STATUS_DISABLE_SYS_MEM_WDT_EN (0X00100000U)
- #define VHA_CR_SYS_EVENT_STATUS_DISABLE_MMU_PARITY_ERROR_SHIFT (16U)
- #define VHA_CR_SYS_EVENT_STATUS_DISABLE_MMU_PARITY_ERROR_CLRMSK (0XFFF0FFFFU)
- #define VHA_CR_SYS_EVENT_STATUS_DISABLE_MMU_PAGE_FAULT_SHIFT (8U)
- #define VHA_CR_SYS_EVENT_STATUS_DISABLE_MMU_PAGE_FAULT_CLRMSK (0XFFFF00FFU)
- #define VHA_CR_SYS_EVENT_STATUS_DISABLE_AXI_ERROR_SHIFT (4U)
- #define VHA_CR_SYS_EVENT_STATUS_DISABLE_AXI_ERROR_CLRMSK (0XFFFFFF0FU)
- #define VHA_CR_SYS_EVENT_STATUS_DISABLE_RAM_INIT_DONE_SHIFT (3U)
- #define VHA_CR_SYS_EVENT_STATUS_DISABLE_RAM_INIT_DONE_CLRMSK (0XFFFFFFF7U)
- #define VHA_CR_SYS_EVENT_STATUS_DISABLE_RAM_INIT_DONE_EN (0X00000008U)
- #define VHA_CR_SYS_EVENT_STATUS_DISABLE_MEMBUS_RESET_DONE_SHIFT (2U)
- #define VHA_CR_SYS_EVENT_STATUS_DISABLE_MEMBUS_RESET_DONE_CLRMSK (0XFFFFFFFBU)
- #define VHA_CR_SYS_EVENT_STATUS_DISABLE_MEMBUS_RESET_DONE_EN (0X00000004U)
- #define VHA_CR_SYS_EVENT_STATUS_DISABLE_POWER_ABORT_SHIFT (1U)
- #define VHA_CR_SYS_EVENT_STATUS_DISABLE_POWER_ABORT_CLRMSK (0XFFFFFFFDU)
- #define VHA_CR_SYS_EVENT_STATUS_DISABLE_POWER_ABORT_EN (0X00000002U)
- #define VHA_CR_SYS_EVENT_STATUS_DISABLE_POWER_COMPLETE_SHIFT (0U)
- #define VHA_CR_SYS_EVENT_STATUS_DISABLE_POWER_COMPLETE_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_SYS_EVENT_STATUS_DISABLE_POWER_COMPLETE_EN (0X00000001U)
- /*
- Register VHA_CR_SYS_EVENT_CLEAR
- */
- #define VHA_CR_SYS_EVENT_CLEAR (0x0230U)
- #define VHA_CR_SYS_EVENT_CLEAR_MASKFULL (IMG_UINT64_C(0x000000007DFFFFFF))
- #define VHA_CR_SYS_EVENT_CLEAR_LOGIC_ERROR_SHIFT (30U)
- #define VHA_CR_SYS_EVENT_CLEAR_LOGIC_ERROR_CLRMSK (0XBFFFFFFFU)
- #define VHA_CR_SYS_EVENT_CLEAR_LOGIC_ERROR_EN (0X40000000U)
- #define VHA_CR_SYS_EVENT_CLEAR_RAM_CORRECTION_SHIFT (29U)
- #define VHA_CR_SYS_EVENT_CLEAR_RAM_CORRECTION_CLRMSK (0XDFFFFFFFU)
- #define VHA_CR_SYS_EVENT_CLEAR_RAM_CORRECTION_EN (0X20000000U)
- #define VHA_CR_SYS_EVENT_CLEAR_RAM_DETECTION_SHIFT (28U)
- #define VHA_CR_SYS_EVENT_CLEAR_RAM_DETECTION_CLRMSK (0XEFFFFFFFU)
- #define VHA_CR_SYS_EVENT_CLEAR_RAM_DETECTION_EN (0X10000000U)
- #define VHA_CR_SYS_EVENT_CLEAR_LSYNC_INV_REQ_SHIFT (27U)
- #define VHA_CR_SYS_EVENT_CLEAR_LSYNC_INV_REQ_CLRMSK (0XF7FFFFFFU)
- #define VHA_CR_SYS_EVENT_CLEAR_LSYNC_INV_REQ_EN (0X08000000U)
- #define VHA_CR_SYS_EVENT_CLEAR_SOCM_SCRUB_DONE_SHIFT (26U)
- #define VHA_CR_SYS_EVENT_CLEAR_SOCM_SCRUB_DONE_CLRMSK (0XFBFFFFFFU)
- #define VHA_CR_SYS_EVENT_CLEAR_SOCM_SCRUB_DONE_EN (0X04000000U)
- #define VHA_CR_SYS_EVENT_CLEAR_AXI_MEMORY_PARITY_ERROR_SHIFT (21U)
- #define VHA_CR_SYS_EVENT_CLEAR_AXI_MEMORY_PARITY_ERROR_CLRMSK (0XFE1FFFFFU)
- #define VHA_CR_SYS_EVENT_CLEAR_SYS_MEM_WDT_SHIFT (20U)
- #define VHA_CR_SYS_EVENT_CLEAR_SYS_MEM_WDT_CLRMSK (0XFFEFFFFFU)
- #define VHA_CR_SYS_EVENT_CLEAR_SYS_MEM_WDT_EN (0X00100000U)
- #define VHA_CR_SYS_EVENT_CLEAR_MMU_PARITY_ERROR_SHIFT (16U)
- #define VHA_CR_SYS_EVENT_CLEAR_MMU_PARITY_ERROR_CLRMSK (0XFFF0FFFFU)
- #define VHA_CR_SYS_EVENT_CLEAR_MMU_PAGE_FAULT_SHIFT (8U)
- #define VHA_CR_SYS_EVENT_CLEAR_MMU_PAGE_FAULT_CLRMSK (0XFFFF00FFU)
- #define VHA_CR_SYS_EVENT_CLEAR_AXI_ERROR_SHIFT (4U)
- #define VHA_CR_SYS_EVENT_CLEAR_AXI_ERROR_CLRMSK (0XFFFFFF0FU)
- #define VHA_CR_SYS_EVENT_CLEAR_RAM_INIT_DONE_SHIFT (3U)
- #define VHA_CR_SYS_EVENT_CLEAR_RAM_INIT_DONE_CLRMSK (0XFFFFFFF7U)
- #define VHA_CR_SYS_EVENT_CLEAR_RAM_INIT_DONE_EN (0X00000008U)
- #define VHA_CR_SYS_EVENT_CLEAR_MEMBUS_RESET_DONE_SHIFT (2U)
- #define VHA_CR_SYS_EVENT_CLEAR_MEMBUS_RESET_DONE_CLRMSK (0XFFFFFFFBU)
- #define VHA_CR_SYS_EVENT_CLEAR_MEMBUS_RESET_DONE_EN (0X00000004U)
- #define VHA_CR_SYS_EVENT_CLEAR_POWER_ABORT_SHIFT (1U)
- #define VHA_CR_SYS_EVENT_CLEAR_POWER_ABORT_CLRMSK (0XFFFFFFFDU)
- #define VHA_CR_SYS_EVENT_CLEAR_POWER_ABORT_EN (0X00000002U)
- #define VHA_CR_SYS_EVENT_CLEAR_POWER_COMPLETE_SHIFT (0U)
- #define VHA_CR_SYS_EVENT_CLEAR_POWER_COMPLETE_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_SYS_EVENT_CLEAR_POWER_COMPLETE_EN (0X00000001U)
- /*
- Register VHA_CR_SYS_EVENT_INJECT
- */
- #define VHA_CR_SYS_EVENT_INJECT (0x0288U)
- #define VHA_CR_SYS_EVENT_INJECT_MASKFULL (IMG_UINT64_C(0x000000007DFFFFFF))
- #define VHA_CR_SYS_EVENT_INJECT_LOGIC_ERROR_SHIFT (30U)
- #define VHA_CR_SYS_EVENT_INJECT_LOGIC_ERROR_CLRMSK (0XBFFFFFFFU)
- #define VHA_CR_SYS_EVENT_INJECT_LOGIC_ERROR_EN (0X40000000U)
- #define VHA_CR_SYS_EVENT_INJECT_RAM_CORRECTION_SHIFT (29U)
- #define VHA_CR_SYS_EVENT_INJECT_RAM_CORRECTION_CLRMSK (0XDFFFFFFFU)
- #define VHA_CR_SYS_EVENT_INJECT_RAM_CORRECTION_EN (0X20000000U)
- #define VHA_CR_SYS_EVENT_INJECT_RAM_DETECTION_SHIFT (28U)
- #define VHA_CR_SYS_EVENT_INJECT_RAM_DETECTION_CLRMSK (0XEFFFFFFFU)
- #define VHA_CR_SYS_EVENT_INJECT_RAM_DETECTION_EN (0X10000000U)
- #define VHA_CR_SYS_EVENT_INJECT_LSYNC_INV_REQ_SHIFT (27U)
- #define VHA_CR_SYS_EVENT_INJECT_LSYNC_INV_REQ_CLRMSK (0XF7FFFFFFU)
- #define VHA_CR_SYS_EVENT_INJECT_LSYNC_INV_REQ_EN (0X08000000U)
- #define VHA_CR_SYS_EVENT_INJECT_SOCM_SCRUB_DONE_SHIFT (26U)
- #define VHA_CR_SYS_EVENT_INJECT_SOCM_SCRUB_DONE_CLRMSK (0XFBFFFFFFU)
- #define VHA_CR_SYS_EVENT_INJECT_SOCM_SCRUB_DONE_EN (0X04000000U)
- #define VHA_CR_SYS_EVENT_INJECT_AXI_MEMORY_PARITY_ERROR_SHIFT (21U)
- #define VHA_CR_SYS_EVENT_INJECT_AXI_MEMORY_PARITY_ERROR_CLRMSK (0XFE1FFFFFU)
- #define VHA_CR_SYS_EVENT_INJECT_SYS_MEM_WDT_SHIFT (20U)
- #define VHA_CR_SYS_EVENT_INJECT_SYS_MEM_WDT_CLRMSK (0XFFEFFFFFU)
- #define VHA_CR_SYS_EVENT_INJECT_SYS_MEM_WDT_EN (0X00100000U)
- #define VHA_CR_SYS_EVENT_INJECT_MMU_PARITY_ERROR_SHIFT (16U)
- #define VHA_CR_SYS_EVENT_INJECT_MMU_PARITY_ERROR_CLRMSK (0XFFF0FFFFU)
- #define VHA_CR_SYS_EVENT_INJECT_MMU_PAGE_FAULT_SHIFT (8U)
- #define VHA_CR_SYS_EVENT_INJECT_MMU_PAGE_FAULT_CLRMSK (0XFFFF00FFU)
- #define VHA_CR_SYS_EVENT_INJECT_AXI_ERROR_SHIFT (4U)
- #define VHA_CR_SYS_EVENT_INJECT_AXI_ERROR_CLRMSK (0XFFFFFF0FU)
- #define VHA_CR_SYS_EVENT_INJECT_RAM_INIT_DONE_SHIFT (3U)
- #define VHA_CR_SYS_EVENT_INJECT_RAM_INIT_DONE_CLRMSK (0XFFFFFFF7U)
- #define VHA_CR_SYS_EVENT_INJECT_RAM_INIT_DONE_EN (0X00000008U)
- #define VHA_CR_SYS_EVENT_INJECT_MEMBUS_RESET_DONE_SHIFT (2U)
- #define VHA_CR_SYS_EVENT_INJECT_MEMBUS_RESET_DONE_CLRMSK (0XFFFFFFFBU)
- #define VHA_CR_SYS_EVENT_INJECT_MEMBUS_RESET_DONE_EN (0X00000004U)
- #define VHA_CR_SYS_EVENT_INJECT_POWER_ABORT_SHIFT (1U)
- #define VHA_CR_SYS_EVENT_INJECT_POWER_ABORT_CLRMSK (0XFFFFFFFDU)
- #define VHA_CR_SYS_EVENT_INJECT_POWER_ABORT_EN (0X00000002U)
- #define VHA_CR_SYS_EVENT_INJECT_POWER_COMPLETE_SHIFT (0U)
- #define VHA_CR_SYS_EVENT_INJECT_POWER_COMPLETE_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_SYS_EVENT_INJECT_POWER_COMPLETE_EN (0X00000001U)
- /*
- Register VHA_CR_SYS_EVENT_THRESHOLD
- */
- #define VHA_CR_SYS_EVENT_THRESHOLD (0x0238U)
- #define VHA_CR_SYS_EVENT_THRESHOLD_MASKFULL (IMG_UINT64_C(0x000000000000FFFF))
- #define VHA_CR_SYS_EVENT_THRESHOLD_RAM_CORRECTION_SHIFT (0U)
- #define VHA_CR_SYS_EVENT_THRESHOLD_RAM_CORRECTION_CLRMSK (0XFFFF0000U)
- /*
- Register VHA_CR_SYS_EVENT_THRESHOLD_VAL
- */
- #define VHA_CR_SYS_EVENT_THRESHOLD_VAL (0x0240U)
- #define VHA_CR_SYS_EVENT_THRESHOLD_VAL_MASKFULL (IMG_UINT64_C(0x000000000000FFFF))
- #define VHA_CR_SYS_EVENT_THRESHOLD_VAL_RAM_CORRECTION_SHIFT (0U)
- #define VHA_CR_SYS_EVENT_THRESHOLD_VAL_RAM_CORRECTION_CLRMSK (0XFFFF0000U)
- /*
- Register VHA_CR_POWER_EVENT
- */
- #define VHA_CR_POWER_EVENT (0x0248U)
- #define VHA_CR_POWER_EVENT_MASKFULL (IMG_UINT64_C(0x0000000000FFFF03))
- #define VHA_CR_POWER_EVENT_DOMAIN_SHIFT (8U)
- #define VHA_CR_POWER_EVENT_DOMAIN_CLRMSK (0XFF0000FFU)
- #define VHA_CR_POWER_EVENT_DOMAIN_RESERVED_SHIFT (17U)
- #define VHA_CR_POWER_EVENT_DOMAIN_RESERVED_CLRMSK (0xff01ffff)
- #define VHA_CR_POWER_EVENT_DOMAIN_CORE7_SHIFT (16U)
- #define VHA_CR_POWER_EVENT_DOMAIN_CORE7_CLRMSK (0xfffeffff)
- #define VHA_CR_POWER_EVENT_DOMAIN_CORE6_SHIFT (15U)
- #define VHA_CR_POWER_EVENT_DOMAIN_CORE6_CLRMSK (0xffff7fff)
- #define VHA_CR_POWER_EVENT_DOMAIN_CORE5_SHIFT (14U)
- #define VHA_CR_POWER_EVENT_DOMAIN_CORE5_CLRMSK (0xffffbfff)
- #define VHA_CR_POWER_EVENT_DOMAIN_CORE4_SHIFT (13U)
- #define VHA_CR_POWER_EVENT_DOMAIN_CORE4_CLRMSK (0xffffdfff)
- #define VHA_CR_POWER_EVENT_DOMAIN_CORE3_SHIFT (12U)
- #define VHA_CR_POWER_EVENT_DOMAIN_CORE3_CLRMSK (0xffffefff)
- #define VHA_CR_POWER_EVENT_DOMAIN_CORE2_SHIFT (11U)
- #define VHA_CR_POWER_EVENT_DOMAIN_CORE2_CLRMSK (0xfffff7ff)
- #define VHA_CR_POWER_EVENT_DOMAIN_CORE1_SHIFT (10U)
- #define VHA_CR_POWER_EVENT_DOMAIN_CORE1_CLRMSK (0xfffffbff)
- #define VHA_CR_POWER_EVENT_DOMAIN_CORE0_SHIFT (9U)
- #define VHA_CR_POWER_EVENT_DOMAIN_CORE0_CLRMSK (0xfffffdff)
- #define VHA_CR_POWER_EVENT_DOMAIN_TLC_SHIFT (8U)
- #define VHA_CR_POWER_EVENT_DOMAIN_TLC_CLRMSK (0xfffffeff)
- #define VHA_CR_POWER_EVENT_REQ_SHIFT (1U)
- #define VHA_CR_POWER_EVENT_REQ_CLRMSK (0XFFFFFFFDU)
- #define VHA_CR_POWER_EVENT_REQ_EN (0X00000002U)
- #define VHA_CR_POWER_EVENT_TYPE_SHIFT (0U)
- #define VHA_CR_POWER_EVENT_TYPE_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_POWER_EVENT_TYPE_POWER_DOWN (00000000U)
- #define VHA_CR_POWER_EVENT_TYPE_POWER_UP (0X00000001U)
- /*
- Register VHA_CR_IDLE_HYSTERESIS_COUNT
- */
- #define VHA_CR_IDLE_HYSTERESIS_COUNT (0x0250U)
- #define VHA_CR_IDLE_HYSTERESIS_COUNT_MASKFULL (IMG_UINT64_C(0x000000000000001F))
- #define VHA_CR_IDLE_HYSTERESIS_COUNT_VALUE_SHIFT (0U)
- #define VHA_CR_IDLE_HYSTERESIS_COUNT_VALUE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFE0))
- #define VHA_CR_RESET_CLK_CTRL_MODE_MASK (0x00000003U)
- /*
- Clock always OFF during reset. */
- #define VHA_CR_RESET_CLK_CTRL_MODE_OFF (0x00000000U)
- /*
- Clock ON for 16 clock cycles during reset. */
- #define VHA_CR_RESET_CLK_CTRL_MODE_ON_16 (0x00000001U)
- /*
- Clock ON for 64 clock cycles during reset. */
- #define VHA_CR_RESET_CLK_CTRL_MODE_ON_64 (0x00000002U)
- /*
- Clock always ON during reset. */
- #define VHA_CR_RESET_CLK_CTRL_MODE_ON (0x00000003U)
- /*
- Register VHA_CR_RESET_CLK_CTRL
- */
- #define VHA_CR_RESET_CLK_CTRL (0x0258U)
- #define VHA_CR_RESET_CLK_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000000003))
- #define VHA_CR_RESET_CLK_CTRL_CTRL_SHIFT (0U)
- #define VHA_CR_RESET_CLK_CTRL_CTRL_CLRMSK (0XFFFFFFFCU)
- #define VHA_CR_RESET_CLK_CTRL_CTRL_OFF (00000000U)
- #define VHA_CR_RESET_CLK_CTRL_CTRL_ON_16 (0X00000001U)
- #define VHA_CR_RESET_CLK_CTRL_CTRL_ON_64 (0X00000002U)
- #define VHA_CR_RESET_CLK_CTRL_CTRL_ON (0X00000003U)
- /*
- Register VHA_CR_VHA_AXI_RESET_CTRL
- */
- #define VHA_CR_VHA_AXI_RESET_CTRL (0x0260U)
- #define VHA_CR_VHA_AXI_RESET_CTRL_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_VHA_AXI_RESET_CTRL_SOFT_RESET_CYCLES_SHIFT (0U)
- #define VHA_CR_VHA_AXI_RESET_CTRL_SOFT_RESET_CYCLES_CLRMSK (00000000U)
- /*
- Register VHA_CR_SYS_RAM_INIT
- */
- #define VHA_CR_SYS_RAM_INIT (0x0268U)
- #define VHA_CR_SYS_RAM_INIT_MASKFULL (IMG_UINT64_C(0x0000000000000001))
- #define VHA_CR_SYS_RAM_INIT_KICK_SHIFT (0U)
- #define VHA_CR_SYS_RAM_INIT_KICK_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_SYS_RAM_INIT_KICK_EN (0X00000001U)
- /*
- Register VHA_CR_WM_EVENT_SOURCE
- */
- #define VHA_CR_WM_EVENT_SOURCE (0x0270U)
- #define VHA_CR_WM_EVENT_SOURCE_MASKFULL (IMG_UINT64_C(0x00000000FFFF0000))
- #define VHA_CR_WM_EVENT_SOURCE_IC_SHIFT (24U)
- #define VHA_CR_WM_EVENT_SOURCE_IC_CLRMSK (0X00FFFFFFU)
- #define VHA_CR_WM_EVENT_SOURCE_CORE_SHIFT (16U)
- #define VHA_CR_WM_EVENT_SOURCE_CORE_CLRMSK (0XFF00FFFFU)
- /*
- Register VHA_CR_SYS_RTM_CTRL
- */
- #define VHA_CR_SYS_RTM_CTRL (0x0278U)
- #define VHA_CR_SYS_RTM_CTRL_MASKFULL (IMG_UINT64_C(0x00000000C0FFFFF8))
- #define VHA_CR_SYS_RTM_CTRL_RTM_ENABLE_SHIFT (31U)
- #define VHA_CR_SYS_RTM_CTRL_RTM_ENABLE_CLRMSK (0X7FFFFFFFU)
- #define VHA_CR_SYS_RTM_CTRL_RTM_ENABLE_EN (0X80000000U)
- #define VHA_CR_SYS_RTM_CTRL_RTM_CHECK_SHIFT (30U)
- #define VHA_CR_SYS_RTM_CTRL_RTM_CHECK_CLRMSK (0XBFFFFFFFU)
- #define VHA_CR_SYS_RTM_CTRL_RTM_CHECK_EN (0X40000000U)
- #define VHA_CR_SYS_RTM_CTRL_RTM_SELECTOR_SHIFT (3U)
- #define VHA_CR_SYS_RTM_CTRL_RTM_SELECTOR_CLRMSK (0XFF000007U)
- /*
- Register VHA_CR_SYS_RTM_DATA
- */
- #define VHA_CR_SYS_RTM_DATA (0x0280U)
- #define VHA_CR_SYS_RTM_DATA_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_SYS_RTM_DATA_RTM_DATA_SHIFT (0U)
- #define VHA_CR_SYS_RTM_DATA_RTM_DATA_CLRMSK (00000000U)
- /*
- Register VHA_CR_SOCIF_WAKEUP_ENABLE
- */
- #define VHA_CR_SOCIF_WAKEUP_ENABLE (0x0400U)
- #define VHA_CR_SOCIF_WAKEUP_ENABLE_MASKFULL (IMG_UINT64_C(0x0000000000000001))
- #define VHA_CR_SOCIF_WAKEUP_ENABLE_ALWAYS_SHIFT (0U)
- #define VHA_CR_SOCIF_WAKEUP_ENABLE_ALWAYS_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_SOCIF_WAKEUP_ENABLE_ALWAYS_EN (0X00000001U)
- /*
- Register VHA_CR_AXI_EXACCESS
- */
- #define VHA_CR_AXI_EXACCESS (0x0408U)
- #define VHA_CR_AXI_EXACCESS_MASKFULL (IMG_UINT64_C(0x0000000000000001))
- #define VHA_CR_AXI_EXACCESS_SOCIF_ENABLE_SHIFT (0U)
- #define VHA_CR_AXI_EXACCESS_SOCIF_ENABLE_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_AXI_EXACCESS_SOCIF_ENABLE_EN (0X00000001U)
- /*
- Register VHA_CR_REGBANK_REQUEST_INVALID
- */
- #define VHA_CR_REGBANK_REQUEST_INVALID (0x0410U)
- #define VHA_CR_REGBANK_REQUEST_INVALID_MASKFULL (IMG_UINT64_C(0x0000000000000001))
- #define VHA_CR_REGBANK_REQUEST_INVALID_FLAG_SHIFT (0U)
- #define VHA_CR_REGBANK_REQUEST_INVALID_FLAG_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_REGBANK_REQUEST_INVALID_FLAG_EN (0X00000001U)
- #define VHA_CR_CORE_MAPPING_MASK (0x0000000FU)
- /*
- Core mapped to Workload Manager 0 */
- #define VHA_CR_CORE_MAPPING_WM0 (0x00000000U)
- /*
- Core mapped to Workload Manager 1 */
- #define VHA_CR_CORE_MAPPING_WM1 (0x00000001U)
- /*
- Core mapped to Workload Manager 2 */
- #define VHA_CR_CORE_MAPPING_WM2 (0x00000002U)
- /*
- Core mapped to Workload Manager 3 */
- #define VHA_CR_CORE_MAPPING_WM3 (0x00000003U)
- /*
- Core mapped to Workload Manager 4 */
- #define VHA_CR_CORE_MAPPING_WM4 (0x00000004U)
- /*
- Core mapped to Workload Manager 5 */
- #define VHA_CR_CORE_MAPPING_WM5 (0x00000005U)
- /*
- Core mapped to Workload Manager 6 */
- #define VHA_CR_CORE_MAPPING_WM6 (0x00000006U)
- /*
- Core mapped to Workload Manager 7 */
- #define VHA_CR_CORE_MAPPING_WM7 (0x00000007U)
- /*
- Dual lockstep with Core N-1 */
- #define VHA_CR_CORE_MAPPING_LOCKSTEP (0x00000008U)
- /*
- Unallocated */
- #define VHA_CR_CORE_MAPPING_UNALLOCATED (0x00000009U)
- /*
- Register VHA_CR_CORE_ASSIGNMENT
- */
- #define VHA_CR_CORE_ASSIGNMENT (0x0418U)
- #define VHA_CR_CORE_ASSIGNMENT_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_CORE_ASSIGNMENT_CORE_7_WM_MAPPING_SHIFT (28U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_7_WM_MAPPING_CLRMSK (0X0FFFFFFFU)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_7_WM_MAPPING_WM0 (00000000U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_7_WM_MAPPING_WM1 (0X10000000U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_7_WM_MAPPING_WM2 (0X20000000U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_7_WM_MAPPING_WM3 (0X30000000U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_7_WM_MAPPING_WM4 (0X40000000U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_7_WM_MAPPING_WM5 (0X50000000U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_7_WM_MAPPING_WM6 (0X60000000U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_7_WM_MAPPING_WM7 (0X70000000U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_7_WM_MAPPING_LOCKSTEP (0X80000000U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_7_WM_MAPPING_UNALLOCATED (0X90000000U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_6_WM_MAPPING_SHIFT (24U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_6_WM_MAPPING_CLRMSK (0XF0FFFFFFU)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_6_WM_MAPPING_WM0 (00000000U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_6_WM_MAPPING_WM1 (0X01000000U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_6_WM_MAPPING_WM2 (0X02000000U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_6_WM_MAPPING_WM3 (0X03000000U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_6_WM_MAPPING_WM4 (0X04000000U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_6_WM_MAPPING_WM5 (0X05000000U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_6_WM_MAPPING_WM6 (0X06000000U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_6_WM_MAPPING_WM7 (0X07000000U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_6_WM_MAPPING_LOCKSTEP (0X08000000U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_6_WM_MAPPING_UNALLOCATED (0X09000000U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_5_WM_MAPPING_SHIFT (20U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_5_WM_MAPPING_CLRMSK (0XFF0FFFFFU)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_5_WM_MAPPING_WM0 (00000000U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_5_WM_MAPPING_WM1 (0X00100000U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_5_WM_MAPPING_WM2 (0X00200000U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_5_WM_MAPPING_WM3 (0X00300000U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_5_WM_MAPPING_WM4 (0X00400000U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_5_WM_MAPPING_WM5 (0X00500000U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_5_WM_MAPPING_WM6 (0X00600000U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_5_WM_MAPPING_WM7 (0X00700000U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_5_WM_MAPPING_LOCKSTEP (0X00800000U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_5_WM_MAPPING_UNALLOCATED (0X00900000U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_4_WM_MAPPING_SHIFT (16U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_4_WM_MAPPING_CLRMSK (0XFFF0FFFFU)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_4_WM_MAPPING_WM0 (00000000U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_4_WM_MAPPING_WM1 (0X00010000U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_4_WM_MAPPING_WM2 (0X00020000U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_4_WM_MAPPING_WM3 (0X00030000U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_4_WM_MAPPING_WM4 (0X00040000U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_4_WM_MAPPING_WM5 (0X00050000U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_4_WM_MAPPING_WM6 (0X00060000U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_4_WM_MAPPING_WM7 (0X00070000U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_4_WM_MAPPING_LOCKSTEP (0X00080000U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_4_WM_MAPPING_UNALLOCATED (0X00090000U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_3_WM_MAPPING_SHIFT (12U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_3_WM_MAPPING_CLRMSK (0XFFFF0FFFU)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_3_WM_MAPPING_WM0 (00000000U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_3_WM_MAPPING_WM1 (0X00001000U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_3_WM_MAPPING_WM2 (0X00002000U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_3_WM_MAPPING_WM3 (0X00003000U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_3_WM_MAPPING_WM4 (0X00004000U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_3_WM_MAPPING_WM5 (0X00005000U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_3_WM_MAPPING_WM6 (0X00006000U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_3_WM_MAPPING_WM7 (0X00007000U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_3_WM_MAPPING_LOCKSTEP (0X00008000U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_3_WM_MAPPING_UNALLOCATED (0X00009000U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_2_WM_MAPPING_SHIFT (8U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_2_WM_MAPPING_CLRMSK (0XFFFFF0FFU)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_2_WM_MAPPING_WM0 (00000000U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_2_WM_MAPPING_WM1 (0X00000100U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_2_WM_MAPPING_WM2 (0X00000200U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_2_WM_MAPPING_WM3 (0X00000300U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_2_WM_MAPPING_WM4 (0X00000400U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_2_WM_MAPPING_WM5 (0X00000500U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_2_WM_MAPPING_WM6 (0X00000600U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_2_WM_MAPPING_WM7 (0X00000700U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_2_WM_MAPPING_LOCKSTEP (0X00000800U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_2_WM_MAPPING_UNALLOCATED (0X00000900U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_1_WM_MAPPING_SHIFT (4U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_1_WM_MAPPING_CLRMSK (0XFFFFFF0FU)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_1_WM_MAPPING_WM0 (00000000U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_1_WM_MAPPING_WM1 (0X00000010U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_1_WM_MAPPING_WM2 (0X00000020U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_1_WM_MAPPING_WM3 (0X00000030U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_1_WM_MAPPING_WM4 (0X00000040U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_1_WM_MAPPING_WM5 (0X00000050U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_1_WM_MAPPING_WM6 (0X00000060U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_1_WM_MAPPING_WM7 (0X00000070U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_1_WM_MAPPING_LOCKSTEP (0X00000080U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_1_WM_MAPPING_UNALLOCATED (0X00000090U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_0_WM_MAPPING_SHIFT (0U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_0_WM_MAPPING_CLRMSK (0XFFFFFFF0U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_0_WM_MAPPING_WM0 (00000000U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_0_WM_MAPPING_WM1 (0X00000001U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_0_WM_MAPPING_WM2 (0X00000002U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_0_WM_MAPPING_WM3 (0X00000003U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_0_WM_MAPPING_WM4 (0X00000004U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_0_WM_MAPPING_WM5 (0X00000005U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_0_WM_MAPPING_WM6 (0X00000006U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_0_WM_MAPPING_WM7 (0X00000007U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_0_WM_MAPPING_LOCKSTEP (0X00000008U)
- #define VHA_CR_CORE_ASSIGNMENT_CORE_0_WM_MAPPING_UNALLOCATED (0X00000009U)
- /*
- Register VHA_CR_SOCM_BUF_ASSIGNMENT
- */
- #define VHA_CR_SOCM_BUF_ASSIGNMENT (0x0420U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_7_WM_MAPPING_SHIFT (28U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_7_WM_MAPPING_CLRMSK (0X0FFFFFFFU)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_7_WM_MAPPING_WM0 (00000000U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_7_WM_MAPPING_WM1 (0X10000000U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_7_WM_MAPPING_WM2 (0X20000000U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_7_WM_MAPPING_WM3 (0X30000000U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_7_WM_MAPPING_WM4 (0X40000000U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_7_WM_MAPPING_WM5 (0X50000000U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_7_WM_MAPPING_WM6 (0X60000000U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_7_WM_MAPPING_WM7 (0X70000000U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_7_WM_MAPPING_LOCKSTEP (0X80000000U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_7_WM_MAPPING_UNALLOCATED (0X90000000U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_6_WM_MAPPING_SHIFT (24U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_6_WM_MAPPING_CLRMSK (0XF0FFFFFFU)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_6_WM_MAPPING_WM0 (00000000U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_6_WM_MAPPING_WM1 (0X01000000U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_6_WM_MAPPING_WM2 (0X02000000U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_6_WM_MAPPING_WM3 (0X03000000U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_6_WM_MAPPING_WM4 (0X04000000U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_6_WM_MAPPING_WM5 (0X05000000U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_6_WM_MAPPING_WM6 (0X06000000U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_6_WM_MAPPING_WM7 (0X07000000U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_6_WM_MAPPING_LOCKSTEP (0X08000000U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_6_WM_MAPPING_UNALLOCATED (0X09000000U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_5_WM_MAPPING_SHIFT (20U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_5_WM_MAPPING_CLRMSK (0XFF0FFFFFU)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_5_WM_MAPPING_WM0 (00000000U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_5_WM_MAPPING_WM1 (0X00100000U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_5_WM_MAPPING_WM2 (0X00200000U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_5_WM_MAPPING_WM3 (0X00300000U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_5_WM_MAPPING_WM4 (0X00400000U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_5_WM_MAPPING_WM5 (0X00500000U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_5_WM_MAPPING_WM6 (0X00600000U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_5_WM_MAPPING_WM7 (0X00700000U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_5_WM_MAPPING_LOCKSTEP (0X00800000U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_5_WM_MAPPING_UNALLOCATED (0X00900000U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_4_WM_MAPPING_SHIFT (16U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_4_WM_MAPPING_CLRMSK (0XFFF0FFFFU)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_4_WM_MAPPING_WM0 (00000000U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_4_WM_MAPPING_WM1 (0X00010000U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_4_WM_MAPPING_WM2 (0X00020000U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_4_WM_MAPPING_WM3 (0X00030000U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_4_WM_MAPPING_WM4 (0X00040000U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_4_WM_MAPPING_WM5 (0X00050000U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_4_WM_MAPPING_WM6 (0X00060000U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_4_WM_MAPPING_WM7 (0X00070000U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_4_WM_MAPPING_LOCKSTEP (0X00080000U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_4_WM_MAPPING_UNALLOCATED (0X00090000U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_3_WM_MAPPING_SHIFT (12U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_3_WM_MAPPING_CLRMSK (0XFFFF0FFFU)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_3_WM_MAPPING_WM0 (00000000U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_3_WM_MAPPING_WM1 (0X00001000U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_3_WM_MAPPING_WM2 (0X00002000U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_3_WM_MAPPING_WM3 (0X00003000U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_3_WM_MAPPING_WM4 (0X00004000U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_3_WM_MAPPING_WM5 (0X00005000U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_3_WM_MAPPING_WM6 (0X00006000U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_3_WM_MAPPING_WM7 (0X00007000U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_3_WM_MAPPING_LOCKSTEP (0X00008000U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_3_WM_MAPPING_UNALLOCATED (0X00009000U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_2_WM_MAPPING_SHIFT (8U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_2_WM_MAPPING_CLRMSK (0XFFFFF0FFU)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_2_WM_MAPPING_WM0 (00000000U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_2_WM_MAPPING_WM1 (0X00000100U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_2_WM_MAPPING_WM2 (0X00000200U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_2_WM_MAPPING_WM3 (0X00000300U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_2_WM_MAPPING_WM4 (0X00000400U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_2_WM_MAPPING_WM5 (0X00000500U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_2_WM_MAPPING_WM6 (0X00000600U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_2_WM_MAPPING_WM7 (0X00000700U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_2_WM_MAPPING_LOCKSTEP (0X00000800U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_2_WM_MAPPING_UNALLOCATED (0X00000900U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_1_WM_MAPPING_SHIFT (4U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_1_WM_MAPPING_CLRMSK (0XFFFFFF0FU)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_1_WM_MAPPING_WM0 (00000000U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_1_WM_MAPPING_WM1 (0X00000010U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_1_WM_MAPPING_WM2 (0X00000020U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_1_WM_MAPPING_WM3 (0X00000030U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_1_WM_MAPPING_WM4 (0X00000040U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_1_WM_MAPPING_WM5 (0X00000050U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_1_WM_MAPPING_WM6 (0X00000060U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_1_WM_MAPPING_WM7 (0X00000070U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_1_WM_MAPPING_LOCKSTEP (0X00000080U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_1_WM_MAPPING_UNALLOCATED (0X00000090U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_0_WM_MAPPING_SHIFT (0U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_0_WM_MAPPING_CLRMSK (0XFFFFFFF0U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_0_WM_MAPPING_WM0 (00000000U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_0_WM_MAPPING_WM1 (0X00000001U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_0_WM_MAPPING_WM2 (0X00000002U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_0_WM_MAPPING_WM3 (0X00000003U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_0_WM_MAPPING_WM4 (0X00000004U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_0_WM_MAPPING_WM5 (0X00000005U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_0_WM_MAPPING_WM6 (0X00000006U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_0_WM_MAPPING_WM7 (0X00000007U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_0_WM_MAPPING_LOCKSTEP (0X00000008U)
- #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_0_WM_MAPPING_UNALLOCATED (0X00000009U)
- /*
- Host gets assigned the same priority level as the rest of internal system bus requestors */
- #define VHA_CR_SOCIF_ARBITER_CONFIG_ENUM_SOCIF_PRIORITIES_EQUAL (0x00000000U)
- /*
- Host gets assigned the higher priority level than the rest of internal system bus requestors */
- #define VHA_CR_SOCIF_ARBITER_CONFIG_ENUM_SOCIF_PRIORITIES_HIGHEST (0x00000001U)
- /*
- Register VHA_CR_SOCIF_ARBITER_CONFIG
- */
- #define VHA_CR_SOCIF_ARBITER_CONFIG (0x0428U)
- #define VHA_CR_SOCIF_ARBITER_CONFIG_MASKFULL (IMG_UINT64_C(0x000000000000001F))
- #define VHA_CR_SOCIF_ARBITER_CONFIG_SOCIF_HOST_EXTRA_ALLOC_SHIFT (1U)
- #define VHA_CR_SOCIF_ARBITER_CONFIG_SOCIF_HOST_EXTRA_ALLOC_CLRMSK (0XFFFFFFE1U)
- #define VHA_CR_SOCIF_ARBITER_CONFIG_SOCIF_HOST_PRIORITY_SHIFT (0U)
- #define VHA_CR_SOCIF_ARBITER_CONFIG_SOCIF_HOST_PRIORITY_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_SOCIF_ARBITER_CONFIG_SOCIF_HOST_PRIORITY_EQUAL (00000000U)
- #define VHA_CR_SOCIF_ARBITER_CONFIG_SOCIF_HOST_PRIORITY_HIGHEST (0X00000001U)
- #define VHA_CR_INTERCONNECT_EVENT_TYPE_LOGIC_ERROR_SHIFT (30U)
- #define VHA_CR_INTERCONNECT_EVENT_TYPE_LOGIC_ERROR_CLRMSK (0XBFFFFFFFU)
- #define VHA_CR_INTERCONNECT_EVENT_TYPE_LOGIC_ERROR_EN (0X40000000U)
- #define VHA_CR_INTERCONNECT_EVENT_TYPE_SOCIF_READ_MISMATCH_SHIFT (8U)
- #define VHA_CR_INTERCONNECT_EVENT_TYPE_SOCIF_READ_MISMATCH_CLRMSK (0XFFFFFEFFU)
- #define VHA_CR_INTERCONNECT_EVENT_TYPE_SOCIF_READ_MISMATCH_EN (0X00000100U)
- #define VHA_CR_INTERCONNECT_EVENT_TYPE_SOCIF_READ_UNRESPONSIVE_SHIFT (4U)
- #define VHA_CR_INTERCONNECT_EVENT_TYPE_SOCIF_READ_UNRESPONSIVE_CLRMSK (0XFFFFFFEFU)
- #define VHA_CR_INTERCONNECT_EVENT_TYPE_SOCIF_READ_UNRESPONSIVE_EN (0X00000010U)
- #define VHA_CR_INTERCONNECT_EVENT_TYPE_LOCKSTEP_ERROR_SHIFT (0U)
- #define VHA_CR_INTERCONNECT_EVENT_TYPE_LOCKSTEP_ERROR_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_INTERCONNECT_EVENT_TYPE_LOCKSTEP_ERROR_EN (0X00000001U)
- #define VHA_CR_INTERCONNECT_EVENT_STATUS_TYPE_PARITY_SHIFT (31U)
- #define VHA_CR_INTERCONNECT_EVENT_STATUS_TYPE_PARITY_CLRMSK (0X7FFFFFFFU)
- #define VHA_CR_INTERCONNECT_EVENT_STATUS_TYPE_PARITY_EN (0X80000000U)
- #define VHA_CR_INTERCONNECT_EVENT_STATUS_TYPE_LOGIC_ERROR_SHIFT (30U)
- #define VHA_CR_INTERCONNECT_EVENT_STATUS_TYPE_LOGIC_ERROR_CLRMSK (0XBFFFFFFFU)
- #define VHA_CR_INTERCONNECT_EVENT_STATUS_TYPE_LOGIC_ERROR_EN (0X40000000U)
- #define VHA_CR_INTERCONNECT_EVENT_STATUS_TYPE_SOCIF_READ_MISMATCH_SHIFT (8U)
- #define VHA_CR_INTERCONNECT_EVENT_STATUS_TYPE_SOCIF_READ_MISMATCH_CLRMSK (0XFFFFFEFFU)
- #define VHA_CR_INTERCONNECT_EVENT_STATUS_TYPE_SOCIF_READ_MISMATCH_EN (0X00000100U)
- #define VHA_CR_INTERCONNECT_EVENT_STATUS_TYPE_SOCIF_READ_UNRESPONSIVE_SHIFT (4U)
- #define VHA_CR_INTERCONNECT_EVENT_STATUS_TYPE_SOCIF_READ_UNRESPONSIVE_CLRMSK (0XFFFFFFEFU)
- #define VHA_CR_INTERCONNECT_EVENT_STATUS_TYPE_SOCIF_READ_UNRESPONSIVE_EN (0X00000010U)
- #define VHA_CR_INTERCONNECT_EVENT_STATUS_TYPE_LOCKSTEP_ERROR_SHIFT (0U)
- #define VHA_CR_INTERCONNECT_EVENT_STATUS_TYPE_LOCKSTEP_ERROR_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_INTERCONNECT_EVENT_STATUS_TYPE_LOCKSTEP_ERROR_EN (0X00000001U)
- /*
- Register VHA_CR_INTERCONNECT_EVENT_HOST_ENABLE
- */
- #define VHA_CR_INTERCONNECT_EVENT_HOST_ENABLE (0x0500U)
- #define VHA_CR_INTERCONNECT_EVENT_HOST_ENABLE_MASKFULL (IMG_UINT64_C(0x0000000040000111))
- #define VHA_CR_INTERCONNECT_EVENT_HOST_ENABLE_LOGIC_ERROR_SHIFT (30U)
- #define VHA_CR_INTERCONNECT_EVENT_HOST_ENABLE_LOGIC_ERROR_CLRMSK (0XBFFFFFFFU)
- #define VHA_CR_INTERCONNECT_EVENT_HOST_ENABLE_LOGIC_ERROR_EN (0X40000000U)
- #define VHA_CR_INTERCONNECT_EVENT_HOST_ENABLE_SOCIF_READ_MISMATCH_SHIFT (8U)
- #define VHA_CR_INTERCONNECT_EVENT_HOST_ENABLE_SOCIF_READ_MISMATCH_CLRMSK (0XFFFFFEFFU)
- #define VHA_CR_INTERCONNECT_EVENT_HOST_ENABLE_SOCIF_READ_MISMATCH_EN (0X00000100U)
- #define VHA_CR_INTERCONNECT_EVENT_HOST_ENABLE_SOCIF_READ_UNRESPONSIVE_SHIFT (4U)
- #define VHA_CR_INTERCONNECT_EVENT_HOST_ENABLE_SOCIF_READ_UNRESPONSIVE_CLRMSK (0XFFFFFFEFU)
- #define VHA_CR_INTERCONNECT_EVENT_HOST_ENABLE_SOCIF_READ_UNRESPONSIVE_EN (0X00000010U)
- #define VHA_CR_INTERCONNECT_EVENT_HOST_ENABLE_LOCKSTEP_ERROR_SHIFT (0U)
- #define VHA_CR_INTERCONNECT_EVENT_HOST_ENABLE_LOCKSTEP_ERROR_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_INTERCONNECT_EVENT_HOST_ENABLE_LOCKSTEP_ERROR_EN (0X00000001U)
- /*
- Register VHA_CR_INTERCONNECT_EVENT_HOST_STATUS
- */
- #define VHA_CR_INTERCONNECT_EVENT_HOST_STATUS (0x0508U)
- #define VHA_CR_INTERCONNECT_EVENT_HOST_STATUS_MASKFULL (IMG_UINT64_C(0x00000000C0000111))
- #define VHA_CR_INTERCONNECT_EVENT_HOST_STATUS_PARITY_SHIFT (31U)
- #define VHA_CR_INTERCONNECT_EVENT_HOST_STATUS_PARITY_CLRMSK (0X7FFFFFFFU)
- #define VHA_CR_INTERCONNECT_EVENT_HOST_STATUS_PARITY_EN (0X80000000U)
- #define VHA_CR_INTERCONNECT_EVENT_HOST_STATUS_LOGIC_ERROR_SHIFT (30U)
- #define VHA_CR_INTERCONNECT_EVENT_HOST_STATUS_LOGIC_ERROR_CLRMSK (0XBFFFFFFFU)
- #define VHA_CR_INTERCONNECT_EVENT_HOST_STATUS_LOGIC_ERROR_EN (0X40000000U)
- #define VHA_CR_INTERCONNECT_EVENT_HOST_STATUS_SOCIF_READ_MISMATCH_SHIFT (8U)
- #define VHA_CR_INTERCONNECT_EVENT_HOST_STATUS_SOCIF_READ_MISMATCH_CLRMSK (0XFFFFFEFFU)
- #define VHA_CR_INTERCONNECT_EVENT_HOST_STATUS_SOCIF_READ_MISMATCH_EN (0X00000100U)
- #define VHA_CR_INTERCONNECT_EVENT_HOST_STATUS_SOCIF_READ_UNRESPONSIVE_SHIFT (4U)
- #define VHA_CR_INTERCONNECT_EVENT_HOST_STATUS_SOCIF_READ_UNRESPONSIVE_CLRMSK (0XFFFFFFEFU)
- #define VHA_CR_INTERCONNECT_EVENT_HOST_STATUS_SOCIF_READ_UNRESPONSIVE_EN (0X00000010U)
- #define VHA_CR_INTERCONNECT_EVENT_HOST_STATUS_LOCKSTEP_ERROR_SHIFT (0U)
- #define VHA_CR_INTERCONNECT_EVENT_HOST_STATUS_LOCKSTEP_ERROR_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_INTERCONNECT_EVENT_HOST_STATUS_LOCKSTEP_ERROR_EN (0X00000001U)
- /*
- Register VHA_CR_INTERCONNECT_EVENT_HOST_STATUS_DISABLE
- */
- #define VHA_CR_INTERCONNECT_EVENT_HOST_STATUS_DISABLE (0x0530U)
- #define VHA_CR_INTERCONNECT_EVENT_HOST_STATUS_DISABLE_MASKFULL (IMG_UINT64_C(0x0000000040000111))
- #define VHA_CR_INTERCONNECT_EVENT_HOST_STATUS_DISABLE_LOGIC_ERROR_SHIFT (30U)
- #define VHA_CR_INTERCONNECT_EVENT_HOST_STATUS_DISABLE_LOGIC_ERROR_CLRMSK (0XBFFFFFFFU)
- #define VHA_CR_INTERCONNECT_EVENT_HOST_STATUS_DISABLE_LOGIC_ERROR_EN (0X40000000U)
- #define VHA_CR_INTERCONNECT_EVENT_HOST_STATUS_DISABLE_SOCIF_READ_MISMATCH_SHIFT (8U)
- #define VHA_CR_INTERCONNECT_EVENT_HOST_STATUS_DISABLE_SOCIF_READ_MISMATCH_CLRMSK (0XFFFFFEFFU)
- #define VHA_CR_INTERCONNECT_EVENT_HOST_STATUS_DISABLE_SOCIF_READ_MISMATCH_EN (0X00000100U)
- #define VHA_CR_INTERCONNECT_EVENT_HOST_STATUS_DISABLE_SOCIF_READ_UNRESPONSIVE_SHIFT (4U)
- #define VHA_CR_INTERCONNECT_EVENT_HOST_STATUS_DISABLE_SOCIF_READ_UNRESPONSIVE_CLRMSK (0XFFFFFFEFU)
- #define VHA_CR_INTERCONNECT_EVENT_HOST_STATUS_DISABLE_SOCIF_READ_UNRESPONSIVE_EN (0X00000010U)
- #define VHA_CR_INTERCONNECT_EVENT_HOST_STATUS_DISABLE_LOCKSTEP_ERROR_SHIFT (0U)
- #define VHA_CR_INTERCONNECT_EVENT_HOST_STATUS_DISABLE_LOCKSTEP_ERROR_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_INTERCONNECT_EVENT_HOST_STATUS_DISABLE_LOCKSTEP_ERROR_EN (0X00000001U)
- /*
- Register VHA_CR_INTERCONNECT_EVENT_HOST_CLEAR
- */
- #define VHA_CR_INTERCONNECT_EVENT_HOST_CLEAR (0x0510U)
- #define VHA_CR_INTERCONNECT_EVENT_HOST_CLEAR_MASKFULL (IMG_UINT64_C(0x0000000040000111))
- #define VHA_CR_INTERCONNECT_EVENT_HOST_CLEAR_LOGIC_ERROR_SHIFT (30U)
- #define VHA_CR_INTERCONNECT_EVENT_HOST_CLEAR_LOGIC_ERROR_CLRMSK (0XBFFFFFFFU)
- #define VHA_CR_INTERCONNECT_EVENT_HOST_CLEAR_LOGIC_ERROR_EN (0X40000000U)
- #define VHA_CR_INTERCONNECT_EVENT_HOST_CLEAR_SOCIF_READ_MISMATCH_SHIFT (8U)
- #define VHA_CR_INTERCONNECT_EVENT_HOST_CLEAR_SOCIF_READ_MISMATCH_CLRMSK (0XFFFFFEFFU)
- #define VHA_CR_INTERCONNECT_EVENT_HOST_CLEAR_SOCIF_READ_MISMATCH_EN (0X00000100U)
- #define VHA_CR_INTERCONNECT_EVENT_HOST_CLEAR_SOCIF_READ_UNRESPONSIVE_SHIFT (4U)
- #define VHA_CR_INTERCONNECT_EVENT_HOST_CLEAR_SOCIF_READ_UNRESPONSIVE_CLRMSK (0XFFFFFFEFU)
- #define VHA_CR_INTERCONNECT_EVENT_HOST_CLEAR_SOCIF_READ_UNRESPONSIVE_EN (0X00000010U)
- #define VHA_CR_INTERCONNECT_EVENT_HOST_CLEAR_LOCKSTEP_ERROR_SHIFT (0U)
- #define VHA_CR_INTERCONNECT_EVENT_HOST_CLEAR_LOCKSTEP_ERROR_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_INTERCONNECT_EVENT_HOST_CLEAR_LOCKSTEP_ERROR_EN (0X00000001U)
- /*
- Register VHA_CR_INTERCONNECT_EVENT_WM_ENABLE
- */
- #define VHA_CR_INTERCONNECT_EVENT_WM_ENABLE (0x0518U)
- #define VHA_CR_INTERCONNECT_EVENT_WM_ENABLE_MASKFULL (IMG_UINT64_C(0x0000000040000111))
- #define VHA_CR_INTERCONNECT_EVENT_WM_ENABLE_LOGIC_ERROR_SHIFT (30U)
- #define VHA_CR_INTERCONNECT_EVENT_WM_ENABLE_LOGIC_ERROR_CLRMSK (0XBFFFFFFFU)
- #define VHA_CR_INTERCONNECT_EVENT_WM_ENABLE_LOGIC_ERROR_EN (0X40000000U)
- #define VHA_CR_INTERCONNECT_EVENT_WM_ENABLE_SOCIF_READ_MISMATCH_SHIFT (8U)
- #define VHA_CR_INTERCONNECT_EVENT_WM_ENABLE_SOCIF_READ_MISMATCH_CLRMSK (0XFFFFFEFFU)
- #define VHA_CR_INTERCONNECT_EVENT_WM_ENABLE_SOCIF_READ_MISMATCH_EN (0X00000100U)
- #define VHA_CR_INTERCONNECT_EVENT_WM_ENABLE_SOCIF_READ_UNRESPONSIVE_SHIFT (4U)
- #define VHA_CR_INTERCONNECT_EVENT_WM_ENABLE_SOCIF_READ_UNRESPONSIVE_CLRMSK (0XFFFFFFEFU)
- #define VHA_CR_INTERCONNECT_EVENT_WM_ENABLE_SOCIF_READ_UNRESPONSIVE_EN (0X00000010U)
- #define VHA_CR_INTERCONNECT_EVENT_WM_ENABLE_LOCKSTEP_ERROR_SHIFT (0U)
- #define VHA_CR_INTERCONNECT_EVENT_WM_ENABLE_LOCKSTEP_ERROR_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_INTERCONNECT_EVENT_WM_ENABLE_LOCKSTEP_ERROR_EN (0X00000001U)
- /*
- Register VHA_CR_INTERCONNECT_EVENT_WM_STATUS
- */
- #define VHA_CR_INTERCONNECT_EVENT_WM_STATUS (0x0520U)
- #define VHA_CR_INTERCONNECT_EVENT_WM_STATUS_MASKFULL (IMG_UINT64_C(0x00000000C0000111))
- #define VHA_CR_INTERCONNECT_EVENT_WM_STATUS_PARITY_SHIFT (31U)
- #define VHA_CR_INTERCONNECT_EVENT_WM_STATUS_PARITY_CLRMSK (0X7FFFFFFFU)
- #define VHA_CR_INTERCONNECT_EVENT_WM_STATUS_PARITY_EN (0X80000000U)
- #define VHA_CR_INTERCONNECT_EVENT_WM_STATUS_LOGIC_ERROR_SHIFT (30U)
- #define VHA_CR_INTERCONNECT_EVENT_WM_STATUS_LOGIC_ERROR_CLRMSK (0XBFFFFFFFU)
- #define VHA_CR_INTERCONNECT_EVENT_WM_STATUS_LOGIC_ERROR_EN (0X40000000U)
- #define VHA_CR_INTERCONNECT_EVENT_WM_STATUS_SOCIF_READ_MISMATCH_SHIFT (8U)
- #define VHA_CR_INTERCONNECT_EVENT_WM_STATUS_SOCIF_READ_MISMATCH_CLRMSK (0XFFFFFEFFU)
- #define VHA_CR_INTERCONNECT_EVENT_WM_STATUS_SOCIF_READ_MISMATCH_EN (0X00000100U)
- #define VHA_CR_INTERCONNECT_EVENT_WM_STATUS_SOCIF_READ_UNRESPONSIVE_SHIFT (4U)
- #define VHA_CR_INTERCONNECT_EVENT_WM_STATUS_SOCIF_READ_UNRESPONSIVE_CLRMSK (0XFFFFFFEFU)
- #define VHA_CR_INTERCONNECT_EVENT_WM_STATUS_SOCIF_READ_UNRESPONSIVE_EN (0X00000010U)
- #define VHA_CR_INTERCONNECT_EVENT_WM_STATUS_LOCKSTEP_ERROR_SHIFT (0U)
- #define VHA_CR_INTERCONNECT_EVENT_WM_STATUS_LOCKSTEP_ERROR_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_INTERCONNECT_EVENT_WM_STATUS_LOCKSTEP_ERROR_EN (0X00000001U)
- /*
- Register VHA_CR_INTERCONNECT_EVENT_WM_STATUS_DISABLE
- */
- #define VHA_CR_INTERCONNECT_EVENT_WM_STATUS_DISABLE (0x0538U)
- #define VHA_CR_INTERCONNECT_EVENT_WM_STATUS_DISABLE_MASKFULL (IMG_UINT64_C(0x0000000040000111))
- #define VHA_CR_INTERCONNECT_EVENT_WM_STATUS_DISABLE_LOGIC_ERROR_SHIFT (30U)
- #define VHA_CR_INTERCONNECT_EVENT_WM_STATUS_DISABLE_LOGIC_ERROR_CLRMSK (0XBFFFFFFFU)
- #define VHA_CR_INTERCONNECT_EVENT_WM_STATUS_DISABLE_LOGIC_ERROR_EN (0X40000000U)
- #define VHA_CR_INTERCONNECT_EVENT_WM_STATUS_DISABLE_SOCIF_READ_MISMATCH_SHIFT (8U)
- #define VHA_CR_INTERCONNECT_EVENT_WM_STATUS_DISABLE_SOCIF_READ_MISMATCH_CLRMSK (0XFFFFFEFFU)
- #define VHA_CR_INTERCONNECT_EVENT_WM_STATUS_DISABLE_SOCIF_READ_MISMATCH_EN (0X00000100U)
- #define VHA_CR_INTERCONNECT_EVENT_WM_STATUS_DISABLE_SOCIF_READ_UNRESPONSIVE_SHIFT (4U)
- #define VHA_CR_INTERCONNECT_EVENT_WM_STATUS_DISABLE_SOCIF_READ_UNRESPONSIVE_CLRMSK (0XFFFFFFEFU)
- #define VHA_CR_INTERCONNECT_EVENT_WM_STATUS_DISABLE_SOCIF_READ_UNRESPONSIVE_EN (0X00000010U)
- #define VHA_CR_INTERCONNECT_EVENT_WM_STATUS_DISABLE_LOCKSTEP_ERROR_SHIFT (0U)
- #define VHA_CR_INTERCONNECT_EVENT_WM_STATUS_DISABLE_LOCKSTEP_ERROR_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_INTERCONNECT_EVENT_WM_STATUS_DISABLE_LOCKSTEP_ERROR_EN (0X00000001U)
- /*
- Register VHA_CR_INTERCONNECT_EVENT_WM_CLEAR
- */
- #define VHA_CR_INTERCONNECT_EVENT_WM_CLEAR (0x0528U)
- #define VHA_CR_INTERCONNECT_EVENT_WM_CLEAR_MASKFULL (IMG_UINT64_C(0x0000000040000111))
- #define VHA_CR_INTERCONNECT_EVENT_WM_CLEAR_LOGIC_ERROR_SHIFT (30U)
- #define VHA_CR_INTERCONNECT_EVENT_WM_CLEAR_LOGIC_ERROR_CLRMSK (0XBFFFFFFFU)
- #define VHA_CR_INTERCONNECT_EVENT_WM_CLEAR_LOGIC_ERROR_EN (0X40000000U)
- #define VHA_CR_INTERCONNECT_EVENT_WM_CLEAR_SOCIF_READ_MISMATCH_SHIFT (8U)
- #define VHA_CR_INTERCONNECT_EVENT_WM_CLEAR_SOCIF_READ_MISMATCH_CLRMSK (0XFFFFFEFFU)
- #define VHA_CR_INTERCONNECT_EVENT_WM_CLEAR_SOCIF_READ_MISMATCH_EN (0X00000100U)
- #define VHA_CR_INTERCONNECT_EVENT_WM_CLEAR_SOCIF_READ_UNRESPONSIVE_SHIFT (4U)
- #define VHA_CR_INTERCONNECT_EVENT_WM_CLEAR_SOCIF_READ_UNRESPONSIVE_CLRMSK (0XFFFFFFEFU)
- #define VHA_CR_INTERCONNECT_EVENT_WM_CLEAR_SOCIF_READ_UNRESPONSIVE_EN (0X00000010U)
- #define VHA_CR_INTERCONNECT_EVENT_WM_CLEAR_LOCKSTEP_ERROR_SHIFT (0U)
- #define VHA_CR_INTERCONNECT_EVENT_WM_CLEAR_LOCKSTEP_ERROR_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_INTERCONNECT_EVENT_WM_CLEAR_LOCKSTEP_ERROR_EN (0X00000001U)
- /*
- Register VHA_CR_INTERCONNECT_EVENT_INJECT
- */
- #define VHA_CR_INTERCONNECT_EVENT_INJECT (0x0540U)
- #define VHA_CR_INTERCONNECT_EVENT_INJECT_MASKFULL (IMG_UINT64_C(0x0000000040000111))
- #define VHA_CR_INTERCONNECT_EVENT_INJECT_LOGIC_ERROR_SHIFT (30U)
- #define VHA_CR_INTERCONNECT_EVENT_INJECT_LOGIC_ERROR_CLRMSK (0XBFFFFFFFU)
- #define VHA_CR_INTERCONNECT_EVENT_INJECT_LOGIC_ERROR_EN (0X40000000U)
- #define VHA_CR_INTERCONNECT_EVENT_INJECT_SOCIF_READ_MISMATCH_SHIFT (8U)
- #define VHA_CR_INTERCONNECT_EVENT_INJECT_SOCIF_READ_MISMATCH_CLRMSK (0XFFFFFEFFU)
- #define VHA_CR_INTERCONNECT_EVENT_INJECT_SOCIF_READ_MISMATCH_EN (0X00000100U)
- #define VHA_CR_INTERCONNECT_EVENT_INJECT_SOCIF_READ_UNRESPONSIVE_SHIFT (4U)
- #define VHA_CR_INTERCONNECT_EVENT_INJECT_SOCIF_READ_UNRESPONSIVE_CLRMSK (0XFFFFFFEFU)
- #define VHA_CR_INTERCONNECT_EVENT_INJECT_SOCIF_READ_UNRESPONSIVE_EN (0X00000010U)
- #define VHA_CR_INTERCONNECT_EVENT_INJECT_LOCKSTEP_ERROR_SHIFT (0U)
- #define VHA_CR_INTERCONNECT_EVENT_INJECT_LOCKSTEP_ERROR_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_INTERCONNECT_EVENT_INJECT_LOCKSTEP_ERROR_EN (0X00000001U)
- /*
- Register VHA_CR_IC_VHA_FLOP_ERR_INJ_CTRL
- */
- #define VHA_CR_IC_VHA_FLOP_ERR_INJ_CTRL (0x0800U)
- #define VHA_CR_IC_VHA_FLOP_ERR_INJ_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000000001))
- #define VHA_CR_IC_VHA_FLOP_ERR_INJ_CTRL_ERR_INJ_CTRL_SHIFT (0U)
- #define VHA_CR_IC_VHA_FLOP_ERR_INJ_CTRL_ERR_INJ_CTRL_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_IC_VHA_FLOP_ERR_INJ_CTRL_ERR_INJ_CTRL_EN (0X00000001U)
- /*
- Register VHA_CR_IC_VHA_FLOP_ERR_INJ_STATUS
- */
- #define VHA_CR_IC_VHA_FLOP_ERR_INJ_STATUS (0x0808U)
- #define VHA_CR_IC_VHA_FLOP_ERR_INJ_STATUS_MASKFULL (IMG_UINT64_C(0x0000000000000001))
- #define VHA_CR_IC_VHA_FLOP_ERR_INJ_STATUS_ERR_INJ_STATUS_SHIFT (0U)
- #define VHA_CR_IC_VHA_FLOP_ERR_INJ_STATUS_ERR_INJ_STATUS_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_IC_VHA_FLOP_ERR_INJ_STATUS_ERR_INJ_STATUS_EN (0X00000001U)
- /*
- Register VHA_CR_NN_SYS2_SYSBUS_HOST_STALL_RATIO
- */
- #define VHA_CR_NN_SYS2_SYSBUS_HOST_STALL_RATIO (0x1000U)
- #define VHA_CR_NN_SYS2_SYSBUS_HOST_STALL_RATIO_MASKFULL (IMG_UINT64_C(0x000000000000FFFF))
- #define VHA_CR_NN_SYS2_SYSBUS_HOST_STALL_RATIO_LSYNC_SOCIF_RTN_SHIFT (12U)
- #define VHA_CR_NN_SYS2_SYSBUS_HOST_STALL_RATIO_LSYNC_SOCIF_RTN_CLRMSK (0XFFFF0FFFU)
- #define VHA_CR_NN_SYS2_SYSBUS_HOST_STALL_RATIO_LSYNC_SOCIF_SHIFT (8U)
- #define VHA_CR_NN_SYS2_SYSBUS_HOST_STALL_RATIO_LSYNC_SOCIF_CLRMSK (0XFFFFF0FFU)
- #define VHA_CR_NN_SYS2_SYSBUS_HOST_STALL_RATIO_HOST_SOCIF_RTN_SHIFT (4U)
- #define VHA_CR_NN_SYS2_SYSBUS_HOST_STALL_RATIO_HOST_SOCIF_RTN_CLRMSK (0XFFFFFF0FU)
- #define VHA_CR_NN_SYS2_SYSBUS_HOST_STALL_RATIO_HOST_SOCIF_SHIFT (0U)
- #define VHA_CR_NN_SYS2_SYSBUS_HOST_STALL_RATIO_HOST_SOCIF_CLRMSK (0XFFFFFFF0U)
- /*
- Register VHA_CR_NN_SYS2_SYSBUS_WM_STALL_RATIO
- */
- #define VHA_CR_NN_SYS2_SYSBUS_WM_STALL_RATIO (0x1008U)
- #define VHA_CR_NN_SYS2_SYSBUS_WM_STALL_RATIO_MASKFULL (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
- #define VHA_CR_NN_SYS2_SYSBUS_WM_STALL_RATIO_WM7_SOCIF_RTN_SHIFT (60U)
- #define VHA_CR_NN_SYS2_SYSBUS_WM_STALL_RATIO_WM7_SOCIF_RTN_CLRMSK (IMG_UINT64_C(0X0FFFFFFFFFFFFFFF))
- #define VHA_CR_NN_SYS2_SYSBUS_WM_STALL_RATIO_WM7_SOCIF_SHIFT (56U)
- #define VHA_CR_NN_SYS2_SYSBUS_WM_STALL_RATIO_WM7_SOCIF_CLRMSK (IMG_UINT64_C(0XF0FFFFFFFFFFFFFF))
- #define VHA_CR_NN_SYS2_SYSBUS_WM_STALL_RATIO_WM6_SOCIF_RTN_SHIFT (52U)
- #define VHA_CR_NN_SYS2_SYSBUS_WM_STALL_RATIO_WM6_SOCIF_RTN_CLRMSK (IMG_UINT64_C(0XFF0FFFFFFFFFFFFF))
- #define VHA_CR_NN_SYS2_SYSBUS_WM_STALL_RATIO_WM6_SOCIF_SHIFT (48U)
- #define VHA_CR_NN_SYS2_SYSBUS_WM_STALL_RATIO_WM6_SOCIF_CLRMSK (IMG_UINT64_C(0XFFF0FFFFFFFFFFFF))
- #define VHA_CR_NN_SYS2_SYSBUS_WM_STALL_RATIO_WM5_SOCIF_RTN_SHIFT (44U)
- #define VHA_CR_NN_SYS2_SYSBUS_WM_STALL_RATIO_WM5_SOCIF_RTN_CLRMSK (IMG_UINT64_C(0XFFFF0FFFFFFFFFFF))
- #define VHA_CR_NN_SYS2_SYSBUS_WM_STALL_RATIO_WM5_SOCIF_SHIFT (40U)
- #define VHA_CR_NN_SYS2_SYSBUS_WM_STALL_RATIO_WM5_SOCIF_CLRMSK (IMG_UINT64_C(0XFFFFF0FFFFFFFFFF))
- #define VHA_CR_NN_SYS2_SYSBUS_WM_STALL_RATIO_WM4_SOCIF_RTN_SHIFT (36U)
- #define VHA_CR_NN_SYS2_SYSBUS_WM_STALL_RATIO_WM4_SOCIF_RTN_CLRMSK (IMG_UINT64_C(0XFFFFFF0FFFFFFFFF))
- #define VHA_CR_NN_SYS2_SYSBUS_WM_STALL_RATIO_WM4_SOCIF_SHIFT (32U)
- #define VHA_CR_NN_SYS2_SYSBUS_WM_STALL_RATIO_WM4_SOCIF_CLRMSK (IMG_UINT64_C(0XFFFFFFF0FFFFFFFF))
- #define VHA_CR_NN_SYS2_SYSBUS_WM_STALL_RATIO_WM3_SOCIF_RTN_SHIFT (28U)
- #define VHA_CR_NN_SYS2_SYSBUS_WM_STALL_RATIO_WM3_SOCIF_RTN_CLRMSK (IMG_UINT64_C(0XFFFFFFFF0FFFFFFF))
- #define VHA_CR_NN_SYS2_SYSBUS_WM_STALL_RATIO_WM3_SOCIF_SHIFT (24U)
- #define VHA_CR_NN_SYS2_SYSBUS_WM_STALL_RATIO_WM3_SOCIF_CLRMSK (IMG_UINT64_C(0XFFFFFFFFF0FFFFFF))
- #define VHA_CR_NN_SYS2_SYSBUS_WM_STALL_RATIO_WM2_SOCIF_RTN_SHIFT (20U)
- #define VHA_CR_NN_SYS2_SYSBUS_WM_STALL_RATIO_WM2_SOCIF_RTN_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF0FFFFF))
- #define VHA_CR_NN_SYS2_SYSBUS_WM_STALL_RATIO_WM2_SOCIF_SHIFT (16U)
- #define VHA_CR_NN_SYS2_SYSBUS_WM_STALL_RATIO_WM2_SOCIF_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF0FFFF))
- #define VHA_CR_NN_SYS2_SYSBUS_WM_STALL_RATIO_WM1_SOCIF_RTN_SHIFT (12U)
- #define VHA_CR_NN_SYS2_SYSBUS_WM_STALL_RATIO_WM1_SOCIF_RTN_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF0FFF))
- #define VHA_CR_NN_SYS2_SYSBUS_WM_STALL_RATIO_WM1_SOCIF_SHIFT (8U)
- #define VHA_CR_NN_SYS2_SYSBUS_WM_STALL_RATIO_WM1_SOCIF_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF0FF))
- #define VHA_CR_NN_SYS2_SYSBUS_WM_STALL_RATIO_WM0_SOCIF_RTN_SHIFT (4U)
- #define VHA_CR_NN_SYS2_SYSBUS_WM_STALL_RATIO_WM0_SOCIF_RTN_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFF0F))
- #define VHA_CR_NN_SYS2_SYSBUS_WM_STALL_RATIO_WM0_SOCIF_SHIFT (0U)
- #define VHA_CR_NN_SYS2_SYSBUS_WM_STALL_RATIO_WM0_SOCIF_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF0))
- /*
- Register VHA_CR_TLC_VHA_FLOP_ERR_INJ_CTRL
- */
- #define VHA_CR_TLC_VHA_FLOP_ERR_INJ_CTRL (0x1200U)
- #define VHA_CR_TLC_VHA_FLOP_ERR_INJ_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000000001))
- #define VHA_CR_TLC_VHA_FLOP_ERR_INJ_CTRL_ERR_INJ_CTRL_SHIFT (0U)
- #define VHA_CR_TLC_VHA_FLOP_ERR_INJ_CTRL_ERR_INJ_CTRL_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_TLC_VHA_FLOP_ERR_INJ_CTRL_ERR_INJ_CTRL_EN (0X00000001U)
- /*
- Register VHA_CR_TLC_VHA_FLOP_ERR_INJ_STATUS
- */
- #define VHA_CR_TLC_VHA_FLOP_ERR_INJ_STATUS (0x1208U)
- #define VHA_CR_TLC_VHA_FLOP_ERR_INJ_STATUS_MASKFULL (IMG_UINT64_C(0x0000000000000001))
- #define VHA_CR_TLC_VHA_FLOP_ERR_INJ_STATUS_ERR_INJ_STATUS_SHIFT (0U)
- #define VHA_CR_TLC_VHA_FLOP_ERR_INJ_STATUS_ERR_INJ_STATUS_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_TLC_VHA_FLOP_ERR_INJ_STATUS_ERR_INJ_STATUS_EN (0X00000001U)
- /*
- Register VHA_CR_LOW_LEVEL_SYNC_BASE_ADDR
- */
- #define VHA_CR_LOW_LEVEL_SYNC_BASE_ADDR (0x3000U)
- #define VHA_CR_LOW_LEVEL_SYNC_BASE_ADDR_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFE0))
- #define VHA_CR_LOW_LEVEL_SYNC_BASE_ADDR_BASE_ADDR_SHIFT (5U)
- #define VHA_CR_LOW_LEVEL_SYNC_BASE_ADDR_BASE_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF000000001F))
- /*
- Register VHA_CR_SOCM_BASE_ADDR
- */
- #define VHA_CR_SOCM_BASE_ADDR (0x3008U)
- #define VHA_CR_SOCM_BASE_ADDR_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFE0))
- #define VHA_CR_SOCM_BASE_ADDR_BASE_ADDR_SHIFT (5U)
- #define VHA_CR_SOCM_BASE_ADDR_BASE_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF000000001F))
- /*
- Register VHA_CR_SOCM_CIRCULAR_BUFFER_SIZE
- */
- #define VHA_CR_SOCM_CIRCULAR_BUFFER_SIZE (0x3010U)
- #define VHA_CR_SOCM_CIRCULAR_BUFFER_SIZE_MASKFULL (IMG_UINT64_C(0x00000000FFFFFF80))
- #define VHA_CR_SOCM_CIRCULAR_BUFFER_SIZE_SOCM_CIRCULAR_BUFFER_SIZE_SHIFT (7U)
- #define VHA_CR_SOCM_CIRCULAR_BUFFER_SIZE_SOCM_CIRCULAR_BUFFER_SIZE_CLRMSK (IMG_UINT64_C(0XFFFFFFFF0000007F))
- #define VHA_CR_SOCM_CIRCULAR_BUFFER_SIZE_SOCM_CIRCULAR_BUFFER_SIZE_ALIGNSHIFT (7U)
- #define VHA_CR_SOCM_CIRCULAR_BUFFER_SIZE_SOCM_CIRCULAR_BUFFER_SIZE_ALIGNSIZE (128U)
- /*
- Register VHA_CR_SOCM_B7_XOR_BITS
- */
- #define VHA_CR_SOCM_B7_XOR_BITS (0x3018U)
- #define VHA_CR_SOCM_B7_XOR_BITS_MASKFULL (IMG_UINT64_C(0x0000000001FFFE00))
- #define VHA_CR_SOCM_B7_XOR_BITS_SOCM_B7_XOR_BITS_SHIFT (9U)
- #define VHA_CR_SOCM_B7_XOR_BITS_SOCM_B7_XOR_BITS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFE0001FF))
- /*
- Register VHA_CR_SOCM_B8_XOR_BITS
- */
- #define VHA_CR_SOCM_B8_XOR_BITS (0x3020U)
- #define VHA_CR_SOCM_B8_XOR_BITS_MASKFULL (IMG_UINT64_C(0x0000000001FFFE00))
- #define VHA_CR_SOCM_B8_XOR_BITS_SOCM_B8_XOR_BITS_SHIFT (9U)
- #define VHA_CR_SOCM_B8_XOR_BITS_SOCM_B8_XOR_BITS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFE0001FF))
- /*
- Register VHA_CR_SOCM_MASKEDWRITE_STALL
- */
- #define VHA_CR_SOCM_MASKEDWRITE_STALL (0x3028U)
- #define VHA_CR_SOCM_MASKEDWRITE_STALL_MASKFULL (IMG_UINT64_C(0x0000000000000FFF))
- #define VHA_CR_SOCM_MASKEDWRITE_STALL_IDLE_SHIFT (6U)
- #define VHA_CR_SOCM_MASKEDWRITE_STALL_IDLE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF03F))
- #define VHA_CR_SOCM_MASKEDWRITE_STALL_BUSY_SHIFT (0U)
- #define VHA_CR_SOCM_MASKEDWRITE_STALL_BUSY_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFC0))
- /*
- Register VHA_CR_BW_LIMIT_CTRL
- */
- #define VHA_CR_BW_LIMIT_CTRL (0x3030U)
- #define VHA_CR_BW_LIMIT_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000000001))
- #define VHA_CR_BW_LIMIT_CTRL_BW_LIMIT_ENABLE_SHIFT (0U)
- #define VHA_CR_BW_LIMIT_CTRL_BW_LIMIT_ENABLE_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_BW_LIMIT_CTRL_BW_LIMIT_ENABLE_EN (0X00000001U)
- /*
- Register VHA_CR_BW_LIMIT_CTRL1
- */
- #define VHA_CR_BW_LIMIT_CTRL1 (0x3038U)
- #define VHA_CR_BW_LIMIT_CTRL1_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
- #define VHA_CR_BW_LIMIT_CTRL1_BW_LIMIT_MAX_FLEX_SHIFT (24U)
- #define VHA_CR_BW_LIMIT_CTRL1_BW_LIMIT_MAX_FLEX_CLRMSK (IMG_UINT64_C(0XFFFFFF0000FFFFFF))
- #define VHA_CR_BW_LIMIT_CTRL1_BW_LIMIT_MAX_SLOPE_SHIFT (16U)
- #define VHA_CR_BW_LIMIT_CTRL1_BW_LIMIT_MAX_SLOPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF00FFFF))
- #define VHA_CR_BW_LIMIT_CTRL1_BW_LIMIT_REQ_INCR_SHIFT (8U)
- #define VHA_CR_BW_LIMIT_CTRL1_BW_LIMIT_REQ_INCR_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF00FF))
- #define VHA_CR_BW_LIMIT_CTRL1_BW_LIMIT_PERIOD_MIN1_SHIFT (0U)
- #define VHA_CR_BW_LIMIT_CTRL1_BW_LIMIT_PERIOD_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFF00))
- /*
- Register VHA_CR_NOC_BWM_CONTROL
- */
- #define VHA_CR_NOC_BWM_CONTROL (0x3040U)
- #define VHA_CR_NOC_BWM_CONTROL_MASKFULL (IMG_UINT64_C(0x00000000000000FF))
- #define VHA_CR_NOC_BWM_CONTROL_NOC_BWM_REQUESTER_SHIFT (1U)
- #define VHA_CR_NOC_BWM_CONTROL_NOC_BWM_REQUESTER_CLRMSK (0XFFFFFF01U)
- #define VHA_CR_NOC_BWM_CONTROL_NOC_BWM_ENABLE_SHIFT (0U)
- #define VHA_CR_NOC_BWM_CONTROL_NOC_BWM_ENABLE_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_NOC_BWM_CONTROL_NOC_BWM_ENABLE_EN (0X00000001U)
- /*
- Register VHA_CR_CORE_BW_SOCM_RD
- */
- #define VHA_CR_CORE_BW_SOCM_RD (0x3100U)
- #define VHA_CR_CORE_BW_SOCM_RD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_CORE_BW_SOCM_RD_BW_SHIFT (0U)
- #define VHA_CR_CORE_BW_SOCM_RD_BW_CLRMSK (00000000U)
- /*
- Register VHA_CR_CORE_BW_SOCM_WR
- */
- #define VHA_CR_CORE_BW_SOCM_WR (0x3108U)
- #define VHA_CR_CORE_BW_SOCM_WR_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_CORE_BW_SOCM_WR_BW_SHIFT (0U)
- #define VHA_CR_CORE_BW_SOCM_WR_BW_CLRMSK (00000000U)
- /*
- Register VHA_CR_CORE_BW_SOCM_MWR
- */
- #define VHA_CR_CORE_BW_SOCM_MWR (0x3110U)
- #define VHA_CR_CORE_BW_SOCM_MWR_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_CORE_BW_SOCM_MWR_BW_SHIFT (0U)
- #define VHA_CR_CORE_BW_SOCM_MWR_BW_CLRMSK (00000000U)
- /*
- Register VHA_CR_CORE_BW_DDR_RD
- */
- #define VHA_CR_CORE_BW_DDR_RD (0x3118U)
- #define VHA_CR_CORE_BW_DDR_RD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_CORE_BW_DDR_RD_BW_SHIFT (0U)
- #define VHA_CR_CORE_BW_DDR_RD_BW_CLRMSK (00000000U)
- /*
- Register VHA_CR_CORE_BW_DDR_WR
- */
- #define VHA_CR_CORE_BW_DDR_WR (0x3120U)
- #define VHA_CR_CORE_BW_DDR_WR_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_CORE_BW_DDR_WR_BW_SHIFT (0U)
- #define VHA_CR_CORE_BW_DDR_WR_BW_CLRMSK (00000000U)
- /*
- Register VHA_CR_CORE_BW_DDR_MWR
- */
- #define VHA_CR_CORE_BW_DDR_MWR (0x3128U)
- #define VHA_CR_CORE_BW_DDR_MWR_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_CORE_BW_DDR_MWR_BW_SHIFT (0U)
- #define VHA_CR_CORE_BW_DDR_MWR_BW_CLRMSK (00000000U)
- /*
- Register VHA_CR_CORE_BW_SOCM_RD_WORD
- */
- #define VHA_CR_CORE_BW_SOCM_RD_WORD (0x3130U)
- #define VHA_CR_CORE_BW_SOCM_RD_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_CORE_BW_SOCM_RD_WORD_BW_SHIFT (0U)
- #define VHA_CR_CORE_BW_SOCM_RD_WORD_BW_CLRMSK (00000000U)
- /*
- Register VHA_CR_CORE_BW_SOCM_WR_WORD
- */
- #define VHA_CR_CORE_BW_SOCM_WR_WORD (0x3138U)
- #define VHA_CR_CORE_BW_SOCM_WR_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_CORE_BW_SOCM_WR_WORD_BW_SHIFT (0U)
- #define VHA_CR_CORE_BW_SOCM_WR_WORD_BW_CLRMSK (00000000U)
- /*
- Register VHA_CR_CORE_BW_DDR_RD_WORD
- */
- #define VHA_CR_CORE_BW_DDR_RD_WORD (0x3140U)
- #define VHA_CR_CORE_BW_DDR_RD_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_CORE_BW_DDR_RD_WORD_BW_SHIFT (0U)
- #define VHA_CR_CORE_BW_DDR_RD_WORD_BW_CLRMSK (00000000U)
- /*
- Register VHA_CR_CORE_BW_DDR_WR_WORD
- */
- #define VHA_CR_CORE_BW_DDR_WR_WORD (0x3148U)
- #define VHA_CR_CORE_BW_DDR_WR_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_CORE_BW_DDR_WR_WORD_BW_SHIFT (0U)
- #define VHA_CR_CORE_BW_DDR_WR_WORD_BW_CLRMSK (00000000U)
- /*
- Register VHA_CR_NN_SYS2_MEMBUS_SYS_STALL_RATIO
- */
- #define VHA_CR_NN_SYS2_MEMBUS_SYS_STALL_RATIO (0x3150U)
- #define VHA_CR_NN_SYS2_MEMBUS_SYS_STALL_RATIO_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_NN_SYS2_MEMBUS_SYS_STALL_RATIO_SYS_NOC_LSYNC_RTN_SHIFT (28U)
- #define VHA_CR_NN_SYS2_MEMBUS_SYS_STALL_RATIO_SYS_NOC_LSYNC_RTN_CLRMSK (0X0FFFFFFFU)
- #define VHA_CR_NN_SYS2_MEMBUS_SYS_STALL_RATIO_SYS_NOC_LSYNC_SHIFT (24U)
- #define VHA_CR_NN_SYS2_MEMBUS_SYS_STALL_RATIO_SYS_NOC_LSYNC_CLRMSK (0XF0FFFFFFU)
- #define VHA_CR_NN_SYS2_MEMBUS_SYS_STALL_RATIO_SYS_NOC_SOCM_RTN_SHIFT (20U)
- #define VHA_CR_NN_SYS2_MEMBUS_SYS_STALL_RATIO_SYS_NOC_SOCM_RTN_CLRMSK (0XFF0FFFFFU)
- #define VHA_CR_NN_SYS2_MEMBUS_SYS_STALL_RATIO_SYS_NOC_SOCM_SHIFT (16U)
- #define VHA_CR_NN_SYS2_MEMBUS_SYS_STALL_RATIO_SYS_NOC_SOCM_CLRMSK (0XFFF0FFFFU)
- #define VHA_CR_NN_SYS2_MEMBUS_SYS_STALL_RATIO_SYS_NOC_SLC_RTN_SHIFT (12U)
- #define VHA_CR_NN_SYS2_MEMBUS_SYS_STALL_RATIO_SYS_NOC_SLC_RTN_CLRMSK (0XFFFF0FFFU)
- #define VHA_CR_NN_SYS2_MEMBUS_SYS_STALL_RATIO_SYS_NOC_SLC_SHIFT (8U)
- #define VHA_CR_NN_SYS2_MEMBUS_SYS_STALL_RATIO_SYS_NOC_SLC_CLRMSK (0XFFFFF0FFU)
- #define VHA_CR_NN_SYS2_MEMBUS_SYS_STALL_RATIO_CORE_SYS_NOC_RTN_SHIFT (4U)
- #define VHA_CR_NN_SYS2_MEMBUS_SYS_STALL_RATIO_CORE_SYS_NOC_RTN_CLRMSK (0XFFFFFF0FU)
- #define VHA_CR_NN_SYS2_MEMBUS_SYS_STALL_RATIO_CORE_SYS_NOC_SHIFT (0U)
- #define VHA_CR_NN_SYS2_MEMBUS_SYS_STALL_RATIO_CORE_SYS_NOC_CLRMSK (0XFFFFFFF0U)
- /*
- SYS_MEM_WDT is Disabled */
- #define VHA_CR_SYS_MEM_WDT_CTRL_SYS_MEM_WDT_CTRL_NONE (0x00000000U)
- /*
- SYS_MEM_WDT is Cleared when WM is running */
- #define VHA_CR_SYS_MEM_WDT_CTRL_SYS_MEM_WDT_CTRL_KICK_WL (0x00000001U)
- /*
- Register VHA_CR_SYS_MEM_WDT_CTRL
- */
- #define VHA_CR_SYS_MEM_WDT_CTRL (0x5000U)
- #define VHA_CR_SYS_MEM_WDT_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000000001))
- #define VHA_CR_SYS_MEM_WDT_CTRL_MODE_SHIFT (0U)
- #define VHA_CR_SYS_MEM_WDT_CTRL_MODE_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_SYS_MEM_WDT_CTRL_MODE_NONE (00000000U)
- #define VHA_CR_SYS_MEM_WDT_CTRL_MODE_KICK_WL (0X00000001U)
- /*
- Register VHA_CR_SYS_MEM_WDT_COMPAREMATCH
- */
- #define VHA_CR_SYS_MEM_WDT_COMPAREMATCH (0x5008U)
- #define VHA_CR_SYS_MEM_WDT_COMPAREMATCH_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_SYS_MEM_WDT_COMPAREMATCH_VALUE_SHIFT (0U)
- #define VHA_CR_SYS_MEM_WDT_COMPAREMATCH_VALUE_CLRMSK (00000000U)
- /*
- Register VHA_CR_SYS_MEM_WDT_TIMER
- */
- #define VHA_CR_SYS_MEM_WDT_TIMER (0x5010U)
- #define VHA_CR_SYS_MEM_WDT_TIMER_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_SYS_MEM_WDT_TIMER_VALUE_SHIFT (0U)
- #define VHA_CR_SYS_MEM_WDT_TIMER_VALUE_CLRMSK (00000000U)
- /*
- Register VHA_CR_LOW_LEVEL_SYNC_STATUS
- */
- #define VHA_CR_LOW_LEVEL_SYNC_STATUS (0x5018U)
- #define VHA_CR_LOW_LEVEL_SYNC_STATUS_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_LOW_LEVEL_SYNC_STATUS_CORE7_SHIFT (28U)
- #define VHA_CR_LOW_LEVEL_SYNC_STATUS_CORE7_CLRMSK (0X0FFFFFFFU)
- #define VHA_CR_LOW_LEVEL_SYNC_STATUS_CORE6_SHIFT (24U)
- #define VHA_CR_LOW_LEVEL_SYNC_STATUS_CORE6_CLRMSK (0XF0FFFFFFU)
- #define VHA_CR_LOW_LEVEL_SYNC_STATUS_CORE5_SHIFT (20U)
- #define VHA_CR_LOW_LEVEL_SYNC_STATUS_CORE5_CLRMSK (0XFF0FFFFFU)
- #define VHA_CR_LOW_LEVEL_SYNC_STATUS_CORE4_SHIFT (16U)
- #define VHA_CR_LOW_LEVEL_SYNC_STATUS_CORE4_CLRMSK (0XFFF0FFFFU)
- #define VHA_CR_LOW_LEVEL_SYNC_STATUS_CORE3_SHIFT (12U)
- #define VHA_CR_LOW_LEVEL_SYNC_STATUS_CORE3_CLRMSK (0XFFFF0FFFU)
- #define VHA_CR_LOW_LEVEL_SYNC_STATUS_CORE2_SHIFT (8U)
- #define VHA_CR_LOW_LEVEL_SYNC_STATUS_CORE2_CLRMSK (0XFFFFF0FFU)
- #define VHA_CR_LOW_LEVEL_SYNC_STATUS_CORE1_SHIFT (4U)
- #define VHA_CR_LOW_LEVEL_SYNC_STATUS_CORE1_CLRMSK (0XFFFFFF0FU)
- #define VHA_CR_LOW_LEVEL_SYNC_STATUS_CORE0_SHIFT (0U)
- #define VHA_CR_LOW_LEVEL_SYNC_STATUS_CORE0_CLRMSK (0XFFFFFFF0U)
- /*
- Register VHA_CR_LOW_LEVEL_SYNC_CLEAR
- */
- #define VHA_CR_LOW_LEVEL_SYNC_CLEAR (0x5020U)
- #define VHA_CR_LOW_LEVEL_SYNC_CLEAR_MASKFULL (IMG_UINT64_C(0x00000000000000FF))
- #define VHA_CR_LOW_LEVEL_SYNC_CLEAR_CORE7_SHIFT (7U)
- #define VHA_CR_LOW_LEVEL_SYNC_CLEAR_CORE7_CLRMSK (0XFFFFFF7FU)
- #define VHA_CR_LOW_LEVEL_SYNC_CLEAR_CORE7_EN (0X00000080U)
- #define VHA_CR_LOW_LEVEL_SYNC_CLEAR_CORE6_SHIFT (6U)
- #define VHA_CR_LOW_LEVEL_SYNC_CLEAR_CORE6_CLRMSK (0XFFFFFFBFU)
- #define VHA_CR_LOW_LEVEL_SYNC_CLEAR_CORE6_EN (0X00000040U)
- #define VHA_CR_LOW_LEVEL_SYNC_CLEAR_CORE5_SHIFT (5U)
- #define VHA_CR_LOW_LEVEL_SYNC_CLEAR_CORE5_CLRMSK (0XFFFFFFDFU)
- #define VHA_CR_LOW_LEVEL_SYNC_CLEAR_CORE5_EN (0X00000020U)
- #define VHA_CR_LOW_LEVEL_SYNC_CLEAR_CORE4_SHIFT (4U)
- #define VHA_CR_LOW_LEVEL_SYNC_CLEAR_CORE4_CLRMSK (0XFFFFFFEFU)
- #define VHA_CR_LOW_LEVEL_SYNC_CLEAR_CORE4_EN (0X00000010U)
- #define VHA_CR_LOW_LEVEL_SYNC_CLEAR_CORE3_SHIFT (3U)
- #define VHA_CR_LOW_LEVEL_SYNC_CLEAR_CORE3_CLRMSK (0XFFFFFFF7U)
- #define VHA_CR_LOW_LEVEL_SYNC_CLEAR_CORE3_EN (0X00000008U)
- #define VHA_CR_LOW_LEVEL_SYNC_CLEAR_CORE2_SHIFT (2U)
- #define VHA_CR_LOW_LEVEL_SYNC_CLEAR_CORE2_CLRMSK (0XFFFFFFFBU)
- #define VHA_CR_LOW_LEVEL_SYNC_CLEAR_CORE2_EN (0X00000004U)
- #define VHA_CR_LOW_LEVEL_SYNC_CLEAR_CORE1_SHIFT (1U)
- #define VHA_CR_LOW_LEVEL_SYNC_CLEAR_CORE1_CLRMSK (0XFFFFFFFDU)
- #define VHA_CR_LOW_LEVEL_SYNC_CLEAR_CORE1_EN (0X00000002U)
- #define VHA_CR_LOW_LEVEL_SYNC_CLEAR_CORE0_SHIFT (0U)
- #define VHA_CR_LOW_LEVEL_SYNC_CLEAR_CORE0_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_LOW_LEVEL_SYNC_CLEAR_CORE0_EN (0X00000001U)
- /*
- Register VHA_CR_SOCM_SCRUB_CTRL
- */
- #define VHA_CR_SOCM_SCRUB_CTRL (0x5028U)
- #define VHA_CR_SOCM_SCRUB_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000000011))
- #define VHA_CR_SOCM_SCRUB_CTRL_MODE_SHIFT (4U)
- #define VHA_CR_SOCM_SCRUB_CTRL_MODE_CLRMSK (0XFFFFFFEFU)
- #define VHA_CR_SOCM_SCRUB_CTRL_MODE_EN (0X00000010U)
- #define VHA_CR_SOCM_SCRUB_CTRL_KICK_SHIFT (0U)
- #define VHA_CR_SOCM_SCRUB_CTRL_KICK_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_SOCM_SCRUB_CTRL_KICK_EN (0X00000001U)
- /*
- Register VHA_CR_PERF_SLC0_READ
- */
- #define VHA_CR_PERF_SLC0_READ (0x7000U)
- #define VHA_CR_PERF_SLC0_READ_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_PERF_SLC0_READ_COUNT_SHIFT (0U)
- #define VHA_CR_PERF_SLC0_READ_COUNT_CLRMSK (00000000U)
- /*
- Register VHA_CR_PERF_SLC0_WRITE
- */
- #define VHA_CR_PERF_SLC0_WRITE (0x7008U)
- #define VHA_CR_PERF_SLC0_WRITE_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_PERF_SLC0_WRITE_COUNT_SHIFT (0U)
- #define VHA_CR_PERF_SLC0_WRITE_COUNT_CLRMSK (00000000U)
- /*
- Register VHA_CR_PERF_SLC0_WRITE_DATA_STALL
- */
- #define VHA_CR_PERF_SLC0_WRITE_DATA_STALL (0x7010U)
- #define VHA_CR_PERF_SLC0_WRITE_DATA_STALL_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_PERF_SLC0_WRITE_DATA_STALL_COUNT_SHIFT (0U)
- #define VHA_CR_PERF_SLC0_WRITE_DATA_STALL_COUNT_CLRMSK (00000000U)
- /*
- Register VHA_CR_PERF_SLC0_READ_STALL
- */
- #define VHA_CR_PERF_SLC0_READ_STALL (0x7018U)
- #define VHA_CR_PERF_SLC0_READ_STALL_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_PERF_SLC0_READ_STALL_COUNT_SHIFT (0U)
- #define VHA_CR_PERF_SLC0_READ_STALL_COUNT_CLRMSK (00000000U)
- /*
- Register VHA_CR_PERF_SLC0_WRITE_STALL
- */
- #define VHA_CR_PERF_SLC0_WRITE_STALL (0x7020U)
- #define VHA_CR_PERF_SLC0_WRITE_STALL_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_PERF_SLC0_WRITE_STALL_COUNT_SHIFT (0U)
- #define VHA_CR_PERF_SLC0_WRITE_STALL_COUNT_CLRMSK (00000000U)
- /*
- Register VHA_CR_PERF_SLC0_READ_ID_STALL
- */
- #define VHA_CR_PERF_SLC0_READ_ID_STALL (0x7028U)
- #define VHA_CR_PERF_SLC0_READ_ID_STALL_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_PERF_SLC0_READ_ID_STALL_COUNT_SHIFT (0U)
- #define VHA_CR_PERF_SLC0_READ_ID_STALL_COUNT_CLRMSK (00000000U)
- /*
- Register VHA_CR_PERF_SLC0_WRITE_ID_STALL
- */
- #define VHA_CR_PERF_SLC0_WRITE_ID_STALL (0x7030U)
- #define VHA_CR_PERF_SLC0_WRITE_ID_STALL_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_PERF_SLC0_WRITE_ID_STALL_COUNT_SHIFT (0U)
- #define VHA_CR_PERF_SLC0_WRITE_ID_STALL_COUNT_CLRMSK (00000000U)
- /*
- Register VHA_CR_PERF_SLC0_RD_BURST_SIZE1
- */
- #define VHA_CR_PERF_SLC0_RD_BURST_SIZE1 (0x7038U)
- #define VHA_CR_PERF_SLC0_RD_BURST_SIZE1_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_PERF_SLC0_RD_BURST_SIZE1_COUNT_SHIFT (0U)
- #define VHA_CR_PERF_SLC0_RD_BURST_SIZE1_COUNT_CLRMSK (00000000U)
- /*
- Register VHA_CR_PERF_SLC0_WR_BURST_SIZE1
- */
- #define VHA_CR_PERF_SLC0_WR_BURST_SIZE1 (0x7040U)
- #define VHA_CR_PERF_SLC0_WR_BURST_SIZE1_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_PERF_SLC0_WR_BURST_SIZE1_COUNT_SHIFT (0U)
- #define VHA_CR_PERF_SLC0_WR_BURST_SIZE1_COUNT_CLRMSK (00000000U)
- /*
- Register VHA_CR_PERF_SLC0_RD_BURST_SIZE2
- */
- #define VHA_CR_PERF_SLC0_RD_BURST_SIZE2 (0x7048U)
- #define VHA_CR_PERF_SLC0_RD_BURST_SIZE2_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_PERF_SLC0_RD_BURST_SIZE2_COUNT_SHIFT (0U)
- #define VHA_CR_PERF_SLC0_RD_BURST_SIZE2_COUNT_CLRMSK (00000000U)
- /*
- Register VHA_CR_PERF_SLC0_WR_BURST_SIZE2
- */
- #define VHA_CR_PERF_SLC0_WR_BURST_SIZE2 (0x7050U)
- #define VHA_CR_PERF_SLC0_WR_BURST_SIZE2_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_PERF_SLC0_WR_BURST_SIZE2_COUNT_SHIFT (0U)
- #define VHA_CR_PERF_SLC0_WR_BURST_SIZE2_COUNT_CLRMSK (00000000U)
- /*
- Register VHA_CR_PERF_SLC0_RD_BURST_SIZE3
- */
- #define VHA_CR_PERF_SLC0_RD_BURST_SIZE3 (0x7058U)
- #define VHA_CR_PERF_SLC0_RD_BURST_SIZE3_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_PERF_SLC0_RD_BURST_SIZE3_COUNT_SHIFT (0U)
- #define VHA_CR_PERF_SLC0_RD_BURST_SIZE3_COUNT_CLRMSK (00000000U)
- /*
- Register VHA_CR_PERF_SLC0_WR_BURST_SIZE3
- */
- #define VHA_CR_PERF_SLC0_WR_BURST_SIZE3 (0x7060U)
- #define VHA_CR_PERF_SLC0_WR_BURST_SIZE3_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_PERF_SLC0_WR_BURST_SIZE3_COUNT_SHIFT (0U)
- #define VHA_CR_PERF_SLC0_WR_BURST_SIZE3_COUNT_CLRMSK (00000000U)
- /*
- Register VHA_CR_PERF_SLC0_RD_BURST_SIZE4
- */
- #define VHA_CR_PERF_SLC0_RD_BURST_SIZE4 (0x7068U)
- #define VHA_CR_PERF_SLC0_RD_BURST_SIZE4_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_PERF_SLC0_RD_BURST_SIZE4_COUNT_SHIFT (0U)
- #define VHA_CR_PERF_SLC0_RD_BURST_SIZE4_COUNT_CLRMSK (00000000U)
- /*
- Register VHA_CR_PERF_SLC0_WR_BURST_SIZE4
- */
- #define VHA_CR_PERF_SLC0_WR_BURST_SIZE4 (0x7070U)
- #define VHA_CR_PERF_SLC0_WR_BURST_SIZE4_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_PERF_SLC0_WR_BURST_SIZE4_COUNT_SHIFT (0U)
- #define VHA_CR_PERF_SLC0_WR_BURST_SIZE4_COUNT_CLRMSK (00000000U)
- /*
- Register VHA_CR_PERF_RESET_FULL
- */
- #define VHA_CR_PERF_RESET_FULL (0x7078U)
- #define VHA_CR_PERF_RESET_FULL_MASKFULL (IMG_UINT64_C(0x0000000000000001))
- #define VHA_CR_PERF_RESET_FULL_RANGE_SHIFT (0U)
- #define VHA_CR_PERF_RESET_FULL_RANGE_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_PERF_RESET_FULL_RANGE_EN (0X00000001U)
- /*
- Register VHA_CR_PERF_ENABLE_FULL
- */
- #define VHA_CR_PERF_ENABLE_FULL (0x7080U)
- #define VHA_CR_PERF_ENABLE_FULL_MASKFULL (IMG_UINT64_C(0x0000000000000001))
- #define VHA_CR_PERF_ENABLE_FULL_RANGE_SHIFT (0U)
- #define VHA_CR_PERF_ENABLE_FULL_RANGE_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_PERF_ENABLE_FULL_RANGE_EN (0X00000001U)
- /*
- Register VHA_CR_MMU_STATUS
- */
- #define VHA_CR_MMU_STATUS (0x7088U)
- #define VHA_CR_MMU_STATUS_MASKFULL (IMG_UINT64_C(0x000001FFFFFFFFFF))
- #define VHA_CR_MMU_STATUS_MMU_STALLED_SHIFT (40U)
- #define VHA_CR_MMU_STATUS_MMU_STALLED_CLRMSK (IMG_UINT64_C(0XFFFFFEFFFFFFFFFF))
- #define VHA_CR_MMU_STATUS_MMU_STALLED_EN (IMG_UINT64_C(0X0000010000000000))
- #define VHA_CR_MMU_STATUS_PM_WRITES_SHIFT (38U)
- #define VHA_CR_MMU_STATUS_PM_WRITES_CLRMSK (IMG_UINT64_C(0XFFFFFF3FFFFFFFFF))
- #define VHA_CR_MMU_STATUS_PM_READS_SHIFT (36U)
- #define VHA_CR_MMU_STATUS_PM_READS_CLRMSK (IMG_UINT64_C(0XFFFFFFCFFFFFFFFF))
- #define VHA_CR_MMU_STATUS_PC_READS_SHIFT (24U)
- #define VHA_CR_MMU_STATUS_PC_READS_CLRMSK (IMG_UINT64_C(0XFFFFFFF000FFFFFF))
- #define VHA_CR_MMU_STATUS_PD_READS_SHIFT (12U)
- #define VHA_CR_MMU_STATUS_PD_READS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF000FFF))
- #define VHA_CR_MMU_STATUS_PT_READS_SHIFT (0U)
- #define VHA_CR_MMU_STATUS_PT_READS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF000))
- /*
- Register VHA_CR_SLC_STATUS1
- */
- #define VHA_CR_SLC_STATUS1 (0x7090U)
- #define VHA_CR_SLC_STATUS1_MASKFULL (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
- #define VHA_CR_SLC_STATUS1_RESERVED_SHIFT (48U)
- #define VHA_CR_SLC_STATUS1_RESERVED_CLRMSK (IMG_UINT64_C(0X0000FFFFFFFFFFFF))
- #define VHA_CR_SLC_STATUS1_BUS1_OUTSTANDING_WRITES_SHIFT (36U)
- #define VHA_CR_SLC_STATUS1_BUS1_OUTSTANDING_WRITES_CLRMSK (IMG_UINT64_C(0XFFFF000FFFFFFFFF))
- #define VHA_CR_SLC_STATUS1_BUS0_OUTSTANDING_WRITES_SHIFT (24U)
- #define VHA_CR_SLC_STATUS1_BUS0_OUTSTANDING_WRITES_CLRMSK (IMG_UINT64_C(0XFFFFFFF000FFFFFF))
- #define VHA_CR_SLC_STATUS1_BUS1_OUTSTANDING_READS_SHIFT (12U)
- #define VHA_CR_SLC_STATUS1_BUS1_OUTSTANDING_READS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF000FFF))
- #define VHA_CR_SLC_STATUS1_BUS0_OUTSTANDING_READS_SHIFT (0U)
- #define VHA_CR_SLC_STATUS1_BUS0_OUTSTANDING_READS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF000))
- /*
- Register VHA_CR_SLC_STATUS2
- */
- #define VHA_CR_SLC_STATUS2 (0x7098U)
- #define VHA_CR_SLC_STATUS2_MASKFULL (IMG_UINT64_C(0x0000FFFFFFFFFFFF))
- #define VHA_CR_SLC_STATUS2_BUS3_OUTSTANDING_WRITES_SHIFT (36U)
- #define VHA_CR_SLC_STATUS2_BUS3_OUTSTANDING_WRITES_CLRMSK (IMG_UINT64_C(0XFFFF000FFFFFFFFF))
- #define VHA_CR_SLC_STATUS2_BUS2_OUTSTANDING_WRITES_SHIFT (24U)
- #define VHA_CR_SLC_STATUS2_BUS2_OUTSTANDING_WRITES_CLRMSK (IMG_UINT64_C(0XFFFFFFF000FFFFFF))
- #define VHA_CR_SLC_STATUS2_BUS3_OUTSTANDING_READS_SHIFT (12U)
- #define VHA_CR_SLC_STATUS2_BUS3_OUTSTANDING_READS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF000FFF))
- #define VHA_CR_SLC_STATUS2_BUS2_OUTSTANDING_READS_SHIFT (0U)
- #define VHA_CR_SLC_STATUS2_BUS2_OUTSTANDING_READS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF000))
- /*
- Register VHA_CR_SLC_IDLE
- */
- #define VHA_CR_SLC_IDLE (0x70A0U)
- #define VHA_CR_SLC_IDLE_MASKFULL (IMG_UINT64_C(0x000000000000FFFF))
- #define VHA_CR_SLC_IDLE_ACE_CONVERTERS_SHIFT (12U)
- #define VHA_CR_SLC_IDLE_ACE_CONVERTERS_CLRMSK (0XFFFF0FFFU)
- #define VHA_CR_SLC_IDLE_CACHE_BANKS_SHIFT (4U)
- #define VHA_CR_SLC_IDLE_CACHE_BANKS_CLRMSK (0XFFFFF00FU)
- #define VHA_CR_SLC_IDLE_MMU_SHIFT (3U)
- #define VHA_CR_SLC_IDLE_MMU_CLRMSK (0XFFFFFFF7U)
- #define VHA_CR_SLC_IDLE_MMU_EN (0X00000008U)
- #define VHA_CR_SLC_IDLE_CCM_SHIFT (2U)
- #define VHA_CR_SLC_IDLE_CCM_CLRMSK (0XFFFFFFFBU)
- #define VHA_CR_SLC_IDLE_CCM_EN (0X00000004U)
- #define VHA_CR_SLC_IDLE_RDI_SHIFT (1U)
- #define VHA_CR_SLC_IDLE_RDI_CLRMSK (0XFFFFFFFDU)
- #define VHA_CR_SLC_IDLE_RDI_EN (0X00000002U)
- #define VHA_CR_SLC_IDLE_XBAR_SHIFT (0U)
- #define VHA_CR_SLC_IDLE_XBAR_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_SLC_IDLE_XBAR_EN (0X00000001U)
- /*
- Register VHA_CR_SLC_STATUS3
- */
- #define VHA_CR_SLC_STATUS3 (0x70A8U)
- #define VHA_CR_SLC_STATUS3_MASKFULL (IMG_UINT64_C(0x0FFFFFFFFFFFFFFF))
- #define VHA_CR_SLC_STATUS3_MAX_CRITICAL_QOS_READ_LATENCY_SHIFT (50U)
- #define VHA_CR_SLC_STATUS3_MAX_CRITICAL_QOS_READ_LATENCY_CLRMSK (IMG_UINT64_C(0XF003FFFFFFFFFFFF))
- #define VHA_CR_SLC_STATUS3_MAX_LOW_QOS_READ_LATENCY_SHIFT (40U)
- #define VHA_CR_SLC_STATUS3_MAX_LOW_QOS_READ_LATENCY_CLRMSK (IMG_UINT64_C(0XFFFC00FFFFFFFFFF))
- #define VHA_CR_SLC_STATUS3_AVG_CRITICAL_QOS_READ_LATENCY_SHIFT (30U)
- #define VHA_CR_SLC_STATUS3_AVG_CRITICAL_QOS_READ_LATENCY_CLRMSK (IMG_UINT64_C(0XFFFFFF003FFFFFFF))
- #define VHA_CR_SLC_STATUS3_AVG_LOW_QOS_READ_LATENCY_SHIFT (20U)
- #define VHA_CR_SLC_STATUS3_AVG_LOW_QOS_READ_LATENCY_CLRMSK (IMG_UINT64_C(0XFFFFFFFFC00FFFFF))
- #define VHA_CR_SLC_STATUS3_MIN_CRITICAL_QOS_READ_LATENCY_SHIFT (10U)
- #define VHA_CR_SLC_STATUS3_MIN_CRITICAL_QOS_READ_LATENCY_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF003FF))
- #define VHA_CR_SLC_STATUS3_MIN_LOW_QOS_READ_LATENCY_SHIFT (0U)
- #define VHA_CR_SLC_STATUS3_MIN_LOW_QOS_READ_LATENCY_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFC00))
- /*
- Register VHA_CR_SLC_FAULT_STOP_STATUS
- */
- #define VHA_CR_SLC_FAULT_STOP_STATUS (0x70B0U)
- #define VHA_CR_SLC_FAULT_STOP_STATUS_MASKFULL (IMG_UINT64_C(0x000000000001FFFF))
- #define VHA_CR_SLC_FAULT_STOP_STATUS_BIF_SHIFT (0U)
- #define VHA_CR_SLC_FAULT_STOP_STATUS_BIF_CLRMSK (0XFFFE0000U)
- /*
- Register VHA_CR_SLC_STATUS_DEBUG
- */
- #define VHA_CR_SLC_STATUS_DEBUG (0x70B8U)
- #define VHA_CR_SLC_STATUS_DEBUG_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_SLC_STATUS_DEBUG_ERR_COH_REQ_SHIFT (16U)
- #define VHA_CR_SLC_STATUS_DEBUG_ERR_COH_REQ_CLRMSK (0X0000FFFFU)
- #define VHA_CR_SLC_STATUS_DEBUG_ERR_ADDR_ALIAS_SHIFT (0U)
- #define VHA_CR_SLC_STATUS_DEBUG_ERR_ADDR_ALIAS_CLRMSK (0XFFFF0000U)
- /*
- Register VHA_CR_PERF_SLC
- */
- #define VHA_CR_PERF_SLC (0x70C0U)
- #define VHA_CR_PERF_SLC_MASKFULL (IMG_UINT64_C(0x000000000FEFFEFF))
- #define VHA_CR_PERF_SLC_EWO_REQ_RD_WORD_COUNTER_RESET_SHIFT (27U)
- #define VHA_CR_PERF_SLC_EWO_REQ_RD_WORD_COUNTER_RESET_CLRMSK (IMG_UINT64_C(0XFFFFFFFFF7FFFFFF))
- #define VHA_CR_PERF_SLC_EWO_REQ_RD_WORD_COUNTER_RESET_EN (IMG_UINT64_C(0X0000000008000000))
- #define VHA_CR_PERF_SLC_EWO_REQ_RD_COUNTER_RESET_SHIFT (26U)
- #define VHA_CR_PERF_SLC_EWO_REQ_RD_COUNTER_RESET_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFBFFFFFF))
- #define VHA_CR_PERF_SLC_EWO_REQ_RD_COUNTER_RESET_EN (IMG_UINT64_C(0X0000000004000000))
- #define VHA_CR_PERF_SLC_MMU_REQ_RD_WORD_COUNTER_RESET_SHIFT (25U)
- #define VHA_CR_PERF_SLC_MMU_REQ_RD_WORD_COUNTER_RESET_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFDFFFFFF))
- #define VHA_CR_PERF_SLC_MMU_REQ_RD_WORD_COUNTER_RESET_EN (IMG_UINT64_C(0X0000000002000000))
- #define VHA_CR_PERF_SLC_MMU_REQ_RD_COUNTER_RESET_SHIFT (24U)
- #define VHA_CR_PERF_SLC_MMU_REQ_RD_COUNTER_RESET_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFEFFFFFF))
- #define VHA_CR_PERF_SLC_MMU_REQ_RD_COUNTER_RESET_EN (IMG_UINT64_C(0X0000000001000000))
- #define VHA_CR_PERF_SLC_OPK_REQ_WR_WORD_COUNTER_RESET_SHIFT (23U)
- #define VHA_CR_PERF_SLC_OPK_REQ_WR_WORD_COUNTER_RESET_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF7FFFFF))
- #define VHA_CR_PERF_SLC_OPK_REQ_WR_WORD_COUNTER_RESET_EN (IMG_UINT64_C(0X0000000000800000))
- #define VHA_CR_PERF_SLC_ABUF_REQ_RD_WORD_COUNTER_RESET_SHIFT (22U)
- #define VHA_CR_PERF_SLC_ABUF_REQ_RD_WORD_COUNTER_RESET_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFBFFFFF))
- #define VHA_CR_PERF_SLC_ABUF_REQ_RD_WORD_COUNTER_RESET_EN (IMG_UINT64_C(0X0000000000400000))
- #define VHA_CR_PERF_SLC_CBUF_REQ_RD_WORD_COUNTER_RESET_SHIFT (21U)
- #define VHA_CR_PERF_SLC_CBUF_REQ_RD_WORD_COUNTER_RESET_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFDFFFFF))
- #define VHA_CR_PERF_SLC_CBUF_REQ_RD_WORD_COUNTER_RESET_EN (IMG_UINT64_C(0X0000000000200000))
- #define VHA_CR_PERF_SLC_MMM_REQ_WR_WORD_COUNTER_RESET_SHIFT (19U)
- #define VHA_CR_PERF_SLC_MMM_REQ_WR_WORD_COUNTER_RESET_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF7FFFF))
- #define VHA_CR_PERF_SLC_MMM_REQ_WR_WORD_COUNTER_RESET_EN (IMG_UINT64_C(0X0000000000080000))
- #define VHA_CR_PERF_SLC_MMM_REQ_RD_WORD_COUNTER_RESET_SHIFT (18U)
- #define VHA_CR_PERF_SLC_MMM_REQ_RD_WORD_COUNTER_RESET_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFBFFFF))
- #define VHA_CR_PERF_SLC_MMM_REQ_RD_WORD_COUNTER_RESET_EN (IMG_UINT64_C(0X0000000000040000))
- #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_WORD_COUNTER_RESET_SHIFT (17U)
- #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_WORD_COUNTER_RESET_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFDFFFF))
- #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_WORD_COUNTER_RESET_EN (IMG_UINT64_C(0X0000000000020000))
- #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_WORD_COUNTER_RESET_SHIFT (16U)
- #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_WORD_COUNTER_RESET_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFEFFFF))
- #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_WORD_COUNTER_RESET_EN (IMG_UINT64_C(0X0000000000010000))
- #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_WORD_COUNTER_RESET_SHIFT (15U)
- #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_WORD_COUNTER_RESET_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF7FFF))
- #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_WORD_COUNTER_RESET_EN (IMG_UINT64_C(0X0000000000008000))
- #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_WORD_COUNTER_RESET_SHIFT (14U)
- #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_WORD_COUNTER_RESET_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFBFFF))
- #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_WORD_COUNTER_RESET_EN (IMG_UINT64_C(0X0000000000004000))
- #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_WORD_COUNTER_RESET_SHIFT (13U)
- #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_WORD_COUNTER_RESET_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFDFFF))
- #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_WORD_COUNTER_RESET_EN (IMG_UINT64_C(0X0000000000002000))
- #define VHA_CR_PERF_SLC_CMD_REQ_RD_WORD_COUNTER_RESET_SHIFT (12U)
- #define VHA_CR_PERF_SLC_CMD_REQ_RD_WORD_COUNTER_RESET_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFEFFF))
- #define VHA_CR_PERF_SLC_CMD_REQ_RD_WORD_COUNTER_RESET_EN (IMG_UINT64_C(0X0000000000001000))
- #define VHA_CR_PERF_SLC_OPK_REQ_WR_COUNTER_RESET_SHIFT (11U)
- #define VHA_CR_PERF_SLC_OPK_REQ_WR_COUNTER_RESET_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF7FF))
- #define VHA_CR_PERF_SLC_OPK_REQ_WR_COUNTER_RESET_EN (IMG_UINT64_C(0X0000000000000800))
- #define VHA_CR_PERF_SLC_ABUF_REQ_RD_COUNTER_RESET_SHIFT (10U)
- #define VHA_CR_PERF_SLC_ABUF_REQ_RD_COUNTER_RESET_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFBFF))
- #define VHA_CR_PERF_SLC_ABUF_REQ_RD_COUNTER_RESET_EN (IMG_UINT64_C(0X0000000000000400))
- #define VHA_CR_PERF_SLC_CBUF_REQ_RD_COUNTER_RESET_SHIFT (9U)
- #define VHA_CR_PERF_SLC_CBUF_REQ_RD_COUNTER_RESET_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFDFF))
- #define VHA_CR_PERF_SLC_CBUF_REQ_RD_COUNTER_RESET_EN (IMG_UINT64_C(0X0000000000000200))
- #define VHA_CR_PERF_SLC_MMM_REQ_WR_COUNTER_RESET_SHIFT (7U)
- #define VHA_CR_PERF_SLC_MMM_REQ_WR_COUNTER_RESET_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFF7F))
- #define VHA_CR_PERF_SLC_MMM_REQ_WR_COUNTER_RESET_EN (IMG_UINT64_C(0X0000000000000080))
- #define VHA_CR_PERF_SLC_MMM_REQ_RD_COUNTER_RESET_SHIFT (6U)
- #define VHA_CR_PERF_SLC_MMM_REQ_RD_COUNTER_RESET_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFBF))
- #define VHA_CR_PERF_SLC_MMM_REQ_RD_COUNTER_RESET_EN (IMG_UINT64_C(0X0000000000000040))
- #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_COUNTER_RESET_SHIFT (5U)
- #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_COUNTER_RESET_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFDF))
- #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_COUNTER_RESET_EN (IMG_UINT64_C(0X0000000000000020))
- #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_COUNTER_RESET_SHIFT (4U)
- #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_COUNTER_RESET_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFEF))
- #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_COUNTER_RESET_EN (IMG_UINT64_C(0X0000000000000010))
- #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_COUNTER_RESET_SHIFT (3U)
- #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_COUNTER_RESET_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF7))
- #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_COUNTER_RESET_EN (IMG_UINT64_C(0X0000000000000008))
- #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_COUNTER_RESET_SHIFT (2U)
- #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_COUNTER_RESET_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFB))
- #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_COUNTER_RESET_EN (IMG_UINT64_C(0X0000000000000004))
- #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_COUNTER_RESET_SHIFT (1U)
- #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_COUNTER_RESET_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFD))
- #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_COUNTER_RESET_EN (IMG_UINT64_C(0X0000000000000002))
- #define VHA_CR_PERF_SLC_CMD_REQ_RD_COUNTER_RESET_SHIFT (0U)
- #define VHA_CR_PERF_SLC_CMD_REQ_RD_COUNTER_RESET_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
- #define VHA_CR_PERF_SLC_CMD_REQ_RD_COUNTER_RESET_EN (IMG_UINT64_C(0X0000000000000001))
- /*
- Register VHA_CR_PERF_SLC_REQ_COUNT
- */
- #define VHA_CR_PERF_SLC_REQ_COUNT (0x70C8U)
- #define VHA_CR_PERF_SLC_REQ_COUNT_MASKFULL (IMG_UINT64_C(0x0000000000000001))
- #define VHA_CR_PERF_SLC_REQ_COUNT_ENABLE_SHIFT (0U)
- #define VHA_CR_PERF_SLC_REQ_COUNT_ENABLE_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_PERF_SLC_REQ_COUNT_ENABLE_EN (0X00000001U)
- /*
- Register VHA_CR_PERF_SLC_CMD_REQ_RD
- */
- #define VHA_CR_PERF_SLC_CMD_REQ_RD (0x70D0U)
- #define VHA_CR_PERF_SLC_CMD_REQ_RD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_PERF_SLC_CMD_REQ_RD_COUNTER_SHIFT (0U)
- #define VHA_CR_PERF_SLC_CMD_REQ_RD_COUNTER_CLRMSK (00000000U)
- /*
- Register VHA_CR_PERF_SLC_CMD_BCK_REQ_WR
- */
- #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR (0x70D8U)
- #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_COUNTER_SHIFT (0U)
- #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_COUNTER_CLRMSK (00000000U)
- /*
- Register VHA_CR_PERF_SLC_CMD_CRC_REQ_WR
- */
- #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR (0x70E0U)
- #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_COUNTER_SHIFT (0U)
- #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_COUNTER_CLRMSK (00000000U)
- /*
- Register VHA_CR_PERF_SLC_CMD_DBG_REQ_WR
- */
- #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR (0x70E8U)
- #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_COUNTER_SHIFT (0U)
- #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_COUNTER_CLRMSK (00000000U)
- /*
- Register VHA_CR_PERF_SLC_CMD_REQ_FENCE
- */
- #define VHA_CR_PERF_SLC_CMD_REQ_FENCE (0x70F0U)
- #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_COUNTER_SHIFT (0U)
- #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_COUNTER_CLRMSK (00000000U)
- /*
- Register VHA_CR_PERF_SLC_IBUF_REQ0_RD
- */
- #define VHA_CR_PERF_SLC_IBUF_REQ0_RD (0x70F8U)
- #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_COUNTER_SHIFT (0U)
- #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_COUNTER_CLRMSK (00000000U)
- /*
- Register VHA_CR_PERF_SLC_MMM_REQ_RD
- */
- #define VHA_CR_PERF_SLC_MMM_REQ_RD (0x7100U)
- #define VHA_CR_PERF_SLC_MMM_REQ_RD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_PERF_SLC_MMM_REQ_RD_COUNTER_SHIFT (0U)
- #define VHA_CR_PERF_SLC_MMM_REQ_RD_COUNTER_CLRMSK (00000000U)
- /*
- Register VHA_CR_PERF_SLC_MMM_REQ_WR
- */
- #define VHA_CR_PERF_SLC_MMM_REQ_WR (0x7108U)
- #define VHA_CR_PERF_SLC_MMM_REQ_WR_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_PERF_SLC_MMM_REQ_WR_COUNTER_SHIFT (0U)
- #define VHA_CR_PERF_SLC_MMM_REQ_WR_COUNTER_CLRMSK (00000000U)
- /*
- Register VHA_CR_PERF_SLC_CBUF_REQ_RD
- */
- #define VHA_CR_PERF_SLC_CBUF_REQ_RD (0x7110U)
- #define VHA_CR_PERF_SLC_CBUF_REQ_RD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_PERF_SLC_CBUF_REQ_RD_COUNTER_SHIFT (0U)
- #define VHA_CR_PERF_SLC_CBUF_REQ_RD_COUNTER_CLRMSK (00000000U)
- /*
- Register VHA_CR_PERF_SLC_ABUF_REQ_RD
- */
- #define VHA_CR_PERF_SLC_ABUF_REQ_RD (0x7118U)
- #define VHA_CR_PERF_SLC_ABUF_REQ_RD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_PERF_SLC_ABUF_REQ_RD_COUNTER_SHIFT (0U)
- #define VHA_CR_PERF_SLC_ABUF_REQ_RD_COUNTER_CLRMSK (00000000U)
- /*
- Register VHA_CR_PERF_SLC_OPK_REQ_WR
- */
- #define VHA_CR_PERF_SLC_OPK_REQ_WR (0x7120U)
- #define VHA_CR_PERF_SLC_OPK_REQ_WR_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_PERF_SLC_OPK_REQ_WR_COUNTER_SHIFT (0U)
- #define VHA_CR_PERF_SLC_OPK_REQ_WR_COUNTER_CLRMSK (00000000U)
- /*
- Register VHA_CR_PERF_SLC_CMD_REQ_RD_WORD
- */
- #define VHA_CR_PERF_SLC_CMD_REQ_RD_WORD (0x7128U)
- #define VHA_CR_PERF_SLC_CMD_REQ_RD_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_PERF_SLC_CMD_REQ_RD_WORD_COUNTER_SHIFT (0U)
- #define VHA_CR_PERF_SLC_CMD_REQ_RD_WORD_COUNTER_CLRMSK (00000000U)
- /*
- Register VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_WORD
- */
- #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_WORD (0x7130U)
- #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_WORD_COUNTER_SHIFT (0U)
- #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_WORD_COUNTER_CLRMSK (00000000U)
- /*
- Register VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_WORD
- */
- #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_WORD (0x7138U)
- #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_WORD_COUNTER_SHIFT (0U)
- #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_WORD_COUNTER_CLRMSK (00000000U)
- /*
- Register VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_WORD
- */
- #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_WORD (0x7140U)
- #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_WORD_COUNTER_SHIFT (0U)
- #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_WORD_COUNTER_CLRMSK (00000000U)
- /*
- Register VHA_CR_PERF_SLC_CMD_REQ_FENCE_WORD
- */
- #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_WORD (0x7148U)
- #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_WORD_COUNTER_SHIFT (0U)
- #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_WORD_COUNTER_CLRMSK (00000000U)
- /*
- Register VHA_CR_PERF_SLC_IBUF_REQ0_RD_WORD
- */
- #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_WORD (0x7150U)
- #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_WORD_COUNTER_SHIFT (0U)
- #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_WORD_COUNTER_CLRMSK (00000000U)
- /*
- Register VHA_CR_PERF_SLC_MMM_REQ_RD_WORD
- */
- #define VHA_CR_PERF_SLC_MMM_REQ_RD_WORD (0x7158U)
- #define VHA_CR_PERF_SLC_MMM_REQ_RD_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_PERF_SLC_MMM_REQ_RD_WORD_COUNTER_SHIFT (0U)
- #define VHA_CR_PERF_SLC_MMM_REQ_RD_WORD_COUNTER_CLRMSK (00000000U)
- /*
- Register VHA_CR_PERF_SLC_MMM_REQ_WR_WORD
- */
- #define VHA_CR_PERF_SLC_MMM_REQ_WR_WORD (0x7160U)
- #define VHA_CR_PERF_SLC_MMM_REQ_WR_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_PERF_SLC_MMM_REQ_WR_WORD_COUNTER_SHIFT (0U)
- #define VHA_CR_PERF_SLC_MMM_REQ_WR_WORD_COUNTER_CLRMSK (00000000U)
- /*
- Register VHA_CR_PERF_SLC_CBUF_REQ_RD_WORD
- */
- #define VHA_CR_PERF_SLC_CBUF_REQ_RD_WORD (0x7168U)
- #define VHA_CR_PERF_SLC_CBUF_REQ_RD_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_PERF_SLC_CBUF_REQ_RD_WORD_COUNTER_SHIFT (0U)
- #define VHA_CR_PERF_SLC_CBUF_REQ_RD_WORD_COUNTER_CLRMSK (00000000U)
- /*
- Register VHA_CR_PERF_SLC_ABUF_REQ_RD_WORD
- */
- #define VHA_CR_PERF_SLC_ABUF_REQ_RD_WORD (0x7170U)
- #define VHA_CR_PERF_SLC_ABUF_REQ_RD_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_PERF_SLC_ABUF_REQ_RD_WORD_COUNTER_SHIFT (0U)
- #define VHA_CR_PERF_SLC_ABUF_REQ_RD_WORD_COUNTER_CLRMSK (00000000U)
- /*
- Register VHA_CR_PERF_SLC_OPK_REQ_WR_WORD
- */
- #define VHA_CR_PERF_SLC_OPK_REQ_WR_WORD (0x7178U)
- #define VHA_CR_PERF_SLC_OPK_REQ_WR_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_PERF_SLC_OPK_REQ_WR_WORD_COUNTER_SHIFT (0U)
- #define VHA_CR_PERF_SLC_OPK_REQ_WR_WORD_COUNTER_CLRMSK (00000000U)
- /*
- Register VHA_CR_PERF_SLC_MMU_REQ_RD
- */
- #define VHA_CR_PERF_SLC_MMU_REQ_RD (0x7180U)
- #define VHA_CR_PERF_SLC_MMU_REQ_RD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_PERF_SLC_MMU_REQ_RD_COUNTER_SHIFT (0U)
- #define VHA_CR_PERF_SLC_MMU_REQ_RD_COUNTER_CLRMSK (00000000U)
- /*
- Register VHA_CR_PERF_SLC_MMU_REQ_RD_WORD
- */
- #define VHA_CR_PERF_SLC_MMU_REQ_RD_WORD (0x7188U)
- #define VHA_CR_PERF_SLC_MMU_REQ_RD_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_PERF_SLC_MMU_REQ_RD_WORD_COUNTER_SHIFT (0U)
- #define VHA_CR_PERF_SLC_MMU_REQ_RD_WORD_COUNTER_CLRMSK (00000000U)
- /*
- Register VHA_CR_PERF_SLC_EWO_REQ_RD
- */
- #define VHA_CR_PERF_SLC_EWO_REQ_RD (0x7190U)
- #define VHA_CR_PERF_SLC_EWO_REQ_RD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_PERF_SLC_EWO_REQ_RD_COUNTER_SHIFT (0U)
- #define VHA_CR_PERF_SLC_EWO_REQ_RD_COUNTER_CLRMSK (00000000U)
- /*
- Register VHA_CR_PERF_SLC_EWO_REQ_RD_WORD
- */
- #define VHA_CR_PERF_SLC_EWO_REQ_RD_WORD (0x7198U)
- #define VHA_CR_PERF_SLC_EWO_REQ_RD_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_PERF_SLC_EWO_REQ_RD_WORD_COUNTER_SHIFT (0U)
- #define VHA_CR_PERF_SLC_EWO_REQ_RD_WORD_COUNTER_CLRMSK (00000000U)
- /*
- Register VHA_CR_MMU_PAGE_SIZE_RANGE_ONE
- */
- #define VHA_CR_MMU_PAGE_SIZE_RANGE_ONE (0x7468U)
- #define VHA_CR_MMU_PAGE_SIZE_RANGE_ONE_MASKFULL (IMG_UINT64_C(0x000001FFFFFFFFFF))
- #define VHA_CR_MMU_PAGE_SIZE_RANGE_ONE_PAGE_SIZE_SHIFT (38U)
- #define VHA_CR_MMU_PAGE_SIZE_RANGE_ONE_PAGE_SIZE_CLRMSK (IMG_UINT64_C(0XFFFFFE3FFFFFFFFF))
- #define VHA_CR_MMU_PAGE_SIZE_RANGE_ONE_END_ADDR_SHIFT (19U)
- #define VHA_CR_MMU_PAGE_SIZE_RANGE_ONE_END_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFFC00007FFFF))
- #define VHA_CR_MMU_PAGE_SIZE_RANGE_ONE_END_ADDR_ALIGNSHIFT (21U)
- #define VHA_CR_MMU_PAGE_SIZE_RANGE_ONE_END_ADDR_ALIGNSIZE (2097152U)
- #define VHA_CR_MMU_PAGE_SIZE_RANGE_ONE_BASE_ADDR_SHIFT (0U)
- #define VHA_CR_MMU_PAGE_SIZE_RANGE_ONE_BASE_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF80000))
- #define VHA_CR_MMU_PAGE_SIZE_RANGE_ONE_BASE_ADDR_ALIGNSHIFT (21U)
- #define VHA_CR_MMU_PAGE_SIZE_RANGE_ONE_BASE_ADDR_ALIGNSIZE (2097152U)
- /*
- Register VHA_CR_MMU_PAGE_SIZE_RANGE_TWO
- */
- #define VHA_CR_MMU_PAGE_SIZE_RANGE_TWO (0x7470U)
- #define VHA_CR_MMU_PAGE_SIZE_RANGE_TWO_MASKFULL (IMG_UINT64_C(0x000001FFFFFFFFFF))
- #define VHA_CR_MMU_PAGE_SIZE_RANGE_TWO_PAGE_SIZE_SHIFT (38U)
- #define VHA_CR_MMU_PAGE_SIZE_RANGE_TWO_PAGE_SIZE_CLRMSK (IMG_UINT64_C(0XFFFFFE3FFFFFFFFF))
- #define VHA_CR_MMU_PAGE_SIZE_RANGE_TWO_END_ADDR_SHIFT (19U)
- #define VHA_CR_MMU_PAGE_SIZE_RANGE_TWO_END_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFFC00007FFFF))
- #define VHA_CR_MMU_PAGE_SIZE_RANGE_TWO_END_ADDR_ALIGNSHIFT (21U)
- #define VHA_CR_MMU_PAGE_SIZE_RANGE_TWO_END_ADDR_ALIGNSIZE (2097152U)
- #define VHA_CR_MMU_PAGE_SIZE_RANGE_TWO_BASE_ADDR_SHIFT (0U)
- #define VHA_CR_MMU_PAGE_SIZE_RANGE_TWO_BASE_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF80000))
- #define VHA_CR_MMU_PAGE_SIZE_RANGE_TWO_BASE_ADDR_ALIGNSHIFT (21U)
- #define VHA_CR_MMU_PAGE_SIZE_RANGE_TWO_BASE_ADDR_ALIGNSIZE (2097152U)
- /*
- Register VHA_CR_MMU_PAGE_SIZE_RANGE_THREE
- */
- #define VHA_CR_MMU_PAGE_SIZE_RANGE_THREE (0x7478U)
- #define VHA_CR_MMU_PAGE_SIZE_RANGE_THREE_MASKFULL (IMG_UINT64_C(0x000001FFFFFFFFFF))
- #define VHA_CR_MMU_PAGE_SIZE_RANGE_THREE_PAGE_SIZE_SHIFT (38U)
- #define VHA_CR_MMU_PAGE_SIZE_RANGE_THREE_PAGE_SIZE_CLRMSK (IMG_UINT64_C(0XFFFFFE3FFFFFFFFF))
- #define VHA_CR_MMU_PAGE_SIZE_RANGE_THREE_END_ADDR_SHIFT (19U)
- #define VHA_CR_MMU_PAGE_SIZE_RANGE_THREE_END_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFFC00007FFFF))
- #define VHA_CR_MMU_PAGE_SIZE_RANGE_THREE_END_ADDR_ALIGNSHIFT (21U)
- #define VHA_CR_MMU_PAGE_SIZE_RANGE_THREE_END_ADDR_ALIGNSIZE (2097152U)
- #define VHA_CR_MMU_PAGE_SIZE_RANGE_THREE_BASE_ADDR_SHIFT (0U)
- #define VHA_CR_MMU_PAGE_SIZE_RANGE_THREE_BASE_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF80000))
- #define VHA_CR_MMU_PAGE_SIZE_RANGE_THREE_BASE_ADDR_ALIGNSHIFT (21U)
- #define VHA_CR_MMU_PAGE_SIZE_RANGE_THREE_BASE_ADDR_ALIGNSIZE (2097152U)
- /*
- Register VHA_CR_MMU_PAGE_SIZE_RANGE_FOUR
- */
- #define VHA_CR_MMU_PAGE_SIZE_RANGE_FOUR (0x7480U)
- #define VHA_CR_MMU_PAGE_SIZE_RANGE_FOUR_MASKFULL (IMG_UINT64_C(0x000001FFFFFFFFFF))
- #define VHA_CR_MMU_PAGE_SIZE_RANGE_FOUR_PAGE_SIZE_SHIFT (38U)
- #define VHA_CR_MMU_PAGE_SIZE_RANGE_FOUR_PAGE_SIZE_CLRMSK (IMG_UINT64_C(0XFFFFFE3FFFFFFFFF))
- #define VHA_CR_MMU_PAGE_SIZE_RANGE_FOUR_END_ADDR_SHIFT (19U)
- #define VHA_CR_MMU_PAGE_SIZE_RANGE_FOUR_END_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFFC00007FFFF))
- #define VHA_CR_MMU_PAGE_SIZE_RANGE_FOUR_END_ADDR_ALIGNSHIFT (21U)
- #define VHA_CR_MMU_PAGE_SIZE_RANGE_FOUR_END_ADDR_ALIGNSIZE (2097152U)
- #define VHA_CR_MMU_PAGE_SIZE_RANGE_FOUR_BASE_ADDR_SHIFT (0U)
- #define VHA_CR_MMU_PAGE_SIZE_RANGE_FOUR_BASE_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF80000))
- #define VHA_CR_MMU_PAGE_SIZE_RANGE_FOUR_BASE_ADDR_ALIGNSHIFT (21U)
- #define VHA_CR_MMU_PAGE_SIZE_RANGE_FOUR_BASE_ADDR_ALIGNSIZE (2097152U)
- #define VHA_CR_SLC_CTRL_ENUM_HASH_MODE_MASK (0x00000003U)
- /*
- Reserved value */
- #define VHA_CR_SLC_CTRL_ENUM_HASH_MODE_RESERVED (0x00000000U)
- /*
- Addresses interleaved between Cache Bank using a combined Set & Bank hash of the upper address bits */
- #define VHA_CR_SLC_CTRL_ENUM_HASH_MODE_PVR_V3_HASHING (0x00000001U)
- /*
- Addresses are interleaved between Cache Banks on a Cacheline boundary */
- #define VHA_CR_SLC_CTRL_ENUM_HASH_MODE_LINEAR (0x00000002U)
- /*
- Addresses interleaved between Cache Banks using an XOR hash of the address bits below the 4KB page granularity */
- #define VHA_CR_SLC_CTRL_ENUM_HASH_MODE_IN_PAGE_HASH (0x00000003U)
- /*
- Register VHA_CR_SLC_CTRL
- */
- #define VHA_CR_SLC_CTRL (0x7488U)
- #define VHA_CR_SLC_CTRL_MASKFULL (IMG_UINT64_C(0x000000000001FFF3))
- #define VHA_CR_SLC_CTRL_RESERVED_SHIFT (7U)
- #define VHA_CR_SLC_CTRL_RESERVED_CLRMSK (0XFFFE007FU)
- #define VHA_CR_SLC_CTRL_MAX_FENCES_SHIFT (4U)
- #define VHA_CR_SLC_CTRL_MAX_FENCES_CLRMSK (0XFFFFFF8FU)
- #define VHA_CR_SLC_CTRL_HASH_MODE_SHIFT (0U)
- #define VHA_CR_SLC_CTRL_HASH_MODE_CLRMSK (0XFFFFFFFCU)
- #define VHA_CR_SLC_CTRL_HASH_MODE_RESERVED (00000000U)
- #define VHA_CR_SLC_CTRL_HASH_MODE_PVR_V3_HASHING (0X00000001U)
- #define VHA_CR_SLC_CTRL_HASH_MODE_LINEAR (0X00000002U)
- #define VHA_CR_SLC_CTRL_HASH_MODE_IN_PAGE_HASH (0X00000003U)
- /*
- Register VHA_CR_SLC_FAULT_STOP_CTRL
- */
- #define VHA_CR_SLC_FAULT_STOP_CTRL (0x7498U)
- #define VHA_CR_SLC_FAULT_STOP_CTRL_MASKFULL (IMG_UINT64_C(0x000000000003FFFF))
- #define VHA_CR_SLC_FAULT_STOP_CTRL_ALL_SHIFT (17U)
- #define VHA_CR_SLC_FAULT_STOP_CTRL_ALL_CLRMSK (0XFFFDFFFFU)
- #define VHA_CR_SLC_FAULT_STOP_CTRL_ALL_EN (0X00020000U)
- #define VHA_CR_SLC_FAULT_STOP_CTRL_ENABLE_SHIFT (0U)
- #define VHA_CR_SLC_FAULT_STOP_CTRL_ENABLE_CLRMSK (0XFFFE0000U)
- /*
- Register VHA_CR_MMU_OSID_CTXT_MAPPING0
- */
- #define VHA_CR_MMU_OSID_CTXT_MAPPING0 (0x7500U)
- #define VHA_CR_MMU_OSID_CTXT_MAPPING0_MASKFULL (IMG_UINT64_C(0x7777777777777777))
- #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_15_SHIFT (60U)
- #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_15_CLRMSK (IMG_UINT64_C(0X8FFFFFFFFFFFFFFF))
- #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_14_SHIFT (56U)
- #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_14_CLRMSK (IMG_UINT64_C(0XF8FFFFFFFFFFFFFF))
- #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_13_SHIFT (52U)
- #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_13_CLRMSK (IMG_UINT64_C(0XFF8FFFFFFFFFFFFF))
- #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_12_SHIFT (48U)
- #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_12_CLRMSK (IMG_UINT64_C(0XFFF8FFFFFFFFFFFF))
- #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_11_SHIFT (44U)
- #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_11_CLRMSK (IMG_UINT64_C(0XFFFF8FFFFFFFFFFF))
- #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_10_SHIFT (40U)
- #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_10_CLRMSK (IMG_UINT64_C(0XFFFFF8FFFFFFFFFF))
- #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_9_SHIFT (36U)
- #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_9_CLRMSK (IMG_UINT64_C(0XFFFFFF8FFFFFFFFF))
- #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_8_SHIFT (32U)
- #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_8_CLRMSK (IMG_UINT64_C(0XFFFFFFF8FFFFFFFF))
- #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_7_SHIFT (28U)
- #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_7_CLRMSK (IMG_UINT64_C(0XFFFFFFFF8FFFFFFF))
- #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_6_SHIFT (24U)
- #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_6_CLRMSK (IMG_UINT64_C(0XFFFFFFFFF8FFFFFF))
- #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_5_SHIFT (20U)
- #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_5_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF8FFFFF))
- #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_4_SHIFT (16U)
- #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_4_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF8FFFF))
- #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_3_SHIFT (12U)
- #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_3_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF8FFF))
- #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_2_SHIFT (8U)
- #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_2_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF8FF))
- #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_1_SHIFT (4U)
- #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFF8F))
- #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_0_SHIFT (0U)
- #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_0_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF8))
- /*
- Register VHA_CR_MMU_OSID_CTXT_MAPPING1
- */
- #define VHA_CR_MMU_OSID_CTXT_MAPPING1 (0x7508U)
- #define VHA_CR_MMU_OSID_CTXT_MAPPING1_MASKFULL (IMG_UINT64_C(0x7777777777777777))
- #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_31_SHIFT (60U)
- #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_31_CLRMSK (IMG_UINT64_C(0X8FFFFFFFFFFFFFFF))
- #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_30_SHIFT (56U)
- #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_30_CLRMSK (IMG_UINT64_C(0XF8FFFFFFFFFFFFFF))
- #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_29_SHIFT (52U)
- #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_29_CLRMSK (IMG_UINT64_C(0XFF8FFFFFFFFFFFFF))
- #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_28_SHIFT (48U)
- #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_28_CLRMSK (IMG_UINT64_C(0XFFF8FFFFFFFFFFFF))
- #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_27_SHIFT (44U)
- #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_27_CLRMSK (IMG_UINT64_C(0XFFFF8FFFFFFFFFFF))
- #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_26_SHIFT (40U)
- #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_26_CLRMSK (IMG_UINT64_C(0XFFFFF8FFFFFFFFFF))
- #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_25_SHIFT (36U)
- #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_25_CLRMSK (IMG_UINT64_C(0XFFFFFF8FFFFFFFFF))
- #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_24_SHIFT (32U)
- #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_24_CLRMSK (IMG_UINT64_C(0XFFFFFFF8FFFFFFFF))
- #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_23_SHIFT (28U)
- #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_23_CLRMSK (IMG_UINT64_C(0XFFFFFFFF8FFFFFFF))
- #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_22_SHIFT (24U)
- #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_22_CLRMSK (IMG_UINT64_C(0XFFFFFFFFF8FFFFFF))
- #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_21_SHIFT (20U)
- #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_21_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF8FFFFF))
- #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_20_SHIFT (16U)
- #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_20_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF8FFFF))
- #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_19_SHIFT (12U)
- #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_19_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF8FFF))
- #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_18_SHIFT (8U)
- #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_18_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF8FF))
- #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_17_SHIFT (4U)
- #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_17_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFF8F))
- #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_16_SHIFT (0U)
- #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_16_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF8))
- /*
- Register VHA_CR_ACE_QOS_CTRL
- */
- #define VHA_CR_ACE_QOS_CTRL (0x7580U)
- #define VHA_CR_ACE_QOS_CTRL_MASKFULL (IMG_UINT64_C(0x000000000000FFFF))
- #define VHA_CR_ACE_QOS_CTRL_CRITICAL_SHIFT (12U)
- #define VHA_CR_ACE_QOS_CTRL_CRITICAL_CLRMSK (0XFFFF0FFFU)
- #define VHA_CR_ACE_QOS_CTRL_HIGH_SHIFT (8U)
- #define VHA_CR_ACE_QOS_CTRL_HIGH_CLRMSK (0XFFFFF0FFU)
- #define VHA_CR_ACE_QOS_CTRL_MEDIUM_SHIFT (4U)
- #define VHA_CR_ACE_QOS_CTRL_MEDIUM_CLRMSK (0XFFFFFF0FU)
- #define VHA_CR_ACE_QOS_CTRL_LOW_SHIFT (0U)
- #define VHA_CR_ACE_QOS_CTRL_LOW_CLRMSK (0XFFFFFFF0U)
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_ENUM_PRIORITIES_MASK (0x00000003U)
- /*
- Low */
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_ENUM_PRIORITIES_LOW (0x00000000U)
- /*
- Medium */
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_ENUM_PRIORITIES_MEDIUM (0x00000001U)
- /*
- High */
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_ENUM_PRIORITIES_HIGH (0x00000002U)
- /*
- Critical */
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_ENUM_PRIORITIES_CRITICAL (0x00000003U)
- /*
- Register VHA_CR_ACE_PRIORITY_MAPPING_CTRL
- */
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL (0x7588U)
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MASKFULL (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMU_SHIFT (62U)
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMU_CLRMSK (IMG_UINT64_C(0X3FFFFFFFFFFFFFFF))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMU_LOW (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMU_MEDIUM (IMG_UINT64_C(0x4000000000000000))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMU_HIGH (IMG_UINT64_C(0x8000000000000000))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMU_CRITICAL (IMG_UINT64_C(0xc000000000000000))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_RESERVED_SHIFT (32U)
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_RESERVED_CLRMSK (IMG_UINT64_C(0XC0000000FFFFFFFF))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TRS_B_SHIFT (30U)
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TRS_B_CLRMSK (IMG_UINT64_C(0XFFFFFFFF3FFFFFFF))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TRS_B_LOW (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TRS_B_MEDIUM (IMG_UINT64_C(0x0000000040000000))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TRS_B_HIGH (IMG_UINT64_C(0x0000000080000000))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TRS_B_CRITICAL (IMG_UINT64_C(0x00000000c0000000))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TRS_A_SHIFT (28U)
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TRS_A_CLRMSK (IMG_UINT64_C(0XFFFFFFFFCFFFFFFF))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TRS_A_LOW (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TRS_A_MEDIUM (IMG_UINT64_C(0x0000000010000000))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TRS_A_HIGH (IMG_UINT64_C(0x0000000020000000))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TRS_A_CRITICAL (IMG_UINT64_C(0x0000000030000000))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_POOL_SHIFT (26U)
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_POOL_CLRMSK (IMG_UINT64_C(0XFFFFFFFFF3FFFFFF))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_POOL_LOW (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_POOL_MEDIUM (IMG_UINT64_C(0x0000000004000000))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_POOL_HIGH (IMG_UINT64_C(0x0000000008000000))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_POOL_CRITICAL (IMG_UINT64_C(0x000000000c000000))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMM_WR_SHIFT (24U)
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMM_WR_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFCFFFFFF))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMM_WR_LOW (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMM_WR_MEDIUM (IMG_UINT64_C(0x0000000001000000))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMM_WR_HIGH (IMG_UINT64_C(0x0000000002000000))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMM_WR_CRITICAL (IMG_UINT64_C(0x0000000003000000))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMM_RD_SHIFT (22U)
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMM_RD_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF3FFFFF))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMM_RD_LOW (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMM_RD_MEDIUM (IMG_UINT64_C(0x0000000000400000))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMM_RD_HIGH (IMG_UINT64_C(0x0000000000800000))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMM_RD_CRITICAL (IMG_UINT64_C(0x0000000000c00000))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_EWO_PSF_SHIFT (20U)
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_EWO_PSF_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFCFFFFF))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_EWO_PSF_LOW (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_EWO_PSF_MEDIUM (IMG_UINT64_C(0x0000000000100000))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_EWO_PSF_HIGH (IMG_UINT64_C(0x0000000000200000))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_EWO_PSF_CRITICAL (IMG_UINT64_C(0x0000000000300000))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_EWO_SHIFT (18U)
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_EWO_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF3FFFF))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_EWO_LOW (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_EWO_MEDIUM (IMG_UINT64_C(0x0000000000040000))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_EWO_HIGH (IMG_UINT64_C(0x0000000000080000))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_EWO_CRITICAL (IMG_UINT64_C(0x00000000000c0000))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_OUTPACK_SHIFT (16U)
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_OUTPACK_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFCFFFF))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_OUTPACK_LOW (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_OUTPACK_MEDIUM (IMG_UINT64_C(0x0000000000010000))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_OUTPACK_HIGH (IMG_UINT64_C(0x0000000000020000))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_OUTPACK_CRITICAL (IMG_UINT64_C(0x0000000000030000))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_ABUF_SHIFT (14U)
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_ABUF_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF3FFF))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_ABUF_LOW (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_ABUF_MEDIUM (IMG_UINT64_C(0x0000000000004000))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_ABUF_HIGH (IMG_UINT64_C(0x0000000000008000))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_ABUF_CRITICAL (IMG_UINT64_C(0x000000000000c000))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CBUF_SHIFT (12U)
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CBUF_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFCFFF))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CBUF_LOW (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CBUF_MEDIUM (IMG_UINT64_C(0x0000000000001000))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CBUF_HIGH (IMG_UINT64_C(0x0000000000002000))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CBUF_CRITICAL (IMG_UINT64_C(0x0000000000003000))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_IBUF_0_SHIFT (10U)
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_IBUF_0_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF3FF))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_IBUF_0_LOW (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_IBUF_0_MEDIUM (IMG_UINT64_C(0x0000000000000400))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_IBUF_0_HIGH (IMG_UINT64_C(0x0000000000000800))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_IBUF_0_CRITICAL (IMG_UINT64_C(0x0000000000000c00))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_4_SHIFT (8U)
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_4_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFCFF))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_4_LOW (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_4_MEDIUM (IMG_UINT64_C(0x0000000000000100))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_4_HIGH (IMG_UINT64_C(0x0000000000000200))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_4_CRITICAL (IMG_UINT64_C(0x0000000000000300))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_3_SHIFT (6U)
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_3_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFF3F))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_3_LOW (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_3_MEDIUM (IMG_UINT64_C(0x0000000000000040))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_3_HIGH (IMG_UINT64_C(0x0000000000000080))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_3_CRITICAL (IMG_UINT64_C(0x00000000000000c0))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_2_SHIFT (4U)
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_2_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFCF))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_2_LOW (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_2_MEDIUM (IMG_UINT64_C(0x0000000000000010))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_2_HIGH (IMG_UINT64_C(0x0000000000000020))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_2_CRITICAL (IMG_UINT64_C(0x0000000000000030))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_1_SHIFT (2U)
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF3))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_1_LOW (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_1_MEDIUM (IMG_UINT64_C(0x0000000000000004))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_1_HIGH (IMG_UINT64_C(0x0000000000000008))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_1_CRITICAL (IMG_UINT64_C(0x000000000000000c))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_0_SHIFT (0U)
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_0_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFC))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_0_LOW (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_0_MEDIUM (IMG_UINT64_C(0x0000000000000001))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_0_HIGH (IMG_UINT64_C(0x0000000000000002))
- #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_0_CRITICAL (IMG_UINT64_C(0x0000000000000003))
- #define VHA_CR_ACE_CTRL_ENUM_WR_CACHEABLE_MASK (0x0000000FU)
- /*
- Device Non-bufferable */
- #define VHA_CR_ACE_CTRL_ENUM_WR_CACHEABLE_DEVICE_NON_BUFFERABLE (0x00000000U)
- /*
- Device Bufferable */
- #define VHA_CR_ACE_CTRL_ENUM_WR_CACHEABLE_DEVICE_BUFFERABLE (0x00000001U)
- /*
- Normal Non-cacheable Non-bufferable */
- #define VHA_CR_ACE_CTRL_ENUM_WR_CACHEABLE_NORMAL_NC_NON_BUFFERABLE (0x00000002U)
- /*
- Normal Non-cacheable Bufferable */
- #define VHA_CR_ACE_CTRL_ENUM_WR_CACHEABLE_NORMAL_NC_BUFFERABLE (0x00000003U)
- /*
- Write-through No-allocate */
- #define VHA_CR_ACE_CTRL_ENUM_WR_CACHEABLE_WRITE_THROUGH_NO_ALLOCATE (0x00000006U)
- /*
- Write-through Write-allocate */
- #define VHA_CR_ACE_CTRL_ENUM_WR_CACHEABLE_WRITE_THROUGH_WRITE_ALLOCATE (0x0000000eU)
- /*
- Write-back No-allocate */
- #define VHA_CR_ACE_CTRL_ENUM_WR_CACHEABLE_WRITE_BACK_NO_ALLOCATE (0x00000007U)
- /*
- Write-back Write-allocate */
- #define VHA_CR_ACE_CTRL_ENUM_WR_CACHEABLE_WRITE_BACK_WRITE_ALLOCATE (0x0000000fU)
- #define VHA_CR_ACE_CTRL_ENUM_RD_CACHEABLE_MASK (0x0000000FU)
- /*
- Device Non-bufferable */
- #define VHA_CR_ACE_CTRL_ENUM_RD_CACHEABLE_DEVICE_NON_BUFFERABLE (0x00000000U)
- /*
- Device Bufferable */
- #define VHA_CR_ACE_CTRL_ENUM_RD_CACHEABLE_DEVICE_BUFFERABLE (0x00000001U)
- /*
- Normal Non-cacheable Non-bufferable */
- #define VHA_CR_ACE_CTRL_ENUM_RD_CACHEABLE_NORMAL_NC_NON_BUFFERABLE (0x00000002U)
- /*
- Normal Non-cacheable Bufferable */
- #define VHA_CR_ACE_CTRL_ENUM_RD_CACHEABLE_NORMAL_NC_BUFFERABLE (0x00000003U)
- /*
- Write-through No-allocate */
- #define VHA_CR_ACE_CTRL_ENUM_RD_CACHEABLE_WRITE_THROUGH_NO_ALLOCATE (0x0000000aU)
- /*
- Write-through Read-allocate */
- #define VHA_CR_ACE_CTRL_ENUM_RD_CACHEABLE_WRITE_THROUGH_READ_ALLOCATE (0x0000000eU)
- /*
- Write-back No-allocate */
- #define VHA_CR_ACE_CTRL_ENUM_RD_CACHEABLE_WRITE_BACK_NO_ALLOCATE (0x0000000bU)
- /*
- Write-back Read-allocate */
- #define VHA_CR_ACE_CTRL_ENUM_RD_CACHEABLE_WRITE_BACK_READ_ALLOCATE (0x0000000fU)
- /*
- Non-Shareable */
- #define VHA_CR_ACE_CTRL_ENUM_NCOH_DOMAIN_NON_SHAREABLE (0x00000000U)
- /*
- System */
- #define VHA_CR_ACE_CTRL_ENUM_NCOH_DOMAIN_SYSTEM (0x00000001U)
- /*
- Inner-Shareable */
- #define VHA_CR_ACE_CTRL_ENUM_COH_DOMAIN_INNER_SHAREABLE (0x00000000U)
- /*
- Outer-Shareable */
- #define VHA_CR_ACE_CTRL_ENUM_COH_DOMAIN_OUTER_SHAREABLE (0x00000001U)
- /*
- Register VHA_CR_ACE_CTRL
- */
- #define VHA_CR_ACE_CTRL (0x7590U)
- #define VHA_CR_ACE_CTRL_MASKFULL (IMG_UINT64_C(0x00000000007FCFFF))
- #define VHA_CR_ACE_CTRL_CLB_AXQOS_SHIFT (19U)
- #define VHA_CR_ACE_CTRL_CLB_AXQOS_CLRMSK (0XFF87FFFFU)
- #define VHA_CR_ACE_CTRL_PM_MMU_AXCACHE_SHIFT (15U)
- #define VHA_CR_ACE_CTRL_PM_MMU_AXCACHE_CLRMSK (0XFFF87FFFU)
- #define VHA_CR_ACE_CTRL_ENABLE_NONSECURE_PROT_MATCH_SHIFT (14U)
- #define VHA_CR_ACE_CTRL_ENABLE_NONSECURE_PROT_MATCH_CLRMSK (0XFFFFBFFFU)
- #define VHA_CR_ACE_CTRL_ENABLE_NONSECURE_PROT_MATCH_EN (0X00004000U)
- #define VHA_CR_ACE_CTRL_MMU_AWCACHE_SHIFT (8U)
- #define VHA_CR_ACE_CTRL_MMU_AWCACHE_CLRMSK (0XFFFFF0FFU)
- #define VHA_CR_ACE_CTRL_MMU_AWCACHE_DEVICE_NON_BUFFERABLE (00000000U)
- #define VHA_CR_ACE_CTRL_MMU_AWCACHE_DEVICE_BUFFERABLE (0X00000100U)
- #define VHA_CR_ACE_CTRL_MMU_AWCACHE_NORMAL_NC_NON_BUFFERABLE (0X00000200U)
- #define VHA_CR_ACE_CTRL_MMU_AWCACHE_NORMAL_NC_BUFFERABLE (0X00000300U)
- #define VHA_CR_ACE_CTRL_MMU_AWCACHE_WRITE_THROUGH_NO_ALLOCATE (0X00000600U)
- #define VHA_CR_ACE_CTRL_MMU_AWCACHE_WRITE_THROUGH_WRITE_ALLOCATE (0X00000E00U)
- #define VHA_CR_ACE_CTRL_MMU_AWCACHE_WRITE_BACK_NO_ALLOCATE (0X00000700U)
- #define VHA_CR_ACE_CTRL_MMU_AWCACHE_WRITE_BACK_WRITE_ALLOCATE (0X00000F00U)
- #define VHA_CR_ACE_CTRL_MMU_ARCACHE_SHIFT (4U)
- #define VHA_CR_ACE_CTRL_MMU_ARCACHE_CLRMSK (0XFFFFFF0FU)
- #define VHA_CR_ACE_CTRL_MMU_ARCACHE_DEVICE_NON_BUFFERABLE (00000000U)
- #define VHA_CR_ACE_CTRL_MMU_ARCACHE_DEVICE_BUFFERABLE (0X00000010U)
- #define VHA_CR_ACE_CTRL_MMU_ARCACHE_NORMAL_NC_NON_BUFFERABLE (0X00000020U)
- #define VHA_CR_ACE_CTRL_MMU_ARCACHE_NORMAL_NC_BUFFERABLE (0X00000030U)
- #define VHA_CR_ACE_CTRL_MMU_ARCACHE_WRITE_THROUGH_NO_ALLOCATE (0X000000A0U)
- #define VHA_CR_ACE_CTRL_MMU_ARCACHE_WRITE_THROUGH_READ_ALLOCATE (0X000000E0U)
- #define VHA_CR_ACE_CTRL_MMU_ARCACHE_WRITE_BACK_NO_ALLOCATE (0X000000B0U)
- #define VHA_CR_ACE_CTRL_MMU_ARCACHE_WRITE_BACK_READ_ALLOCATE (0X000000F0U)
- #define VHA_CR_ACE_CTRL_MMU_DOMAIN_SHIFT (2U)
- #define VHA_CR_ACE_CTRL_MMU_DOMAIN_CLRMSK (0XFFFFFFF3U)
- #define VHA_CR_ACE_CTRL_COH_DOMAIN_SHIFT (1U)
- #define VHA_CR_ACE_CTRL_COH_DOMAIN_CLRMSK (0XFFFFFFFDU)
- #define VHA_CR_ACE_CTRL_COH_DOMAIN_INNER_SHAREABLE (00000000U)
- #define VHA_CR_ACE_CTRL_COH_DOMAIN_OUTER_SHAREABLE (0X00000002U)
- #define VHA_CR_ACE_CTRL_NON_COH_DOMAIN_SHIFT (0U)
- #define VHA_CR_ACE_CTRL_NON_COH_DOMAIN_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_ACE_CTRL_NON_COH_DOMAIN_NON_SHAREABLE (00000000U)
- #define VHA_CR_ACE_CTRL_NON_COH_DOMAIN_SYSTEM (0X00000001U)
- /*
- Register VHA_CR_ACE_STATUS
- */
- #define VHA_CR_ACE_STATUS (0x7598U)
- #define VHA_CR_ACE_STATUS_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_ACE_STATUS_WR_BUS3_ERROR_SHIFT (28U)
- #define VHA_CR_ACE_STATUS_WR_BUS3_ERROR_CLRMSK (0X0FFFFFFFU)
- #define VHA_CR_ACE_STATUS_RD_BUS3_ERROR_SHIFT (24U)
- #define VHA_CR_ACE_STATUS_RD_BUS3_ERROR_CLRMSK (0XF0FFFFFFU)
- #define VHA_CR_ACE_STATUS_WR_BUS2_ERROR_SHIFT (20U)
- #define VHA_CR_ACE_STATUS_WR_BUS2_ERROR_CLRMSK (0XFF0FFFFFU)
- #define VHA_CR_ACE_STATUS_RD_BUS2_ERROR_SHIFT (16U)
- #define VHA_CR_ACE_STATUS_RD_BUS2_ERROR_CLRMSK (0XFFF0FFFFU)
- #define VHA_CR_ACE_STATUS_WR_BUS1_ERROR_SHIFT (12U)
- #define VHA_CR_ACE_STATUS_WR_BUS1_ERROR_CLRMSK (0XFFFF0FFFU)
- #define VHA_CR_ACE_STATUS_RD_BUS1_ERROR_SHIFT (8U)
- #define VHA_CR_ACE_STATUS_RD_BUS1_ERROR_CLRMSK (0XFFFFF0FFU)
- #define VHA_CR_ACE_STATUS_WR_BUS0_ERROR_SHIFT (4U)
- #define VHA_CR_ACE_STATUS_WR_BUS0_ERROR_CLRMSK (0XFFFFFF0FU)
- #define VHA_CR_ACE_STATUS_RD_BUS0_ERROR_SHIFT (0U)
- #define VHA_CR_ACE_STATUS_RD_BUS0_ERROR_CLRMSK (0XFFFFFFF0U)
- /*
- Register VHA_CR_PWR_MAN_HYSTERESIS
- */
- #define VHA_CR_PWR_MAN_HYSTERESIS (0x7608U)
- #define VHA_CR_PWR_MAN_HYSTERESIS_MASKFULL (IMG_UINT64_C(0x000000000000001F))
- #define VHA_CR_PWR_MAN_HYSTERESIS_VALUE_SHIFT (0U)
- #define VHA_CR_PWR_MAN_HYSTERESIS_VALUE_CLRMSK (0XFFFFFFE0U)
- /*
- Register VHA_CR_OS0_MMU_CTRL_INVAL
- */
- #define VHA_CR_OS0_MMU_CTRL_INVAL (0x76A8U)
- #define VHA_CR_OS0_MMU_CTRL_INVAL_MASKFULL (IMG_UINT64_C(0x0000000000000FFF))
- #define VHA_CR_OS0_MMU_CTRL_INVAL_ALL_CONTEXTS_SHIFT (11U)
- #define VHA_CR_OS0_MMU_CTRL_INVAL_ALL_CONTEXTS_CLRMSK (0XFFFFF7FFU)
- #define VHA_CR_OS0_MMU_CTRL_INVAL_ALL_CONTEXTS_EN (0X00000800U)
- #define VHA_CR_OS0_MMU_CTRL_INVAL_CONTEXT_SHIFT (3U)
- #define VHA_CR_OS0_MMU_CTRL_INVAL_CONTEXT_CLRMSK (0XFFFFF807U)
- #define VHA_CR_OS0_MMU_CTRL_INVAL_PC_SHIFT (2U)
- #define VHA_CR_OS0_MMU_CTRL_INVAL_PC_CLRMSK (0XFFFFFFFBU)
- #define VHA_CR_OS0_MMU_CTRL_INVAL_PC_EN (0X00000004U)
- #define VHA_CR_OS0_MMU_CTRL_INVAL_PD_SHIFT (1U)
- #define VHA_CR_OS0_MMU_CTRL_INVAL_PD_CLRMSK (0XFFFFFFFDU)
- #define VHA_CR_OS0_MMU_CTRL_INVAL_PD_EN (0X00000002U)
- #define VHA_CR_OS0_MMU_CTRL_INVAL_PT_SHIFT (0U)
- #define VHA_CR_OS0_MMU_CTRL_INVAL_PT_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_OS0_MMU_CTRL_INVAL_PT_EN (0X00000001U)
- /*
- Register VHA_CR_OS0_MMU_CTRL_INVAL_STATUS
- */
- #define VHA_CR_OS0_MMU_CTRL_INVAL_STATUS (0x76B0U)
- #define VHA_CR_OS0_MMU_CTRL_INVAL_STATUS_MASKFULL (IMG_UINT64_C(0x0000000080000001))
- #define VHA_CR_OS0_MMU_CTRL_INVAL_STATUS_PARITY_SHIFT (31U)
- #define VHA_CR_OS0_MMU_CTRL_INVAL_STATUS_PARITY_CLRMSK (0X7FFFFFFFU)
- #define VHA_CR_OS0_MMU_CTRL_INVAL_STATUS_PARITY_EN (0X80000000U)
- #define VHA_CR_OS0_MMU_CTRL_INVAL_STATUS_PENDING_SHIFT (0U)
- #define VHA_CR_OS0_MMU_CTRL_INVAL_STATUS_PENDING_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_OS0_MMU_CTRL_INVAL_STATUS_PENDING_EN (0X00000001U)
- /*
- Register VHA_CR_OS0_MMU_CBASE_MAPPING_CONTEXT
- */
- #define VHA_CR_OS0_MMU_CBASE_MAPPING_CONTEXT (0x76B8U)
- #define VHA_CR_OS0_MMU_CBASE_MAPPING_CONTEXT_MASKFULL (IMG_UINT64_C(0x00000000000000FF))
- #define VHA_CR_OS0_MMU_CBASE_MAPPING_CONTEXT_ID_SHIFT (0U)
- #define VHA_CR_OS0_MMU_CBASE_MAPPING_CONTEXT_ID_CLRMSK (0XFFFFFF00U)
- /*
- Register VHA_CR_OS0_MMU_CBASE_MAPPING
- */
- #define VHA_CR_OS0_MMU_CBASE_MAPPING (0x76C0U)
- #define VHA_CR_OS0_MMU_CBASE_MAPPING_MASKFULL (IMG_UINT64_C(0x000000001FFFFFFF))
- #define VHA_CR_OS0_MMU_CBASE_MAPPING_INVALID_SHIFT (28U)
- #define VHA_CR_OS0_MMU_CBASE_MAPPING_INVALID_CLRMSK (0XEFFFFFFFU)
- #define VHA_CR_OS0_MMU_CBASE_MAPPING_INVALID_EN (0X10000000U)
- #define VHA_CR_OS0_MMU_CBASE_MAPPING_BASE_ADDR_SHIFT (0U)
- #define VHA_CR_OS0_MMU_CBASE_MAPPING_BASE_ADDR_CLRMSK (0XF0000000U)
- #define VHA_CR_OS0_MMU_CBASE_MAPPING_BASE_ADDR_ALIGNSHIFT (12U)
- #define VHA_CR_OS0_MMU_CBASE_MAPPING_BASE_ADDR_ALIGNSIZE (4096U)
- /*
- Register VHA_CR_OS0_MMU_CTRL_LEGACY
- */
- #define VHA_CR_OS0_MMU_CTRL_LEGACY (0x76E8U)
- #define VHA_CR_OS0_MMU_CTRL_LEGACY_MASKFULL (IMG_UINT64_C(0x0000000000000001))
- #define VHA_CR_OS0_MMU_CTRL_LEGACY_RESERVED_SHIFT (0U)
- #define VHA_CR_OS0_MMU_CTRL_LEGACY_RESERVED_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_OS0_MMU_CTRL_LEGACY_RESERVED_EN (0X00000001U)
- #define VHA_CR_ACE_PROT_CTRL_ENUM_PROT_MASK (0x00000007U)
- /*
- Unprivileged secure data access*/
- #define VHA_CR_ACE_PROT_CTRL_ENUM_PROT_UNPRIVILEGED_SECURE_DATA (0x00000000U)
- /*
- Privileged secure data access*/
- #define VHA_CR_ACE_PROT_CTRL_ENUM_PROT_PRIVILEGED_SECURE_DATA (0x00000001U)
- /*
- Unprivileged non-secure data access*/
- #define VHA_CR_ACE_PROT_CTRL_ENUM_PROT_UNPRIVILEGED_NONSECURE_DATA (0x00000002U)
- /*
- Privileged non-secure data access*/
- #define VHA_CR_ACE_PROT_CTRL_ENUM_PROT_PRIVILEGED_NONSECURE_DATA (0x00000003U)
- /*
- Unprivileged secure instruction access*/
- #define VHA_CR_ACE_PROT_CTRL_ENUM_PROT_UNPRIVILEGED_SECURE_INSTRUCTION (0x00000004U)
- /*
- Privileged secure instruction access*/
- #define VHA_CR_ACE_PROT_CTRL_ENUM_PROT_PRIVILEGED_SECURE_INSTRUCTION (0x00000005U)
- /*
- Unprivileged non-secure instruction access*/
- #define VHA_CR_ACE_PROT_CTRL_ENUM_PROT_UNPRIVILEGED_NONSECURE_INSTRUCTION (0x00000006U)
- /*
- Privileged non-secure instruction access*/
- #define VHA_CR_ACE_PROT_CTRL_ENUM_PROT_PRIVILEGED_NONSECURE_INSTRUCTION (0x00000007U)
- /*
- Register VHA_CR_ACE_PROT_CTRL
- */
- #define VHA_CR_ACE_PROT_CTRL (0x76F8U)
- #define VHA_CR_ACE_PROT_CTRL_MASKFULL (IMG_UINT64_C(0x0707070707070707))
- #define VHA_CR_ACE_PROT_CTRL_OSID7_SHIFT (56U)
- #define VHA_CR_ACE_PROT_CTRL_OSID7_CLRMSK (IMG_UINT64_C(0XF8FFFFFFFFFFFFFF))
- #define VHA_CR_ACE_PROT_CTRL_OSID7_UNPRIVILEGED_SECURE_DATA (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_ACE_PROT_CTRL_OSID7_PRIVILEGED_SECURE_DATA (IMG_UINT64_C(0x0100000000000000))
- #define VHA_CR_ACE_PROT_CTRL_OSID7_UNPRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0200000000000000))
- #define VHA_CR_ACE_PROT_CTRL_OSID7_PRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0300000000000000))
- #define VHA_CR_ACE_PROT_CTRL_OSID7_UNPRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0400000000000000))
- #define VHA_CR_ACE_PROT_CTRL_OSID7_PRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0500000000000000))
- #define VHA_CR_ACE_PROT_CTRL_OSID7_UNPRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0600000000000000))
- #define VHA_CR_ACE_PROT_CTRL_OSID7_PRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0700000000000000))
- #define VHA_CR_ACE_PROT_CTRL_OSID6_SHIFT (48U)
- #define VHA_CR_ACE_PROT_CTRL_OSID6_CLRMSK (IMG_UINT64_C(0XFFF8FFFFFFFFFFFF))
- #define VHA_CR_ACE_PROT_CTRL_OSID6_UNPRIVILEGED_SECURE_DATA (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_ACE_PROT_CTRL_OSID6_PRIVILEGED_SECURE_DATA (IMG_UINT64_C(0x0001000000000000))
- #define VHA_CR_ACE_PROT_CTRL_OSID6_UNPRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0002000000000000))
- #define VHA_CR_ACE_PROT_CTRL_OSID6_PRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0003000000000000))
- #define VHA_CR_ACE_PROT_CTRL_OSID6_UNPRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0004000000000000))
- #define VHA_CR_ACE_PROT_CTRL_OSID6_PRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0005000000000000))
- #define VHA_CR_ACE_PROT_CTRL_OSID6_UNPRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0006000000000000))
- #define VHA_CR_ACE_PROT_CTRL_OSID6_PRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0007000000000000))
- #define VHA_CR_ACE_PROT_CTRL_OSID5_SHIFT (40U)
- #define VHA_CR_ACE_PROT_CTRL_OSID5_CLRMSK (IMG_UINT64_C(0XFFFFF8FFFFFFFFFF))
- #define VHA_CR_ACE_PROT_CTRL_OSID5_UNPRIVILEGED_SECURE_DATA (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_ACE_PROT_CTRL_OSID5_PRIVILEGED_SECURE_DATA (IMG_UINT64_C(0x0000010000000000))
- #define VHA_CR_ACE_PROT_CTRL_OSID5_UNPRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0000020000000000))
- #define VHA_CR_ACE_PROT_CTRL_OSID5_PRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0000030000000000))
- #define VHA_CR_ACE_PROT_CTRL_OSID5_UNPRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0000040000000000))
- #define VHA_CR_ACE_PROT_CTRL_OSID5_PRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0000050000000000))
- #define VHA_CR_ACE_PROT_CTRL_OSID5_UNPRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0000060000000000))
- #define VHA_CR_ACE_PROT_CTRL_OSID5_PRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0000070000000000))
- #define VHA_CR_ACE_PROT_CTRL_OSID4_SHIFT (32U)
- #define VHA_CR_ACE_PROT_CTRL_OSID4_CLRMSK (IMG_UINT64_C(0XFFFFFFF8FFFFFFFF))
- #define VHA_CR_ACE_PROT_CTRL_OSID4_UNPRIVILEGED_SECURE_DATA (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_ACE_PROT_CTRL_OSID4_PRIVILEGED_SECURE_DATA (IMG_UINT64_C(0x0000000100000000))
- #define VHA_CR_ACE_PROT_CTRL_OSID4_UNPRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0000000200000000))
- #define VHA_CR_ACE_PROT_CTRL_OSID4_PRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0000000300000000))
- #define VHA_CR_ACE_PROT_CTRL_OSID4_UNPRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0000000400000000))
- #define VHA_CR_ACE_PROT_CTRL_OSID4_PRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0000000500000000))
- #define VHA_CR_ACE_PROT_CTRL_OSID4_UNPRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0000000600000000))
- #define VHA_CR_ACE_PROT_CTRL_OSID4_PRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0000000700000000))
- #define VHA_CR_ACE_PROT_CTRL_OSID3_SHIFT (24U)
- #define VHA_CR_ACE_PROT_CTRL_OSID3_CLRMSK (IMG_UINT64_C(0XFFFFFFFFF8FFFFFF))
- #define VHA_CR_ACE_PROT_CTRL_OSID3_UNPRIVILEGED_SECURE_DATA (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_ACE_PROT_CTRL_OSID3_PRIVILEGED_SECURE_DATA (IMG_UINT64_C(0x0000000001000000))
- #define VHA_CR_ACE_PROT_CTRL_OSID3_UNPRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0000000002000000))
- #define VHA_CR_ACE_PROT_CTRL_OSID3_PRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0000000003000000))
- #define VHA_CR_ACE_PROT_CTRL_OSID3_UNPRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0000000004000000))
- #define VHA_CR_ACE_PROT_CTRL_OSID3_PRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0000000005000000))
- #define VHA_CR_ACE_PROT_CTRL_OSID3_UNPRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0000000006000000))
- #define VHA_CR_ACE_PROT_CTRL_OSID3_PRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0000000007000000))
- #define VHA_CR_ACE_PROT_CTRL_OSID2_SHIFT (16U)
- #define VHA_CR_ACE_PROT_CTRL_OSID2_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF8FFFF))
- #define VHA_CR_ACE_PROT_CTRL_OSID2_UNPRIVILEGED_SECURE_DATA (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_ACE_PROT_CTRL_OSID2_PRIVILEGED_SECURE_DATA (IMG_UINT64_C(0x0000000000010000))
- #define VHA_CR_ACE_PROT_CTRL_OSID2_UNPRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0000000000020000))
- #define VHA_CR_ACE_PROT_CTRL_OSID2_PRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0000000000030000))
- #define VHA_CR_ACE_PROT_CTRL_OSID2_UNPRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0000000000040000))
- #define VHA_CR_ACE_PROT_CTRL_OSID2_PRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0000000000050000))
- #define VHA_CR_ACE_PROT_CTRL_OSID2_UNPRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0000000000060000))
- #define VHA_CR_ACE_PROT_CTRL_OSID2_PRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0000000000070000))
- #define VHA_CR_ACE_PROT_CTRL_OSID1_SHIFT (8U)
- #define VHA_CR_ACE_PROT_CTRL_OSID1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF8FF))
- #define VHA_CR_ACE_PROT_CTRL_OSID1_UNPRIVILEGED_SECURE_DATA (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_ACE_PROT_CTRL_OSID1_PRIVILEGED_SECURE_DATA (IMG_UINT64_C(0x0000000000000100))
- #define VHA_CR_ACE_PROT_CTRL_OSID1_UNPRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0000000000000200))
- #define VHA_CR_ACE_PROT_CTRL_OSID1_PRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0000000000000300))
- #define VHA_CR_ACE_PROT_CTRL_OSID1_UNPRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0000000000000400))
- #define VHA_CR_ACE_PROT_CTRL_OSID1_PRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0000000000000500))
- #define VHA_CR_ACE_PROT_CTRL_OSID1_UNPRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0000000000000600))
- #define VHA_CR_ACE_PROT_CTRL_OSID1_PRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0000000000000700))
- #define VHA_CR_ACE_PROT_CTRL_OSID0_SHIFT (0U)
- #define VHA_CR_ACE_PROT_CTRL_OSID0_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF8))
- #define VHA_CR_ACE_PROT_CTRL_OSID0_UNPRIVILEGED_SECURE_DATA (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_ACE_PROT_CTRL_OSID0_PRIVILEGED_SECURE_DATA (IMG_UINT64_C(0x0000000000000001))
- #define VHA_CR_ACE_PROT_CTRL_OSID0_UNPRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0000000000000002))
- #define VHA_CR_ACE_PROT_CTRL_OSID0_PRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0000000000000003))
- #define VHA_CR_ACE_PROT_CTRL_OSID0_UNPRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0000000000000004))
- #define VHA_CR_ACE_PROT_CTRL_OSID0_PRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0000000000000005))
- #define VHA_CR_ACE_PROT_CTRL_OSID0_UNPRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0000000000000006))
- #define VHA_CR_ACE_PROT_CTRL_OSID0_PRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0000000000000007))
- /*
- Register VHA_CR_OS0_MMU_CTRL
- */
- #define VHA_CR_OS0_MMU_CTRL (0x7708U)
- #define VHA_CR_OS0_MMU_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000000001))
- #define VHA_CR_OS0_MMU_CTRL_BYPASS_SHIFT (0U)
- #define VHA_CR_OS0_MMU_CTRL_BYPASS_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_OS0_MMU_CTRL_BYPASS_EN (0X00000001U)
- /*
- Register VHA_CR_OS1_MMU_CTRL
- */
- #define VHA_CR_OS1_MMU_CTRL (0x7710U)
- #define VHA_CR_OS1_MMU_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000000001))
- #define VHA_CR_OS1_MMU_CTRL_BYPASS_SHIFT (0U)
- #define VHA_CR_OS1_MMU_CTRL_BYPASS_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_OS1_MMU_CTRL_BYPASS_EN (0X00000001U)
- /*
- Register VHA_CR_OS2_MMU_CTRL
- */
- #define VHA_CR_OS2_MMU_CTRL (0x7718U)
- #define VHA_CR_OS2_MMU_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000000001))
- #define VHA_CR_OS2_MMU_CTRL_BYPASS_SHIFT (0U)
- #define VHA_CR_OS2_MMU_CTRL_BYPASS_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_OS2_MMU_CTRL_BYPASS_EN (0X00000001U)
- /*
- Register VHA_CR_CORE0_MMU_FAULT_STATUS1
- */
- #define VHA_CR_CORE0_MMU_FAULT_STATUS1 (0x7B00U)
- #define VHA_CR_CORE0_MMU_FAULT_STATUS1_MASKFULL (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
- #define VHA_CR_CORE0_MMU_FAULT_STATUS1_LEVEL_SHIFT (62U)
- #define VHA_CR_CORE0_MMU_FAULT_STATUS1_LEVEL_CLRMSK (IMG_UINT64_C(0X3FFFFFFFFFFFFFFF))
- #define VHA_CR_CORE0_MMU_FAULT_STATUS1_REQ_ID_SHIFT (56U)
- #define VHA_CR_CORE0_MMU_FAULT_STATUS1_REQ_ID_CLRMSK (IMG_UINT64_C(0XC0FFFFFFFFFFFFFF))
- #define VHA_CR_CORE0_MMU_FAULT_STATUS1_CONTEXT_SHIFT (48U)
- #define VHA_CR_CORE0_MMU_FAULT_STATUS1_CONTEXT_CLRMSK (IMG_UINT64_C(0XFF00FFFFFFFFFFFF))
- #define VHA_CR_CORE0_MMU_FAULT_STATUS1_ADDRESS_SHIFT (4U)
- #define VHA_CR_CORE0_MMU_FAULT_STATUS1_ADDRESS_CLRMSK (IMG_UINT64_C(0XFFFF00000000000F))
- #define VHA_CR_CORE0_MMU_FAULT_STATUS1_RNW_SHIFT (3U)
- #define VHA_CR_CORE0_MMU_FAULT_STATUS1_RNW_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF7))
- #define VHA_CR_CORE0_MMU_FAULT_STATUS1_RNW_EN (IMG_UINT64_C(0X0000000000000008))
- #define VHA_CR_CORE0_MMU_FAULT_STATUS1_TYPE_SHIFT (1U)
- #define VHA_CR_CORE0_MMU_FAULT_STATUS1_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF9))
- #define VHA_CR_CORE0_MMU_FAULT_STATUS1_FAULT_SHIFT (0U)
- #define VHA_CR_CORE0_MMU_FAULT_STATUS1_FAULT_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
- #define VHA_CR_CORE0_MMU_FAULT_STATUS1_FAULT_EN (IMG_UINT64_C(0X0000000000000001))
- /*
- Register VHA_CR_CORE0_MMU_FAULT_STATUS2
- */
- #define VHA_CR_CORE0_MMU_FAULT_STATUS2 (0x7B08U)
- #define VHA_CR_CORE0_MMU_FAULT_STATUS2_MASKFULL (IMG_UINT64_C(0x000000003FFF07FF))
- #define VHA_CR_CORE0_MMU_FAULT_STATUS2_WRITEBACK_SHIFT (29U)
- #define VHA_CR_CORE0_MMU_FAULT_STATUS2_WRITEBACK_CLRMSK (0XDFFFFFFFU)
- #define VHA_CR_CORE0_MMU_FAULT_STATUS2_WRITEBACK_EN (0X20000000U)
- #define VHA_CR_CORE0_MMU_FAULT_STATUS2_CLEANUNIQUE_SHIFT (28U)
- #define VHA_CR_CORE0_MMU_FAULT_STATUS2_CLEANUNIQUE_CLRMSK (0XEFFFFFFFU)
- #define VHA_CR_CORE0_MMU_FAULT_STATUS2_CLEANUNIQUE_EN (0X10000000U)
- #define VHA_CR_CORE0_MMU_FAULT_STATUS2_BANK_SHIFT (24U)
- #define VHA_CR_CORE0_MMU_FAULT_STATUS2_BANK_CLRMSK (0XF0FFFFFFU)
- #define VHA_CR_CORE0_MMU_FAULT_STATUS2_TLB_ENTRY_SHIFT (16U)
- #define VHA_CR_CORE0_MMU_FAULT_STATUS2_TLB_ENTRY_CLRMSK (0XFF00FFFFU)
- #define VHA_CR_CORE0_MMU_FAULT_STATUS2_FBM_FAULT_SHIFT (10U)
- #define VHA_CR_CORE0_MMU_FAULT_STATUS2_FBM_FAULT_CLRMSK (0XFFFFFBFFU)
- #define VHA_CR_CORE0_MMU_FAULT_STATUS2_FBM_FAULT_EN (0X00000400U)
- #define VHA_CR_CORE0_MMU_FAULT_STATUS2_BIF_ID_SHIFT (0U)
- #define VHA_CR_CORE0_MMU_FAULT_STATUS2_BIF_ID_CLRMSK (0XFFFFFC00U)
- /*
- Register VHA_CR_CORE1_MMU_FAULT_STATUS1
- */
- #define VHA_CR_CORE1_MMU_FAULT_STATUS1 (0x7B10U)
- #define VHA_CR_CORE1_MMU_FAULT_STATUS1_MASKFULL (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
- #define VHA_CR_CORE1_MMU_FAULT_STATUS1_LEVEL_SHIFT (62U)
- #define VHA_CR_CORE1_MMU_FAULT_STATUS1_LEVEL_CLRMSK (IMG_UINT64_C(0X3FFFFFFFFFFFFFFF))
- #define VHA_CR_CORE1_MMU_FAULT_STATUS1_REQ_ID_SHIFT (56U)
- #define VHA_CR_CORE1_MMU_FAULT_STATUS1_REQ_ID_CLRMSK (IMG_UINT64_C(0XC0FFFFFFFFFFFFFF))
- #define VHA_CR_CORE1_MMU_FAULT_STATUS1_CONTEXT_SHIFT (48U)
- #define VHA_CR_CORE1_MMU_FAULT_STATUS1_CONTEXT_CLRMSK (IMG_UINT64_C(0XFF00FFFFFFFFFFFF))
- #define VHA_CR_CORE1_MMU_FAULT_STATUS1_ADDRESS_SHIFT (4U)
- #define VHA_CR_CORE1_MMU_FAULT_STATUS1_ADDRESS_CLRMSK (IMG_UINT64_C(0XFFFF00000000000F))
- #define VHA_CR_CORE1_MMU_FAULT_STATUS1_RNW_SHIFT (3U)
- #define VHA_CR_CORE1_MMU_FAULT_STATUS1_RNW_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF7))
- #define VHA_CR_CORE1_MMU_FAULT_STATUS1_RNW_EN (IMG_UINT64_C(0X0000000000000008))
- #define VHA_CR_CORE1_MMU_FAULT_STATUS1_TYPE_SHIFT (1U)
- #define VHA_CR_CORE1_MMU_FAULT_STATUS1_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF9))
- #define VHA_CR_CORE1_MMU_FAULT_STATUS1_FAULT_SHIFT (0U)
- #define VHA_CR_CORE1_MMU_FAULT_STATUS1_FAULT_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
- #define VHA_CR_CORE1_MMU_FAULT_STATUS1_FAULT_EN (IMG_UINT64_C(0X0000000000000001))
- /*
- Register VHA_CR_CORE1_MMU_FAULT_STATUS2
- */
- #define VHA_CR_CORE1_MMU_FAULT_STATUS2 (0x7B18U)
- #define VHA_CR_CORE1_MMU_FAULT_STATUS2_MASKFULL (IMG_UINT64_C(0x000000003FFF07FF))
- #define VHA_CR_CORE1_MMU_FAULT_STATUS2_WRITEBACK_SHIFT (29U)
- #define VHA_CR_CORE1_MMU_FAULT_STATUS2_WRITEBACK_CLRMSK (0XDFFFFFFFU)
- #define VHA_CR_CORE1_MMU_FAULT_STATUS2_WRITEBACK_EN (0X20000000U)
- #define VHA_CR_CORE1_MMU_FAULT_STATUS2_CLEANUNIQUE_SHIFT (28U)
- #define VHA_CR_CORE1_MMU_FAULT_STATUS2_CLEANUNIQUE_CLRMSK (0XEFFFFFFFU)
- #define VHA_CR_CORE1_MMU_FAULT_STATUS2_CLEANUNIQUE_EN (0X10000000U)
- #define VHA_CR_CORE1_MMU_FAULT_STATUS2_BANK_SHIFT (24U)
- #define VHA_CR_CORE1_MMU_FAULT_STATUS2_BANK_CLRMSK (0XF0FFFFFFU)
- #define VHA_CR_CORE1_MMU_FAULT_STATUS2_TLB_ENTRY_SHIFT (16U)
- #define VHA_CR_CORE1_MMU_FAULT_STATUS2_TLB_ENTRY_CLRMSK (0XFF00FFFFU)
- #define VHA_CR_CORE1_MMU_FAULT_STATUS2_FBM_FAULT_SHIFT (10U)
- #define VHA_CR_CORE1_MMU_FAULT_STATUS2_FBM_FAULT_CLRMSK (0XFFFFFBFFU)
- #define VHA_CR_CORE1_MMU_FAULT_STATUS2_FBM_FAULT_EN (0X00000400U)
- #define VHA_CR_CORE1_MMU_FAULT_STATUS2_BIF_ID_SHIFT (0U)
- #define VHA_CR_CORE1_MMU_FAULT_STATUS2_BIF_ID_CLRMSK (0XFFFFFC00U)
- /*
- Register VHA_CR_CORE2_MMU_FAULT_STATUS1
- */
- #define VHA_CR_CORE2_MMU_FAULT_STATUS1 (0x7B20U)
- #define VHA_CR_CORE2_MMU_FAULT_STATUS1_MASKFULL (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
- #define VHA_CR_CORE2_MMU_FAULT_STATUS1_LEVEL_SHIFT (62U)
- #define VHA_CR_CORE2_MMU_FAULT_STATUS1_LEVEL_CLRMSK (IMG_UINT64_C(0X3FFFFFFFFFFFFFFF))
- #define VHA_CR_CORE2_MMU_FAULT_STATUS1_REQ_ID_SHIFT (56U)
- #define VHA_CR_CORE2_MMU_FAULT_STATUS1_REQ_ID_CLRMSK (IMG_UINT64_C(0XC0FFFFFFFFFFFFFF))
- #define VHA_CR_CORE2_MMU_FAULT_STATUS1_CONTEXT_SHIFT (48U)
- #define VHA_CR_CORE2_MMU_FAULT_STATUS1_CONTEXT_CLRMSK (IMG_UINT64_C(0XFF00FFFFFFFFFFFF))
- #define VHA_CR_CORE2_MMU_FAULT_STATUS1_ADDRESS_SHIFT (4U)
- #define VHA_CR_CORE2_MMU_FAULT_STATUS1_ADDRESS_CLRMSK (IMG_UINT64_C(0XFFFF00000000000F))
- #define VHA_CR_CORE2_MMU_FAULT_STATUS1_RNW_SHIFT (3U)
- #define VHA_CR_CORE2_MMU_FAULT_STATUS1_RNW_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF7))
- #define VHA_CR_CORE2_MMU_FAULT_STATUS1_RNW_EN (IMG_UINT64_C(0X0000000000000008))
- #define VHA_CR_CORE2_MMU_FAULT_STATUS1_TYPE_SHIFT (1U)
- #define VHA_CR_CORE2_MMU_FAULT_STATUS1_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF9))
- #define VHA_CR_CORE2_MMU_FAULT_STATUS1_FAULT_SHIFT (0U)
- #define VHA_CR_CORE2_MMU_FAULT_STATUS1_FAULT_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
- #define VHA_CR_CORE2_MMU_FAULT_STATUS1_FAULT_EN (IMG_UINT64_C(0X0000000000000001))
- /*
- Register VHA_CR_CORE2_MMU_FAULT_STATUS2
- */
- #define VHA_CR_CORE2_MMU_FAULT_STATUS2 (0x7B28U)
- #define VHA_CR_CORE2_MMU_FAULT_STATUS2_MASKFULL (IMG_UINT64_C(0x000000003FFF07FF))
- #define VHA_CR_CORE2_MMU_FAULT_STATUS2_WRITEBACK_SHIFT (29U)
- #define VHA_CR_CORE2_MMU_FAULT_STATUS2_WRITEBACK_CLRMSK (0XDFFFFFFFU)
- #define VHA_CR_CORE2_MMU_FAULT_STATUS2_WRITEBACK_EN (0X20000000U)
- #define VHA_CR_CORE2_MMU_FAULT_STATUS2_CLEANUNIQUE_SHIFT (28U)
- #define VHA_CR_CORE2_MMU_FAULT_STATUS2_CLEANUNIQUE_CLRMSK (0XEFFFFFFFU)
- #define VHA_CR_CORE2_MMU_FAULT_STATUS2_CLEANUNIQUE_EN (0X10000000U)
- #define VHA_CR_CORE2_MMU_FAULT_STATUS2_BANK_SHIFT (24U)
- #define VHA_CR_CORE2_MMU_FAULT_STATUS2_BANK_CLRMSK (0XF0FFFFFFU)
- #define VHA_CR_CORE2_MMU_FAULT_STATUS2_TLB_ENTRY_SHIFT (16U)
- #define VHA_CR_CORE2_MMU_FAULT_STATUS2_TLB_ENTRY_CLRMSK (0XFF00FFFFU)
- #define VHA_CR_CORE2_MMU_FAULT_STATUS2_FBM_FAULT_SHIFT (10U)
- #define VHA_CR_CORE2_MMU_FAULT_STATUS2_FBM_FAULT_CLRMSK (0XFFFFFBFFU)
- #define VHA_CR_CORE2_MMU_FAULT_STATUS2_FBM_FAULT_EN (0X00000400U)
- #define VHA_CR_CORE2_MMU_FAULT_STATUS2_BIF_ID_SHIFT (0U)
- #define VHA_CR_CORE2_MMU_FAULT_STATUS2_BIF_ID_CLRMSK (0XFFFFFC00U)
- /*
- Register VHA_CR_CORE3_MMU_FAULT_STATUS1
- */
- #define VHA_CR_CORE3_MMU_FAULT_STATUS1 (0x7B30U)
- #define VHA_CR_CORE3_MMU_FAULT_STATUS1_MASKFULL (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
- #define VHA_CR_CORE3_MMU_FAULT_STATUS1_LEVEL_SHIFT (62U)
- #define VHA_CR_CORE3_MMU_FAULT_STATUS1_LEVEL_CLRMSK (IMG_UINT64_C(0X3FFFFFFFFFFFFFFF))
- #define VHA_CR_CORE3_MMU_FAULT_STATUS1_REQ_ID_SHIFT (56U)
- #define VHA_CR_CORE3_MMU_FAULT_STATUS1_REQ_ID_CLRMSK (IMG_UINT64_C(0XC0FFFFFFFFFFFFFF))
- #define VHA_CR_CORE3_MMU_FAULT_STATUS1_CONTEXT_SHIFT (48U)
- #define VHA_CR_CORE3_MMU_FAULT_STATUS1_CONTEXT_CLRMSK (IMG_UINT64_C(0XFF00FFFFFFFFFFFF))
- #define VHA_CR_CORE3_MMU_FAULT_STATUS1_ADDRESS_SHIFT (4U)
- #define VHA_CR_CORE3_MMU_FAULT_STATUS1_ADDRESS_CLRMSK (IMG_UINT64_C(0XFFFF00000000000F))
- #define VHA_CR_CORE3_MMU_FAULT_STATUS1_RNW_SHIFT (3U)
- #define VHA_CR_CORE3_MMU_FAULT_STATUS1_RNW_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF7))
- #define VHA_CR_CORE3_MMU_FAULT_STATUS1_RNW_EN (IMG_UINT64_C(0X0000000000000008))
- #define VHA_CR_CORE3_MMU_FAULT_STATUS1_TYPE_SHIFT (1U)
- #define VHA_CR_CORE3_MMU_FAULT_STATUS1_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF9))
- #define VHA_CR_CORE3_MMU_FAULT_STATUS1_FAULT_SHIFT (0U)
- #define VHA_CR_CORE3_MMU_FAULT_STATUS1_FAULT_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
- #define VHA_CR_CORE3_MMU_FAULT_STATUS1_FAULT_EN (IMG_UINT64_C(0X0000000000000001))
- /*
- Register VHA_CR_CORE3_MMU_FAULT_STATUS2
- */
- #define VHA_CR_CORE3_MMU_FAULT_STATUS2 (0x7B38U)
- #define VHA_CR_CORE3_MMU_FAULT_STATUS2_MASKFULL (IMG_UINT64_C(0x000000003FFF07FF))
- #define VHA_CR_CORE3_MMU_FAULT_STATUS2_WRITEBACK_SHIFT (29U)
- #define VHA_CR_CORE3_MMU_FAULT_STATUS2_WRITEBACK_CLRMSK (0XDFFFFFFFU)
- #define VHA_CR_CORE3_MMU_FAULT_STATUS2_WRITEBACK_EN (0X20000000U)
- #define VHA_CR_CORE3_MMU_FAULT_STATUS2_CLEANUNIQUE_SHIFT (28U)
- #define VHA_CR_CORE3_MMU_FAULT_STATUS2_CLEANUNIQUE_CLRMSK (0XEFFFFFFFU)
- #define VHA_CR_CORE3_MMU_FAULT_STATUS2_CLEANUNIQUE_EN (0X10000000U)
- #define VHA_CR_CORE3_MMU_FAULT_STATUS2_BANK_SHIFT (24U)
- #define VHA_CR_CORE3_MMU_FAULT_STATUS2_BANK_CLRMSK (0XF0FFFFFFU)
- #define VHA_CR_CORE3_MMU_FAULT_STATUS2_TLB_ENTRY_SHIFT (16U)
- #define VHA_CR_CORE3_MMU_FAULT_STATUS2_TLB_ENTRY_CLRMSK (0XFF00FFFFU)
- #define VHA_CR_CORE3_MMU_FAULT_STATUS2_FBM_FAULT_SHIFT (10U)
- #define VHA_CR_CORE3_MMU_FAULT_STATUS2_FBM_FAULT_CLRMSK (0XFFFFFBFFU)
- #define VHA_CR_CORE3_MMU_FAULT_STATUS2_FBM_FAULT_EN (0X00000400U)
- #define VHA_CR_CORE3_MMU_FAULT_STATUS2_BIF_ID_SHIFT (0U)
- #define VHA_CR_CORE3_MMU_FAULT_STATUS2_BIF_ID_CLRMSK (0XFFFFFC00U)
- /*
- Register VHA_CR_CORE4_MMU_FAULT_STATUS1
- */
- #define VHA_CR_CORE4_MMU_FAULT_STATUS1 (0x7B40U)
- #define VHA_CR_CORE4_MMU_FAULT_STATUS1_MASKFULL (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
- #define VHA_CR_CORE4_MMU_FAULT_STATUS1_LEVEL_SHIFT (62U)
- #define VHA_CR_CORE4_MMU_FAULT_STATUS1_LEVEL_CLRMSK (IMG_UINT64_C(0X3FFFFFFFFFFFFFFF))
- #define VHA_CR_CORE4_MMU_FAULT_STATUS1_REQ_ID_SHIFT (56U)
- #define VHA_CR_CORE4_MMU_FAULT_STATUS1_REQ_ID_CLRMSK (IMG_UINT64_C(0XC0FFFFFFFFFFFFFF))
- #define VHA_CR_CORE4_MMU_FAULT_STATUS1_CONTEXT_SHIFT (48U)
- #define VHA_CR_CORE4_MMU_FAULT_STATUS1_CONTEXT_CLRMSK (IMG_UINT64_C(0XFF00FFFFFFFFFFFF))
- #define VHA_CR_CORE4_MMU_FAULT_STATUS1_ADDRESS_SHIFT (4U)
- #define VHA_CR_CORE4_MMU_FAULT_STATUS1_ADDRESS_CLRMSK (IMG_UINT64_C(0XFFFF00000000000F))
- #define VHA_CR_CORE4_MMU_FAULT_STATUS1_RNW_SHIFT (3U)
- #define VHA_CR_CORE4_MMU_FAULT_STATUS1_RNW_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF7))
- #define VHA_CR_CORE4_MMU_FAULT_STATUS1_RNW_EN (IMG_UINT64_C(0X0000000000000008))
- #define VHA_CR_CORE4_MMU_FAULT_STATUS1_TYPE_SHIFT (1U)
- #define VHA_CR_CORE4_MMU_FAULT_STATUS1_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF9))
- #define VHA_CR_CORE4_MMU_FAULT_STATUS1_FAULT_SHIFT (0U)
- #define VHA_CR_CORE4_MMU_FAULT_STATUS1_FAULT_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
- #define VHA_CR_CORE4_MMU_FAULT_STATUS1_FAULT_EN (IMG_UINT64_C(0X0000000000000001))
- /*
- Register VHA_CR_CORE4_MMU_FAULT_STATUS2
- */
- #define VHA_CR_CORE4_MMU_FAULT_STATUS2 (0x7B48U)
- #define VHA_CR_CORE4_MMU_FAULT_STATUS2_MASKFULL (IMG_UINT64_C(0x000000003FFF07FF))
- #define VHA_CR_CORE4_MMU_FAULT_STATUS2_WRITEBACK_SHIFT (29U)
- #define VHA_CR_CORE4_MMU_FAULT_STATUS2_WRITEBACK_CLRMSK (0XDFFFFFFFU)
- #define VHA_CR_CORE4_MMU_FAULT_STATUS2_WRITEBACK_EN (0X20000000U)
- #define VHA_CR_CORE4_MMU_FAULT_STATUS2_CLEANUNIQUE_SHIFT (28U)
- #define VHA_CR_CORE4_MMU_FAULT_STATUS2_CLEANUNIQUE_CLRMSK (0XEFFFFFFFU)
- #define VHA_CR_CORE4_MMU_FAULT_STATUS2_CLEANUNIQUE_EN (0X10000000U)
- #define VHA_CR_CORE4_MMU_FAULT_STATUS2_BANK_SHIFT (24U)
- #define VHA_CR_CORE4_MMU_FAULT_STATUS2_BANK_CLRMSK (0XF0FFFFFFU)
- #define VHA_CR_CORE4_MMU_FAULT_STATUS2_TLB_ENTRY_SHIFT (16U)
- #define VHA_CR_CORE4_MMU_FAULT_STATUS2_TLB_ENTRY_CLRMSK (0XFF00FFFFU)
- #define VHA_CR_CORE4_MMU_FAULT_STATUS2_FBM_FAULT_SHIFT (10U)
- #define VHA_CR_CORE4_MMU_FAULT_STATUS2_FBM_FAULT_CLRMSK (0XFFFFFBFFU)
- #define VHA_CR_CORE4_MMU_FAULT_STATUS2_FBM_FAULT_EN (0X00000400U)
- #define VHA_CR_CORE4_MMU_FAULT_STATUS2_BIF_ID_SHIFT (0U)
- #define VHA_CR_CORE4_MMU_FAULT_STATUS2_BIF_ID_CLRMSK (0XFFFFFC00U)
- /*
- Register VHA_CR_CORE5_MMU_FAULT_STATUS1
- */
- #define VHA_CR_CORE5_MMU_FAULT_STATUS1 (0x7B50U)
- #define VHA_CR_CORE5_MMU_FAULT_STATUS1_MASKFULL (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
- #define VHA_CR_CORE5_MMU_FAULT_STATUS1_LEVEL_SHIFT (62U)
- #define VHA_CR_CORE5_MMU_FAULT_STATUS1_LEVEL_CLRMSK (IMG_UINT64_C(0X3FFFFFFFFFFFFFFF))
- #define VHA_CR_CORE5_MMU_FAULT_STATUS1_REQ_ID_SHIFT (56U)
- #define VHA_CR_CORE5_MMU_FAULT_STATUS1_REQ_ID_CLRMSK (IMG_UINT64_C(0XC0FFFFFFFFFFFFFF))
- #define VHA_CR_CORE5_MMU_FAULT_STATUS1_CONTEXT_SHIFT (48U)
- #define VHA_CR_CORE5_MMU_FAULT_STATUS1_CONTEXT_CLRMSK (IMG_UINT64_C(0XFF00FFFFFFFFFFFF))
- #define VHA_CR_CORE5_MMU_FAULT_STATUS1_ADDRESS_SHIFT (4U)
- #define VHA_CR_CORE5_MMU_FAULT_STATUS1_ADDRESS_CLRMSK (IMG_UINT64_C(0XFFFF00000000000F))
- #define VHA_CR_CORE5_MMU_FAULT_STATUS1_RNW_SHIFT (3U)
- #define VHA_CR_CORE5_MMU_FAULT_STATUS1_RNW_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF7))
- #define VHA_CR_CORE5_MMU_FAULT_STATUS1_RNW_EN (IMG_UINT64_C(0X0000000000000008))
- #define VHA_CR_CORE5_MMU_FAULT_STATUS1_TYPE_SHIFT (1U)
- #define VHA_CR_CORE5_MMU_FAULT_STATUS1_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF9))
- #define VHA_CR_CORE5_MMU_FAULT_STATUS1_FAULT_SHIFT (0U)
- #define VHA_CR_CORE5_MMU_FAULT_STATUS1_FAULT_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
- #define VHA_CR_CORE5_MMU_FAULT_STATUS1_FAULT_EN (IMG_UINT64_C(0X0000000000000001))
- /*
- Register VHA_CR_CORE5_MMU_FAULT_STATUS2
- */
- #define VHA_CR_CORE5_MMU_FAULT_STATUS2 (0x7B58U)
- #define VHA_CR_CORE5_MMU_FAULT_STATUS2_MASKFULL (IMG_UINT64_C(0x000000003FFF07FF))
- #define VHA_CR_CORE5_MMU_FAULT_STATUS2_WRITEBACK_SHIFT (29U)
- #define VHA_CR_CORE5_MMU_FAULT_STATUS2_WRITEBACK_CLRMSK (0XDFFFFFFFU)
- #define VHA_CR_CORE5_MMU_FAULT_STATUS2_WRITEBACK_EN (0X20000000U)
- #define VHA_CR_CORE5_MMU_FAULT_STATUS2_CLEANUNIQUE_SHIFT (28U)
- #define VHA_CR_CORE5_MMU_FAULT_STATUS2_CLEANUNIQUE_CLRMSK (0XEFFFFFFFU)
- #define VHA_CR_CORE5_MMU_FAULT_STATUS2_CLEANUNIQUE_EN (0X10000000U)
- #define VHA_CR_CORE5_MMU_FAULT_STATUS2_BANK_SHIFT (24U)
- #define VHA_CR_CORE5_MMU_FAULT_STATUS2_BANK_CLRMSK (0XF0FFFFFFU)
- #define VHA_CR_CORE5_MMU_FAULT_STATUS2_TLB_ENTRY_SHIFT (16U)
- #define VHA_CR_CORE5_MMU_FAULT_STATUS2_TLB_ENTRY_CLRMSK (0XFF00FFFFU)
- #define VHA_CR_CORE5_MMU_FAULT_STATUS2_FBM_FAULT_SHIFT (10U)
- #define VHA_CR_CORE5_MMU_FAULT_STATUS2_FBM_FAULT_CLRMSK (0XFFFFFBFFU)
- #define VHA_CR_CORE5_MMU_FAULT_STATUS2_FBM_FAULT_EN (0X00000400U)
- #define VHA_CR_CORE5_MMU_FAULT_STATUS2_BIF_ID_SHIFT (0U)
- #define VHA_CR_CORE5_MMU_FAULT_STATUS2_BIF_ID_CLRMSK (0XFFFFFC00U)
- /*
- Register VHA_CR_CORE6_MMU_FAULT_STATUS1
- */
- #define VHA_CR_CORE6_MMU_FAULT_STATUS1 (0x7B60U)
- #define VHA_CR_CORE6_MMU_FAULT_STATUS1_MASKFULL (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
- #define VHA_CR_CORE6_MMU_FAULT_STATUS1_LEVEL_SHIFT (62U)
- #define VHA_CR_CORE6_MMU_FAULT_STATUS1_LEVEL_CLRMSK (IMG_UINT64_C(0X3FFFFFFFFFFFFFFF))
- #define VHA_CR_CORE6_MMU_FAULT_STATUS1_REQ_ID_SHIFT (56U)
- #define VHA_CR_CORE6_MMU_FAULT_STATUS1_REQ_ID_CLRMSK (IMG_UINT64_C(0XC0FFFFFFFFFFFFFF))
- #define VHA_CR_CORE6_MMU_FAULT_STATUS1_CONTEXT_SHIFT (48U)
- #define VHA_CR_CORE6_MMU_FAULT_STATUS1_CONTEXT_CLRMSK (IMG_UINT64_C(0XFF00FFFFFFFFFFFF))
- #define VHA_CR_CORE6_MMU_FAULT_STATUS1_ADDRESS_SHIFT (4U)
- #define VHA_CR_CORE6_MMU_FAULT_STATUS1_ADDRESS_CLRMSK (IMG_UINT64_C(0XFFFF00000000000F))
- #define VHA_CR_CORE6_MMU_FAULT_STATUS1_RNW_SHIFT (3U)
- #define VHA_CR_CORE6_MMU_FAULT_STATUS1_RNW_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF7))
- #define VHA_CR_CORE6_MMU_FAULT_STATUS1_RNW_EN (IMG_UINT64_C(0X0000000000000008))
- #define VHA_CR_CORE6_MMU_FAULT_STATUS1_TYPE_SHIFT (1U)
- #define VHA_CR_CORE6_MMU_FAULT_STATUS1_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF9))
- #define VHA_CR_CORE6_MMU_FAULT_STATUS1_FAULT_SHIFT (0U)
- #define VHA_CR_CORE6_MMU_FAULT_STATUS1_FAULT_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
- #define VHA_CR_CORE6_MMU_FAULT_STATUS1_FAULT_EN (IMG_UINT64_C(0X0000000000000001))
- /*
- Register VHA_CR_CORE6_MMU_FAULT_STATUS2
- */
- #define VHA_CR_CORE6_MMU_FAULT_STATUS2 (0x7B68U)
- #define VHA_CR_CORE6_MMU_FAULT_STATUS2_MASKFULL (IMG_UINT64_C(0x000000003FFF07FF))
- #define VHA_CR_CORE6_MMU_FAULT_STATUS2_WRITEBACK_SHIFT (29U)
- #define VHA_CR_CORE6_MMU_FAULT_STATUS2_WRITEBACK_CLRMSK (0XDFFFFFFFU)
- #define VHA_CR_CORE6_MMU_FAULT_STATUS2_WRITEBACK_EN (0X20000000U)
- #define VHA_CR_CORE6_MMU_FAULT_STATUS2_CLEANUNIQUE_SHIFT (28U)
- #define VHA_CR_CORE6_MMU_FAULT_STATUS2_CLEANUNIQUE_CLRMSK (0XEFFFFFFFU)
- #define VHA_CR_CORE6_MMU_FAULT_STATUS2_CLEANUNIQUE_EN (0X10000000U)
- #define VHA_CR_CORE6_MMU_FAULT_STATUS2_BANK_SHIFT (24U)
- #define VHA_CR_CORE6_MMU_FAULT_STATUS2_BANK_CLRMSK (0XF0FFFFFFU)
- #define VHA_CR_CORE6_MMU_FAULT_STATUS2_TLB_ENTRY_SHIFT (16U)
- #define VHA_CR_CORE6_MMU_FAULT_STATUS2_TLB_ENTRY_CLRMSK (0XFF00FFFFU)
- #define VHA_CR_CORE6_MMU_FAULT_STATUS2_FBM_FAULT_SHIFT (10U)
- #define VHA_CR_CORE6_MMU_FAULT_STATUS2_FBM_FAULT_CLRMSK (0XFFFFFBFFU)
- #define VHA_CR_CORE6_MMU_FAULT_STATUS2_FBM_FAULT_EN (0X00000400U)
- #define VHA_CR_CORE6_MMU_FAULT_STATUS2_BIF_ID_SHIFT (0U)
- #define VHA_CR_CORE6_MMU_FAULT_STATUS2_BIF_ID_CLRMSK (0XFFFFFC00U)
- /*
- Register VHA_CR_CORE7_MMU_FAULT_STATUS1
- */
- #define VHA_CR_CORE7_MMU_FAULT_STATUS1 (0x7B70U)
- #define VHA_CR_CORE7_MMU_FAULT_STATUS1_MASKFULL (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
- #define VHA_CR_CORE7_MMU_FAULT_STATUS1_LEVEL_SHIFT (62U)
- #define VHA_CR_CORE7_MMU_FAULT_STATUS1_LEVEL_CLRMSK (IMG_UINT64_C(0X3FFFFFFFFFFFFFFF))
- #define VHA_CR_CORE7_MMU_FAULT_STATUS1_REQ_ID_SHIFT (56U)
- #define VHA_CR_CORE7_MMU_FAULT_STATUS1_REQ_ID_CLRMSK (IMG_UINT64_C(0XC0FFFFFFFFFFFFFF))
- #define VHA_CR_CORE7_MMU_FAULT_STATUS1_CONTEXT_SHIFT (48U)
- #define VHA_CR_CORE7_MMU_FAULT_STATUS1_CONTEXT_CLRMSK (IMG_UINT64_C(0XFF00FFFFFFFFFFFF))
- #define VHA_CR_CORE7_MMU_FAULT_STATUS1_ADDRESS_SHIFT (4U)
- #define VHA_CR_CORE7_MMU_FAULT_STATUS1_ADDRESS_CLRMSK (IMG_UINT64_C(0XFFFF00000000000F))
- #define VHA_CR_CORE7_MMU_FAULT_STATUS1_RNW_SHIFT (3U)
- #define VHA_CR_CORE7_MMU_FAULT_STATUS1_RNW_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF7))
- #define VHA_CR_CORE7_MMU_FAULT_STATUS1_RNW_EN (IMG_UINT64_C(0X0000000000000008))
- #define VHA_CR_CORE7_MMU_FAULT_STATUS1_TYPE_SHIFT (1U)
- #define VHA_CR_CORE7_MMU_FAULT_STATUS1_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF9))
- #define VHA_CR_CORE7_MMU_FAULT_STATUS1_FAULT_SHIFT (0U)
- #define VHA_CR_CORE7_MMU_FAULT_STATUS1_FAULT_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
- #define VHA_CR_CORE7_MMU_FAULT_STATUS1_FAULT_EN (IMG_UINT64_C(0X0000000000000001))
- /*
- Register VHA_CR_CORE7_MMU_FAULT_STATUS2
- */
- #define VHA_CR_CORE7_MMU_FAULT_STATUS2 (0x7B78U)
- #define VHA_CR_CORE7_MMU_FAULT_STATUS2_MASKFULL (IMG_UINT64_C(0x000000003FFF07FF))
- #define VHA_CR_CORE7_MMU_FAULT_STATUS2_WRITEBACK_SHIFT (29U)
- #define VHA_CR_CORE7_MMU_FAULT_STATUS2_WRITEBACK_CLRMSK (0XDFFFFFFFU)
- #define VHA_CR_CORE7_MMU_FAULT_STATUS2_WRITEBACK_EN (0X20000000U)
- #define VHA_CR_CORE7_MMU_FAULT_STATUS2_CLEANUNIQUE_SHIFT (28U)
- #define VHA_CR_CORE7_MMU_FAULT_STATUS2_CLEANUNIQUE_CLRMSK (0XEFFFFFFFU)
- #define VHA_CR_CORE7_MMU_FAULT_STATUS2_CLEANUNIQUE_EN (0X10000000U)
- #define VHA_CR_CORE7_MMU_FAULT_STATUS2_BANK_SHIFT (24U)
- #define VHA_CR_CORE7_MMU_FAULT_STATUS2_BANK_CLRMSK (0XF0FFFFFFU)
- #define VHA_CR_CORE7_MMU_FAULT_STATUS2_TLB_ENTRY_SHIFT (16U)
- #define VHA_CR_CORE7_MMU_FAULT_STATUS2_TLB_ENTRY_CLRMSK (0XFF00FFFFU)
- #define VHA_CR_CORE7_MMU_FAULT_STATUS2_FBM_FAULT_SHIFT (10U)
- #define VHA_CR_CORE7_MMU_FAULT_STATUS2_FBM_FAULT_CLRMSK (0XFFFFFBFFU)
- #define VHA_CR_CORE7_MMU_FAULT_STATUS2_FBM_FAULT_EN (0X00000400U)
- #define VHA_CR_CORE7_MMU_FAULT_STATUS2_BIF_ID_SHIFT (0U)
- #define VHA_CR_CORE7_MMU_FAULT_STATUS2_BIF_ID_CLRMSK (0XFFFFFC00U)
- /*
- Register VHA_CR_WM_WL_CONTROL
- */
- #define VHA_CR_WM_WL_CONTROL (0x10000U)
- #define VHA_CR_WM_WL_CONTROL_MASKFULL (IMG_UINT64_C(0x0000000000000001))
- #define VHA_CR_WM_WL_CONTROL_WL_START_SHIFT (0U)
- #define VHA_CR_WM_WL_CONTROL_WL_START_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_WM_WL_CONTROL_WL_START_EN (0X00000001U)
- #define VHA_CR_WM_STATUS_STATE_MASK (0x00000007U)
- /*
- The WM is ready to be programmed */
- #define VHA_CR_WM_STATUS_STATE_IDLE (0x00000000U)
- /*
- The WM is initiating the execution of a Workload*/
- #define VHA_CR_WM_STATUS_STATE_PENDING (0x00000001U)
- /*
- A Workload is being run */
- #define VHA_CR_WM_STATUS_STATE_RUN (0x00000002U)
- /*
- The Workload had an error and execution is halted. A WM reset is required */
- #define VHA_CR_WM_STATUS_STATE_HALTED (0x00000003U)
- /*
- The Workload Manager's Response FIFO is full. Workloads cannot be kicked in the WM unless a RESPONSE_FIFO_READ is issued*/
- #define VHA_CR_WM_STATUS_STATE_RESPONSE_FIFO_FULL (0x00000004U)
- /*
- Register VHA_CR_WM_STATUS
- */
- #define VHA_CR_WM_STATUS (0x10008U)
- #define VHA_CR_WM_STATUS_MASKFULL (IMG_UINT64_C(0x0000000001000007))
- #define VHA_CR_WM_STATUS_PARITY_SHIFT (24U)
- #define VHA_CR_WM_STATUS_PARITY_CLRMSK (0XFEFFFFFFU)
- #define VHA_CR_WM_STATUS_PARITY_EN (0X01000000U)
- #define VHA_CR_WM_STATUS_CURRENT_STATE_SHIFT (0U)
- #define VHA_CR_WM_STATUS_CURRENT_STATE_CLRMSK (0XFFFFFFF8U)
- #define VHA_CR_WM_STATUS_CURRENT_STATE_IDLE (00000000U)
- #define VHA_CR_WM_STATUS_CURRENT_STATE_PENDING (0X00000001U)
- #define VHA_CR_WM_STATUS_CURRENT_STATE_RUN (0X00000002U)
- #define VHA_CR_WM_STATUS_CURRENT_STATE_HALTED (0X00000003U)
- #define VHA_CR_WM_STATUS_CURRENT_STATE_RESPONSE_FIFO_FULL (0X00000004U)
- #define VHA_CR_WM_EVENT_TYPE_WM_WL_WDT_SHIFT (4U)
- #define VHA_CR_WM_EVENT_TYPE_WM_WL_WDT_CLRMSK (0XFFFFFFEFU)
- #define VHA_CR_WM_EVENT_TYPE_WM_WL_WDT_EN (0X00000010U)
- #define VHA_CR_WM_EVENT_TYPE_WM_WL_IDLE_WDT_SHIFT (3U)
- #define VHA_CR_WM_EVENT_TYPE_WM_WL_IDLE_WDT_CLRMSK (0XFFFFFFF7U)
- #define VHA_CR_WM_EVENT_TYPE_WM_WL_IDLE_WDT_EN (0X00000008U)
- #define VHA_CR_WM_EVENT_TYPE_WM_SOCIF_WDT_SHIFT (2U)
- #define VHA_CR_WM_EVENT_TYPE_WM_SOCIF_WDT_CLRMSK (0XFFFFFFFBU)
- #define VHA_CR_WM_EVENT_TYPE_WM_SOCIF_WDT_EN (0X00000004U)
- #define VHA_CR_WM_EVENT_TYPE_LOGIC_FAULT_SHIFT (1U)
- #define VHA_CR_WM_EVENT_TYPE_LOGIC_FAULT_CLRMSK (0XFFFFFFFDU)
- #define VHA_CR_WM_EVENT_TYPE_LOGIC_FAULT_EN (0X00000002U)
- #define VHA_CR_WM_EVENT_TYPE_RESPONSE_FIFO_READY_SHIFT (0U)
- #define VHA_CR_WM_EVENT_TYPE_RESPONSE_FIFO_READY_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_WM_EVENT_TYPE_RESPONSE_FIFO_READY_EN (0X00000001U)
- #define VHA_CR_WM_EVENT_STATUS_TYPE_PARITY_SHIFT (31U)
- #define VHA_CR_WM_EVENT_STATUS_TYPE_PARITY_CLRMSK (0X7FFFFFFFU)
- #define VHA_CR_WM_EVENT_STATUS_TYPE_PARITY_EN (0X80000000U)
- #define VHA_CR_WM_EVENT_STATUS_TYPE_WM_WL_WDT_SHIFT (4U)
- #define VHA_CR_WM_EVENT_STATUS_TYPE_WM_WL_WDT_CLRMSK (0XFFFFFFEFU)
- #define VHA_CR_WM_EVENT_STATUS_TYPE_WM_WL_WDT_EN (0X00000010U)
- #define VHA_CR_WM_EVENT_STATUS_TYPE_WM_WL_IDLE_WDT_SHIFT (3U)
- #define VHA_CR_WM_EVENT_STATUS_TYPE_WM_WL_IDLE_WDT_CLRMSK (0XFFFFFFF7U)
- #define VHA_CR_WM_EVENT_STATUS_TYPE_WM_WL_IDLE_WDT_EN (0X00000008U)
- #define VHA_CR_WM_EVENT_STATUS_TYPE_WM_SOCIF_WDT_SHIFT (2U)
- #define VHA_CR_WM_EVENT_STATUS_TYPE_WM_SOCIF_WDT_CLRMSK (0XFFFFFFFBU)
- #define VHA_CR_WM_EVENT_STATUS_TYPE_WM_SOCIF_WDT_EN (0X00000004U)
- #define VHA_CR_WM_EVENT_STATUS_TYPE_LOGIC_FAULT_SHIFT (1U)
- #define VHA_CR_WM_EVENT_STATUS_TYPE_LOGIC_FAULT_CLRMSK (0XFFFFFFFDU)
- #define VHA_CR_WM_EVENT_STATUS_TYPE_LOGIC_FAULT_EN (0X00000002U)
- #define VHA_CR_WM_EVENT_STATUS_TYPE_RESPONSE_FIFO_READY_SHIFT (0U)
- #define VHA_CR_WM_EVENT_STATUS_TYPE_RESPONSE_FIFO_READY_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_WM_EVENT_STATUS_TYPE_RESPONSE_FIFO_READY_EN (0X00000001U)
- /*
- Register VHA_CR_WM_EVENT_ENABLE
- */
- #define VHA_CR_WM_EVENT_ENABLE (0x10010U)
- #define VHA_CR_WM_EVENT_ENABLE_MASKFULL (IMG_UINT64_C(0x000000000000001F))
- #define VHA_CR_WM_EVENT_ENABLE_WM_WL_WDT_SHIFT (4U)
- #define VHA_CR_WM_EVENT_ENABLE_WM_WL_WDT_CLRMSK (0XFFFFFFEFU)
- #define VHA_CR_WM_EVENT_ENABLE_WM_WL_WDT_EN (0X00000010U)
- #define VHA_CR_WM_EVENT_ENABLE_WM_WL_IDLE_WDT_SHIFT (3U)
- #define VHA_CR_WM_EVENT_ENABLE_WM_WL_IDLE_WDT_CLRMSK (0XFFFFFFF7U)
- #define VHA_CR_WM_EVENT_ENABLE_WM_WL_IDLE_WDT_EN (0X00000008U)
- #define VHA_CR_WM_EVENT_ENABLE_WM_SOCIF_WDT_SHIFT (2U)
- #define VHA_CR_WM_EVENT_ENABLE_WM_SOCIF_WDT_CLRMSK (0XFFFFFFFBU)
- #define VHA_CR_WM_EVENT_ENABLE_WM_SOCIF_WDT_EN (0X00000004U)
- #define VHA_CR_WM_EVENT_ENABLE_LOGIC_FAULT_SHIFT (1U)
- #define VHA_CR_WM_EVENT_ENABLE_LOGIC_FAULT_CLRMSK (0XFFFFFFFDU)
- #define VHA_CR_WM_EVENT_ENABLE_LOGIC_FAULT_EN (0X00000002U)
- #define VHA_CR_WM_EVENT_ENABLE_RESPONSE_FIFO_READY_SHIFT (0U)
- #define VHA_CR_WM_EVENT_ENABLE_RESPONSE_FIFO_READY_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_WM_EVENT_ENABLE_RESPONSE_FIFO_READY_EN (0X00000001U)
- /*
- Register VHA_CR_WM_EVENT_STATUS
- */
- #define VHA_CR_WM_EVENT_STATUS (0x10018U)
- #define VHA_CR_WM_EVENT_STATUS_MASKFULL (IMG_UINT64_C(0x000000008000001F))
- #define VHA_CR_WM_EVENT_STATUS_PARITY_SHIFT (31U)
- #define VHA_CR_WM_EVENT_STATUS_PARITY_CLRMSK (0X7FFFFFFFU)
- #define VHA_CR_WM_EVENT_STATUS_PARITY_EN (0X80000000U)
- #define VHA_CR_WM_EVENT_STATUS_WM_WL_WDT_SHIFT (4U)
- #define VHA_CR_WM_EVENT_STATUS_WM_WL_WDT_CLRMSK (0XFFFFFFEFU)
- #define VHA_CR_WM_EVENT_STATUS_WM_WL_WDT_EN (0X00000010U)
- #define VHA_CR_WM_EVENT_STATUS_WM_WL_IDLE_WDT_SHIFT (3U)
- #define VHA_CR_WM_EVENT_STATUS_WM_WL_IDLE_WDT_CLRMSK (0XFFFFFFF7U)
- #define VHA_CR_WM_EVENT_STATUS_WM_WL_IDLE_WDT_EN (0X00000008U)
- #define VHA_CR_WM_EVENT_STATUS_WM_SOCIF_WDT_SHIFT (2U)
- #define VHA_CR_WM_EVENT_STATUS_WM_SOCIF_WDT_CLRMSK (0XFFFFFFFBU)
- #define VHA_CR_WM_EVENT_STATUS_WM_SOCIF_WDT_EN (0X00000004U)
- #define VHA_CR_WM_EVENT_STATUS_LOGIC_FAULT_SHIFT (1U)
- #define VHA_CR_WM_EVENT_STATUS_LOGIC_FAULT_CLRMSK (0XFFFFFFFDU)
- #define VHA_CR_WM_EVENT_STATUS_LOGIC_FAULT_EN (0X00000002U)
- #define VHA_CR_WM_EVENT_STATUS_RESPONSE_FIFO_READY_SHIFT (0U)
- #define VHA_CR_WM_EVENT_STATUS_RESPONSE_FIFO_READY_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_WM_EVENT_STATUS_RESPONSE_FIFO_READY_EN (0X00000001U)
- /*
- Register VHA_CR_WM_EVENT_STATUS_DISABLE
- */
- #define VHA_CR_WM_EVENT_STATUS_DISABLE (0x10028U)
- #define VHA_CR_WM_EVENT_STATUS_DISABLE_MASKFULL (IMG_UINT64_C(0x000000000000001F))
- #define VHA_CR_WM_EVENT_STATUS_DISABLE_WM_WL_WDT_SHIFT (4U)
- #define VHA_CR_WM_EVENT_STATUS_DISABLE_WM_WL_WDT_CLRMSK (0XFFFFFFEFU)
- #define VHA_CR_WM_EVENT_STATUS_DISABLE_WM_WL_WDT_EN (0X00000010U)
- #define VHA_CR_WM_EVENT_STATUS_DISABLE_WM_WL_IDLE_WDT_SHIFT (3U)
- #define VHA_CR_WM_EVENT_STATUS_DISABLE_WM_WL_IDLE_WDT_CLRMSK (0XFFFFFFF7U)
- #define VHA_CR_WM_EVENT_STATUS_DISABLE_WM_WL_IDLE_WDT_EN (0X00000008U)
- #define VHA_CR_WM_EVENT_STATUS_DISABLE_WM_SOCIF_WDT_SHIFT (2U)
- #define VHA_CR_WM_EVENT_STATUS_DISABLE_WM_SOCIF_WDT_CLRMSK (0XFFFFFFFBU)
- #define VHA_CR_WM_EVENT_STATUS_DISABLE_WM_SOCIF_WDT_EN (0X00000004U)
- #define VHA_CR_WM_EVENT_STATUS_DISABLE_LOGIC_FAULT_SHIFT (1U)
- #define VHA_CR_WM_EVENT_STATUS_DISABLE_LOGIC_FAULT_CLRMSK (0XFFFFFFFDU)
- #define VHA_CR_WM_EVENT_STATUS_DISABLE_LOGIC_FAULT_EN (0X00000002U)
- #define VHA_CR_WM_EVENT_STATUS_DISABLE_RESPONSE_FIFO_READY_SHIFT (0U)
- #define VHA_CR_WM_EVENT_STATUS_DISABLE_RESPONSE_FIFO_READY_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_WM_EVENT_STATUS_DISABLE_RESPONSE_FIFO_READY_EN (0X00000001U)
- /*
- Register VHA_CR_WM_EVENT_CLEAR
- */
- #define VHA_CR_WM_EVENT_CLEAR (0x10020U)
- #define VHA_CR_WM_EVENT_CLEAR_MASKFULL (IMG_UINT64_C(0x000000000000001F))
- #define VHA_CR_WM_EVENT_CLEAR_WM_WL_WDT_SHIFT (4U)
- #define VHA_CR_WM_EVENT_CLEAR_WM_WL_WDT_CLRMSK (0XFFFFFFEFU)
- #define VHA_CR_WM_EVENT_CLEAR_WM_WL_WDT_EN (0X00000010U)
- #define VHA_CR_WM_EVENT_CLEAR_WM_WL_IDLE_WDT_SHIFT (3U)
- #define VHA_CR_WM_EVENT_CLEAR_WM_WL_IDLE_WDT_CLRMSK (0XFFFFFFF7U)
- #define VHA_CR_WM_EVENT_CLEAR_WM_WL_IDLE_WDT_EN (0X00000008U)
- #define VHA_CR_WM_EVENT_CLEAR_WM_SOCIF_WDT_SHIFT (2U)
- #define VHA_CR_WM_EVENT_CLEAR_WM_SOCIF_WDT_CLRMSK (0XFFFFFFFBU)
- #define VHA_CR_WM_EVENT_CLEAR_WM_SOCIF_WDT_EN (0X00000004U)
- #define VHA_CR_WM_EVENT_CLEAR_LOGIC_FAULT_SHIFT (1U)
- #define VHA_CR_WM_EVENT_CLEAR_LOGIC_FAULT_CLRMSK (0XFFFFFFFDU)
- #define VHA_CR_WM_EVENT_CLEAR_LOGIC_FAULT_EN (0X00000002U)
- #define VHA_CR_WM_EVENT_CLEAR_RESPONSE_FIFO_READY_SHIFT (0U)
- #define VHA_CR_WM_EVENT_CLEAR_RESPONSE_FIFO_READY_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_WM_EVENT_CLEAR_RESPONSE_FIFO_READY_EN (0X00000001U)
- /*
- Register VHA_CR_WM_EVENT_INJECT
- */
- #define VHA_CR_WM_EVENT_INJECT (0x10030U)
- #define VHA_CR_WM_EVENT_INJECT_MASKFULL (IMG_UINT64_C(0x000000000000001F))
- #define VHA_CR_WM_EVENT_INJECT_WM_WL_WDT_SHIFT (4U)
- #define VHA_CR_WM_EVENT_INJECT_WM_WL_WDT_CLRMSK (0XFFFFFFEFU)
- #define VHA_CR_WM_EVENT_INJECT_WM_WL_WDT_EN (0X00000010U)
- #define VHA_CR_WM_EVENT_INJECT_WM_WL_IDLE_WDT_SHIFT (3U)
- #define VHA_CR_WM_EVENT_INJECT_WM_WL_IDLE_WDT_CLRMSK (0XFFFFFFF7U)
- #define VHA_CR_WM_EVENT_INJECT_WM_WL_IDLE_WDT_EN (0X00000008U)
- #define VHA_CR_WM_EVENT_INJECT_WM_SOCIF_WDT_SHIFT (2U)
- #define VHA_CR_WM_EVENT_INJECT_WM_SOCIF_WDT_CLRMSK (0XFFFFFFFBU)
- #define VHA_CR_WM_EVENT_INJECT_WM_SOCIF_WDT_EN (0X00000004U)
- #define VHA_CR_WM_EVENT_INJECT_LOGIC_FAULT_SHIFT (1U)
- #define VHA_CR_WM_EVENT_INJECT_LOGIC_FAULT_CLRMSK (0XFFFFFFFDU)
- #define VHA_CR_WM_EVENT_INJECT_LOGIC_FAULT_EN (0X00000002U)
- #define VHA_CR_WM_EVENT_INJECT_RESPONSE_FIFO_READY_SHIFT (0U)
- #define VHA_CR_WM_EVENT_INJECT_RESPONSE_FIFO_READY_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_WM_EVENT_INJECT_RESPONSE_FIFO_READY_EN (0X00000001U)
- /*
- Register VHA_CR_WM_WL_ID
- */
- #define VHA_CR_WM_WL_ID (0x10040U)
- #define VHA_CR_WM_WL_ID_MASKFULL (IMG_UINT64_C(0x000000000000FFFF))
- #define VHA_CR_WM_WL_ID_WL_ID_SHIFT (0U)
- #define VHA_CR_WM_WL_ID_WL_ID_CLRMSK (0XFFFF0000U)
- /*
- Register VHA_CR_WM_DEBUG_CONTROL
- */
- #define VHA_CR_WM_DEBUG_CONTROL (0x10048U)
- #define VHA_CR_WM_DEBUG_CONTROL_MASKFULL (IMG_UINT64_C(0x0000000000000003))
- #define VHA_CR_WM_DEBUG_CONTROL_BW_ENABLE_SHIFT (1U)
- #define VHA_CR_WM_DEBUG_CONTROL_BW_ENABLE_CLRMSK (0XFFFFFFFDU)
- #define VHA_CR_WM_DEBUG_CONTROL_BW_ENABLE_EN (0X00000002U)
- #define VHA_CR_WM_DEBUG_CONTROL_PERF_ENABLE_SHIFT (0U)
- #define VHA_CR_WM_DEBUG_CONTROL_PERF_ENABLE_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_WM_DEBUG_CONTROL_PERF_ENABLE_EN (0X00000001U)
- /*
- WM_WL_WDT is Disabled */
- #define VHA_CR_WM_WL_WDT_CTRL_WL_WDT_CTRL_NONE (0x00000000U)
- /*
- WM_WL_WDT is Cleared when WM kicks a Workload */
- #define VHA_CR_WM_WL_WDT_CTRL_WL_WDT_CTRL_KICK_WL (0x00000001U)
- /*
- Register VHA_CR_WM_WL_WDT_CTRL
- */
- #define VHA_CR_WM_WL_WDT_CTRL (0x10100U)
- #define VHA_CR_WM_WL_WDT_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000000001))
- #define VHA_CR_WM_WL_WDT_CTRL_MODE_SHIFT (0U)
- #define VHA_CR_WM_WL_WDT_CTRL_MODE_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_WM_WL_WDT_CTRL_MODE_NONE (00000000U)
- #define VHA_CR_WM_WL_WDT_CTRL_MODE_KICK_WL (0X00000001U)
- /*
- Register VHA_CR_WM_WL_WDT_COMPAREMATCH
- */
- #define VHA_CR_WM_WL_WDT_COMPAREMATCH (0x10108U)
- #define VHA_CR_WM_WL_WDT_COMPAREMATCH_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_WM_WL_WDT_COMPAREMATCH_VALUE_SHIFT (0U)
- #define VHA_CR_WM_WL_WDT_COMPAREMATCH_VALUE_CLRMSK (00000000U)
- /*
- Register VHA_CR_WM_WL_WDT_TIMER
- */
- #define VHA_CR_WM_WL_WDT_TIMER (0x10110U)
- #define VHA_CR_WM_WL_WDT_TIMER_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_WM_WL_WDT_TIMER_VALUE_SHIFT (0U)
- #define VHA_CR_WM_WL_WDT_TIMER_VALUE_CLRMSK (00000000U)
- /*
- WL_IDLE_WDT is Disabled */
- #define VHA_CR_WM_WL_IDLE_WDT_CTRL_WL_IDLE_WDT_CTRL_NONE (0x00000000U)
- /*
- WL_IDLE_WDT is Enabled */
- #define VHA_CR_WM_WL_IDLE_WDT_CTRL_WL_IDLE_WDT_CTRL_ENABLED (0x00000001U)
- /*
- Register VHA_CR_WM_WL_IDLE_WDT_CTRL
- */
- #define VHA_CR_WM_WL_IDLE_WDT_CTRL (0x10118U)
- #define VHA_CR_WM_WL_IDLE_WDT_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000000001))
- #define VHA_CR_WM_WL_IDLE_WDT_CTRL_MODE_SHIFT (0U)
- #define VHA_CR_WM_WL_IDLE_WDT_CTRL_MODE_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_WM_WL_IDLE_WDT_CTRL_MODE_NONE (00000000U)
- #define VHA_CR_WM_WL_IDLE_WDT_CTRL_MODE_ENABLED (0X00000001U)
- /*
- Register VHA_CR_WM_WL_IDLE_WDT_COMPAREMATCH
- */
- #define VHA_CR_WM_WL_IDLE_WDT_COMPAREMATCH (0x10120U)
- #define VHA_CR_WM_WL_IDLE_WDT_COMPAREMATCH_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_WM_WL_IDLE_WDT_COMPAREMATCH_VALUE_SHIFT (0U)
- #define VHA_CR_WM_WL_IDLE_WDT_COMPAREMATCH_VALUE_CLRMSK (00000000U)
- /*
- Register VHA_CR_WM_WL_IDLE_WDT_TIMER
- */
- #define VHA_CR_WM_WL_IDLE_WDT_TIMER (0x10128U)
- #define VHA_CR_WM_WL_IDLE_WDT_TIMER_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_WM_WL_IDLE_WDT_TIMER_VALUE_SHIFT (0U)
- #define VHA_CR_WM_WL_IDLE_WDT_TIMER_VALUE_CLRMSK (00000000U)
- /*
- WM_SOCIF_WDT is Disabled */
- #define VHA_CR_WM_SOCIF_WDT_CTRL_WM_SOCIF_WDT_CTRL_NONE (0x00000000U)
- /*
- WM_SOFIC_WDT is Enabled */
- #define VHA_CR_WM_SOCIF_WDT_CTRL_WM_SOCIF_WDT_CTRL_ENABLED (0x00000001U)
- /*
- Register VHA_CR_WM_SOCIF_WDT_CTRL
- */
- #define VHA_CR_WM_SOCIF_WDT_CTRL (0x10130U)
- #define VHA_CR_WM_SOCIF_WDT_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000000001))
- #define VHA_CR_WM_SOCIF_WDT_CTRL_MODE_SHIFT (0U)
- #define VHA_CR_WM_SOCIF_WDT_CTRL_MODE_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_WM_SOCIF_WDT_CTRL_MODE_NONE (00000000U)
- #define VHA_CR_WM_SOCIF_WDT_CTRL_MODE_ENABLED (0X00000001U)
- /*
- Register VHA_CR_WM_SOCIF_WDT_COMPAREMATCH
- */
- #define VHA_CR_WM_SOCIF_WDT_COMPAREMATCH (0x10138U)
- #define VHA_CR_WM_SOCIF_WDT_COMPAREMATCH_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_WM_SOCIF_WDT_COMPAREMATCH_VALUE_SHIFT (0U)
- #define VHA_CR_WM_SOCIF_WDT_COMPAREMATCH_VALUE_CLRMSK (00000000U)
- /*
- Register VHA_CR_WM_SOCIF_WDT_TIMER
- */
- #define VHA_CR_WM_SOCIF_WDT_TIMER (0x10140U)
- #define VHA_CR_WM_SOCIF_WDT_TIMER_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_WM_SOCIF_WDT_TIMER_VALUE_SHIFT (0U)
- #define VHA_CR_WM_SOCIF_WDT_TIMER_VALUE_CLRMSK (00000000U)
- /*
- Register VHA_CR_WM_RESPONSE_FIFO_READ
- */
- #define VHA_CR_WM_RESPONSE_FIFO_READ (0x101F8U)
- #define VHA_CR_WM_RESPONSE_FIFO_READ_MASKFULL (IMG_UINT64_C(0x0000000000000001))
- #define VHA_CR_WM_RESPONSE_FIFO_READ_FIFO_READ_SHIFT (0U)
- #define VHA_CR_WM_RESPONSE_FIFO_READ_FIFO_READ_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_WM_RESPONSE_FIFO_READ_FIFO_READ_EN (0X00000001U)
- /*
- Register VHA_CR_WM_RESPONSE_FIFO_WL_ID
- */
- #define VHA_CR_WM_RESPONSE_FIFO_WL_ID (0x10200U)
- #define VHA_CR_WM_RESPONSE_FIFO_WL_ID_MASKFULL (IMG_UINT64_C(0x000000000000FFFF))
- #define VHA_CR_WM_RESPONSE_FIFO_WL_ID_WL_ID_SHIFT (0U)
- #define VHA_CR_WM_RESPONSE_FIFO_WL_ID_WL_ID_CLRMSK (0XFFFF0000U)
- #define VHA_CR_WM_RESPONSE_FIFO_WL_STATUS_WL_ERROR_CODE_MASK (0x0000000FU)
- /*
- Workload was not kicked because an interrupt was raised from a core before start, FAILED_CORE_IDX indicates the core associated with the error.*/
- #define VHA_CR_WM_RESPONSE_FIFO_WL_STATUS_WL_ERROR_CODE_CORE_IRQ_BEFORE_KICK (0x00000000U)
- /*
- Error while read-back CORE_MASK for multi-cast kick*/
- #define VHA_CR_WM_RESPONSE_FIFO_WL_STATUS_WL_ERROR_CODE_INDIRECT_MASK_SET_ERROR (0x00000001U)
- /*
- Error while read-back CORE_MASK for single-core checks, FAILED_CORE_IDX indicates the core associated with the error.*/
- #define VHA_CR_WM_RESPONSE_FIFO_WL_STATUS_WL_ERROR_CODE_KICK_CORE_ACCESS_ERROR (0x00000002U)
- /*
- Error while checking VHA_CR_OS0_CNN_CONTROL.START, FAILED_CORE_IDX indicates the core associated with the error.*/
- #define VHA_CR_WM_RESPONSE_FIFO_WL_STATUS_WL_ERROR_CODE_CNN_CONTROL_START_HIGH (0x00000003U)
- /*
- Error while checking VHA_CR_OS0_CNN_STATUS, FAILED_CORE_IDX indicates the core associated with the error.*/
- #define VHA_CR_WM_RESPONSE_FIFO_WL_STATUS_WL_ERROR_CODE_CNN_STATUS_ERROR (0x00000004U)
- /*
- Error while read-back CORE_MASK for single-core checks, FAILED_CORE_IDX indicates the core associated with the error.*/
- #define VHA_CR_WM_RESPONSE_FIFO_WL_STATUS_WL_ERROR_CODE_INT_CORE_ACCESS_ERROR (0x00000005U)
- /*
- Error while checking VHA_CR_CORE_EVENT_WM_STATUS before clear, FAILED_CORE_IDX indicates the core associated with the error.*/
- #define VHA_CR_WM_RESPONSE_FIFO_WL_STATUS_WL_ERROR_CODE_CORE_EVENT_ERROR (0x00000006U)
- /*
- Error while checking VHA_CR_CORE_EVENT_WM_STATUS after clear, FAILED_CORE_IDX indicates the core associated with the error.*/
- #define VHA_CR_WM_RESPONSE_FIFO_WL_STATUS_WL_ERROR_CODE_CORE_EVENT_NOT_CLEARED (0x00000007U)
- /*
- Error while checking IRQ signal after clear, FAILED_CORE_IDX indicates the core associated with the error.*/
- #define VHA_CR_WM_RESPONSE_FIFO_WL_STATUS_WL_ERROR_CODE_CORE_EVENT_IRQ_HIGH (0x00000008U)
- /*
- Detected an error in the interconnect parity or on lockstep cores, FAILED_CORE_IDX indicates the core associated with the error.*/
- #define VHA_CR_WM_RESPONSE_FIFO_WL_STATUS_WL_ERROR_CODE_INTERCONNECT_ERROR (0x00000009U)
- /*
- Register VHA_CR_WM_RESPONSE_FIFO_WL_STATUS
- */
- #define VHA_CR_WM_RESPONSE_FIFO_WL_STATUS (0x10208U)
- #define VHA_CR_WM_RESPONSE_FIFO_WL_STATUS_MASKFULL (IMG_UINT64_C(0x00000000800007F3))
- #define VHA_CR_WM_RESPONSE_FIFO_WL_STATUS_PARITY_SHIFT (31U)
- #define VHA_CR_WM_RESPONSE_FIFO_WL_STATUS_PARITY_CLRMSK (0X7FFFFFFFU)
- #define VHA_CR_WM_RESPONSE_FIFO_WL_STATUS_PARITY_EN (0X80000000U)
- #define VHA_CR_WM_RESPONSE_FIFO_WL_STATUS_FAILED_CORE_IDX_SHIFT (8U)
- #define VHA_CR_WM_RESPONSE_FIFO_WL_STATUS_FAILED_CORE_IDX_CLRMSK (0XFFFFF8FFU)
- #define VHA_CR_WM_RESPONSE_FIFO_WL_STATUS_ERROR_CODE_SHIFT (4U)
- #define VHA_CR_WM_RESPONSE_FIFO_WL_STATUS_ERROR_CODE_CLRMSK (0XFFFFFF0FU)
- #define VHA_CR_WM_RESPONSE_FIFO_WL_STATUS_ERROR_CODE_CORE_IRQ_BEFORE_KICK (00000000U)
- #define VHA_CR_WM_RESPONSE_FIFO_WL_STATUS_ERROR_CODE_INDIRECT_MASK_SET_ERROR (0X00000010U)
- #define VHA_CR_WM_RESPONSE_FIFO_WL_STATUS_ERROR_CODE_KICK_CORE_ACCESS_ERROR (0X00000020U)
- #define VHA_CR_WM_RESPONSE_FIFO_WL_STATUS_ERROR_CODE_CNN_CONTROL_START_HIGH (0X00000030U)
- #define VHA_CR_WM_RESPONSE_FIFO_WL_STATUS_ERROR_CODE_CNN_STATUS_ERROR (0X00000040U)
- #define VHA_CR_WM_RESPONSE_FIFO_WL_STATUS_ERROR_CODE_INT_CORE_ACCESS_ERROR (0X00000050U)
- #define VHA_CR_WM_RESPONSE_FIFO_WL_STATUS_ERROR_CODE_CORE_EVENT_ERROR (0X00000060U)
- #define VHA_CR_WM_RESPONSE_FIFO_WL_STATUS_ERROR_CODE_CORE_EVENT_NOT_CLEARED (0X00000070U)
- #define VHA_CR_WM_RESPONSE_FIFO_WL_STATUS_ERROR_CODE_CORE_EVENT_IRQ_HIGH (0X00000080U)
- #define VHA_CR_WM_RESPONSE_FIFO_WL_STATUS_ERROR_CODE_INTERCONNECT_ERROR (0X00000090U)
- #define VHA_CR_WM_RESPONSE_FIFO_WL_STATUS_WL_FAILURE_SHIFT (1U)
- #define VHA_CR_WM_RESPONSE_FIFO_WL_STATUS_WL_FAILURE_CLRMSK (0XFFFFFFFDU)
- #define VHA_CR_WM_RESPONSE_FIFO_WL_STATUS_WL_FAILURE_EN (0X00000002U)
- #define VHA_CR_WM_RESPONSE_FIFO_WL_STATUS_SUCCESS_SHIFT (0U)
- #define VHA_CR_WM_RESPONSE_FIFO_WL_STATUS_SUCCESS_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_WM_RESPONSE_FIFO_WL_STATUS_SUCCESS_EN (0X00000001U)
- /*
- Register VHA_CR_WM_RESPONSE_FIFO_WL_PERF
- */
- #define VHA_CR_WM_RESPONSE_FIFO_WL_PERF (0x10210U)
- #define VHA_CR_WM_RESPONSE_FIFO_WL_PERF_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_WM_RESPONSE_FIFO_WL_PERF_CYCLES_SHIFT (0U)
- #define VHA_CR_WM_RESPONSE_FIFO_WL_PERF_CYCLES_CLRMSK (00000000U)
- /*
- Register VHA_CR_WM_RESPONSE_FIFO_WL_BW_LOCM_RD
- */
- #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_LOCM_RD (0x10218U)
- #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_LOCM_RD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_LOCM_RD_BW_SHIFT (0U)
- #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_LOCM_RD_BW_CLRMSK (00000000U)
- /*
- Register VHA_CR_WM_RESPONSE_FIFO_WL_BW_LOCM_WR
- */
- #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_LOCM_WR (0x10220U)
- #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_LOCM_WR_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_LOCM_WR_BW_SHIFT (0U)
- #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_LOCM_WR_BW_CLRMSK (00000000U)
- /*
- Register VHA_CR_WM_RESPONSE_FIFO_WL_BW_LOCM_MWR
- */
- #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_LOCM_MWR (0x10228U)
- #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_LOCM_MWR_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_LOCM_MWR_BW_SHIFT (0U)
- #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_LOCM_MWR_BW_CLRMSK (00000000U)
- /*
- Register VHA_CR_WM_RESPONSE_FIFO_WL_BW_SOCM_RD
- */
- #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_SOCM_RD (0x10230U)
- #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_SOCM_RD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_SOCM_RD_BW_SHIFT (0U)
- #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_SOCM_RD_BW_CLRMSK (00000000U)
- /*
- Register VHA_CR_WM_RESPONSE_FIFO_WL_BW_SOCM_WR
- */
- #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_SOCM_WR (0x10238U)
- #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_SOCM_WR_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_SOCM_WR_BW_SHIFT (0U)
- #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_SOCM_WR_BW_CLRMSK (00000000U)
- /*
- Register VHA_CR_WM_RESPONSE_FIFO_WL_BW_SOCM_MWR
- */
- #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_SOCM_MWR (0x10240U)
- #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_SOCM_MWR_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_SOCM_MWR_BW_SHIFT (0U)
- #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_SOCM_MWR_BW_CLRMSK (00000000U)
- /*
- Register VHA_CR_WM_RESPONSE_FIFO_WL_BW_DDR_RD
- */
- #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_DDR_RD (0x10248U)
- #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_DDR_RD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_DDR_RD_BW_SHIFT (0U)
- #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_DDR_RD_BW_CLRMSK (00000000U)
- /*
- Register VHA_CR_WM_RESPONSE_FIFO_WL_BW_DDR_WR
- */
- #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_DDR_WR (0x10250U)
- #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_DDR_WR_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_DDR_WR_BW_SHIFT (0U)
- #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_DDR_WR_BW_CLRMSK (00000000U)
- /*
- Register VHA_CR_WM_RESPONSE_FIFO_WL_BW_DDR_MWR
- */
- #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_DDR_MWR (0x10258U)
- #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_DDR_MWR_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_DDR_MWR_BW_SHIFT (0U)
- #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_DDR_MWR_BW_CLRMSK (00000000U)
- /*
- Register VHA_CR_WM_RESPONSE_FIFO_WL_BW_LOCM_RD_WORD
- */
- #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_LOCM_RD_WORD (0x10260U)
- #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_LOCM_RD_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_LOCM_RD_WORD_BW_SHIFT (0U)
- #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_LOCM_RD_WORD_BW_CLRMSK (00000000U)
- /*
- Register VHA_CR_WM_RESPONSE_FIFO_WL_BW_LOCM_WR_WORD
- */
- #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_LOCM_WR_WORD (0x10268U)
- #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_LOCM_WR_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_LOCM_WR_WORD_BW_SHIFT (0U)
- #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_LOCM_WR_WORD_BW_CLRMSK (00000000U)
- /*
- Register VHA_CR_WM_RESPONSE_FIFO_WL_BW_SOCM_RD_WORD
- */
- #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_SOCM_RD_WORD (0x10270U)
- #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_SOCM_RD_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_SOCM_RD_WORD_BW_SHIFT (0U)
- #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_SOCM_RD_WORD_BW_CLRMSK (00000000U)
- /*
- Register VHA_CR_WM_RESPONSE_FIFO_WL_BW_SOCM_WR_WORD
- */
- #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_SOCM_WR_WORD (0x10278U)
- #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_SOCM_WR_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_SOCM_WR_WORD_BW_SHIFT (0U)
- #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_SOCM_WR_WORD_BW_CLRMSK (00000000U)
- /*
- Register VHA_CR_WM_RESPONSE_FIFO_WL_BW_DDR_RD_WORD
- */
- #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_DDR_RD_WORD (0x10280U)
- #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_DDR_RD_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_DDR_RD_WORD_BW_SHIFT (0U)
- #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_DDR_RD_WORD_BW_CLRMSK (00000000U)
- /*
- Register VHA_CR_WM_RESPONSE_FIFO_WL_BW_DDR_WR_WORD
- */
- #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_DDR_WR_WORD (0x10288U)
- #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_DDR_WR_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_DDR_WR_WORD_BW_SHIFT (0U)
- #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_DDR_WR_WORD_BW_CLRMSK (00000000U)
- #define VHA_CR_MH_CONTROL_MAX_BURST_LENGTH_MASK (0x00000003U)
- /*
- Register VHA_CR_CORE_MASK
- */
- #define VHA_CR_CORE_MASK (0x20000U)
- #define VHA_CR_CORE_MASK_MASKFULL (IMG_UINT64_C(0x00000000000000FF))
- #define VHA_CR_CORE_MASK_CORE_MASK_SHIFT (0U)
- #define VHA_CR_CORE_MASK_CORE_MASK_CLRMSK (0XFFFFFF00U)
- #define VHA_CR_CLK_CTRL0_MODE_MASK (0x00000003U)
- /*
- The domain clock is forced off */
- #define VHA_CR_CLK_CTRL0_MODE_OFF (0x00000000U)
- /*
- The domain clock is forced on */
- #define VHA_CR_CLK_CTRL0_MODE_ON (0x00000001U)
- /*
- Automatic clock gating is active, the domain clock is only on whilst data is being processed */
- #define VHA_CR_CLK_CTRL0_MODE_AUTO (0x00000002U)
- /*
- Register VHA_CR_CLK_CTRL0
- */
- #define VHA_CR_CLK_CTRL0 (0x20100U)
- #define VHA_CR_CLK_CTRL0_MASKFULL (IMG_UINT64_C(0xF3FFFFFF3F00FF33))
- #define VHA_CR_CLK_CTRL0_CNN_CORE_XBAR_SHIFT (62U)
- #define VHA_CR_CLK_CTRL0_CNN_CORE_XBAR_CLRMSK (IMG_UINT64_C(0X3FFFFFFFFFFFFFFF))
- #define VHA_CR_CLK_CTRL0_CNN_CORE_XBAR_OFF (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_CLK_CTRL0_CNN_CORE_XBAR_ON (IMG_UINT64_C(0x4000000000000000))
- #define VHA_CR_CLK_CTRL0_CNN_CORE_XBAR_AUTO (IMG_UINT64_C(0x8000000000000000))
- #define VHA_CR_CLK_CTRL0_CNN_MMM_SHIFT (60U)
- #define VHA_CR_CLK_CTRL0_CNN_MMM_CLRMSK (IMG_UINT64_C(0XCFFFFFFFFFFFFFFF))
- #define VHA_CR_CLK_CTRL0_CNN_MMM_OFF (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_CLK_CTRL0_CNN_MMM_ON (IMG_UINT64_C(0x1000000000000000))
- #define VHA_CR_CLK_CTRL0_CNN_MMM_AUTO (IMG_UINT64_C(0x2000000000000000))
- #define VHA_CR_CLK_CTRL0_CNN_EWO_SHIFT (56U)
- #define VHA_CR_CLK_CTRL0_CNN_EWO_CLRMSK (IMG_UINT64_C(0XFCFFFFFFFFFFFFFF))
- #define VHA_CR_CLK_CTRL0_CNN_EWO_OFF (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_CLK_CTRL0_CNN_EWO_ON (IMG_UINT64_C(0x0100000000000000))
- #define VHA_CR_CLK_CTRL0_CNN_EWO_AUTO (IMG_UINT64_C(0x0200000000000000))
- #define VHA_CR_CLK_CTRL0_CNN_PACK_SHIFT (54U)
- #define VHA_CR_CLK_CTRL0_CNN_PACK_CLRMSK (IMG_UINT64_C(0XFF3FFFFFFFFFFFFF))
- #define VHA_CR_CLK_CTRL0_CNN_PACK_OFF (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_CLK_CTRL0_CNN_PACK_ON (IMG_UINT64_C(0x0040000000000000))
- #define VHA_CR_CLK_CTRL0_CNN_PACK_AUTO (IMG_UINT64_C(0x0080000000000000))
- #define VHA_CR_CLK_CTRL0_CNN_OIN_SHIFT (52U)
- #define VHA_CR_CLK_CTRL0_CNN_OIN_CLRMSK (IMG_UINT64_C(0XFFCFFFFFFFFFFFFF))
- #define VHA_CR_CLK_CTRL0_CNN_OIN_OFF (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_CLK_CTRL0_CNN_OIN_ON (IMG_UINT64_C(0x0010000000000000))
- #define VHA_CR_CLK_CTRL0_CNN_OIN_AUTO (IMG_UINT64_C(0x0020000000000000))
- #define VHA_CR_CLK_CTRL0_CNN_POOL_SHIFT (50U)
- #define VHA_CR_CLK_CTRL0_CNN_POOL_CLRMSK (IMG_UINT64_C(0XFFF3FFFFFFFFFFFF))
- #define VHA_CR_CLK_CTRL0_CNN_POOL_OFF (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_CLK_CTRL0_CNN_POOL_ON (IMG_UINT64_C(0x0004000000000000))
- #define VHA_CR_CLK_CTRL0_CNN_POOL_AUTO (IMG_UINT64_C(0x0008000000000000))
- #define VHA_CR_CLK_CTRL0_CNN_SB_SHIFT (48U)
- #define VHA_CR_CLK_CTRL0_CNN_SB_CLRMSK (IMG_UINT64_C(0XFFFCFFFFFFFFFFFF))
- #define VHA_CR_CLK_CTRL0_CNN_SB_OFF (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_CLK_CTRL0_CNN_SB_ON (IMG_UINT64_C(0x0001000000000000))
- #define VHA_CR_CLK_CTRL0_CNN_SB_AUTO (IMG_UINT64_C(0x0002000000000000))
- #define VHA_CR_CLK_CTRL0_CNN_XBAR_SHIFT (46U)
- #define VHA_CR_CLK_CTRL0_CNN_XBAR_CLRMSK (IMG_UINT64_C(0XFFFF3FFFFFFFFFFF))
- #define VHA_CR_CLK_CTRL0_CNN_XBAR_OFF (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_CLK_CTRL0_CNN_XBAR_ON (IMG_UINT64_C(0x0000400000000000))
- #define VHA_CR_CLK_CTRL0_CNN_XBAR_AUTO (IMG_UINT64_C(0x0000800000000000))
- #define VHA_CR_CLK_CTRL0_CNN_NORM_SHIFT (44U)
- #define VHA_CR_CLK_CTRL0_CNN_NORM_CLRMSK (IMG_UINT64_C(0XFFFFCFFFFFFFFFFF))
- #define VHA_CR_CLK_CTRL0_CNN_NORM_OFF (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_CLK_CTRL0_CNN_NORM_ON (IMG_UINT64_C(0x0000100000000000))
- #define VHA_CR_CLK_CTRL0_CNN_NORM_AUTO (IMG_UINT64_C(0x0000200000000000))
- #define VHA_CR_CLK_CTRL0_CNN_ACT_SHIFT (42U)
- #define VHA_CR_CLK_CTRL0_CNN_ACT_CLRMSK (IMG_UINT64_C(0XFFFFF3FFFFFFFFFF))
- #define VHA_CR_CLK_CTRL0_CNN_ACT_OFF (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_CLK_CTRL0_CNN_ACT_ON (IMG_UINT64_C(0x0000040000000000))
- #define VHA_CR_CLK_CTRL0_CNN_ACT_AUTO (IMG_UINT64_C(0x0000080000000000))
- #define VHA_CR_CLK_CTRL0_CNN_ACCUM_SHIFT (40U)
- #define VHA_CR_CLK_CTRL0_CNN_ACCUM_CLRMSK (IMG_UINT64_C(0XFFFFFCFFFFFFFFFF))
- #define VHA_CR_CLK_CTRL0_CNN_ACCUM_OFF (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_CLK_CTRL0_CNN_ACCUM_ON (IMG_UINT64_C(0x0000010000000000))
- #define VHA_CR_CLK_CTRL0_CNN_ACCUM_AUTO (IMG_UINT64_C(0x0000020000000000))
- #define VHA_CR_CLK_CTRL0_CNN_CNV_SHIFT (38U)
- #define VHA_CR_CLK_CTRL0_CNN_CNV_CLRMSK (IMG_UINT64_C(0XFFFFFF3FFFFFFFFF))
- #define VHA_CR_CLK_CTRL0_CNN_CNV_OFF (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_CLK_CTRL0_CNN_CNV_ON (IMG_UINT64_C(0x0000004000000000))
- #define VHA_CR_CLK_CTRL0_CNN_CNV_AUTO (IMG_UINT64_C(0x0000008000000000))
- #define VHA_CR_CLK_CTRL0_CNN_CBUF_SHIFT (36U)
- #define VHA_CR_CLK_CTRL0_CNN_CBUF_CLRMSK (IMG_UINT64_C(0XFFFFFFCFFFFFFFFF))
- #define VHA_CR_CLK_CTRL0_CNN_CBUF_OFF (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_CLK_CTRL0_CNN_CBUF_ON (IMG_UINT64_C(0x0000001000000000))
- #define VHA_CR_CLK_CTRL0_CNN_CBUF_AUTO (IMG_UINT64_C(0x0000002000000000))
- #define VHA_CR_CLK_CTRL0_CNN_IBUF_SHIFT (34U)
- #define VHA_CR_CLK_CTRL0_CNN_IBUF_CLRMSK (IMG_UINT64_C(0XFFFFFFF3FFFFFFFF))
- #define VHA_CR_CLK_CTRL0_CNN_IBUF_OFF (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_CLK_CTRL0_CNN_IBUF_ON (IMG_UINT64_C(0x0000000400000000))
- #define VHA_CR_CLK_CTRL0_CNN_IBUF_AUTO (IMG_UINT64_C(0x0000000800000000))
- #define VHA_CR_CLK_CTRL0_CNN_CMD_SHIFT (32U)
- #define VHA_CR_CLK_CTRL0_CNN_CMD_CLRMSK (IMG_UINT64_C(0XFFFFFFFCFFFFFFFF))
- #define VHA_CR_CLK_CTRL0_CNN_CMD_OFF (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_CLK_CTRL0_CNN_CMD_ON (IMG_UINT64_C(0x0000000100000000))
- #define VHA_CR_CLK_CTRL0_CNN_CMD_AUTO (IMG_UINT64_C(0x0000000200000000))
- #define VHA_CR_CLK_CTRL0_CNN_SHIFT (28U)
- #define VHA_CR_CLK_CTRL0_CNN_CLRMSK (IMG_UINT64_C(0XFFFFFFFFCFFFFFFF))
- #define VHA_CR_CLK_CTRL0_CNN_OFF (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_CLK_CTRL0_CNN_ON (IMG_UINT64_C(0x0000000010000000))
- #define VHA_CR_CLK_CTRL0_CNN_AUTO (IMG_UINT64_C(0x0000000020000000))
- #define VHA_CR_CLK_CTRL0_CNN_TRS_A_SHIFT (26U)
- #define VHA_CR_CLK_CTRL0_CNN_TRS_A_CLRMSK (IMG_UINT64_C(0XFFFFFFFFF3FFFFFF))
- #define VHA_CR_CLK_CTRL0_CNN_TRS_A_OFF (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_CLK_CTRL0_CNN_TRS_A_ON (IMG_UINT64_C(0x0000000004000000))
- #define VHA_CR_CLK_CTRL0_CNN_TRS_A_AUTO (IMG_UINT64_C(0x0000000008000000))
- #define VHA_CR_CLK_CTRL0_CNN_TRS_B_SHIFT (24U)
- #define VHA_CR_CLK_CTRL0_CNN_TRS_B_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFCFFFFFF))
- #define VHA_CR_CLK_CTRL0_CNN_TRS_B_OFF (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_CLK_CTRL0_CNN_TRS_B_ON (IMG_UINT64_C(0x0000000001000000))
- #define VHA_CR_CLK_CTRL0_CNN_TRS_B_AUTO (IMG_UINT64_C(0x0000000002000000))
- #define VHA_CR_CLK_CTRL0_MEMBUS_RESET_SHIFT (14U)
- #define VHA_CR_CLK_CTRL0_MEMBUS_RESET_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF3FFF))
- #define VHA_CR_CLK_CTRL0_MEMBUS_RESET_OFF (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_CLK_CTRL0_MEMBUS_RESET_ON (IMG_UINT64_C(0x0000000000004000))
- #define VHA_CR_CLK_CTRL0_MEMBUS_RESET_AUTO (IMG_UINT64_C(0x0000000000008000))
- #define VHA_CR_CLK_CTRL0_BWM_SHIFT (12U)
- #define VHA_CR_CLK_CTRL0_BWM_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFCFFF))
- #define VHA_CR_CLK_CTRL0_BWM_OFF (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_CLK_CTRL0_BWM_ON (IMG_UINT64_C(0x0000000000001000))
- #define VHA_CR_CLK_CTRL0_BWM_AUTO (IMG_UINT64_C(0x0000000000002000))
- #define VHA_CR_CLK_CTRL0_LOCM_SHIFT (10U)
- #define VHA_CR_CLK_CTRL0_LOCM_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF3FF))
- #define VHA_CR_CLK_CTRL0_LOCM_OFF (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_CLK_CTRL0_LOCM_ON (IMG_UINT64_C(0x0000000000000400))
- #define VHA_CR_CLK_CTRL0_LOCM_AUTO (IMG_UINT64_C(0x0000000000000800))
- #define VHA_CR_CLK_CTRL0_NOC_SHIFT (8U)
- #define VHA_CR_CLK_CTRL0_NOC_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFCFF))
- #define VHA_CR_CLK_CTRL0_NOC_OFF (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_CLK_CTRL0_NOC_ON (IMG_UINT64_C(0x0000000000000100))
- #define VHA_CR_CLK_CTRL0_NOC_AUTO (IMG_UINT64_C(0x0000000000000200))
- #define VHA_CR_CLK_CTRL0_ARB_SHIFT (4U)
- #define VHA_CR_CLK_CTRL0_ARB_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFCF))
- #define VHA_CR_CLK_CTRL0_ARB_OFF (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_CLK_CTRL0_ARB_ON (IMG_UINT64_C(0x0000000000000010))
- #define VHA_CR_CLK_CTRL0_ARB_AUTO (IMG_UINT64_C(0x0000000000000020))
- #define VHA_CR_CLK_CTRL0_BIF_SHIFT (0U)
- #define VHA_CR_CLK_CTRL0_BIF_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFC))
- #define VHA_CR_CLK_CTRL0_BIF_OFF (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_CLK_CTRL0_BIF_ON (IMG_UINT64_C(0x0000000000000001))
- #define VHA_CR_CLK_CTRL0_BIF_AUTO (IMG_UINT64_C(0x0000000000000002))
- /*
- Clock is gated and the module is inactive */
- #define VHA_CR_CLK_STATUS0_MODE_GATED (0x00000000U)
- /*
- Clock is running */
- #define VHA_CR_CLK_STATUS0_MODE_RUNNING (0x00000001U)
- /*
- Register VHA_CR_CLK_STATUS0
- */
- #define VHA_CR_CLK_STATUS0 (0x20108U)
- #define VHA_CR_CLK_STATUS0_MASKFULL (IMG_UINT64_C(0x00000037FFDC1F04))
- #define VHA_CR_CLK_STATUS0_CNN_CORE_XBAR_SHIFT (37U)
- #define VHA_CR_CLK_STATUS0_CNN_CORE_XBAR_CLRMSK (IMG_UINT64_C(0XFFFFFFDFFFFFFFFF))
- #define VHA_CR_CLK_STATUS0_CNN_CORE_XBAR_GATED (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_CLK_STATUS0_CNN_CORE_XBAR_RUNNING (IMG_UINT64_C(0x0000002000000000))
- #define VHA_CR_CLK_STATUS0_CNN_MMM_SHIFT (36U)
- #define VHA_CR_CLK_STATUS0_CNN_MMM_CLRMSK (IMG_UINT64_C(0XFFFFFFEFFFFFFFFF))
- #define VHA_CR_CLK_STATUS0_CNN_MMM_GATED (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_CLK_STATUS0_CNN_MMM_RUNNING (IMG_UINT64_C(0x0000001000000000))
- #define VHA_CR_CLK_STATUS0_CNN_EWO_SHIFT (34U)
- #define VHA_CR_CLK_STATUS0_CNN_EWO_CLRMSK (IMG_UINT64_C(0XFFFFFFFBFFFFFFFF))
- #define VHA_CR_CLK_STATUS0_CNN_EWO_GATED (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_CLK_STATUS0_CNN_EWO_RUNNING (IMG_UINT64_C(0x0000000400000000))
- #define VHA_CR_CLK_STATUS0_CNN_PACK_SHIFT (33U)
- #define VHA_CR_CLK_STATUS0_CNN_PACK_CLRMSK (IMG_UINT64_C(0XFFFFFFFDFFFFFFFF))
- #define VHA_CR_CLK_STATUS0_CNN_PACK_GATED (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_CLK_STATUS0_CNN_PACK_RUNNING (IMG_UINT64_C(0x0000000200000000))
- #define VHA_CR_CLK_STATUS0_CNN_OIN_SHIFT (32U)
- #define VHA_CR_CLK_STATUS0_CNN_OIN_CLRMSK (IMG_UINT64_C(0XFFFFFFFEFFFFFFFF))
- #define VHA_CR_CLK_STATUS0_CNN_OIN_GATED (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_CLK_STATUS0_CNN_OIN_RUNNING (IMG_UINT64_C(0x0000000100000000))
- #define VHA_CR_CLK_STATUS0_CNN_POOL_SHIFT (31U)
- #define VHA_CR_CLK_STATUS0_CNN_POOL_CLRMSK (IMG_UINT64_C(0XFFFFFFFF7FFFFFFF))
- #define VHA_CR_CLK_STATUS0_CNN_POOL_GATED (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_CLK_STATUS0_CNN_POOL_RUNNING (IMG_UINT64_C(0x0000000080000000))
- #define VHA_CR_CLK_STATUS0_CNN_SB_SHIFT (30U)
- #define VHA_CR_CLK_STATUS0_CNN_SB_CLRMSK (IMG_UINT64_C(0XFFFFFFFFBFFFFFFF))
- #define VHA_CR_CLK_STATUS0_CNN_SB_GATED (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_CLK_STATUS0_CNN_SB_RUNNING (IMG_UINT64_C(0x0000000040000000))
- #define VHA_CR_CLK_STATUS0_CNN_XBAR_SHIFT (29U)
- #define VHA_CR_CLK_STATUS0_CNN_XBAR_CLRMSK (IMG_UINT64_C(0XFFFFFFFFDFFFFFFF))
- #define VHA_CR_CLK_STATUS0_CNN_XBAR_GATED (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_CLK_STATUS0_CNN_XBAR_RUNNING (IMG_UINT64_C(0x0000000020000000))
- #define VHA_CR_CLK_STATUS0_CNN_NORM_SHIFT (28U)
- #define VHA_CR_CLK_STATUS0_CNN_NORM_CLRMSK (IMG_UINT64_C(0XFFFFFFFFEFFFFFFF))
- #define VHA_CR_CLK_STATUS0_CNN_NORM_GATED (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_CLK_STATUS0_CNN_NORM_RUNNING (IMG_UINT64_C(0x0000000010000000))
- #define VHA_CR_CLK_STATUS0_CNN_ACT_SHIFT (27U)
- #define VHA_CR_CLK_STATUS0_CNN_ACT_CLRMSK (IMG_UINT64_C(0XFFFFFFFFF7FFFFFF))
- #define VHA_CR_CLK_STATUS0_CNN_ACT_GATED (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_CLK_STATUS0_CNN_ACT_RUNNING (IMG_UINT64_C(0x0000000008000000))
- #define VHA_CR_CLK_STATUS0_CNN_ACCUM_SHIFT (26U)
- #define VHA_CR_CLK_STATUS0_CNN_ACCUM_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFBFFFFFF))
- #define VHA_CR_CLK_STATUS0_CNN_ACCUM_GATED (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_CLK_STATUS0_CNN_ACCUM_RUNNING (IMG_UINT64_C(0x0000000004000000))
- #define VHA_CR_CLK_STATUS0_CNN_CNV_SHIFT (25U)
- #define VHA_CR_CLK_STATUS0_CNN_CNV_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFDFFFFFF))
- #define VHA_CR_CLK_STATUS0_CNN_CNV_GATED (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_CLK_STATUS0_CNN_CNV_RUNNING (IMG_UINT64_C(0x0000000002000000))
- #define VHA_CR_CLK_STATUS0_CNN_CBUF_SHIFT (24U)
- #define VHA_CR_CLK_STATUS0_CNN_CBUF_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFEFFFFFF))
- #define VHA_CR_CLK_STATUS0_CNN_CBUF_GATED (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_CLK_STATUS0_CNN_CBUF_RUNNING (IMG_UINT64_C(0x0000000001000000))
- #define VHA_CR_CLK_STATUS0_CNN_IBUF_SHIFT (23U)
- #define VHA_CR_CLK_STATUS0_CNN_IBUF_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF7FFFFF))
- #define VHA_CR_CLK_STATUS0_CNN_IBUF_GATED (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_CLK_STATUS0_CNN_IBUF_RUNNING (IMG_UINT64_C(0x0000000000800000))
- #define VHA_CR_CLK_STATUS0_CNN_CMD_SHIFT (22U)
- #define VHA_CR_CLK_STATUS0_CNN_CMD_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFBFFFFF))
- #define VHA_CR_CLK_STATUS0_CNN_CMD_GATED (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_CLK_STATUS0_CNN_CMD_RUNNING (IMG_UINT64_C(0x0000000000400000))
- #define VHA_CR_CLK_STATUS0_CNN_SHIFT (20U)
- #define VHA_CR_CLK_STATUS0_CNN_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFEFFFFF))
- #define VHA_CR_CLK_STATUS0_CNN_GATED (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_CLK_STATUS0_CNN_RUNNING (IMG_UINT64_C(0x0000000000100000))
- #define VHA_CR_CLK_STATUS0_CNN_TRS_A_SHIFT (19U)
- #define VHA_CR_CLK_STATUS0_CNN_TRS_A_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF7FFFF))
- #define VHA_CR_CLK_STATUS0_CNN_TRS_A_GATED (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_CLK_STATUS0_CNN_TRS_A_RUNNING (IMG_UINT64_C(0x0000000000080000))
- #define VHA_CR_CLK_STATUS0_CNN_TRS_B_SHIFT (18U)
- #define VHA_CR_CLK_STATUS0_CNN_TRS_B_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFBFFFF))
- #define VHA_CR_CLK_STATUS0_CNN_TRS_B_GATED (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_CLK_STATUS0_CNN_TRS_B_RUNNING (IMG_UINT64_C(0x0000000000040000))
- #define VHA_CR_CLK_STATUS0_MEMBUS_RESET_SHIFT (12U)
- #define VHA_CR_CLK_STATUS0_MEMBUS_RESET_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFEFFF))
- #define VHA_CR_CLK_STATUS0_MEMBUS_RESET_GATED (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_CLK_STATUS0_MEMBUS_RESET_RUNNING (IMG_UINT64_C(0x0000000000001000))
- #define VHA_CR_CLK_STATUS0_BWM_SHIFT (11U)
- #define VHA_CR_CLK_STATUS0_BWM_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF7FF))
- #define VHA_CR_CLK_STATUS0_BWM_GATED (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_CLK_STATUS0_BWM_RUNNING (IMG_UINT64_C(0x0000000000000800))
- #define VHA_CR_CLK_STATUS0_LOCM_SHIFT (10U)
- #define VHA_CR_CLK_STATUS0_LOCM_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFBFF))
- #define VHA_CR_CLK_STATUS0_LOCM_GATED (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_CLK_STATUS0_LOCM_RUNNING (IMG_UINT64_C(0x0000000000000400))
- #define VHA_CR_CLK_STATUS0_NOC_SHIFT (9U)
- #define VHA_CR_CLK_STATUS0_NOC_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFDFF))
- #define VHA_CR_CLK_STATUS0_NOC_GATED (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_CLK_STATUS0_NOC_RUNNING (IMG_UINT64_C(0x0000000000000200))
- #define VHA_CR_CLK_STATUS0_ARB_SHIFT (8U)
- #define VHA_CR_CLK_STATUS0_ARB_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFEFF))
- #define VHA_CR_CLK_STATUS0_ARB_GATED (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_CLK_STATUS0_ARB_RUNNING (IMG_UINT64_C(0x0000000000000100))
- #define VHA_CR_CLK_STATUS0_BIF_SHIFT (2U)
- #define VHA_CR_CLK_STATUS0_BIF_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFB))
- #define VHA_CR_CLK_STATUS0_BIF_GATED (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_CLK_STATUS0_BIF_RUNNING (IMG_UINT64_C(0x0000000000000004))
- /*
- Register VHA_CR_CORE_SOFT_RESET
- */
- #define VHA_CR_CORE_SOFT_RESET (0x20110U)
- #define VHA_CR_CORE_SOFT_RESET_MASKFULL (IMG_UINT64_C(0x0000000000000001))
- #define VHA_CR_CORE_SOFT_RESET_CORE_RESET_SHIFT (0U)
- #define VHA_CR_CORE_SOFT_RESET_CORE_RESET_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_CORE_SOFT_RESET_CORE_RESET_EN (0X00000001U)
- /*
- Register VHA_CR_MEMBUS_RESET_CTRL
- */
- #define VHA_CR_MEMBUS_RESET_CTRL (0x20118U)
- #define VHA_CR_MEMBUS_RESET_CTRL_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_MEMBUS_RESET_CTRL_SOFT_RESET_CYCLES_SHIFT (0U)
- #define VHA_CR_MEMBUS_RESET_CTRL_SOFT_RESET_CYCLES_CLRMSK (00000000U)
- #define VHA_CR_CORE_EVENT_TYPE_LOGIC_ERROR_SHIFT (30U)
- #define VHA_CR_CORE_EVENT_TYPE_LOGIC_ERROR_CLRMSK (0XBFFFFFFFU)
- #define VHA_CR_CORE_EVENT_TYPE_LOGIC_ERROR_EN (0X40000000U)
- #define VHA_CR_CORE_EVENT_TYPE_RAM_CORRECTION_SHIFT (29U)
- #define VHA_CR_CORE_EVENT_TYPE_RAM_CORRECTION_CLRMSK (0XDFFFFFFFU)
- #define VHA_CR_CORE_EVENT_TYPE_RAM_CORRECTION_EN (0X20000000U)
- #define VHA_CR_CORE_EVENT_TYPE_RAM_DETECTION_SHIFT (28U)
- #define VHA_CR_CORE_EVENT_TYPE_RAM_DETECTION_CLRMSK (0XEFFFFFFFU)
- #define VHA_CR_CORE_EVENT_TYPE_RAM_DETECTION_EN (0X10000000U)
- #define VHA_CR_CORE_EVENT_TYPE_LOCM_SCRUB_DONE_SHIFT (16U)
- #define VHA_CR_CORE_EVENT_TYPE_LOCM_SCRUB_DONE_CLRMSK (0XFFFEFFFFU)
- #define VHA_CR_CORE_EVENT_TYPE_LOCM_SCRUB_DONE_EN (0X00010000U)
- #define VHA_CR_CORE_EVENT_TYPE_DMR_COMPLETE_SHIFT (11U)
- #define VHA_CR_CORE_EVENT_TYPE_DMR_COMPLETE_CLRMSK (0XFFFFF7FFU)
- #define VHA_CR_CORE_EVENT_TYPE_DMR_COMPLETE_EN (0X00000800U)
- #define VHA_CR_CORE_EVENT_TYPE_CORE_SYNC_ERROR_SHIFT (10U)
- #define VHA_CR_CORE_EVENT_TYPE_CORE_SYNC_ERROR_CLRMSK (0XFFFFFBFFU)
- #define VHA_CR_CORE_EVENT_TYPE_CORE_SYNC_ERROR_EN (0X00000400U)
- #define VHA_CR_CORE_EVENT_TYPE_CORE_WDT_SHIFT (9U)
- #define VHA_CR_CORE_EVENT_TYPE_CORE_WDT_CLRMSK (0XFFFFFDFFU)
- #define VHA_CR_CORE_EVENT_TYPE_CORE_WDT_EN (0X00000200U)
- #define VHA_CR_CORE_EVENT_TYPE_CORE_MEM_WDT_SHIFT (8U)
- #define VHA_CR_CORE_EVENT_TYPE_CORE_MEM_WDT_CLRMSK (0XFFFFFEFFU)
- #define VHA_CR_CORE_EVENT_TYPE_CORE_MEM_WDT_EN (0X00000100U)
- #define VHA_CR_CORE_EVENT_TYPE_RAM_INIT_DONE_SHIFT (3U)
- #define VHA_CR_CORE_EVENT_TYPE_RAM_INIT_DONE_CLRMSK (0XFFFFFFF7U)
- #define VHA_CR_CORE_EVENT_TYPE_RAM_INIT_DONE_EN (0X00000008U)
- #define VHA_CR_CORE_EVENT_TYPE_MEMBUS_RESET_DONE_SHIFT (2U)
- #define VHA_CR_CORE_EVENT_TYPE_MEMBUS_RESET_DONE_CLRMSK (0XFFFFFFFBU)
- #define VHA_CR_CORE_EVENT_TYPE_MEMBUS_RESET_DONE_EN (0X00000004U)
- #define VHA_CR_CORE_EVENT_TYPE_CNN_ERROR_SHIFT (1U)
- #define VHA_CR_CORE_EVENT_TYPE_CNN_ERROR_CLRMSK (0XFFFFFFFDU)
- #define VHA_CR_CORE_EVENT_TYPE_CNN_ERROR_EN (0X00000002U)
- #define VHA_CR_CORE_EVENT_TYPE_CNN_COMPLETE_SHIFT (0U)
- #define VHA_CR_CORE_EVENT_TYPE_CNN_COMPLETE_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_CORE_EVENT_TYPE_CNN_COMPLETE_EN (0X00000001U)
- #define VHA_CR_CORE_EVENT_STATUS_TYPE_PARITY_SHIFT (31U)
- #define VHA_CR_CORE_EVENT_STATUS_TYPE_PARITY_CLRMSK (0X7FFFFFFFU)
- #define VHA_CR_CORE_EVENT_STATUS_TYPE_PARITY_EN (0X80000000U)
- #define VHA_CR_CORE_EVENT_STATUS_TYPE_LOGIC_ERROR_SHIFT (30U)
- #define VHA_CR_CORE_EVENT_STATUS_TYPE_LOGIC_ERROR_CLRMSK (0XBFFFFFFFU)
- #define VHA_CR_CORE_EVENT_STATUS_TYPE_LOGIC_ERROR_EN (0X40000000U)
- #define VHA_CR_CORE_EVENT_STATUS_TYPE_RAM_CORRECTION_SHIFT (29U)
- #define VHA_CR_CORE_EVENT_STATUS_TYPE_RAM_CORRECTION_CLRMSK (0XDFFFFFFFU)
- #define VHA_CR_CORE_EVENT_STATUS_TYPE_RAM_CORRECTION_EN (0X20000000U)
- #define VHA_CR_CORE_EVENT_STATUS_TYPE_RAM_DETECTION_SHIFT (28U)
- #define VHA_CR_CORE_EVENT_STATUS_TYPE_RAM_DETECTION_CLRMSK (0XEFFFFFFFU)
- #define VHA_CR_CORE_EVENT_STATUS_TYPE_RAM_DETECTION_EN (0X10000000U)
- #define VHA_CR_CORE_EVENT_STATUS_TYPE_LOCM_SCRUB_DONE_SHIFT (16U)
- #define VHA_CR_CORE_EVENT_STATUS_TYPE_LOCM_SCRUB_DONE_CLRMSK (0XFFFEFFFFU)
- #define VHA_CR_CORE_EVENT_STATUS_TYPE_LOCM_SCRUB_DONE_EN (0X00010000U)
- #define VHA_CR_CORE_EVENT_STATUS_TYPE_DMR_COMPLETE_SHIFT (11U)
- #define VHA_CR_CORE_EVENT_STATUS_TYPE_DMR_COMPLETE_CLRMSK (0XFFFFF7FFU)
- #define VHA_CR_CORE_EVENT_STATUS_TYPE_DMR_COMPLETE_EN (0X00000800U)
- #define VHA_CR_CORE_EVENT_STATUS_TYPE_CORE_SYNC_ERROR_SHIFT (10U)
- #define VHA_CR_CORE_EVENT_STATUS_TYPE_CORE_SYNC_ERROR_CLRMSK (0XFFFFFBFFU)
- #define VHA_CR_CORE_EVENT_STATUS_TYPE_CORE_SYNC_ERROR_EN (0X00000400U)
- #define VHA_CR_CORE_EVENT_STATUS_TYPE_CORE_WDT_SHIFT (9U)
- #define VHA_CR_CORE_EVENT_STATUS_TYPE_CORE_WDT_CLRMSK (0XFFFFFDFFU)
- #define VHA_CR_CORE_EVENT_STATUS_TYPE_CORE_WDT_EN (0X00000200U)
- #define VHA_CR_CORE_EVENT_STATUS_TYPE_CORE_MEM_WDT_SHIFT (8U)
- #define VHA_CR_CORE_EVENT_STATUS_TYPE_CORE_MEM_WDT_CLRMSK (0XFFFFFEFFU)
- #define VHA_CR_CORE_EVENT_STATUS_TYPE_CORE_MEM_WDT_EN (0X00000100U)
- #define VHA_CR_CORE_EVENT_STATUS_TYPE_RAM_INIT_DONE_SHIFT (3U)
- #define VHA_CR_CORE_EVENT_STATUS_TYPE_RAM_INIT_DONE_CLRMSK (0XFFFFFFF7U)
- #define VHA_CR_CORE_EVENT_STATUS_TYPE_RAM_INIT_DONE_EN (0X00000008U)
- #define VHA_CR_CORE_EVENT_STATUS_TYPE_MEMBUS_RESET_DONE_SHIFT (2U)
- #define VHA_CR_CORE_EVENT_STATUS_TYPE_MEMBUS_RESET_DONE_CLRMSK (0XFFFFFFFBU)
- #define VHA_CR_CORE_EVENT_STATUS_TYPE_MEMBUS_RESET_DONE_EN (0X00000004U)
- #define VHA_CR_CORE_EVENT_STATUS_TYPE_CNN_ERROR_SHIFT (1U)
- #define VHA_CR_CORE_EVENT_STATUS_TYPE_CNN_ERROR_CLRMSK (0XFFFFFFFDU)
- #define VHA_CR_CORE_EVENT_STATUS_TYPE_CNN_ERROR_EN (0X00000002U)
- #define VHA_CR_CORE_EVENT_STATUS_TYPE_CNN_COMPLETE_SHIFT (0U)
- #define VHA_CR_CORE_EVENT_STATUS_TYPE_CNN_COMPLETE_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_CORE_EVENT_STATUS_TYPE_CNN_COMPLETE_EN (0X00000001U)
- /*
- Register VHA_CR_CORE_EVENT_HOST_ENABLE
- */
- #define VHA_CR_CORE_EVENT_HOST_ENABLE (0x20120U)
- #define VHA_CR_CORE_EVENT_HOST_ENABLE_MASKFULL (IMG_UINT64_C(0x0000000070010F0F))
- #define VHA_CR_CORE_EVENT_HOST_ENABLE_LOGIC_ERROR_SHIFT (30U)
- #define VHA_CR_CORE_EVENT_HOST_ENABLE_LOGIC_ERROR_CLRMSK (0XBFFFFFFFU)
- #define VHA_CR_CORE_EVENT_HOST_ENABLE_LOGIC_ERROR_EN (0X40000000U)
- #define VHA_CR_CORE_EVENT_HOST_ENABLE_RAM_CORRECTION_SHIFT (29U)
- #define VHA_CR_CORE_EVENT_HOST_ENABLE_RAM_CORRECTION_CLRMSK (0XDFFFFFFFU)
- #define VHA_CR_CORE_EVENT_HOST_ENABLE_RAM_CORRECTION_EN (0X20000000U)
- #define VHA_CR_CORE_EVENT_HOST_ENABLE_RAM_DETECTION_SHIFT (28U)
- #define VHA_CR_CORE_EVENT_HOST_ENABLE_RAM_DETECTION_CLRMSK (0XEFFFFFFFU)
- #define VHA_CR_CORE_EVENT_HOST_ENABLE_RAM_DETECTION_EN (0X10000000U)
- #define VHA_CR_CORE_EVENT_HOST_ENABLE_LOCM_SCRUB_DONE_SHIFT (16U)
- #define VHA_CR_CORE_EVENT_HOST_ENABLE_LOCM_SCRUB_DONE_CLRMSK (0XFFFEFFFFU)
- #define VHA_CR_CORE_EVENT_HOST_ENABLE_LOCM_SCRUB_DONE_EN (0X00010000U)
- #define VHA_CR_CORE_EVENT_HOST_ENABLE_DMR_COMPLETE_SHIFT (11U)
- #define VHA_CR_CORE_EVENT_HOST_ENABLE_DMR_COMPLETE_CLRMSK (0XFFFFF7FFU)
- #define VHA_CR_CORE_EVENT_HOST_ENABLE_DMR_COMPLETE_EN (0X00000800U)
- #define VHA_CR_CORE_EVENT_HOST_ENABLE_CORE_SYNC_ERROR_SHIFT (10U)
- #define VHA_CR_CORE_EVENT_HOST_ENABLE_CORE_SYNC_ERROR_CLRMSK (0XFFFFFBFFU)
- #define VHA_CR_CORE_EVENT_HOST_ENABLE_CORE_SYNC_ERROR_EN (0X00000400U)
- #define VHA_CR_CORE_EVENT_HOST_ENABLE_CORE_WDT_SHIFT (9U)
- #define VHA_CR_CORE_EVENT_HOST_ENABLE_CORE_WDT_CLRMSK (0XFFFFFDFFU)
- #define VHA_CR_CORE_EVENT_HOST_ENABLE_CORE_WDT_EN (0X00000200U)
- #define VHA_CR_CORE_EVENT_HOST_ENABLE_CORE_MEM_WDT_SHIFT (8U)
- #define VHA_CR_CORE_EVENT_HOST_ENABLE_CORE_MEM_WDT_CLRMSK (0XFFFFFEFFU)
- #define VHA_CR_CORE_EVENT_HOST_ENABLE_CORE_MEM_WDT_EN (0X00000100U)
- #define VHA_CR_CORE_EVENT_HOST_ENABLE_RAM_INIT_DONE_SHIFT (3U)
- #define VHA_CR_CORE_EVENT_HOST_ENABLE_RAM_INIT_DONE_CLRMSK (0XFFFFFFF7U)
- #define VHA_CR_CORE_EVENT_HOST_ENABLE_RAM_INIT_DONE_EN (0X00000008U)
- #define VHA_CR_CORE_EVENT_HOST_ENABLE_MEMBUS_RESET_DONE_SHIFT (2U)
- #define VHA_CR_CORE_EVENT_HOST_ENABLE_MEMBUS_RESET_DONE_CLRMSK (0XFFFFFFFBU)
- #define VHA_CR_CORE_EVENT_HOST_ENABLE_MEMBUS_RESET_DONE_EN (0X00000004U)
- #define VHA_CR_CORE_EVENT_HOST_ENABLE_CNN_ERROR_SHIFT (1U)
- #define VHA_CR_CORE_EVENT_HOST_ENABLE_CNN_ERROR_CLRMSK (0XFFFFFFFDU)
- #define VHA_CR_CORE_EVENT_HOST_ENABLE_CNN_ERROR_EN (0X00000002U)
- #define VHA_CR_CORE_EVENT_HOST_ENABLE_CNN_COMPLETE_SHIFT (0U)
- #define VHA_CR_CORE_EVENT_HOST_ENABLE_CNN_COMPLETE_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_CORE_EVENT_HOST_ENABLE_CNN_COMPLETE_EN (0X00000001U)
- /*
- Register VHA_CR_CORE_EVENT_HOST_STATUS
- */
- #define VHA_CR_CORE_EVENT_HOST_STATUS (0x20128U)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_MASKFULL (IMG_UINT64_C(0x00000000F0010F0F))
- #define VHA_CR_CORE_EVENT_HOST_STATUS_PARITY_SHIFT (31U)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_PARITY_CLRMSK (0X7FFFFFFFU)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_PARITY_EN (0X80000000U)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_LOGIC_ERROR_SHIFT (30U)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_LOGIC_ERROR_CLRMSK (0XBFFFFFFFU)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_LOGIC_ERROR_EN (0X40000000U)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_RAM_CORRECTION_SHIFT (29U)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_RAM_CORRECTION_CLRMSK (0XDFFFFFFFU)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_RAM_CORRECTION_EN (0X20000000U)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_RAM_DETECTION_SHIFT (28U)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_RAM_DETECTION_CLRMSK (0XEFFFFFFFU)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_RAM_DETECTION_EN (0X10000000U)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_LOCM_SCRUB_DONE_SHIFT (16U)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_LOCM_SCRUB_DONE_CLRMSK (0XFFFEFFFFU)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_LOCM_SCRUB_DONE_EN (0X00010000U)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_DMR_COMPLETE_SHIFT (11U)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_DMR_COMPLETE_CLRMSK (0XFFFFF7FFU)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_DMR_COMPLETE_EN (0X00000800U)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_CORE_SYNC_ERROR_SHIFT (10U)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_CORE_SYNC_ERROR_CLRMSK (0XFFFFFBFFU)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_CORE_SYNC_ERROR_EN (0X00000400U)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_CORE_WDT_SHIFT (9U)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_CORE_WDT_CLRMSK (0XFFFFFDFFU)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_CORE_WDT_EN (0X00000200U)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_CORE_MEM_WDT_SHIFT (8U)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_CORE_MEM_WDT_CLRMSK (0XFFFFFEFFU)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_CORE_MEM_WDT_EN (0X00000100U)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_RAM_INIT_DONE_SHIFT (3U)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_RAM_INIT_DONE_CLRMSK (0XFFFFFFF7U)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_RAM_INIT_DONE_EN (0X00000008U)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_MEMBUS_RESET_DONE_SHIFT (2U)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_MEMBUS_RESET_DONE_CLRMSK (0XFFFFFFFBU)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_MEMBUS_RESET_DONE_EN (0X00000004U)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_CNN_ERROR_SHIFT (1U)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_CNN_ERROR_CLRMSK (0XFFFFFFFDU)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_CNN_ERROR_EN (0X00000002U)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_CNN_COMPLETE_SHIFT (0U)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_CNN_COMPLETE_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_CNN_COMPLETE_EN (0X00000001U)
- /*
- Register VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE
- */
- #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE (0x20178U)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_MASKFULL (IMG_UINT64_C(0x0000000070010F0F))
- #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_LOGIC_ERROR_SHIFT (30U)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_LOGIC_ERROR_CLRMSK (0XBFFFFFFFU)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_LOGIC_ERROR_EN (0X40000000U)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_RAM_CORRECTION_SHIFT (29U)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_RAM_CORRECTION_CLRMSK (0XDFFFFFFFU)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_RAM_CORRECTION_EN (0X20000000U)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_RAM_DETECTION_SHIFT (28U)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_RAM_DETECTION_CLRMSK (0XEFFFFFFFU)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_RAM_DETECTION_EN (0X10000000U)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_LOCM_SCRUB_DONE_SHIFT (16U)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_LOCM_SCRUB_DONE_CLRMSK (0XFFFEFFFFU)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_LOCM_SCRUB_DONE_EN (0X00010000U)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_DMR_COMPLETE_SHIFT (11U)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_DMR_COMPLETE_CLRMSK (0XFFFFF7FFU)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_DMR_COMPLETE_EN (0X00000800U)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_CORE_SYNC_ERROR_SHIFT (10U)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_CORE_SYNC_ERROR_CLRMSK (0XFFFFFBFFU)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_CORE_SYNC_ERROR_EN (0X00000400U)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_CORE_WDT_SHIFT (9U)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_CORE_WDT_CLRMSK (0XFFFFFDFFU)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_CORE_WDT_EN (0X00000200U)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_CORE_MEM_WDT_SHIFT (8U)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_CORE_MEM_WDT_CLRMSK (0XFFFFFEFFU)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_CORE_MEM_WDT_EN (0X00000100U)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_RAM_INIT_DONE_SHIFT (3U)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_RAM_INIT_DONE_CLRMSK (0XFFFFFFF7U)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_RAM_INIT_DONE_EN (0X00000008U)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_MEMBUS_RESET_DONE_SHIFT (2U)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_MEMBUS_RESET_DONE_CLRMSK (0XFFFFFFFBU)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_MEMBUS_RESET_DONE_EN (0X00000004U)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_CNN_ERROR_SHIFT (1U)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_CNN_ERROR_CLRMSK (0XFFFFFFFDU)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_CNN_ERROR_EN (0X00000002U)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_CNN_COMPLETE_SHIFT (0U)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_CNN_COMPLETE_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_CNN_COMPLETE_EN (0X00000001U)
- /*
- Register VHA_CR_CORE_EVENT_HOST_CLEAR
- */
- #define VHA_CR_CORE_EVENT_HOST_CLEAR (0x20130U)
- #define VHA_CR_CORE_EVENT_HOST_CLEAR_MASKFULL (IMG_UINT64_C(0x0000000070010F0F))
- #define VHA_CR_CORE_EVENT_HOST_CLEAR_LOGIC_ERROR_SHIFT (30U)
- #define VHA_CR_CORE_EVENT_HOST_CLEAR_LOGIC_ERROR_CLRMSK (0XBFFFFFFFU)
- #define VHA_CR_CORE_EVENT_HOST_CLEAR_LOGIC_ERROR_EN (0X40000000U)
- #define VHA_CR_CORE_EVENT_HOST_CLEAR_RAM_CORRECTION_SHIFT (29U)
- #define VHA_CR_CORE_EVENT_HOST_CLEAR_RAM_CORRECTION_CLRMSK (0XDFFFFFFFU)
- #define VHA_CR_CORE_EVENT_HOST_CLEAR_RAM_CORRECTION_EN (0X20000000U)
- #define VHA_CR_CORE_EVENT_HOST_CLEAR_RAM_DETECTION_SHIFT (28U)
- #define VHA_CR_CORE_EVENT_HOST_CLEAR_RAM_DETECTION_CLRMSK (0XEFFFFFFFU)
- #define VHA_CR_CORE_EVENT_HOST_CLEAR_RAM_DETECTION_EN (0X10000000U)
- #define VHA_CR_CORE_EVENT_HOST_CLEAR_LOCM_SCRUB_DONE_SHIFT (16U)
- #define VHA_CR_CORE_EVENT_HOST_CLEAR_LOCM_SCRUB_DONE_CLRMSK (0XFFFEFFFFU)
- #define VHA_CR_CORE_EVENT_HOST_CLEAR_LOCM_SCRUB_DONE_EN (0X00010000U)
- #define VHA_CR_CORE_EVENT_HOST_CLEAR_DMR_COMPLETE_SHIFT (11U)
- #define VHA_CR_CORE_EVENT_HOST_CLEAR_DMR_COMPLETE_CLRMSK (0XFFFFF7FFU)
- #define VHA_CR_CORE_EVENT_HOST_CLEAR_DMR_COMPLETE_EN (0X00000800U)
- #define VHA_CR_CORE_EVENT_HOST_CLEAR_CORE_SYNC_ERROR_SHIFT (10U)
- #define VHA_CR_CORE_EVENT_HOST_CLEAR_CORE_SYNC_ERROR_CLRMSK (0XFFFFFBFFU)
- #define VHA_CR_CORE_EVENT_HOST_CLEAR_CORE_SYNC_ERROR_EN (0X00000400U)
- #define VHA_CR_CORE_EVENT_HOST_CLEAR_CORE_WDT_SHIFT (9U)
- #define VHA_CR_CORE_EVENT_HOST_CLEAR_CORE_WDT_CLRMSK (0XFFFFFDFFU)
- #define VHA_CR_CORE_EVENT_HOST_CLEAR_CORE_WDT_EN (0X00000200U)
- #define VHA_CR_CORE_EVENT_HOST_CLEAR_CORE_MEM_WDT_SHIFT (8U)
- #define VHA_CR_CORE_EVENT_HOST_CLEAR_CORE_MEM_WDT_CLRMSK (0XFFFFFEFFU)
- #define VHA_CR_CORE_EVENT_HOST_CLEAR_CORE_MEM_WDT_EN (0X00000100U)
- #define VHA_CR_CORE_EVENT_HOST_CLEAR_RAM_INIT_DONE_SHIFT (3U)
- #define VHA_CR_CORE_EVENT_HOST_CLEAR_RAM_INIT_DONE_CLRMSK (0XFFFFFFF7U)
- #define VHA_CR_CORE_EVENT_HOST_CLEAR_RAM_INIT_DONE_EN (0X00000008U)
- #define VHA_CR_CORE_EVENT_HOST_CLEAR_MEMBUS_RESET_DONE_SHIFT (2U)
- #define VHA_CR_CORE_EVENT_HOST_CLEAR_MEMBUS_RESET_DONE_CLRMSK (0XFFFFFFFBU)
- #define VHA_CR_CORE_EVENT_HOST_CLEAR_MEMBUS_RESET_DONE_EN (0X00000004U)
- #define VHA_CR_CORE_EVENT_HOST_CLEAR_CNN_ERROR_SHIFT (1U)
- #define VHA_CR_CORE_EVENT_HOST_CLEAR_CNN_ERROR_CLRMSK (0XFFFFFFFDU)
- #define VHA_CR_CORE_EVENT_HOST_CLEAR_CNN_ERROR_EN (0X00000002U)
- #define VHA_CR_CORE_EVENT_HOST_CLEAR_CNN_COMPLETE_SHIFT (0U)
- #define VHA_CR_CORE_EVENT_HOST_CLEAR_CNN_COMPLETE_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_CORE_EVENT_HOST_CLEAR_CNN_COMPLETE_EN (0X00000001U)
- /*
- Register VHA_CR_CORE_EVENT_WM_ENABLE
- */
- #define VHA_CR_CORE_EVENT_WM_ENABLE (0x20140U)
- #define VHA_CR_CORE_EVENT_WM_ENABLE_MASKFULL (IMG_UINT64_C(0x0000000070010F0F))
- #define VHA_CR_CORE_EVENT_WM_ENABLE_LOGIC_ERROR_SHIFT (30U)
- #define VHA_CR_CORE_EVENT_WM_ENABLE_LOGIC_ERROR_CLRMSK (0XBFFFFFFFU)
- #define VHA_CR_CORE_EVENT_WM_ENABLE_LOGIC_ERROR_EN (0X40000000U)
- #define VHA_CR_CORE_EVENT_WM_ENABLE_RAM_CORRECTION_SHIFT (29U)
- #define VHA_CR_CORE_EVENT_WM_ENABLE_RAM_CORRECTION_CLRMSK (0XDFFFFFFFU)
- #define VHA_CR_CORE_EVENT_WM_ENABLE_RAM_CORRECTION_EN (0X20000000U)
- #define VHA_CR_CORE_EVENT_WM_ENABLE_RAM_DETECTION_SHIFT (28U)
- #define VHA_CR_CORE_EVENT_WM_ENABLE_RAM_DETECTION_CLRMSK (0XEFFFFFFFU)
- #define VHA_CR_CORE_EVENT_WM_ENABLE_RAM_DETECTION_EN (0X10000000U)
- #define VHA_CR_CORE_EVENT_WM_ENABLE_LOCM_SCRUB_DONE_SHIFT (16U)
- #define VHA_CR_CORE_EVENT_WM_ENABLE_LOCM_SCRUB_DONE_CLRMSK (0XFFFEFFFFU)
- #define VHA_CR_CORE_EVENT_WM_ENABLE_LOCM_SCRUB_DONE_EN (0X00010000U)
- #define VHA_CR_CORE_EVENT_WM_ENABLE_DMR_COMPLETE_SHIFT (11U)
- #define VHA_CR_CORE_EVENT_WM_ENABLE_DMR_COMPLETE_CLRMSK (0XFFFFF7FFU)
- #define VHA_CR_CORE_EVENT_WM_ENABLE_DMR_COMPLETE_EN (0X00000800U)
- #define VHA_CR_CORE_EVENT_WM_ENABLE_CORE_SYNC_ERROR_SHIFT (10U)
- #define VHA_CR_CORE_EVENT_WM_ENABLE_CORE_SYNC_ERROR_CLRMSK (0XFFFFFBFFU)
- #define VHA_CR_CORE_EVENT_WM_ENABLE_CORE_SYNC_ERROR_EN (0X00000400U)
- #define VHA_CR_CORE_EVENT_WM_ENABLE_CORE_WDT_SHIFT (9U)
- #define VHA_CR_CORE_EVENT_WM_ENABLE_CORE_WDT_CLRMSK (0XFFFFFDFFU)
- #define VHA_CR_CORE_EVENT_WM_ENABLE_CORE_WDT_EN (0X00000200U)
- #define VHA_CR_CORE_EVENT_WM_ENABLE_CORE_MEM_WDT_SHIFT (8U)
- #define VHA_CR_CORE_EVENT_WM_ENABLE_CORE_MEM_WDT_CLRMSK (0XFFFFFEFFU)
- #define VHA_CR_CORE_EVENT_WM_ENABLE_CORE_MEM_WDT_EN (0X00000100U)
- #define VHA_CR_CORE_EVENT_WM_ENABLE_RAM_INIT_DONE_SHIFT (3U)
- #define VHA_CR_CORE_EVENT_WM_ENABLE_RAM_INIT_DONE_CLRMSK (0XFFFFFFF7U)
- #define VHA_CR_CORE_EVENT_WM_ENABLE_RAM_INIT_DONE_EN (0X00000008U)
- #define VHA_CR_CORE_EVENT_WM_ENABLE_MEMBUS_RESET_DONE_SHIFT (2U)
- #define VHA_CR_CORE_EVENT_WM_ENABLE_MEMBUS_RESET_DONE_CLRMSK (0XFFFFFFFBU)
- #define VHA_CR_CORE_EVENT_WM_ENABLE_MEMBUS_RESET_DONE_EN (0X00000004U)
- #define VHA_CR_CORE_EVENT_WM_ENABLE_CNN_ERROR_SHIFT (1U)
- #define VHA_CR_CORE_EVENT_WM_ENABLE_CNN_ERROR_CLRMSK (0XFFFFFFFDU)
- #define VHA_CR_CORE_EVENT_WM_ENABLE_CNN_ERROR_EN (0X00000002U)
- #define VHA_CR_CORE_EVENT_WM_ENABLE_CNN_COMPLETE_SHIFT (0U)
- #define VHA_CR_CORE_EVENT_WM_ENABLE_CNN_COMPLETE_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_CORE_EVENT_WM_ENABLE_CNN_COMPLETE_EN (0X00000001U)
- /*
- Register VHA_CR_CORE_EVENT_WM_STATUS
- */
- #define VHA_CR_CORE_EVENT_WM_STATUS (0x20148U)
- #define VHA_CR_CORE_EVENT_WM_STATUS_MASKFULL (IMG_UINT64_C(0x00000000F0010F0F))
- #define VHA_CR_CORE_EVENT_WM_STATUS_PARITY_SHIFT (31U)
- #define VHA_CR_CORE_EVENT_WM_STATUS_PARITY_CLRMSK (0X7FFFFFFFU)
- #define VHA_CR_CORE_EVENT_WM_STATUS_PARITY_EN (0X80000000U)
- #define VHA_CR_CORE_EVENT_WM_STATUS_LOGIC_ERROR_SHIFT (30U)
- #define VHA_CR_CORE_EVENT_WM_STATUS_LOGIC_ERROR_CLRMSK (0XBFFFFFFFU)
- #define VHA_CR_CORE_EVENT_WM_STATUS_LOGIC_ERROR_EN (0X40000000U)
- #define VHA_CR_CORE_EVENT_WM_STATUS_RAM_CORRECTION_SHIFT (29U)
- #define VHA_CR_CORE_EVENT_WM_STATUS_RAM_CORRECTION_CLRMSK (0XDFFFFFFFU)
- #define VHA_CR_CORE_EVENT_WM_STATUS_RAM_CORRECTION_EN (0X20000000U)
- #define VHA_CR_CORE_EVENT_WM_STATUS_RAM_DETECTION_SHIFT (28U)
- #define VHA_CR_CORE_EVENT_WM_STATUS_RAM_DETECTION_CLRMSK (0XEFFFFFFFU)
- #define VHA_CR_CORE_EVENT_WM_STATUS_RAM_DETECTION_EN (0X10000000U)
- #define VHA_CR_CORE_EVENT_WM_STATUS_LOCM_SCRUB_DONE_SHIFT (16U)
- #define VHA_CR_CORE_EVENT_WM_STATUS_LOCM_SCRUB_DONE_CLRMSK (0XFFFEFFFFU)
- #define VHA_CR_CORE_EVENT_WM_STATUS_LOCM_SCRUB_DONE_EN (0X00010000U)
- #define VHA_CR_CORE_EVENT_WM_STATUS_DMR_COMPLETE_SHIFT (11U)
- #define VHA_CR_CORE_EVENT_WM_STATUS_DMR_COMPLETE_CLRMSK (0XFFFFF7FFU)
- #define VHA_CR_CORE_EVENT_WM_STATUS_DMR_COMPLETE_EN (0X00000800U)
- #define VHA_CR_CORE_EVENT_WM_STATUS_CORE_SYNC_ERROR_SHIFT (10U)
- #define VHA_CR_CORE_EVENT_WM_STATUS_CORE_SYNC_ERROR_CLRMSK (0XFFFFFBFFU)
- #define VHA_CR_CORE_EVENT_WM_STATUS_CORE_SYNC_ERROR_EN (0X00000400U)
- #define VHA_CR_CORE_EVENT_WM_STATUS_CORE_WDT_SHIFT (9U)
- #define VHA_CR_CORE_EVENT_WM_STATUS_CORE_WDT_CLRMSK (0XFFFFFDFFU)
- #define VHA_CR_CORE_EVENT_WM_STATUS_CORE_WDT_EN (0X00000200U)
- #define VHA_CR_CORE_EVENT_WM_STATUS_CORE_MEM_WDT_SHIFT (8U)
- #define VHA_CR_CORE_EVENT_WM_STATUS_CORE_MEM_WDT_CLRMSK (0XFFFFFEFFU)
- #define VHA_CR_CORE_EVENT_WM_STATUS_CORE_MEM_WDT_EN (0X00000100U)
- #define VHA_CR_CORE_EVENT_WM_STATUS_RAM_INIT_DONE_SHIFT (3U)
- #define VHA_CR_CORE_EVENT_WM_STATUS_RAM_INIT_DONE_CLRMSK (0XFFFFFFF7U)
- #define VHA_CR_CORE_EVENT_WM_STATUS_RAM_INIT_DONE_EN (0X00000008U)
- #define VHA_CR_CORE_EVENT_WM_STATUS_MEMBUS_RESET_DONE_SHIFT (2U)
- #define VHA_CR_CORE_EVENT_WM_STATUS_MEMBUS_RESET_DONE_CLRMSK (0XFFFFFFFBU)
- #define VHA_CR_CORE_EVENT_WM_STATUS_MEMBUS_RESET_DONE_EN (0X00000004U)
- #define VHA_CR_CORE_EVENT_WM_STATUS_CNN_ERROR_SHIFT (1U)
- #define VHA_CR_CORE_EVENT_WM_STATUS_CNN_ERROR_CLRMSK (0XFFFFFFFDU)
- #define VHA_CR_CORE_EVENT_WM_STATUS_CNN_ERROR_EN (0X00000002U)
- #define VHA_CR_CORE_EVENT_WM_STATUS_CNN_COMPLETE_SHIFT (0U)
- #define VHA_CR_CORE_EVENT_WM_STATUS_CNN_COMPLETE_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_CORE_EVENT_WM_STATUS_CNN_COMPLETE_EN (0X00000001U)
- /*
- Register VHA_CR_CORE_EVENT_WM_STATUS_DISABLE
- */
- #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE (0x20180U)
- #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_MASKFULL (IMG_UINT64_C(0x0000000070010F0F))
- #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_LOGIC_ERROR_SHIFT (30U)
- #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_LOGIC_ERROR_CLRMSK (0XBFFFFFFFU)
- #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_LOGIC_ERROR_EN (0X40000000U)
- #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_RAM_CORRECTION_SHIFT (29U)
- #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_RAM_CORRECTION_CLRMSK (0XDFFFFFFFU)
- #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_RAM_CORRECTION_EN (0X20000000U)
- #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_RAM_DETECTION_SHIFT (28U)
- #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_RAM_DETECTION_CLRMSK (0XEFFFFFFFU)
- #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_RAM_DETECTION_EN (0X10000000U)
- #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_LOCM_SCRUB_DONE_SHIFT (16U)
- #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_LOCM_SCRUB_DONE_CLRMSK (0XFFFEFFFFU)
- #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_LOCM_SCRUB_DONE_EN (0X00010000U)
- #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_DMR_COMPLETE_SHIFT (11U)
- #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_DMR_COMPLETE_CLRMSK (0XFFFFF7FFU)
- #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_DMR_COMPLETE_EN (0X00000800U)
- #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_CORE_SYNC_ERROR_SHIFT (10U)
- #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_CORE_SYNC_ERROR_CLRMSK (0XFFFFFBFFU)
- #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_CORE_SYNC_ERROR_EN (0X00000400U)
- #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_CORE_WDT_SHIFT (9U)
- #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_CORE_WDT_CLRMSK (0XFFFFFDFFU)
- #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_CORE_WDT_EN (0X00000200U)
- #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_CORE_MEM_WDT_SHIFT (8U)
- #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_CORE_MEM_WDT_CLRMSK (0XFFFFFEFFU)
- #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_CORE_MEM_WDT_EN (0X00000100U)
- #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_RAM_INIT_DONE_SHIFT (3U)
- #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_RAM_INIT_DONE_CLRMSK (0XFFFFFFF7U)
- #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_RAM_INIT_DONE_EN (0X00000008U)
- #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_MEMBUS_RESET_DONE_SHIFT (2U)
- #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_MEMBUS_RESET_DONE_CLRMSK (0XFFFFFFFBU)
- #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_MEMBUS_RESET_DONE_EN (0X00000004U)
- #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_CNN_ERROR_SHIFT (1U)
- #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_CNN_ERROR_CLRMSK (0XFFFFFFFDU)
- #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_CNN_ERROR_EN (0X00000002U)
- #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_CNN_COMPLETE_SHIFT (0U)
- #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_CNN_COMPLETE_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_CNN_COMPLETE_EN (0X00000001U)
- /*
- Register VHA_CR_CORE_EVENT_WM_CLEAR
- */
- #define VHA_CR_CORE_EVENT_WM_CLEAR (0x20150U)
- #define VHA_CR_CORE_EVENT_WM_CLEAR_MASKFULL (IMG_UINT64_C(0x0000000070010F0F))
- #define VHA_CR_CORE_EVENT_WM_CLEAR_LOGIC_ERROR_SHIFT (30U)
- #define VHA_CR_CORE_EVENT_WM_CLEAR_LOGIC_ERROR_CLRMSK (0XBFFFFFFFU)
- #define VHA_CR_CORE_EVENT_WM_CLEAR_LOGIC_ERROR_EN (0X40000000U)
- #define VHA_CR_CORE_EVENT_WM_CLEAR_RAM_CORRECTION_SHIFT (29U)
- #define VHA_CR_CORE_EVENT_WM_CLEAR_RAM_CORRECTION_CLRMSK (0XDFFFFFFFU)
- #define VHA_CR_CORE_EVENT_WM_CLEAR_RAM_CORRECTION_EN (0X20000000U)
- #define VHA_CR_CORE_EVENT_WM_CLEAR_RAM_DETECTION_SHIFT (28U)
- #define VHA_CR_CORE_EVENT_WM_CLEAR_RAM_DETECTION_CLRMSK (0XEFFFFFFFU)
- #define VHA_CR_CORE_EVENT_WM_CLEAR_RAM_DETECTION_EN (0X10000000U)
- #define VHA_CR_CORE_EVENT_WM_CLEAR_LOCM_SCRUB_DONE_SHIFT (16U)
- #define VHA_CR_CORE_EVENT_WM_CLEAR_LOCM_SCRUB_DONE_CLRMSK (0XFFFEFFFFU)
- #define VHA_CR_CORE_EVENT_WM_CLEAR_LOCM_SCRUB_DONE_EN (0X00010000U)
- #define VHA_CR_CORE_EVENT_WM_CLEAR_DMR_COMPLETE_SHIFT (11U)
- #define VHA_CR_CORE_EVENT_WM_CLEAR_DMR_COMPLETE_CLRMSK (0XFFFFF7FFU)
- #define VHA_CR_CORE_EVENT_WM_CLEAR_DMR_COMPLETE_EN (0X00000800U)
- #define VHA_CR_CORE_EVENT_WM_CLEAR_CORE_SYNC_ERROR_SHIFT (10U)
- #define VHA_CR_CORE_EVENT_WM_CLEAR_CORE_SYNC_ERROR_CLRMSK (0XFFFFFBFFU)
- #define VHA_CR_CORE_EVENT_WM_CLEAR_CORE_SYNC_ERROR_EN (0X00000400U)
- #define VHA_CR_CORE_EVENT_WM_CLEAR_CORE_WDT_SHIFT (9U)
- #define VHA_CR_CORE_EVENT_WM_CLEAR_CORE_WDT_CLRMSK (0XFFFFFDFFU)
- #define VHA_CR_CORE_EVENT_WM_CLEAR_CORE_WDT_EN (0X00000200U)
- #define VHA_CR_CORE_EVENT_WM_CLEAR_CORE_MEM_WDT_SHIFT (8U)
- #define VHA_CR_CORE_EVENT_WM_CLEAR_CORE_MEM_WDT_CLRMSK (0XFFFFFEFFU)
- #define VHA_CR_CORE_EVENT_WM_CLEAR_CORE_MEM_WDT_EN (0X00000100U)
- #define VHA_CR_CORE_EVENT_WM_CLEAR_RAM_INIT_DONE_SHIFT (3U)
- #define VHA_CR_CORE_EVENT_WM_CLEAR_RAM_INIT_DONE_CLRMSK (0XFFFFFFF7U)
- #define VHA_CR_CORE_EVENT_WM_CLEAR_RAM_INIT_DONE_EN (0X00000008U)
- #define VHA_CR_CORE_EVENT_WM_CLEAR_MEMBUS_RESET_DONE_SHIFT (2U)
- #define VHA_CR_CORE_EVENT_WM_CLEAR_MEMBUS_RESET_DONE_CLRMSK (0XFFFFFFFBU)
- #define VHA_CR_CORE_EVENT_WM_CLEAR_MEMBUS_RESET_DONE_EN (0X00000004U)
- #define VHA_CR_CORE_EVENT_WM_CLEAR_CNN_ERROR_SHIFT (1U)
- #define VHA_CR_CORE_EVENT_WM_CLEAR_CNN_ERROR_CLRMSK (0XFFFFFFFDU)
- #define VHA_CR_CORE_EVENT_WM_CLEAR_CNN_ERROR_EN (0X00000002U)
- #define VHA_CR_CORE_EVENT_WM_CLEAR_CNN_COMPLETE_SHIFT (0U)
- #define VHA_CR_CORE_EVENT_WM_CLEAR_CNN_COMPLETE_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_CORE_EVENT_WM_CLEAR_CNN_COMPLETE_EN (0X00000001U)
- /*
- Register VHA_CR_CORE_EVENT_HOST_THRESHOLD
- */
- #define VHA_CR_CORE_EVENT_HOST_THRESHOLD (0x20158U)
- #define VHA_CR_CORE_EVENT_HOST_THRESHOLD_MASKFULL (IMG_UINT64_C(0x000000000000FFFF))
- #define VHA_CR_CORE_EVENT_HOST_THRESHOLD_RAM_CORRECTION_SHIFT (0U)
- #define VHA_CR_CORE_EVENT_HOST_THRESHOLD_RAM_CORRECTION_CLRMSK (0XFFFF0000U)
- /*
- Register VHA_CR_CORE_EVENT_HOST_THRESHOLD_VAL
- */
- #define VHA_CR_CORE_EVENT_HOST_THRESHOLD_VAL (0x20160U)
- #define VHA_CR_CORE_EVENT_HOST_THRESHOLD_VAL_MASKFULL (IMG_UINT64_C(0x000000000000FFFF))
- #define VHA_CR_CORE_EVENT_HOST_THRESHOLD_VAL_RAM_CORRECTION_SHIFT (0U)
- #define VHA_CR_CORE_EVENT_HOST_THRESHOLD_VAL_RAM_CORRECTION_CLRMSK (0XFFFF0000U)
- /*
- Register VHA_CR_CORE_EVENT_WM_THRESHOLD
- */
- #define VHA_CR_CORE_EVENT_WM_THRESHOLD (0x20168U)
- #define VHA_CR_CORE_EVENT_WM_THRESHOLD_MASKFULL (IMG_UINT64_C(0x000000000000FFFF))
- #define VHA_CR_CORE_EVENT_WM_THRESHOLD_RAM_CORRECTION_SHIFT (0U)
- #define VHA_CR_CORE_EVENT_WM_THRESHOLD_RAM_CORRECTION_CLRMSK (0XFFFF0000U)
- /*
- Register VHA_CR_CORE_EVENT_WM_THRESHOLD_VAL
- */
- #define VHA_CR_CORE_EVENT_WM_THRESHOLD_VAL (0x20170U)
- #define VHA_CR_CORE_EVENT_WM_THRESHOLD_VAL_MASKFULL (IMG_UINT64_C(0x000000000000FFFF))
- #define VHA_CR_CORE_EVENT_WM_THRESHOLD_VAL_RAM_CORRECTION_SHIFT (0U)
- #define VHA_CR_CORE_EVENT_WM_THRESHOLD_VAL_RAM_CORRECTION_CLRMSK (0XFFFF0000U)
- /*
- Register VHA_CR_CORE_EVENT_INJECT
- */
- #define VHA_CR_CORE_EVENT_INJECT (0x20188U)
- #define VHA_CR_CORE_EVENT_INJECT_MASKFULL (IMG_UINT64_C(0x0000000070010F0F))
- #define VHA_CR_CORE_EVENT_INJECT_LOGIC_ERROR_SHIFT (30U)
- #define VHA_CR_CORE_EVENT_INJECT_LOGIC_ERROR_CLRMSK (0XBFFFFFFFU)
- #define VHA_CR_CORE_EVENT_INJECT_LOGIC_ERROR_EN (0X40000000U)
- #define VHA_CR_CORE_EVENT_INJECT_RAM_CORRECTION_SHIFT (29U)
- #define VHA_CR_CORE_EVENT_INJECT_RAM_CORRECTION_CLRMSK (0XDFFFFFFFU)
- #define VHA_CR_CORE_EVENT_INJECT_RAM_CORRECTION_EN (0X20000000U)
- #define VHA_CR_CORE_EVENT_INJECT_RAM_DETECTION_SHIFT (28U)
- #define VHA_CR_CORE_EVENT_INJECT_RAM_DETECTION_CLRMSK (0XEFFFFFFFU)
- #define VHA_CR_CORE_EVENT_INJECT_RAM_DETECTION_EN (0X10000000U)
- #define VHA_CR_CORE_EVENT_INJECT_LOCM_SCRUB_DONE_SHIFT (16U)
- #define VHA_CR_CORE_EVENT_INJECT_LOCM_SCRUB_DONE_CLRMSK (0XFFFEFFFFU)
- #define VHA_CR_CORE_EVENT_INJECT_LOCM_SCRUB_DONE_EN (0X00010000U)
- #define VHA_CR_CORE_EVENT_INJECT_DMR_COMPLETE_SHIFT (11U)
- #define VHA_CR_CORE_EVENT_INJECT_DMR_COMPLETE_CLRMSK (0XFFFFF7FFU)
- #define VHA_CR_CORE_EVENT_INJECT_DMR_COMPLETE_EN (0X00000800U)
- #define VHA_CR_CORE_EVENT_INJECT_CORE_SYNC_ERROR_SHIFT (10U)
- #define VHA_CR_CORE_EVENT_INJECT_CORE_SYNC_ERROR_CLRMSK (0XFFFFFBFFU)
- #define VHA_CR_CORE_EVENT_INJECT_CORE_SYNC_ERROR_EN (0X00000400U)
- #define VHA_CR_CORE_EVENT_INJECT_CORE_WDT_SHIFT (9U)
- #define VHA_CR_CORE_EVENT_INJECT_CORE_WDT_CLRMSK (0XFFFFFDFFU)
- #define VHA_CR_CORE_EVENT_INJECT_CORE_WDT_EN (0X00000200U)
- #define VHA_CR_CORE_EVENT_INJECT_CORE_MEM_WDT_SHIFT (8U)
- #define VHA_CR_CORE_EVENT_INJECT_CORE_MEM_WDT_CLRMSK (0XFFFFFEFFU)
- #define VHA_CR_CORE_EVENT_INJECT_CORE_MEM_WDT_EN (0X00000100U)
- #define VHA_CR_CORE_EVENT_INJECT_RAM_INIT_DONE_SHIFT (3U)
- #define VHA_CR_CORE_EVENT_INJECT_RAM_INIT_DONE_CLRMSK (0XFFFFFFF7U)
- #define VHA_CR_CORE_EVENT_INJECT_RAM_INIT_DONE_EN (0X00000008U)
- #define VHA_CR_CORE_EVENT_INJECT_MEMBUS_RESET_DONE_SHIFT (2U)
- #define VHA_CR_CORE_EVENT_INJECT_MEMBUS_RESET_DONE_CLRMSK (0XFFFFFFFBU)
- #define VHA_CR_CORE_EVENT_INJECT_MEMBUS_RESET_DONE_EN (0X00000004U)
- #define VHA_CR_CORE_EVENT_INJECT_CNN_ERROR_SHIFT (1U)
- #define VHA_CR_CORE_EVENT_INJECT_CNN_ERROR_CLRMSK (0XFFFFFFFDU)
- #define VHA_CR_CORE_EVENT_INJECT_CNN_ERROR_EN (0X00000002U)
- #define VHA_CR_CORE_EVENT_INJECT_CNN_COMPLETE_SHIFT (0U)
- #define VHA_CR_CORE_EVENT_INJECT_CNN_COMPLETE_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_CORE_EVENT_INJECT_CNN_COMPLETE_EN (0X00000001U)
- /*
- Register VHA_CR_CORE_VHA_FLOP_ERR_INJ_CTRL
- */
- #define VHA_CR_CORE_VHA_FLOP_ERR_INJ_CTRL (0x20280U)
- #define VHA_CR_CORE_VHA_FLOP_ERR_INJ_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000000001))
- #define VHA_CR_CORE_VHA_FLOP_ERR_INJ_CTRL_ERR_INJ_CTRL_SHIFT (0U)
- #define VHA_CR_CORE_VHA_FLOP_ERR_INJ_CTRL_ERR_INJ_CTRL_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_CORE_VHA_FLOP_ERR_INJ_CTRL_ERR_INJ_CTRL_EN (0X00000001U)
- /*
- Register VHA_CR_CORE_VHA_FLOP_ERR_INJ_STATUS
- */
- #define VHA_CR_CORE_VHA_FLOP_ERR_INJ_STATUS (0x20288U)
- #define VHA_CR_CORE_VHA_FLOP_ERR_INJ_STATUS_MASKFULL (IMG_UINT64_C(0x0000000000000001))
- #define VHA_CR_CORE_VHA_FLOP_ERR_INJ_STATUS_ERR_INJ_STATUS_SHIFT (0U)
- #define VHA_CR_CORE_VHA_FLOP_ERR_INJ_STATUS_ERR_INJ_STATUS_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_CORE_VHA_FLOP_ERR_INJ_STATUS_ERR_INJ_STATUS_EN (0X00000001U)
- /*
- Register VHA_CR_CNN_MEM_WDT_TIMER
- */
- #define VHA_CR_CNN_MEM_WDT_TIMER (0x20030U)
- #define VHA_CR_CNN_MEM_WDT_TIMER_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_CNN_MEM_WDT_TIMER_VALUE_SHIFT (0U)
- #define VHA_CR_CNN_MEM_WDT_TIMER_VALUE_CLRMSK (00000000U)
- /*
- Register VHA_CR_CNN_WDT_TIMER
- */
- #define VHA_CR_CNN_WDT_TIMER (0x20038U)
- #define VHA_CR_CNN_WDT_TIMER_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_CNN_WDT_TIMER_VALUE_SHIFT (0U)
- #define VHA_CR_CNN_WDT_TIMER_VALUE_CLRMSK (00000000U)
- /*
- Register VHA_CR_RTM_CTRL
- */
- #define VHA_CR_RTM_CTRL (0x20040U)
- #define VHA_CR_RTM_CTRL_MASKFULL (IMG_UINT64_C(0x00000000C0FFFFF8))
- #define VHA_CR_RTM_CTRL_RTM_ENABLE_SHIFT (31U)
- #define VHA_CR_RTM_CTRL_RTM_ENABLE_CLRMSK (0X7FFFFFFFU)
- #define VHA_CR_RTM_CTRL_RTM_ENABLE_EN (0X80000000U)
- #define VHA_CR_RTM_CTRL_RTM_CHECK_SHIFT (30U)
- #define VHA_CR_RTM_CTRL_RTM_CHECK_CLRMSK (0XBFFFFFFFU)
- #define VHA_CR_RTM_CTRL_RTM_CHECK_EN (0X40000000U)
- #define VHA_CR_RTM_CTRL_RTM_SELECTOR_SHIFT (3U)
- #define VHA_CR_RTM_CTRL_RTM_SELECTOR_CLRMSK (0XFF000007U)
- /*
- Register VHA_CR_RTM_DATA
- */
- #define VHA_CR_RTM_DATA (0x20048U)
- #define VHA_CR_RTM_DATA_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_RTM_DATA_RTM_DATA_SHIFT (0U)
- #define VHA_CR_RTM_DATA_RTM_DATA_CLRMSK (00000000U)
- /*
- Register VHA_CR_BIF_OUTSTANDING_READ
- */
- #define VHA_CR_BIF_OUTSTANDING_READ (0x20078U)
- #define VHA_CR_BIF_OUTSTANDING_READ_MASKFULL (IMG_UINT64_C(0x000000000000FFFF))
- #define VHA_CR_BIF_OUTSTANDING_READ_COUNTER_SHIFT (0U)
- #define VHA_CR_BIF_OUTSTANDING_READ_COUNTER_CLRMSK (0XFFFF0000U)
- /*
- Register VHA_CR_BIF_PAGE_FAULT_STALL
- */
- #define VHA_CR_BIF_PAGE_FAULT_STALL (0x20080U)
- #define VHA_CR_BIF_PAGE_FAULT_STALL_MASKFULL (IMG_UINT64_C(0x0000000000000001))
- #define VHA_CR_BIF_PAGE_FAULT_STALL_STATUS_SHIFT (0U)
- #define VHA_CR_BIF_PAGE_FAULT_STALL_STATUS_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_BIF_PAGE_FAULT_STALL_STATUS_EN (0X00000001U)
- /*
- Register VHA_CR_BIF_RTN_FIFO_WORD_COUNT
- */
- #define VHA_CR_BIF_RTN_FIFO_WORD_COUNT (0x20088U)
- #define VHA_CR_BIF_RTN_FIFO_WORD_COUNT_MASKFULL (IMG_UINT64_C(0x00000000000001FF))
- #define VHA_CR_BIF_RTN_FIFO_WORD_COUNT_COUNTER_SHIFT (0U)
- #define VHA_CR_BIF_RTN_FIFO_WORD_COUNT_COUNTER_CLRMSK (0XFFFFFE00U)
- /*
- Register VHA_CR_CNN_CMD_MH_CONTROL
- */
- #define VHA_CR_CNN_CMD_MH_CONTROL (0x201A0U)
- #define VHA_CR_CNN_CMD_MH_CONTROL_MASKFULL (IMG_UINT64_C(0x0000000000000034))
- #define VHA_CR_CNN_CMD_MH_CONTROL_MAX_BURST_LENGTH_SHIFT (4U)
- #define VHA_CR_CNN_CMD_MH_CONTROL_MAX_BURST_LENGTH_CLRMSK (0XFFFFFFCFU)
- #define VHA_CR_CNN_CMD_MH_CONTROL_SLC_CACHE_POLICY_SHIFT (2U)
- #define VHA_CR_CNN_CMD_MH_CONTROL_SLC_CACHE_POLICY_CLRMSK (0XFFFFFFFBU)
- #define VHA_CR_CNN_CMD_MH_CONTROL_SLC_CACHE_POLICY_EN (0X00000004U)
- /*
- Register VHA_CR_CNN_IBUF_MH_CONTROL
- */
- #define VHA_CR_CNN_IBUF_MH_CONTROL (0x201A8U)
- #define VHA_CR_CNN_IBUF_MH_CONTROL_MASKFULL (IMG_UINT64_C(0x0000000000000018))
- #define VHA_CR_CNN_IBUF_MH_CONTROL_MAX_BURST_LENGTH_SHIFT (3U)
- #define VHA_CR_CNN_IBUF_MH_CONTROL_MAX_BURST_LENGTH_CLRMSK (0XFFFFFFE7U)
- /*
- Register VHA_CR_CNN_CBUF_MH_CONTROL
- */
- #define VHA_CR_CNN_CBUF_MH_CONTROL (0x201B0U)
- #define VHA_CR_CNN_CBUF_MH_CONTROL_MASKFULL (IMG_UINT64_C(0x0000000000000018))
- #define VHA_CR_CNN_CBUF_MH_CONTROL_MAX_BURST_LENGTH_SHIFT (3U)
- #define VHA_CR_CNN_CBUF_MH_CONTROL_MAX_BURST_LENGTH_CLRMSK (0XFFFFFFE7U)
- /*
- Register VHA_CR_CNN_ABUF_MH_CONTROL
- */
- #define VHA_CR_CNN_ABUF_MH_CONTROL (0x201B8U)
- #define VHA_CR_CNN_ABUF_MH_CONTROL_MASKFULL (IMG_UINT64_C(0x0000000000000018))
- #define VHA_CR_CNN_ABUF_MH_CONTROL_MAX_BURST_LENGTH_SHIFT (3U)
- #define VHA_CR_CNN_ABUF_MH_CONTROL_MAX_BURST_LENGTH_CLRMSK (0XFFFFFFE7U)
- /*
- Register VHA_CR_CNN_OUTPACK_MH_CONTROL
- */
- #define VHA_CR_CNN_OUTPACK_MH_CONTROL (0x201C0U)
- #define VHA_CR_CNN_OUTPACK_MH_CONTROL_MASKFULL (IMG_UINT64_C(0x0000000000000018))
- #define VHA_CR_CNN_OUTPACK_MH_CONTROL_MAX_BURST_LENGTH_SHIFT (3U)
- #define VHA_CR_CNN_OUTPACK_MH_CONTROL_MAX_BURST_LENGTH_CLRMSK (0XFFFFFFE7U)
- /*
- Register VHA_CR_CNN_ELEMENTOPS_MH_CONTROL
- */
- #define VHA_CR_CNN_ELEMENTOPS_MH_CONTROL (0x201C8U)
- #define VHA_CR_CNN_ELEMENTOPS_MH_CONTROL_MASKFULL (IMG_UINT64_C(0x0000000000000018))
- #define VHA_CR_CNN_ELEMENTOPS_MH_CONTROL_MAX_BURST_LENGTH_SHIFT (3U)
- #define VHA_CR_CNN_ELEMENTOPS_MH_CONTROL_MAX_BURST_LENGTH_CLRMSK (0XFFFFFFE7U)
- /*
- Register VHA_CR_CNN_MMM_MH_CONTROL
- */
- #define VHA_CR_CNN_MMM_MH_CONTROL (0x201D0U)
- #define VHA_CR_CNN_MMM_MH_CONTROL_MASKFULL (IMG_UINT64_C(0x0000000000000018))
- #define VHA_CR_CNN_MMM_MH_CONTROL_MAX_BURST_LENGTH_SHIFT (3U)
- #define VHA_CR_CNN_MMM_MH_CONTROL_MAX_BURST_LENGTH_CLRMSK (0XFFFFFFE7U)
- /*
- Register VHA_CR_CNN_TRS_A_MH_CONTROL
- */
- #define VHA_CR_CNN_TRS_A_MH_CONTROL (0x201D8U)
- #define VHA_CR_CNN_TRS_A_MH_CONTROL_MASKFULL (IMG_UINT64_C(0x0000000000000018))
- #define VHA_CR_CNN_TRS_A_MH_CONTROL_MAX_BURST_LENGTH_SHIFT (3U)
- #define VHA_CR_CNN_TRS_A_MH_CONTROL_MAX_BURST_LENGTH_CLRMSK (0XFFFFFFE7U)
- /*
- Register VHA_CR_CNN_TRS_B_MH_CONTROL
- */
- #define VHA_CR_CNN_TRS_B_MH_CONTROL (0x201E0U)
- #define VHA_CR_CNN_TRS_B_MH_CONTROL_MASKFULL (IMG_UINT64_C(0x0000000000000018))
- #define VHA_CR_CNN_TRS_B_MH_CONTROL_MAX_BURST_LENGTH_SHIFT (3U)
- #define VHA_CR_CNN_TRS_B_MH_CONTROL_MAX_BURST_LENGTH_CLRMSK (0XFFFFFFE7U)
- /*
- Register VHA_CR_CNN_DWPE_MH_CONTROL
- */
- #define VHA_CR_CNN_DWPE_MH_CONTROL (0x201E8U)
- #define VHA_CR_CNN_DWPE_MH_CONTROL_MASKFULL (IMG_UINT64_C(0x0000000000000018))
- #define VHA_CR_CNN_DWPE_MH_CONTROL_MAX_BURST_LENGTH_SHIFT (3U)
- #define VHA_CR_CNN_DWPE_MH_CONTROL_MAX_BURST_LENGTH_CLRMSK (0XFFFFFFE7U)
- /*
- Register VHA_CR_FUSA_CONTROL
- */
- #define VHA_CR_FUSA_CONTROL (0x201F0U)
- #define VHA_CR_FUSA_CONTROL_MASKFULL (IMG_UINT64_C(0x0000000000000001))
- #define VHA_CR_FUSA_CONTROL_ECC_INIT_KICK_SHIFT (0U)
- #define VHA_CR_FUSA_CONTROL_ECC_INIT_KICK_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_FUSA_CONTROL_ECC_INIT_KICK_EN (0X00000001U)
- /*
- Register VHA_CR_CNN_MEM_WDT_COMPAREMATCH
- */
- #define VHA_CR_CNN_MEM_WDT_COMPAREMATCH (0x201F8U)
- #define VHA_CR_CNN_MEM_WDT_COMPAREMATCH_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_CNN_MEM_WDT_COMPAREMATCH_REG_SHIFT (0U)
- #define VHA_CR_CNN_MEM_WDT_COMPAREMATCH_REG_CLRMSK (00000000U)
- #define VHA_CR_CNN_MEM_WDT_CTRL_CNN_MEM_WDT_CTRL_MASK (0x00000003U)
- /*
- WDT is Disabled */
- #define VHA_CR_CNN_MEM_WDT_CTRL_CNN_MEM_WDT_CTRL_NONE (0x00000000U)
- /*
- WDT is Cleared when CMD Parser starts a pass or CMD parser is kicked*/
- #define VHA_CR_CNN_MEM_WDT_CTRL_CNN_MEM_WDT_CTRL_KICK_PASS (0x00000001U)
- /*
- WDT is Cleared when CMD Parser is kicked */
- #define VHA_CR_CNN_MEM_WDT_CTRL_CNN_MEM_WDT_CTRL_KICK (0x00000002U)
- /*
- Register VHA_CR_CNN_MEM_WDT_CTRL
- */
- #define VHA_CR_CNN_MEM_WDT_CTRL (0x20200U)
- #define VHA_CR_CNN_MEM_WDT_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000000003))
- #define VHA_CR_CNN_MEM_WDT_CTRL_MODE_SHIFT (0U)
- #define VHA_CR_CNN_MEM_WDT_CTRL_MODE_CLRMSK (0XFFFFFFFCU)
- #define VHA_CR_CNN_MEM_WDT_CTRL_MODE_NONE (00000000U)
- #define VHA_CR_CNN_MEM_WDT_CTRL_MODE_KICK_PASS (0X00000001U)
- #define VHA_CR_CNN_MEM_WDT_CTRL_MODE_KICK (0X00000002U)
- #define VHA_CR_CNN_WDT_CTRL_CNN_WDT_CTRL_MASK (0x00000003U)
- /*
- WDT is Cleared when CMD Parser starts a pass or CMD parser is kicked*/
- #define VHA_CR_CNN_WDT_CTRL_CNN_WDT_CTRL_KICK_PASS (0x00000001U)
- /*
- WDT is Cleared when CMD Parser starts a layer group or CMD parser is kicked*/
- #define VHA_CR_CNN_WDT_CTRL_CNN_WDT_CTRL_KICK_LAYER (0x00000002U)
- /*
- Register VHA_CR_CNN_WDT_CTRL
- */
- #define VHA_CR_CNN_WDT_CTRL (0x20208U)
- #define VHA_CR_CNN_WDT_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000000003))
- #define VHA_CR_CNN_WDT_CTRL_MODE_SHIFT (0U)
- #define VHA_CR_CNN_WDT_CTRL_MODE_CLRMSK (0XFFFFFFFCU)
- #define VHA_CR_CNN_WDT_CTRL_MODE_KICK_PASS (0X00000001U)
- #define VHA_CR_CNN_WDT_CTRL_MODE_KICK_LAYER (0X00000002U)
- /*
- Register VHA_CR_CNN_WDT_COMPAREMATCH
- */
- #define VHA_CR_CNN_WDT_COMPAREMATCH (0x20210U)
- #define VHA_CR_CNN_WDT_COMPAREMATCH_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_CNN_WDT_COMPAREMATCH_REG_SHIFT (0U)
- #define VHA_CR_CNN_WDT_COMPAREMATCH_REG_CLRMSK (00000000U)
- /*
- Register VHA_CR_VHA_CNN_CMD_SECURITY_CONTROL
- */
- #define VHA_CR_VHA_CNN_CMD_SECURITY_CONTROL (0x20230U)
- #define VHA_CR_VHA_CNN_CMD_SECURITY_CONTROL_MASKFULL (IMG_UINT64_C(0x0000000000000004))
- #define VHA_CR_VHA_CNN_CMD_SECURITY_CONTROL_FORCE_DISABLE_CRC_SHIFT (2U)
- #define VHA_CR_VHA_CNN_CMD_SECURITY_CONTROL_FORCE_DISABLE_CRC_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFB))
- #define VHA_CR_VHA_CNN_CMD_SECURITY_CONTROL_FORCE_DISABLE_CRC_EN (IMG_UINT64_C(0X0000000000000004))
- /*
- Register VHA_CR_CNN_ARB_STALL_RATIO
- */
- #define VHA_CR_CNN_ARB_STALL_RATIO (0x20240U)
- #define VHA_CR_CNN_ARB_STALL_RATIO_MASKFULL (IMG_UINT64_C(0x0000000FFFFFFFFF))
- #define VHA_CR_CNN_ARB_STALL_RATIO_OUTPUT_SHIFT (32U)
- #define VHA_CR_CNN_ARB_STALL_RATIO_OUTPUT_CLRMSK (IMG_UINT64_C(0XFFFFFFF0FFFFFFFF))
- #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_8_SHIFT (28U)
- #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_8_CLRMSK (IMG_UINT64_C(0XFFFFFFFF0FFFFFFF))
- #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_7_SHIFT (24U)
- #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_7_CLRMSK (IMG_UINT64_C(0XFFFFFFFFF0FFFFFF))
- #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_6_SHIFT (20U)
- #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_6_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF0FFFFF))
- #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_5_SHIFT (16U)
- #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_5_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF0FFFF))
- #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_4_SHIFT (12U)
- #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_4_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF0FFF))
- #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_3_SHIFT (8U)
- #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_3_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF0FF))
- #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_2_SHIFT (4U)
- #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_2_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFF0F))
- #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_1_SHIFT (0U)
- #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF0))
- /*
- Register VHA_CR_CNN_DATAPATH_STALL_RATIO_0
- */
- #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0 (0x20248U)
- #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_MASKFULL (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
- #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_CORE_XBAR_ACT_SHIFT (60U)
- #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_CORE_XBAR_ACT_CLRMSK (IMG_UINT64_C(0X0FFFFFFFFFFFFFFF))
- #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_ACT_CORE_XBAR_SHIFT (56U)
- #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_ACT_CORE_XBAR_CLRMSK (IMG_UINT64_C(0XF0FFFFFFFFFFFFFF))
- #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_EWO_CORE_XBAR_SHIFT (52U)
- #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_EWO_CORE_XBAR_CLRMSK (IMG_UINT64_C(0XFF0FFFFFFFFFFFFF))
- #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_TENSORB_CORE_XBAR_SHIFT (48U)
- #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_TENSORB_CORE_XBAR_CLRMSK (IMG_UINT64_C(0XFFF0FFFFFFFFFFFF))
- #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_CORE_XBAR_EWO_SHIFT (44U)
- #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_CORE_XBAR_EWO_CLRMSK (IMG_UINT64_C(0XFFFF0FFFFFFFFFFF))
- #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_CORE_XBAR_TENSORB_SHIFT (40U)
- #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_CORE_XBAR_TENSORB_CLRMSK (IMG_UINT64_C(0XFFFFF0FFFFFFFFFF))
- #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_CORE_XBAR_NORM_SHIFT (36U)
- #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_CORE_XBAR_NORM_CLRMSK (IMG_UINT64_C(0XFFFFFF0FFFFFFFFF))
- #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_NORM_POOL_SHIFT (32U)
- #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_NORM_POOL_CLRMSK (IMG_UINT64_C(0XFFFFFFF0FFFFFFFF))
- #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_CNV_ABUF_SHIFT (28U)
- #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_CNV_ABUF_CLRMSK (IMG_UINT64_C(0XFFFFFFFF0FFFFFFF))
- #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_IBUF_CNV_SHIFT (24U)
- #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_IBUF_CNV_CLRMSK (IMG_UINT64_C(0XFFFFFFFFF0FFFFFF))
- #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_ABUF_CORE_XBAR_SHIFT (20U)
- #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_ABUF_CORE_XBAR_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF0FFFFF))
- #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_CORE_XBAR_IBUF_SHIFT (16U)
- #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_CORE_XBAR_IBUF_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF0FFFF))
- #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_IBUF_CORE_XBAR_SHIFT (12U)
- #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_IBUF_CORE_XBAR_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF0FFF))
- #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_CBUF_CNV_SHIFT (8U)
- #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_CBUF_CNV_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF0FF))
- #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_ABUF_OUTPACK_SHIFT (4U)
- #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_ABUF_OUTPACK_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFF0F))
- #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_CBUF_ABUF_SHIFT (0U)
- #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_CBUF_ABUF_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF0))
- /*
- Register VHA_CR_CNN_DATAPATH_STALL_RATIO_1
- */
- #define VHA_CR_CNN_DATAPATH_STALL_RATIO_1 (0x20250U)
- #define VHA_CR_CNN_DATAPATH_STALL_RATIO_1_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
- #define VHA_CR_CNN_DATAPATH_STALL_RATIO_1_NORM_POOL_BYPASS_SHIFT (36U)
- #define VHA_CR_CNN_DATAPATH_STALL_RATIO_1_NORM_POOL_BYPASS_CLRMSK (IMG_UINT64_C(0XFFFFFF0FFFFFFFFF))
- #define VHA_CR_CNN_DATAPATH_STALL_RATIO_1_TRS_B_XBAR_SHIFT (32U)
- #define VHA_CR_CNN_DATAPATH_STALL_RATIO_1_TRS_B_XBAR_CLRMSK (IMG_UINT64_C(0XFFFFFFF0FFFFFFFF))
- #define VHA_CR_CNN_DATAPATH_STALL_RATIO_1_XBAR_TRS_B_SHIFT (28U)
- #define VHA_CR_CNN_DATAPATH_STALL_RATIO_1_XBAR_TRS_B_CLRMSK (IMG_UINT64_C(0XFFFFFFFF0FFFFFFF))
- #define VHA_CR_CNN_DATAPATH_STALL_RATIO_1_TRS_A_XBAR_SHIFT (24U)
- #define VHA_CR_CNN_DATAPATH_STALL_RATIO_1_TRS_A_XBAR_CLRMSK (IMG_UINT64_C(0XFFFFFFFFF0FFFFFF))
- #define VHA_CR_CNN_DATAPATH_STALL_RATIO_1_XBAR_TRS_A_SHIFT (20U)
- #define VHA_CR_CNN_DATAPATH_STALL_RATIO_1_XBAR_TRS_A_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF0FFFFF))
- #define VHA_CR_CNN_DATAPATH_STALL_RATIO_1_OIN_OPK_SHIFT (16U)
- #define VHA_CR_CNN_DATAPATH_STALL_RATIO_1_OIN_OPK_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF0FFFF))
- #define VHA_CR_CNN_DATAPATH_STALL_RATIO_1_CORE_XBAR_OIN_SHIFT (12U)
- #define VHA_CR_CNN_DATAPATH_STALL_RATIO_1_CORE_XBAR_OIN_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF0FFF))
- #define VHA_CR_CNN_DATAPATH_STALL_RATIO_1_POOL_CORE_XBAR_SHIFT (8U)
- #define VHA_CR_CNN_DATAPATH_STALL_RATIO_1_POOL_CORE_XBAR_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF0FF))
- #define VHA_CR_CNN_DATAPATH_STALL_RATIO_1_POOL_SB_SHIFT (4U)
- #define VHA_CR_CNN_DATAPATH_STALL_RATIO_1_POOL_SB_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFF0F))
- #define VHA_CR_CNN_DATAPATH_STALL_RATIO_1_OIN_SB_SHIFT (0U)
- #define VHA_CR_CNN_DATAPATH_STALL_RATIO_1_OIN_SB_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF0))
- /*
- Register VHA_CR_NN_SYS2_MEMBUS_CORE_STALL_RATIO
- */
- #define VHA_CR_NN_SYS2_MEMBUS_CORE_STALL_RATIO (0x20258U)
- #define VHA_CR_NN_SYS2_MEMBUS_CORE_STALL_RATIO_MASKFULL (IMG_UINT64_C(0x0000000000FFFFFF))
- #define VHA_CR_NN_SYS2_MEMBUS_CORE_STALL_RATIO_CORE_NOC_MEMBUS_RESET_RTN_SHIFT (20U)
- #define VHA_CR_NN_SYS2_MEMBUS_CORE_STALL_RATIO_CORE_NOC_MEMBUS_RESET_RTN_CLRMSK (0XFF0FFFFFU)
- #define VHA_CR_NN_SYS2_MEMBUS_CORE_STALL_RATIO_CORE_NOC_MEMBUS_RESET_SHIFT (16U)
- #define VHA_CR_NN_SYS2_MEMBUS_CORE_STALL_RATIO_CORE_NOC_MEMBUS_RESET_CLRMSK (0XFFF0FFFFU)
- #define VHA_CR_NN_SYS2_MEMBUS_CORE_STALL_RATIO_CORE_NOC_LOCM_RTN_SHIFT (12U)
- #define VHA_CR_NN_SYS2_MEMBUS_CORE_STALL_RATIO_CORE_NOC_LOCM_RTN_CLRMSK (0XFFFF0FFFU)
- #define VHA_CR_NN_SYS2_MEMBUS_CORE_STALL_RATIO_CORE_NOC_LOCM_SHIFT (8U)
- #define VHA_CR_NN_SYS2_MEMBUS_CORE_STALL_RATIO_CORE_NOC_LOCM_CLRMSK (0XFFFFF0FFU)
- #define VHA_CR_NN_SYS2_MEMBUS_CORE_STALL_RATIO_BIF_CORE_NOC_RTN_SHIFT (4U)
- #define VHA_CR_NN_SYS2_MEMBUS_CORE_STALL_RATIO_BIF_CORE_NOC_RTN_CLRMSK (0XFFFFFF0FU)
- #define VHA_CR_NN_SYS2_MEMBUS_CORE_STALL_RATIO_BIF_CORE_NOC_SHIFT (0U)
- #define VHA_CR_NN_SYS2_MEMBUS_CORE_STALL_RATIO_BIF_CORE_NOC_CLRMSK (0XFFFFFFF0U)
- /*
- Register VHA_CR_CNN_ARB_CTRL
- */
- #define VHA_CR_CNN_ARB_CTRL (0x20260U)
- #define VHA_CR_CNN_ARB_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000000307))
- #define VHA_CR_CNN_ARB_CTRL_ENABLE_PASS_PRIORITY_SHIFT (9U)
- #define VHA_CR_CNN_ARB_CTRL_ENABLE_PASS_PRIORITY_CLRMSK (0XFFFFFDFFU)
- #define VHA_CR_CNN_ARB_CTRL_ENABLE_PASS_PRIORITY_EN (0X00000200U)
- #define VHA_CR_CNN_ARB_CTRL_MMM_PRIORITY_SEL_SHIFT (8U)
- #define VHA_CR_CNN_ARB_CTRL_MMM_PRIORITY_SEL_CLRMSK (0XFFFFFEFFU)
- #define VHA_CR_CNN_ARB_CTRL_MMM_PRIORITY_SEL_EN (0X00000100U)
- #define VHA_CR_CNN_ARB_CTRL_MAX_PAGE_COUNT_MIN1_SHIFT (0U)
- #define VHA_CR_CNN_ARB_CTRL_MAX_PAGE_COUNT_MIN1_CLRMSK (0XFFFFFFF8U)
- /*
- Register VHA_CR_REQ_CTXT_OVERRIDE
- */
- #define VHA_CR_REQ_CTXT_OVERRIDE (0x203A8U)
- #define VHA_CR_REQ_CTXT_OVERRIDE_MASKFULL (IMG_UINT64_C(0x0000000000000007))
- #define VHA_CR_REQ_CTXT_OVERRIDE_OVERRIDE_OS2_SHIFT (2U)
- #define VHA_CR_REQ_CTXT_OVERRIDE_OVERRIDE_OS2_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFB))
- #define VHA_CR_REQ_CTXT_OVERRIDE_OVERRIDE_OS2_EN (IMG_UINT64_C(0X0000000000000004))
- #define VHA_CR_REQ_CTXT_OVERRIDE_OVERRIDE_OS1_SHIFT (1U)
- #define VHA_CR_REQ_CTXT_OVERRIDE_OVERRIDE_OS1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFD))
- #define VHA_CR_REQ_CTXT_OVERRIDE_OVERRIDE_OS1_EN (IMG_UINT64_C(0X0000000000000002))
- #define VHA_CR_REQ_CTXT_OVERRIDE_OVERRIDE_OS0_SHIFT (0U)
- #define VHA_CR_REQ_CTXT_OVERRIDE_OVERRIDE_OS0_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
- #define VHA_CR_REQ_CTXT_OVERRIDE_OVERRIDE_OS0_EN (IMG_UINT64_C(0X0000000000000001))
- /*
- Register VHA_CR_CNN_CMD_PRIORITY_LIMITS
- */
- #define VHA_CR_CNN_CMD_PRIORITY_LIMITS (0x203B0U)
- #define VHA_CR_CNN_CMD_PRIORITY_LIMITS_MASKFULL (IMG_UINT64_C(0x000000000000019B))
- #define VHA_CR_CNN_CMD_PRIORITY_LIMITS_OS2_LIMIT_SHIFT (7U)
- #define VHA_CR_CNN_CMD_PRIORITY_LIMITS_OS2_LIMIT_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFE7F))
- #define VHA_CR_CNN_CMD_PRIORITY_LIMITS_OS1_LIMIT_SHIFT (3U)
- #define VHA_CR_CNN_CMD_PRIORITY_LIMITS_OS1_LIMIT_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFE7))
- #define VHA_CR_CNN_CMD_PRIORITY_LIMITS_OS0_LIMIT_SHIFT (0U)
- #define VHA_CR_CNN_CMD_PRIORITY_LIMITS_OS0_LIMIT_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFC))
- /*
- Register VHA_CR_LOCM_SCRUB_CTRL
- */
- #define VHA_CR_LOCM_SCRUB_CTRL (0x203B8U)
- #define VHA_CR_LOCM_SCRUB_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000000011))
- #define VHA_CR_LOCM_SCRUB_CTRL_MODE_SHIFT (4U)
- #define VHA_CR_LOCM_SCRUB_CTRL_MODE_CLRMSK (0XFFFFFFEFU)
- #define VHA_CR_LOCM_SCRUB_CTRL_MODE_EN (0X00000010U)
- #define VHA_CR_LOCM_SCRUB_CTRL_KICK_SHIFT (0U)
- #define VHA_CR_LOCM_SCRUB_CTRL_KICK_CLRMSK (0XFFFFFFFEU)
- #define VHA_CR_LOCM_SCRUB_CTRL_KICK_EN (0X00000001U)
- #define VHA_CR_CNN_MASK_CTRL_MASK (0x00000003U)
- /*
- No Masks Applied */
- #define VHA_CR_CNN_MASK_CTRL_DEBUG_INTERNAL (0x00000000U)
- /*
- Mask port with mask_level < 1 */
- #define VHA_CR_CNN_MASK_CTRL_DEBUG_SILICON (0x00000001U)
- /*
- Mask port with mask_level < 2 */
- #define VHA_CR_CNN_MASK_CTRL_SAFETY (0x00000002U)
- /*
- Mask port with mask_level < 3 */
- #define VHA_CR_CNN_MASK_CTRL_RESERVED (0x00000003U)
- #define VHA_CR_CNN_DEBUG_CTRL_MASK (0x00000003U)
- /*
- Debug is switched off */
- #define VHA_CR_CNN_DEBUG_CTRL_DISABLE (0x00000000U)
- /*
- Debug is output at the end of each stream */
- #define VHA_CR_CNN_DEBUG_CTRL_STREAM (0x00000001U)
- /*
- Debug is output at the end of each layer */
- #define VHA_CR_CNN_DEBUG_CTRL_LAYER (0x00000002U)
- /*
- Debug is output at the end of each pass */
- #define VHA_CR_CNN_DEBUG_CTRL_PASS (0x00000003U)
- #define VHA_CR_CNN_DEBUG_CTRL_BAND_MASK (0x00000003U)
- /*
- Debug is switched off */
- #define VHA_CR_CNN_DEBUG_CTRL_BAND_DISABLE (0x00000000U)
- /*
- Debug is Switched off */
- #define VHA_CR_CNN_DEBUG_CTRL_BAND_RESERVED (0x00000001U)
- /*
- Debug is output at the end of each layer */
- #define VHA_CR_CNN_DEBUG_CTRL_BAND_LAYER (0x00000002U)
- /*
- Debug is output at the end of each pass */
- #define VHA_CR_CNN_DEBUG_CTRL_BAND_PASS (0x00000003U)
- #define VHA_CR_CNN_PRELOAD_CTRL_MASK (0x00000007U)
- /*
- Preloads are switched off */
- #define VHA_CR_CNN_PRELOAD_CTRL_DISABLE (0x00000000U)
- /*
- Preloads are triggered 64 requests after the previous 32k boundary */
- #define VHA_CR_CNN_PRELOAD_CTRL_N_64 (0x00000001U)
- /*
- Preloads are triggered 128 requests after the previous 32k boundary */
- #define VHA_CR_CNN_PRELOAD_CTRL_N_128 (0x00000002U)
- /*
- Preloads are triggered 192 requests after the previous 32k boundary */
- #define VHA_CR_CNN_PRELOAD_CTRL_N_192 (0x00000003U)
- /*
- Preloads are triggered 256 requests after the previous 32k boundary */
- #define VHA_CR_CNN_PRELOAD_CTRL_N_256 (0x00000004U)
- /*
- Preloads are triggered 320 requests after the previous 32k boundary */
- #define VHA_CR_CNN_PRELOAD_CTRL_N_320 (0x00000005U)
- /*
- Preloads are triggered 384 requests after the previous 32k boundary */
- #define VHA_CR_CNN_PRELOAD_CTRL_N_384 (0x00000006U)
- /*
- Preloads are triggered 448 requests after the previous 32k boundary */
- #define VHA_CR_CNN_PRELOAD_CTRL_N_448 (0x00000007U)
- /*
- Memory buffer will be used for MODEL only (CBUF, CMD , DEBUG, PERF) */
- #define VHA_CR_ALT_ADDR_BUF_TYPE_MODEL_ONLY (0x00000000U)
- /*
- Memory buffer will be used for IO Only( OUTPACK , IBUF , ABUF, EWO ) or Both MODEL and IO */
- #define VHA_CR_ALT_ADDR_BUF_TYPE_IO_OR_SHARED (0x00000001U)
- /*
- Register VHA_CR_OS0_CNN_CONTROL
- */
- #define VHA_CR_OS0_CNN_CONTROL (0x30000U)
- #define VHA_CR_OS0_CNN_CONTROL_MASKFULL (IMG_UINT64_C(0x00000000013F7F7E))
- #define VHA_CR_OS0_CNN_CONTROL_START_SHIFT (24U)
- #define VHA_CR_OS0_CNN_CONTROL_START_CLRMSK (0XFEFFFFFFU)
- #define VHA_CR_OS0_CNN_CONTROL_START_EN (0X01000000U)
- #define VHA_CR_OS0_CNN_CONTROL_ENABLE_SKIP_LAYERS_SHIFT (21U)
- #define VHA_CR_OS0_CNN_CONTROL_ENABLE_SKIP_LAYERS_CLRMSK (0XFFDFFFFFU)
- #define VHA_CR_OS0_CNN_CONTROL_ENABLE_SKIP_LAYERS_EN (0X00200000U)
- #define VHA_CR_OS0_CNN_CONTROL_CTXT_PASID_SHIFT (16U)
- #define VHA_CR_OS0_CNN_CONTROL_CTXT_PASID_CLRMSK (0XFFE0FFFFU)
- #define VHA_CR_OS0_CNN_CONTROL_CTXT_PASID_IO_SHIFT (10U)
- #define VHA_CR_OS0_CNN_CONTROL_CTXT_PASID_IO_CLRMSK (0XFFFF83FFU)
- #define VHA_CR_OS0_CNN_CONTROL_PRIORITY_SHIFT (8U)
- #define VHA_CR_OS0_CNN_CONTROL_PRIORITY_CLRMSK (0XFFFFFCFFU)
- #define VHA_CR_OS0_CNN_CONTROL_CMD_SIZE_MIN1_SHIFT (1U)
- #define VHA_CR_OS0_CNN_CONTROL_CMD_SIZE_MIN1_CLRMSK (0XFFFFFF81U)
- #define VHA_CR_OS0_CNN_STATUS_STATE_MASK (0x00000003U)
- /*
- No requests are pending for this host*/
- #define VHA_CR_OS0_CNN_STATUS_STATE_IDLE (0x00000000U)
- /*
- A command stream from this host is being processed*/
- #define VHA_CR_OS0_CNN_STATUS_STATE_RUN (0x00000001U)
- /*
- The command stream from this host has been suspended due to higher priority request from another host*/
- #define VHA_CR_OS0_CNN_STATUS_STATE_SUSPEND (0x00000002U)
- /*
- A command stream from this host is pending but not been started */
- #define VHA_CR_OS0_CNN_STATUS_STATE_PENDING (0x00000003U)
- /*
- Register VHA_CR_OS0_CNN_STATUS
- */
- #define VHA_CR_OS0_CNN_STATUS (0x30008U)
- #define VHA_CR_OS0_CNN_STATUS_MASKFULL (IMG_UINT64_C(0x00000000C1FFFFFF))
- #define VHA_CR_OS0_CNN_STATUS_CURRENT_STATE_SHIFT (30U)
- #define VHA_CR_OS0_CNN_STATUS_CURRENT_STATE_CLRMSK (0X3FFFFFFFU)
- #define VHA_CR_OS0_CNN_STATUS_CURRENT_STATE_IDLE (00000000U)
- #define VHA_CR_OS0_CNN_STATUS_CURRENT_STATE_RUN (0X40000000U)
- #define VHA_CR_OS0_CNN_STATUS_CURRENT_STATE_SUSPEND (0X80000000U)
- #define VHA_CR_OS0_CNN_STATUS_CURRENT_STATE_PENDING (0XC0000000U)
- #define VHA_CR_OS0_CNN_STATUS_PARITY_SHIFT (24U)
- #define VHA_CR_OS0_CNN_STATUS_PARITY_CLRMSK (0XFEFFFFFFU)
- #define VHA_CR_OS0_CNN_STATUS_PARITY_EN (0X01000000U)
- #define VHA_CR_OS0_CNN_STATUS_LAYER_COUNT_SHIFT (8U)
- #define VHA_CR_OS0_CNN_STATUS_LAYER_COUNT_CLRMSK (0XFF0000FFU)
- #define VHA_CR_OS0_CNN_STATUS_STREAM_COUNT_SHIFT (0U)
- #define VHA_CR_OS0_CNN_STATUS_STREAM_COUNT_CLRMSK (0XFFFFFF00U)
- /*
- Register VHA_CR_OS0_CNN_STATUS2
- */
- #define VHA_CR_OS0_CNN_STATUS2 (0x30010U)
- #define VHA_CR_OS0_CNN_STATUS2_MASKFULL (IMG_UINT64_C(0x000000000000FFFF))
- #define VHA_CR_OS0_CNN_STATUS2_PASS_COUNT_SHIFT (0U)
- #define VHA_CR_OS0_CNN_STATUS2_PASS_COUNT_CLRMSK (0XFFFF0000U)
- /*
- Register VHA_CR_OS0_CNN_CMD_BASE_ADDRESS
- */
- #define VHA_CR_OS0_CNN_CMD_BASE_ADDRESS (0x30018U)
- #define VHA_CR_OS0_CNN_CMD_BASE_ADDRESS_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFF80))
- #define VHA_CR_OS0_CNN_CMD_BASE_ADDRESS_BASE_ADDR_SHIFT (7U)
- #define VHA_CR_OS0_CNN_CMD_BASE_ADDRESS_BASE_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF000000007F))
- /*
- Register VHA_CR_OS0_CNN_ALT_ADDRESS_USED
- */
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED (0x30020U)
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR15_BUF_TYPE_SHIFT (31U)
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR15_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFF7FFFFFFF))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR15_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR15_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000080000000))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR14_BUF_TYPE_SHIFT (30U)
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR14_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFBFFFFFFF))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR14_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR14_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000040000000))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR13_BUF_TYPE_SHIFT (29U)
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR13_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFDFFFFFFF))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR13_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR13_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000020000000))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR12_BUF_TYPE_SHIFT (28U)
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR12_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFEFFFFFFF))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR12_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR12_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000010000000))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR11_BUF_TYPE_SHIFT (27U)
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR11_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFF7FFFFFF))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR11_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR11_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000008000000))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR10_BUF_TYPE_SHIFT (26U)
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR10_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFBFFFFFF))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR10_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR10_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000004000000))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR9_BUF_TYPE_SHIFT (25U)
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR9_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFDFFFFFF))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR9_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR9_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000002000000))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR8_BUF_TYPE_SHIFT (24U)
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR8_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFEFFFFFF))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR8_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR8_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000001000000))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR7_BUF_TYPE_SHIFT (23U)
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR7_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF7FFFFF))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR7_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR7_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000000800000))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR6_BUF_TYPE_SHIFT (22U)
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR6_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFBFFFFF))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR6_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR6_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000000400000))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR5_BUF_TYPE_SHIFT (21U)
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR5_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFDFFFFF))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR5_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR5_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000000200000))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR4_BUF_TYPE_SHIFT (20U)
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR4_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFEFFFFF))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR4_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR4_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000000100000))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR3_BUF_TYPE_SHIFT (19U)
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR3_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF7FFFF))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR3_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR3_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000000080000))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR2_BUF_TYPE_SHIFT (18U)
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR2_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFBFFFF))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR2_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR2_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000000040000))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR1_BUF_TYPE_SHIFT (17U)
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR1_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFDFFFF))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR1_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR1_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000000020000))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR0_BUF_TYPE_SHIFT (16U)
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR0_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFEFFFF))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR0_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR0_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000000010000))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR15_USED_SHIFT (15U)
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR15_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF7FFF))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR15_USED_EN (IMG_UINT64_C(0X0000000000008000))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR14_USED_SHIFT (14U)
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR14_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFBFFF))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR14_USED_EN (IMG_UINT64_C(0X0000000000004000))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR13_USED_SHIFT (13U)
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR13_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFDFFF))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR13_USED_EN (IMG_UINT64_C(0X0000000000002000))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR12_USED_SHIFT (12U)
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR12_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFEFFF))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR12_USED_EN (IMG_UINT64_C(0X0000000000001000))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR11_USED_SHIFT (11U)
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR11_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF7FF))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR11_USED_EN (IMG_UINT64_C(0X0000000000000800))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR10_USED_SHIFT (10U)
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR10_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFBFF))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR10_USED_EN (IMG_UINT64_C(0X0000000000000400))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR9_USED_SHIFT (9U)
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR9_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFDFF))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR9_USED_EN (IMG_UINT64_C(0X0000000000000200))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR8_USED_SHIFT (8U)
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR8_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFEFF))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR8_USED_EN (IMG_UINT64_C(0X0000000000000100))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR7_USED_SHIFT (7U)
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR7_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFF7F))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR7_USED_EN (IMG_UINT64_C(0X0000000000000080))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR6_USED_SHIFT (6U)
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR6_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFBF))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR6_USED_EN (IMG_UINT64_C(0X0000000000000040))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR5_USED_SHIFT (5U)
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR5_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFDF))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR5_USED_EN (IMG_UINT64_C(0X0000000000000020))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR4_USED_SHIFT (4U)
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR4_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFEF))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR4_USED_EN (IMG_UINT64_C(0X0000000000000010))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR3_USED_SHIFT (3U)
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR3_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF7))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR3_USED_EN (IMG_UINT64_C(0X0000000000000008))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR2_USED_SHIFT (2U)
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR2_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFB))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR2_USED_EN (IMG_UINT64_C(0X0000000000000004))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR1_USED_SHIFT (1U)
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR1_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFD))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR1_USED_EN (IMG_UINT64_C(0X0000000000000002))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR0_USED_SHIFT (0U)
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR0_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR0_USED_EN (IMG_UINT64_C(0X0000000000000001))
- /*
- Register VHA_CR_OS0_CNN_ALT_ADDRESS0
- */
- #define VHA_CR_OS0_CNN_ALT_ADDRESS0 (0x30028U)
- #define VHA_CR_OS0_CNN_ALT_ADDRESS0_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS0_ALT_ADDR_SHIFT (0U)
- #define VHA_CR_OS0_CNN_ALT_ADDRESS0_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
- /*
- Register VHA_CR_OS0_CNN_ALT_ADDRESS1
- */
- #define VHA_CR_OS0_CNN_ALT_ADDRESS1 (0x30030U)
- #define VHA_CR_OS0_CNN_ALT_ADDRESS1_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS1_ALT_ADDR_SHIFT (0U)
- #define VHA_CR_OS0_CNN_ALT_ADDRESS1_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
- /*
- Register VHA_CR_OS0_CNN_ALT_ADDRESS2
- */
- #define VHA_CR_OS0_CNN_ALT_ADDRESS2 (0x30038U)
- #define VHA_CR_OS0_CNN_ALT_ADDRESS2_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS2_ALT_ADDR_SHIFT (0U)
- #define VHA_CR_OS0_CNN_ALT_ADDRESS2_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
- /*
- Register VHA_CR_OS0_CNN_ALT_ADDRESS3
- */
- #define VHA_CR_OS0_CNN_ALT_ADDRESS3 (0x30040U)
- #define VHA_CR_OS0_CNN_ALT_ADDRESS3_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS3_ALT_ADDR_SHIFT (0U)
- #define VHA_CR_OS0_CNN_ALT_ADDRESS3_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
- /*
- Register VHA_CR_OS0_CNN_ALT_ADDRESS4
- */
- #define VHA_CR_OS0_CNN_ALT_ADDRESS4 (0x30048U)
- #define VHA_CR_OS0_CNN_ALT_ADDRESS4_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS4_ALT_ADDR_SHIFT (0U)
- #define VHA_CR_OS0_CNN_ALT_ADDRESS4_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
- /*
- Register VHA_CR_OS0_CNN_ALT_ADDRESS5
- */
- #define VHA_CR_OS0_CNN_ALT_ADDRESS5 (0x30050U)
- #define VHA_CR_OS0_CNN_ALT_ADDRESS5_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS5_ALT_ADDR_SHIFT (0U)
- #define VHA_CR_OS0_CNN_ALT_ADDRESS5_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
- /*
- Register VHA_CR_OS0_CNN_ALT_ADDRESS6
- */
- #define VHA_CR_OS0_CNN_ALT_ADDRESS6 (0x30058U)
- #define VHA_CR_OS0_CNN_ALT_ADDRESS6_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS6_ALT_ADDR_SHIFT (0U)
- #define VHA_CR_OS0_CNN_ALT_ADDRESS6_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
- /*
- Register VHA_CR_OS0_CNN_ALT_ADDRESS7
- */
- #define VHA_CR_OS0_CNN_ALT_ADDRESS7 (0x30060U)
- #define VHA_CR_OS0_CNN_ALT_ADDRESS7_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS7_ALT_ADDR_SHIFT (0U)
- #define VHA_CR_OS0_CNN_ALT_ADDRESS7_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
- /*
- Register VHA_CR_OS0_CNN_WRITEBACK_CONTROL
- */
- #define VHA_CR_OS0_CNN_WRITEBACK_CONTROL (0x30068U)
- #define VHA_CR_OS0_CNN_WRITEBACK_CONTROL_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_OS0_CNN_WRITEBACK_CONTROL_WRITE_BACK_VALUE_SHIFT (0U)
- #define VHA_CR_OS0_CNN_WRITEBACK_CONTROL_WRITE_BACK_VALUE_CLRMSK (00000000U)
- /*
- Register VHA_CR_OS0_CNN_CRC_CONTROL
- */
- #define VHA_CR_OS0_CNN_CRC_CONTROL (0x30088U)
- #define VHA_CR_OS0_CNN_CRC_CONTROL_MASKFULL (IMG_UINT64_C(0x0000000000000013))
- #define VHA_CR_OS0_CNN_CRC_CONTROL_COMBINED_CNN_CRC_ENABLE_SHIFT (4U)
- #define VHA_CR_OS0_CNN_CRC_CONTROL_COMBINED_CNN_CRC_ENABLE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFEF))
- #define VHA_CR_OS0_CNN_CRC_CONTROL_COMBINED_CNN_CRC_ENABLE_EN (IMG_UINT64_C(0X0000000000000010))
- #define VHA_CR_OS0_CNN_CRC_CONTROL_CNN_CRC_ENABLE_SHIFT (0U)
- #define VHA_CR_OS0_CNN_CRC_CONTROL_CNN_CRC_ENABLE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFC))
- #define VHA_CR_OS0_CNN_CRC_CONTROL_CNN_CRC_ENABLE_DISABLE (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_OS0_CNN_CRC_CONTROL_CNN_CRC_ENABLE_STREAM (IMG_UINT64_C(0x0000000000000001))
- #define VHA_CR_OS0_CNN_CRC_CONTROL_CNN_CRC_ENABLE_LAYER (IMG_UINT64_C(0x0000000000000002))
- #define VHA_CR_OS0_CNN_CRC_CONTROL_CNN_CRC_ENABLE_PASS (IMG_UINT64_C(0x0000000000000003))
- /*
- Register VHA_CR_OS0_CNN_CRC_ADDRESS
- */
- #define VHA_CR_OS0_CNN_CRC_ADDRESS (0x30090U)
- #define VHA_CR_OS0_CNN_CRC_ADDRESS_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFF80))
- #define VHA_CR_OS0_CNN_CRC_ADDRESS_CNN_CRC_ADDR_SHIFT (7U)
- #define VHA_CR_OS0_CNN_CRC_ADDRESS_CNN_CRC_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF000000007F))
- #define VHA_CR_OS0_CNN_CRC_ADDRESS_CNN_CRC_ADDR_ALIGNSHIFT (7U)
- #define VHA_CR_OS0_CNN_CRC_ADDRESS_CNN_CRC_ADDR_ALIGNSIZE (128U)
- /*
- Register VHA_CR_OS0_CNN_DEBUG_ADDRESS
- */
- #define VHA_CR_OS0_CNN_DEBUG_ADDRESS (0x30098U)
- #define VHA_CR_OS0_CNN_DEBUG_ADDRESS_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFF80))
- #define VHA_CR_OS0_CNN_DEBUG_ADDRESS_CNN_DEBUG_ADDR_SHIFT (7U)
- #define VHA_CR_OS0_CNN_DEBUG_ADDRESS_CNN_DEBUG_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF000000007F))
- #define VHA_CR_OS0_CNN_DEBUG_ADDRESS_CNN_DEBUG_ADDR_ALIGNSHIFT (7U)
- #define VHA_CR_OS0_CNN_DEBUG_ADDRESS_CNN_DEBUG_ADDR_ALIGNSIZE (128U)
- /*
- Register VHA_CR_OS0_CNN_DEBUG_SIZE_LEGACY
- */
- #define VHA_CR_OS0_CNN_DEBUG_SIZE_LEGACY (0x300A0U)
- #define VHA_CR_OS0_CNN_DEBUG_SIZE_LEGACY_MASKFULL (IMG_UINT64_C(0x0000000000FFFFE0))
- #define VHA_CR_OS0_CNN_DEBUG_SIZE_LEGACY_CNN_DEBUG_SIZE_SHIFT (5U)
- #define VHA_CR_OS0_CNN_DEBUG_SIZE_LEGACY_CNN_DEBUG_SIZE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF00001F))
- #define VHA_CR_OS0_CNN_DEBUG_SIZE_LEGACY_CNN_DEBUG_SIZE_ALIGNSHIFT (5U)
- #define VHA_CR_OS0_CNN_DEBUG_SIZE_LEGACY_CNN_DEBUG_SIZE_ALIGNSIZE (32U)
- /*
- Register VHA_CR_OS0_CNN_DEBUG_CONTROL
- */
- #define VHA_CR_OS0_CNN_DEBUG_CONTROL (0x300A8U)
- #define VHA_CR_OS0_CNN_DEBUG_CONTROL_MASKFULL (IMG_UINT64_C(0x000000000000000F))
- #define VHA_CR_OS0_CNN_DEBUG_CONTROL_CNN_PERF_ENABLE_SHIFT (2U)
- #define VHA_CR_OS0_CNN_DEBUG_CONTROL_CNN_PERF_ENABLE_CLRMSK (0XFFFFFFF3U)
- #define VHA_CR_OS0_CNN_DEBUG_CONTROL_CNN_PERF_ENABLE_DISABLE (00000000U)
- #define VHA_CR_OS0_CNN_DEBUG_CONTROL_CNN_PERF_ENABLE_STREAM (0X00000004U)
- #define VHA_CR_OS0_CNN_DEBUG_CONTROL_CNN_PERF_ENABLE_LAYER (0X00000008U)
- #define VHA_CR_OS0_CNN_DEBUG_CONTROL_CNN_PERF_ENABLE_PASS (0X0000000CU)
- #define VHA_CR_OS0_CNN_DEBUG_CONTROL_CNN_BAND_ENABLE_SHIFT (0U)
- #define VHA_CR_OS0_CNN_DEBUG_CONTROL_CNN_BAND_ENABLE_CLRMSK (0XFFFFFFFCU)
- #define VHA_CR_OS0_CNN_DEBUG_CONTROL_CNN_BAND_ENABLE_DISABLE (00000000U)
- #define VHA_CR_OS0_CNN_DEBUG_CONTROL_CNN_BAND_ENABLE_RESERVED (0X00000001U)
- #define VHA_CR_OS0_CNN_DEBUG_CONTROL_CNN_BAND_ENABLE_LAYER (0X00000002U)
- #define VHA_CR_OS0_CNN_DEBUG_CONTROL_CNN_BAND_ENABLE_PASS (0X00000003U)
- /*
- Register VHA_CR_OS0_CNN_DEBUG_STATUS
- */
- #define VHA_CR_OS0_CNN_DEBUG_STATUS (0x300B0U)
- #define VHA_CR_OS0_CNN_DEBUG_STATUS_MASKFULL (IMG_UINT64_C(0x000000000007FFFF))
- #define VHA_CR_OS0_CNN_DEBUG_STATUS_CNN_DEBUG_OFFSET_SHIFT (0U)
- #define VHA_CR_OS0_CNN_DEBUG_STATUS_CNN_DEBUG_OFFSET_CLRMSK (0XFFF80000U)
- /*
- Register VHA_CR_OS0_CNN_PRELOAD_CONTROL
- */
- #define VHA_CR_OS0_CNN_PRELOAD_CONTROL (0x300B8U)
- #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MASKFULL (IMG_UINT64_C(0x0000000001FF7777))
- #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_SHIFT (22U)
- #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFE3FFFFF))
- #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_DISABLE (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_N_64 (IMG_UINT64_C(0x0000000000400000))
- #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_N_128 (IMG_UINT64_C(0x0000000000800000))
- #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_N_192 (IMG_UINT64_C(0x0000000000c00000))
- #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_N_256 (IMG_UINT64_C(0x0000000001000000))
- #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_N_320 (IMG_UINT64_C(0x0000000001400000))
- #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_N_384 (IMG_UINT64_C(0x0000000001800000))
- #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_N_448 (IMG_UINT64_C(0x0000000001c00000))
- #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_SHIFT (19U)
- #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFC7FFFF))
- #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_DISABLE (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_N_64 (IMG_UINT64_C(0x0000000000080000))
- #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_N_128 (IMG_UINT64_C(0x0000000000100000))
- #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_N_192 (IMG_UINT64_C(0x0000000000180000))
- #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_N_256 (IMG_UINT64_C(0x0000000000200000))
- #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_N_320 (IMG_UINT64_C(0x0000000000280000))
- #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_N_384 (IMG_UINT64_C(0x0000000000300000))
- #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_N_448 (IMG_UINT64_C(0x0000000000380000))
- #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_SHIFT (16U)
- #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF8FFFF))
- #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_DISABLE (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_N_64 (IMG_UINT64_C(0x0000000000010000))
- #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_N_128 (IMG_UINT64_C(0x0000000000020000))
- #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_N_192 (IMG_UINT64_C(0x0000000000030000))
- #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_N_256 (IMG_UINT64_C(0x0000000000040000))
- #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_N_320 (IMG_UINT64_C(0x0000000000050000))
- #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_N_384 (IMG_UINT64_C(0x0000000000060000))
- #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_N_448 (IMG_UINT64_C(0x0000000000070000))
- #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_EWO_N_REQS_SHIFT (12U)
- #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_EWO_N_REQS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF8FFF))
- #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_EWO_N_REQS_DISABLE (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_EWO_N_REQS_N_64 (IMG_UINT64_C(0x0000000000001000))
- #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_EWO_N_REQS_N_128 (IMG_UINT64_C(0x0000000000002000))
- #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_EWO_N_REQS_N_192 (IMG_UINT64_C(0x0000000000003000))
- #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_EWO_N_REQS_N_256 (IMG_UINT64_C(0x0000000000004000))
- #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_EWO_N_REQS_N_320 (IMG_UINT64_C(0x0000000000005000))
- #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_EWO_N_REQS_N_384 (IMG_UINT64_C(0x0000000000006000))
- #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_EWO_N_REQS_N_448 (IMG_UINT64_C(0x0000000000007000))
- #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_ABUF_N_REQS_SHIFT (8U)
- #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_ABUF_N_REQS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF8FF))
- #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_ABUF_N_REQS_DISABLE (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_ABUF_N_REQS_N_64 (IMG_UINT64_C(0x0000000000000100))
- #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_ABUF_N_REQS_N_128 (IMG_UINT64_C(0x0000000000000200))
- #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_ABUF_N_REQS_N_192 (IMG_UINT64_C(0x0000000000000300))
- #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_ABUF_N_REQS_N_256 (IMG_UINT64_C(0x0000000000000400))
- #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_ABUF_N_REQS_N_320 (IMG_UINT64_C(0x0000000000000500))
- #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_ABUF_N_REQS_N_384 (IMG_UINT64_C(0x0000000000000600))
- #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_ABUF_N_REQS_N_448 (IMG_UINT64_C(0x0000000000000700))
- #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_CBUF_N_REQS_SHIFT (4U)
- #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_CBUF_N_REQS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFF8F))
- #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_CBUF_N_REQS_DISABLE (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_CBUF_N_REQS_N_64 (IMG_UINT64_C(0x0000000000000010))
- #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_CBUF_N_REQS_N_128 (IMG_UINT64_C(0x0000000000000020))
- #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_CBUF_N_REQS_N_192 (IMG_UINT64_C(0x0000000000000030))
- #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_CBUF_N_REQS_N_256 (IMG_UINT64_C(0x0000000000000040))
- #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_CBUF_N_REQS_N_320 (IMG_UINT64_C(0x0000000000000050))
- #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_CBUF_N_REQS_N_384 (IMG_UINT64_C(0x0000000000000060))
- #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_CBUF_N_REQS_N_448 (IMG_UINT64_C(0x0000000000000070))
- #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_IBUF_N_REQS_SHIFT (0U)
- #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_IBUF_N_REQS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF8))
- #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_IBUF_N_REQS_DISABLE (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_IBUF_N_REQS_N_64 (IMG_UINT64_C(0x0000000000000001))
- #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_IBUF_N_REQS_N_128 (IMG_UINT64_C(0x0000000000000002))
- #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_IBUF_N_REQS_N_192 (IMG_UINT64_C(0x0000000000000003))
- #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_IBUF_N_REQS_N_256 (IMG_UINT64_C(0x0000000000000004))
- #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_IBUF_N_REQS_N_320 (IMG_UINT64_C(0x0000000000000005))
- #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_IBUF_N_REQS_N_384 (IMG_UINT64_C(0x0000000000000006))
- #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_IBUF_N_REQS_N_448 (IMG_UINT64_C(0x0000000000000007))
- /*
- Register VHA_CR_OS0_CNN_ALT_ADDRESS8
- */
- #define VHA_CR_OS0_CNN_ALT_ADDRESS8 (0x300C0U)
- #define VHA_CR_OS0_CNN_ALT_ADDRESS8_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS8_ALT_ADDR_SHIFT (0U)
- #define VHA_CR_OS0_CNN_ALT_ADDRESS8_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
- /*
- Register VHA_CR_OS0_CNN_ALT_ADDRESS9
- */
- #define VHA_CR_OS0_CNN_ALT_ADDRESS9 (0x300C8U)
- #define VHA_CR_OS0_CNN_ALT_ADDRESS9_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS9_ALT_ADDR_SHIFT (0U)
- #define VHA_CR_OS0_CNN_ALT_ADDRESS9_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
- /*
- Register VHA_CR_OS0_CNN_ALT_ADDRESS10
- */
- #define VHA_CR_OS0_CNN_ALT_ADDRESS10 (0x300D0U)
- #define VHA_CR_OS0_CNN_ALT_ADDRESS10_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS10_ALT_ADDR_SHIFT (0U)
- #define VHA_CR_OS0_CNN_ALT_ADDRESS10_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
- /*
- Register VHA_CR_OS0_CNN_ALT_ADDRESS11
- */
- #define VHA_CR_OS0_CNN_ALT_ADDRESS11 (0x300D8U)
- #define VHA_CR_OS0_CNN_ALT_ADDRESS11_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS11_ALT_ADDR_SHIFT (0U)
- #define VHA_CR_OS0_CNN_ALT_ADDRESS11_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
- /*
- Register VHA_CR_OS0_CNN_ALT_ADDRESS12
- */
- #define VHA_CR_OS0_CNN_ALT_ADDRESS12 (0x300E0U)
- #define VHA_CR_OS0_CNN_ALT_ADDRESS12_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS12_ALT_ADDR_SHIFT (0U)
- #define VHA_CR_OS0_CNN_ALT_ADDRESS12_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
- /*
- Register VHA_CR_OS0_CNN_ALT_ADDRESS13
- */
- #define VHA_CR_OS0_CNN_ALT_ADDRESS13 (0x300E8U)
- #define VHA_CR_OS0_CNN_ALT_ADDRESS13_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS13_ALT_ADDR_SHIFT (0U)
- #define VHA_CR_OS0_CNN_ALT_ADDRESS13_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
- /*
- Register VHA_CR_OS0_CNN_ALT_ADDRESS14
- */
- #define VHA_CR_OS0_CNN_ALT_ADDRESS14 (0x300F0U)
- #define VHA_CR_OS0_CNN_ALT_ADDRESS14_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS14_ALT_ADDR_SHIFT (0U)
- #define VHA_CR_OS0_CNN_ALT_ADDRESS14_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
- /*
- Register VHA_CR_OS0_CNN_ALT_ADDRESS15
- */
- #define VHA_CR_OS0_CNN_ALT_ADDRESS15 (0x300F8U)
- #define VHA_CR_OS0_CNN_ALT_ADDRESS15_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
- #define VHA_CR_OS0_CNN_ALT_ADDRESS15_ALT_ADDR_SHIFT (0U)
- #define VHA_CR_OS0_CNN_ALT_ADDRESS15_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
- /*
- Register VHA_CR_OS0_CNN_PERFORMANCE
- */
- #define VHA_CR_OS0_CNN_PERFORMANCE (0x30100U)
- #define VHA_CR_OS0_CNN_PERFORMANCE_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_OS0_CNN_PERFORMANCE_VALUE_SHIFT (0U)
- #define VHA_CR_OS0_CNN_PERFORMANCE_VALUE_CLRMSK (00000000U)
- /*
- Register VHA_CR_OS0_LOCM_BASE_ADDR
- */
- #define VHA_CR_OS0_LOCM_BASE_ADDR (0x30108U)
- #define VHA_CR_OS0_LOCM_BASE_ADDR_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFE0))
- #define VHA_CR_OS0_LOCM_BASE_ADDR_BASE_ADDR_SHIFT (5U)
- #define VHA_CR_OS0_LOCM_BASE_ADDR_BASE_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF000000001F))
- /*
- Register VHA_CR_OS0_SAVE_RESTORE_BUFFER_BASE_ADDR
- */
- #define VHA_CR_OS0_SAVE_RESTORE_BUFFER_BASE_ADDR (0x30110U)
- #define VHA_CR_OS0_SAVE_RESTORE_BUFFER_BASE_ADDR_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
- #define VHA_CR_OS0_SAVE_RESTORE_BUFFER_BASE_ADDR_BASE_ADDR_SHIFT (0U)
- #define VHA_CR_OS0_SAVE_RESTORE_BUFFER_BASE_ADDR_BASE_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
- /*
- Register VHA_CR_OS0_SAVE_RESTORE_CTRL
- */
- #define VHA_CR_OS0_SAVE_RESTORE_CTRL (0x30118U)
- #define VHA_CR_OS0_SAVE_RESTORE_CTRL_MASKFULL (IMG_UINT64_C(0x000000000000000F))
- #define VHA_CR_OS0_SAVE_RESTORE_CTRL_N_REQS_SHIFT (1U)
- #define VHA_CR_OS0_SAVE_RESTORE_CTRL_N_REQS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF1))
- #define VHA_CR_OS0_SAVE_RESTORE_CTRL_N_REQS_DISABLE (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_OS0_SAVE_RESTORE_CTRL_N_REQS_N_64 (IMG_UINT64_C(0x0000000000000002))
- #define VHA_CR_OS0_SAVE_RESTORE_CTRL_N_REQS_N_128 (IMG_UINT64_C(0x0000000000000004))
- #define VHA_CR_OS0_SAVE_RESTORE_CTRL_N_REQS_N_192 (IMG_UINT64_C(0x0000000000000006))
- #define VHA_CR_OS0_SAVE_RESTORE_CTRL_N_REQS_N_256 (IMG_UINT64_C(0x0000000000000008))
- #define VHA_CR_OS0_SAVE_RESTORE_CTRL_N_REQS_N_320 (IMG_UINT64_C(0x000000000000000a))
- #define VHA_CR_OS0_SAVE_RESTORE_CTRL_N_REQS_N_384 (IMG_UINT64_C(0x000000000000000c))
- #define VHA_CR_OS0_SAVE_RESTORE_CTRL_N_REQS_N_448 (IMG_UINT64_C(0x000000000000000e))
- #define VHA_CR_OS0_SAVE_RESTORE_CTRL_WRITE_CACHE_POLICY_SHIFT (0U)
- #define VHA_CR_OS0_SAVE_RESTORE_CTRL_WRITE_CACHE_POLICY_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
- #define VHA_CR_OS0_SAVE_RESTORE_CTRL_WRITE_CACHE_POLICY_EN (IMG_UINT64_C(0X0000000000000001))
- /*
- Register VHA_CR_OS0_CNN_CRC_MASK_CTRL
- */
- #define VHA_CR_OS0_CNN_CRC_MASK_CTRL (0x30120U)
- #define VHA_CR_OS0_CNN_CRC_MASK_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000000003))
- #define VHA_CR_OS0_CNN_CRC_MASK_CTRL_LEVEL_SHIFT (0U)
- #define VHA_CR_OS0_CNN_CRC_MASK_CTRL_LEVEL_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFC))
- #define VHA_CR_OS0_CNN_CRC_MASK_CTRL_LEVEL_DEBUG_INTERNAL (IMG_UINT64_C(0000000000000000))
- #define VHA_CR_OS0_CNN_CRC_MASK_CTRL_LEVEL_DEBUG_SILICON (IMG_UINT64_C(0x0000000000000001))
- #define VHA_CR_OS0_CNN_CRC_MASK_CTRL_LEVEL_SAFETY (IMG_UINT64_C(0x0000000000000002))
- #define VHA_CR_OS0_CNN_CRC_MASK_CTRL_LEVEL_RESERVED (IMG_UINT64_C(0x0000000000000003))
- /*
- Register VHA_CR_OS0_CNN_VCORE_MAPPING
- */
- #define VHA_CR_OS0_CNN_VCORE_MAPPING (0x30128U)
- #define VHA_CR_OS0_CNN_VCORE_MAPPING_MASKFULL (IMG_UINT64_C(0x0000000077777777))
- #define VHA_CR_OS0_CNN_VCORE_MAPPING_VCORE7_SHIFT (28U)
- #define VHA_CR_OS0_CNN_VCORE_MAPPING_VCORE7_CLRMSK (IMG_UINT64_C(0XFFFFFFFF8FFFFFFF))
- #define VHA_CR_OS0_CNN_VCORE_MAPPING_VCORE6_SHIFT (24U)
- #define VHA_CR_OS0_CNN_VCORE_MAPPING_VCORE6_CLRMSK (IMG_UINT64_C(0XFFFFFFFFF8FFFFFF))
- #define VHA_CR_OS0_CNN_VCORE_MAPPING_VCORE5_SHIFT (20U)
- #define VHA_CR_OS0_CNN_VCORE_MAPPING_VCORE5_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF8FFFFF))
- #define VHA_CR_OS0_CNN_VCORE_MAPPING_VCORE4_SHIFT (16U)
- #define VHA_CR_OS0_CNN_VCORE_MAPPING_VCORE4_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF8FFFF))
- #define VHA_CR_OS0_CNN_VCORE_MAPPING_VCORE3_SHIFT (12U)
- #define VHA_CR_OS0_CNN_VCORE_MAPPING_VCORE3_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF8FFF))
- #define VHA_CR_OS0_CNN_VCORE_MAPPING_VCORE2_SHIFT (8U)
- #define VHA_CR_OS0_CNN_VCORE_MAPPING_VCORE2_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF8FF))
- #define VHA_CR_OS0_CNN_VCORE_MAPPING_VCORE1_SHIFT (4U)
- #define VHA_CR_OS0_CNN_VCORE_MAPPING_VCORE1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFF8F))
- #define VHA_CR_OS0_CNN_VCORE_MAPPING_VCORE0_SHIFT (0U)
- #define VHA_CR_OS0_CNN_VCORE_MAPPING_VCORE0_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF8))
- /*
- Register VHA_CR_CORE0_LAST_NNA_SYNC_ID
- */
- #define VHA_CR_CORE0_LAST_NNA_SYNC_ID (0x30130U)
- #define VHA_CR_CORE0_LAST_NNA_SYNC_ID_MASKFULL (IMG_UINT64_C(0x0000000070FFFFFF))
- #define VHA_CR_CORE0_LAST_NNA_SYNC_ID_CORE0_LAST_NNA_SYNC_ID_PARITY_SHIFT (28U)
- #define VHA_CR_CORE0_LAST_NNA_SYNC_ID_CORE0_LAST_NNA_SYNC_ID_PARITY_CLRMSK (IMG_UINT64_C(0XFFFFFFFF8FFFFFFF))
- #define VHA_CR_CORE0_LAST_NNA_SYNC_ID_CORE0_LAST_NNA_SYNC_ID_SHIFT (0U)
- #define VHA_CR_CORE0_LAST_NNA_SYNC_ID_CORE0_LAST_NNA_SYNC_ID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF000000))
- /*
- Register VHA_CR_CORE1_LAST_NNA_SYNC_ID
- */
- #define VHA_CR_CORE1_LAST_NNA_SYNC_ID (0x30138U)
- #define VHA_CR_CORE1_LAST_NNA_SYNC_ID_MASKFULL (IMG_UINT64_C(0x0000000070FFFFFF))
- #define VHA_CR_CORE1_LAST_NNA_SYNC_ID_CORE1_LAST_NNA_SYNC_ID_PARITY_SHIFT (28U)
- #define VHA_CR_CORE1_LAST_NNA_SYNC_ID_CORE1_LAST_NNA_SYNC_ID_PARITY_CLRMSK (IMG_UINT64_C(0XFFFFFFFF8FFFFFFF))
- #define VHA_CR_CORE1_LAST_NNA_SYNC_ID_CORE1_LAST_NNA_SYNC_ID_SHIFT (0U)
- #define VHA_CR_CORE1_LAST_NNA_SYNC_ID_CORE1_LAST_NNA_SYNC_ID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF000000))
- /*
- Register VHA_CR_CORE2_LAST_NNA_SYNC_ID
- */
- #define VHA_CR_CORE2_LAST_NNA_SYNC_ID (0x30140U)
- #define VHA_CR_CORE2_LAST_NNA_SYNC_ID_MASKFULL (IMG_UINT64_C(0x0000000070FFFFFF))
- #define VHA_CR_CORE2_LAST_NNA_SYNC_ID_CORE2_LAST_NNA_SYNC_ID_PARITY_SHIFT (28U)
- #define VHA_CR_CORE2_LAST_NNA_SYNC_ID_CORE2_LAST_NNA_SYNC_ID_PARITY_CLRMSK (IMG_UINT64_C(0XFFFFFFFF8FFFFFFF))
- #define VHA_CR_CORE2_LAST_NNA_SYNC_ID_CORE2_LAST_NNA_SYNC_ID_SHIFT (0U)
- #define VHA_CR_CORE2_LAST_NNA_SYNC_ID_CORE2_LAST_NNA_SYNC_ID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF000000))
- /*
- Register VHA_CR_CORE3_LAST_NNA_SYNC_ID
- */
- #define VHA_CR_CORE3_LAST_NNA_SYNC_ID (0x30148U)
- #define VHA_CR_CORE3_LAST_NNA_SYNC_ID_MASKFULL (IMG_UINT64_C(0x0000000070FFFFFF))
- #define VHA_CR_CORE3_LAST_NNA_SYNC_ID_CORE3_LAST_NNA_SYNC_ID_PARITY_SHIFT (28U)
- #define VHA_CR_CORE3_LAST_NNA_SYNC_ID_CORE3_LAST_NNA_SYNC_ID_PARITY_CLRMSK (IMG_UINT64_C(0XFFFFFFFF8FFFFFFF))
- #define VHA_CR_CORE3_LAST_NNA_SYNC_ID_CORE3_LAST_NNA_SYNC_ID_SHIFT (0U)
- #define VHA_CR_CORE3_LAST_NNA_SYNC_ID_CORE3_LAST_NNA_SYNC_ID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF000000))
- /*
- Register VHA_CR_CORE4_LAST_NNA_SYNC_ID
- */
- #define VHA_CR_CORE4_LAST_NNA_SYNC_ID (0x30150U)
- #define VHA_CR_CORE4_LAST_NNA_SYNC_ID_MASKFULL (IMG_UINT64_C(0x0000000070FFFFFF))
- #define VHA_CR_CORE4_LAST_NNA_SYNC_ID_CORE4_LAST_NNA_SYNC_ID_PARITY_SHIFT (28U)
- #define VHA_CR_CORE4_LAST_NNA_SYNC_ID_CORE4_LAST_NNA_SYNC_ID_PARITY_CLRMSK (IMG_UINT64_C(0XFFFFFFFF8FFFFFFF))
- #define VHA_CR_CORE4_LAST_NNA_SYNC_ID_CORE4_LAST_NNA_SYNC_ID_SHIFT (0U)
- #define VHA_CR_CORE4_LAST_NNA_SYNC_ID_CORE4_LAST_NNA_SYNC_ID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF000000))
- /*
- Register VHA_CR_CORE5_LAST_NNA_SYNC_ID
- */
- #define VHA_CR_CORE5_LAST_NNA_SYNC_ID (0x30158U)
- #define VHA_CR_CORE5_LAST_NNA_SYNC_ID_MASKFULL (IMG_UINT64_C(0x0000000070FFFFFF))
- #define VHA_CR_CORE5_LAST_NNA_SYNC_ID_CORE5_LAST_NNA_SYNC_ID_PARITY_SHIFT (28U)
- #define VHA_CR_CORE5_LAST_NNA_SYNC_ID_CORE5_LAST_NNA_SYNC_ID_PARITY_CLRMSK (IMG_UINT64_C(0XFFFFFFFF8FFFFFFF))
- #define VHA_CR_CORE5_LAST_NNA_SYNC_ID_CORE5_LAST_NNA_SYNC_ID_SHIFT (0U)
- #define VHA_CR_CORE5_LAST_NNA_SYNC_ID_CORE5_LAST_NNA_SYNC_ID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF000000))
- /*
- Register VHA_CR_CORE6_LAST_NNA_SYNC_ID
- */
- #define VHA_CR_CORE6_LAST_NNA_SYNC_ID (0x30160U)
- #define VHA_CR_CORE6_LAST_NNA_SYNC_ID_MASKFULL (IMG_UINT64_C(0x0000000070FFFFFF))
- #define VHA_CR_CORE6_LAST_NNA_SYNC_ID_CORE6_LAST_NNA_SYNC_ID_PARITY_SHIFT (28U)
- #define VHA_CR_CORE6_LAST_NNA_SYNC_ID_CORE6_LAST_NNA_SYNC_ID_PARITY_CLRMSK (IMG_UINT64_C(0XFFFFFFFF8FFFFFFF))
- #define VHA_CR_CORE6_LAST_NNA_SYNC_ID_CORE6_LAST_NNA_SYNC_ID_SHIFT (0U)
- #define VHA_CR_CORE6_LAST_NNA_SYNC_ID_CORE6_LAST_NNA_SYNC_ID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF000000))
- /*
- Register VHA_CR_CORE7_LAST_NNA_SYNC_ID
- */
- #define VHA_CR_CORE7_LAST_NNA_SYNC_ID (0x30168U)
- #define VHA_CR_CORE7_LAST_NNA_SYNC_ID_MASKFULL (IMG_UINT64_C(0x0000000070FFFFFF))
- #define VHA_CR_CORE7_LAST_NNA_SYNC_ID_CORE7_LAST_NNA_SYNC_ID_PARITY_SHIFT (28U)
- #define VHA_CR_CORE7_LAST_NNA_SYNC_ID_CORE7_LAST_NNA_SYNC_ID_PARITY_CLRMSK (IMG_UINT64_C(0XFFFFFFFF8FFFFFFF))
- #define VHA_CR_CORE7_LAST_NNA_SYNC_ID_CORE7_LAST_NNA_SYNC_ID_SHIFT (0U)
- #define VHA_CR_CORE7_LAST_NNA_SYNC_ID_CORE7_LAST_NNA_SYNC_ID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF000000))
- /*
- Register VHA_CR_CORE0_LAST_MMM_SYNC_ID
- */
- #define VHA_CR_CORE0_LAST_MMM_SYNC_ID (0x30230U)
- #define VHA_CR_CORE0_LAST_MMM_SYNC_ID_MASKFULL (IMG_UINT64_C(0x0000000070FFFFFF))
- #define VHA_CR_CORE0_LAST_MMM_SYNC_ID_CORE0_LAST_MMM_SYNC_ID_PARITY_SHIFT (28U)
- #define VHA_CR_CORE0_LAST_MMM_SYNC_ID_CORE0_LAST_MMM_SYNC_ID_PARITY_CLRMSK (IMG_UINT64_C(0XFFFFFFFF8FFFFFFF))
- #define VHA_CR_CORE0_LAST_MMM_SYNC_ID_CORE0_LAST_MMM_SYNC_ID_SHIFT (0U)
- #define VHA_CR_CORE0_LAST_MMM_SYNC_ID_CORE0_LAST_MMM_SYNC_ID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF000000))
- /*
- Register VHA_CR_CORE1_LAST_MMM_SYNC_ID
- */
- #define VHA_CR_CORE1_LAST_MMM_SYNC_ID (0x30238U)
- #define VHA_CR_CORE1_LAST_MMM_SYNC_ID_MASKFULL (IMG_UINT64_C(0x0000000070FFFFFF))
- #define VHA_CR_CORE1_LAST_MMM_SYNC_ID_CORE1_LAST_MMM_SYNC_ID_PARITY_SHIFT (28U)
- #define VHA_CR_CORE1_LAST_MMM_SYNC_ID_CORE1_LAST_MMM_SYNC_ID_PARITY_CLRMSK (IMG_UINT64_C(0XFFFFFFFF8FFFFFFF))
- #define VHA_CR_CORE1_LAST_MMM_SYNC_ID_CORE1_LAST_MMM_SYNC_ID_SHIFT (0U)
- #define VHA_CR_CORE1_LAST_MMM_SYNC_ID_CORE1_LAST_MMM_SYNC_ID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF000000))
- /*
- Register VHA_CR_CORE2_LAST_MMM_SYNC_ID
- */
- #define VHA_CR_CORE2_LAST_MMM_SYNC_ID (0x30240U)
- #define VHA_CR_CORE2_LAST_MMM_SYNC_ID_MASKFULL (IMG_UINT64_C(0x0000000070FFFFFF))
- #define VHA_CR_CORE2_LAST_MMM_SYNC_ID_CORE2_LAST_MMM_SYNC_ID_PARITY_SHIFT (28U)
- #define VHA_CR_CORE2_LAST_MMM_SYNC_ID_CORE2_LAST_MMM_SYNC_ID_PARITY_CLRMSK (IMG_UINT64_C(0XFFFFFFFF8FFFFFFF))
- #define VHA_CR_CORE2_LAST_MMM_SYNC_ID_CORE2_LAST_MMM_SYNC_ID_SHIFT (0U)
- #define VHA_CR_CORE2_LAST_MMM_SYNC_ID_CORE2_LAST_MMM_SYNC_ID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF000000))
- /*
- Register VHA_CR_CORE3_LAST_MMM_SYNC_ID
- */
- #define VHA_CR_CORE3_LAST_MMM_SYNC_ID (0x30248U)
- #define VHA_CR_CORE3_LAST_MMM_SYNC_ID_MASKFULL (IMG_UINT64_C(0x0000000070FFFFFF))
- #define VHA_CR_CORE3_LAST_MMM_SYNC_ID_CORE3_LAST_MMM_SYNC_ID_PARITY_SHIFT (28U)
- #define VHA_CR_CORE3_LAST_MMM_SYNC_ID_CORE3_LAST_MMM_SYNC_ID_PARITY_CLRMSK (IMG_UINT64_C(0XFFFFFFFF8FFFFFFF))
- #define VHA_CR_CORE3_LAST_MMM_SYNC_ID_CORE3_LAST_MMM_SYNC_ID_SHIFT (0U)
- #define VHA_CR_CORE3_LAST_MMM_SYNC_ID_CORE3_LAST_MMM_SYNC_ID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF000000))
- /*
- Register VHA_CR_CORE4_LAST_MMM_SYNC_ID
- */
- #define VHA_CR_CORE4_LAST_MMM_SYNC_ID (0x30250U)
- #define VHA_CR_CORE4_LAST_MMM_SYNC_ID_MASKFULL (IMG_UINT64_C(0x0000000070FFFFFF))
- #define VHA_CR_CORE4_LAST_MMM_SYNC_ID_CORE4_LAST_MMM_SYNC_ID_PARITY_SHIFT (28U)
- #define VHA_CR_CORE4_LAST_MMM_SYNC_ID_CORE4_LAST_MMM_SYNC_ID_PARITY_CLRMSK (IMG_UINT64_C(0XFFFFFFFF8FFFFFFF))
- #define VHA_CR_CORE4_LAST_MMM_SYNC_ID_CORE4_LAST_MMM_SYNC_ID_SHIFT (0U)
- #define VHA_CR_CORE4_LAST_MMM_SYNC_ID_CORE4_LAST_MMM_SYNC_ID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF000000))
- /*
- Register VHA_CR_CORE5_LAST_MMM_SYNC_ID
- */
- #define VHA_CR_CORE5_LAST_MMM_SYNC_ID (0x30258U)
- #define VHA_CR_CORE5_LAST_MMM_SYNC_ID_MASKFULL (IMG_UINT64_C(0x0000000070FFFFFF))
- #define VHA_CR_CORE5_LAST_MMM_SYNC_ID_CORE5_LAST_MMM_SYNC_ID_PARITY_SHIFT (28U)
- #define VHA_CR_CORE5_LAST_MMM_SYNC_ID_CORE5_LAST_MMM_SYNC_ID_PARITY_CLRMSK (IMG_UINT64_C(0XFFFFFFFF8FFFFFFF))
- #define VHA_CR_CORE5_LAST_MMM_SYNC_ID_CORE5_LAST_MMM_SYNC_ID_SHIFT (0U)
- #define VHA_CR_CORE5_LAST_MMM_SYNC_ID_CORE5_LAST_MMM_SYNC_ID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF000000))
- /*
- Register VHA_CR_CORE6_LAST_MMM_SYNC_ID
- */
- #define VHA_CR_CORE6_LAST_MMM_SYNC_ID (0x30260U)
- #define VHA_CR_CORE6_LAST_MMM_SYNC_ID_MASKFULL (IMG_UINT64_C(0x0000000070FFFFFF))
- #define VHA_CR_CORE6_LAST_MMM_SYNC_ID_CORE6_LAST_MMM_SYNC_ID_PARITY_SHIFT (28U)
- #define VHA_CR_CORE6_LAST_MMM_SYNC_ID_CORE6_LAST_MMM_SYNC_ID_PARITY_CLRMSK (IMG_UINT64_C(0XFFFFFFFF8FFFFFFF))
- #define VHA_CR_CORE6_LAST_MMM_SYNC_ID_CORE6_LAST_MMM_SYNC_ID_SHIFT (0U)
- #define VHA_CR_CORE6_LAST_MMM_SYNC_ID_CORE6_LAST_MMM_SYNC_ID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF000000))
- /*
- Register VHA_CR_CORE7_LAST_MMM_SYNC_ID
- */
- #define VHA_CR_CORE7_LAST_MMM_SYNC_ID (0x30268U)
- #define VHA_CR_CORE7_LAST_MMM_SYNC_ID_MASKFULL (IMG_UINT64_C(0x0000000070FFFFFF))
- #define VHA_CR_CORE7_LAST_MMM_SYNC_ID_CORE7_LAST_MMM_SYNC_ID_PARITY_SHIFT (28U)
- #define VHA_CR_CORE7_LAST_MMM_SYNC_ID_CORE7_LAST_MMM_SYNC_ID_PARITY_CLRMSK (IMG_UINT64_C(0XFFFFFFFF8FFFFFFF))
- #define VHA_CR_CORE7_LAST_MMM_SYNC_ID_CORE7_LAST_MMM_SYNC_ID_SHIFT (0U)
- #define VHA_CR_CORE7_LAST_MMM_SYNC_ID_CORE7_LAST_MMM_SYNC_ID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF000000))
- /*
- Register VHA_CR_CNN_CORE_SYNC_WDT_CTRL
- */
- #define VHA_CR_CNN_CORE_SYNC_WDT_CTRL (0x30270U)
- #define VHA_CR_CNN_CORE_SYNC_WDT_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000FFFF01))
- #define VHA_CR_CNN_CORE_SYNC_WDT_CTRL_VALUE_SHIFT (8U)
- #define VHA_CR_CNN_CORE_SYNC_WDT_CTRL_VALUE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF0000FF))
- #define VHA_CR_CNN_CORE_SYNC_WDT_CTRL_ENABLE_SHIFT (0U)
- #define VHA_CR_CNN_CORE_SYNC_WDT_CTRL_ENABLE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
- #define VHA_CR_CNN_CORE_SYNC_WDT_CTRL_ENABLE_EN (IMG_UINT64_C(0X0000000000000001))
- /*
- Register VHA_CR_CORE_BW_LOCM_RD
- */
- #define VHA_CR_CORE_BW_LOCM_RD (0x30278U)
- #define VHA_CR_CORE_BW_LOCM_RD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_CORE_BW_LOCM_RD_BW_SHIFT (0U)
- #define VHA_CR_CORE_BW_LOCM_RD_BW_CLRMSK (IMG_UINT64_C(0XFFFFFFFF00000000))
- /*
- Register VHA_CR_CORE_BW_LOCM_WR
- */
- #define VHA_CR_CORE_BW_LOCM_WR (0x30280U)
- #define VHA_CR_CORE_BW_LOCM_WR_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_CORE_BW_LOCM_WR_BW_SHIFT (0U)
- #define VHA_CR_CORE_BW_LOCM_WR_BW_CLRMSK (IMG_UINT64_C(0XFFFFFFFF00000000))
- /*
- Register VHA_CR_CORE_BW_LOCM_MWR
- */
- #define VHA_CR_CORE_BW_LOCM_MWR (0x30288U)
- #define VHA_CR_CORE_BW_LOCM_MWR_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_CORE_BW_LOCM_MWR_BW_SHIFT (0U)
- #define VHA_CR_CORE_BW_LOCM_MWR_BW_CLRMSK (IMG_UINT64_C(0XFFFFFFFF00000000))
- /*
- Register VHA_CR_CORE_BW_LOCM_RD_WORD
- */
- #define VHA_CR_CORE_BW_LOCM_RD_WORD (0x30290U)
- #define VHA_CR_CORE_BW_LOCM_RD_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_CORE_BW_LOCM_RD_WORD_BW_SHIFT (0U)
- #define VHA_CR_CORE_BW_LOCM_RD_WORD_BW_CLRMSK (IMG_UINT64_C(0XFFFFFFFF00000000))
- /*
- Register VHA_CR_CORE_BW_LOCM_WR_WORD
- */
- #define VHA_CR_CORE_BW_LOCM_WR_WORD (0x30298U)
- #define VHA_CR_CORE_BW_LOCM_WR_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_CORE_BW_LOCM_WR_WORD_BW_SHIFT (0U)
- #define VHA_CR_CORE_BW_LOCM_WR_WORD_BW_CLRMSK (IMG_UINT64_C(0XFFFFFFFF00000000))
- /*
- Register VHA_CR_CORE_BW_TLC_RD
- */
- #define VHA_CR_CORE_BW_TLC_RD (0x30300U)
- #define VHA_CR_CORE_BW_TLC_RD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_CORE_BW_TLC_RD_BW_SHIFT (0U)
- #define VHA_CR_CORE_BW_TLC_RD_BW_CLRMSK (IMG_UINT64_C(0XFFFFFFFF00000000))
- /*
- Register VHA_CR_CORE_BW_TLC_WR
- */
- #define VHA_CR_CORE_BW_TLC_WR (0x30308U)
- #define VHA_CR_CORE_BW_TLC_WR_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_CORE_BW_TLC_WR_BW_SHIFT (0U)
- #define VHA_CR_CORE_BW_TLC_WR_BW_CLRMSK (IMG_UINT64_C(0XFFFFFFFF00000000))
- /*
- Register VHA_CR_CORE_BW_TLC_MWR
- */
- #define VHA_CR_CORE_BW_TLC_MWR (0x30310U)
- #define VHA_CR_CORE_BW_TLC_MWR_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_CORE_BW_TLC_MWR_BW_SHIFT (0U)
- #define VHA_CR_CORE_BW_TLC_MWR_BW_CLRMSK (IMG_UINT64_C(0XFFFFFFFF00000000))
- /*
- Register VHA_CR_CORE_BW_TLC_RD_WORD
- */
- #define VHA_CR_CORE_BW_TLC_RD_WORD (0x30318U)
- #define VHA_CR_CORE_BW_TLC_RD_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_CORE_BW_TLC_RD_WORD_BW_SHIFT (0U)
- #define VHA_CR_CORE_BW_TLC_RD_WORD_BW_CLRMSK (IMG_UINT64_C(0XFFFFFFFF00000000))
- /*
- Register VHA_CR_CORE_BW_TLC_WR_WORD
- */
- #define VHA_CR_CORE_BW_TLC_WR_WORD (0x30320U)
- #define VHA_CR_CORE_BW_TLC_WR_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_CORE_BW_TLC_WR_WORD_BW_SHIFT (0U)
- #define VHA_CR_CORE_BW_TLC_WR_WORD_BW_CLRMSK (IMG_UINT64_C(0XFFFFFFFF00000000))
- /*
- Register VHA_CR_OS0_COMBINED_CNN_CRC_ADDRESS
- */
- #define VHA_CR_OS0_COMBINED_CNN_CRC_ADDRESS (0x30328U)
- #define VHA_CR_OS0_COMBINED_CNN_CRC_ADDRESS_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFF80))
- #define VHA_CR_OS0_COMBINED_CNN_CRC_ADDRESS_CNN_CRC_ADDR_SHIFT (7U)
- #define VHA_CR_OS0_COMBINED_CNN_CRC_ADDRESS_CNN_CRC_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF000000007F))
- #define VHA_CR_OS0_COMBINED_CNN_CRC_ADDRESS_CNN_CRC_ADDR_ALIGNSHIFT (7U)
- #define VHA_CR_OS0_COMBINED_CNN_CRC_ADDRESS_CNN_CRC_ADDR_ALIGNSIZE (128U)
- /*
- Register VHA_CR_PERF_SLC_SNOOP_HITS
- */
- #define VHA_CR_PERF_SLC_SNOOP_HITS (0x7728U)
- #define VHA_CR_PERF_SLC_SNOOP_HITS_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_PERF_SLC_SNOOP_HITS_COUNT_SHIFT (0U)
- #define VHA_CR_PERF_SLC_SNOOP_HITS_COUNT_CLRMSK (00000000U)
- /*
- Register VHA_CR_PERF_SLC_SNOOP_MISSES
- */
- #define VHA_CR_PERF_SLC_SNOOP_MISSES (0x7730U)
- #define VHA_CR_PERF_SLC_SNOOP_MISSES_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
- #define VHA_CR_PERF_SLC_SNOOP_MISSES_COUNT_SHIFT (0U)
- #define VHA_CR_PERF_SLC_SNOOP_MISSES_COUNT_CLRMSK (00000000U)
- /*
- Register VHA_CR_SLC_CCM_CTRL
- */
- #define VHA_CR_SLC_CCM_CTRL (0x78F8U)
- #define VHA_CR_SLC_CCM_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000FF00FF))
- #define VHA_CR_SLC_CCM_CTRL_SPILL_AMOUNT_SHIFT (16U)
- #define VHA_CR_SLC_CCM_CTRL_SPILL_AMOUNT_CLRMSK (0XFF00FFFFU)
- #define VHA_CR_SLC_CCM_CTRL_SPILL_THRESHOLD_SHIFT (0U)
- #define VHA_CR_SLC_CCM_CTRL_SPILL_THRESHOLD_CLRMSK (0XFFFFFF00U)
- /*
- Register VHA_CR_SLC_CCM_STATUS
- */
- #define VHA_CR_SLC_CCM_STATUS (0x7900U)
- #define VHA_CR_SLC_CCM_STATUS_MASKFULL (IMG_UINT64_C(0x0FFFFFFFF10FF0FF))
- #define VHA_CR_SLC_CCM_STATUS_SNOOP_COUNT3_SHIFT (52U)
- #define VHA_CR_SLC_CCM_STATUS_SNOOP_COUNT3_CLRMSK (IMG_UINT64_C(0XF00FFFFFFFFFFFFF))
- #define VHA_CR_SLC_CCM_STATUS_SNOOP_COUNT2_SHIFT (44U)
- #define VHA_CR_SLC_CCM_STATUS_SNOOP_COUNT2_CLRMSK (IMG_UINT64_C(0XFFF00FFFFFFFFFFF))
- #define VHA_CR_SLC_CCM_STATUS_SNOOP_COUNT1_SHIFT (36U)
- #define VHA_CR_SLC_CCM_STATUS_SNOOP_COUNT1_CLRMSK (IMG_UINT64_C(0XFFFFF00FFFFFFFFF))
- #define VHA_CR_SLC_CCM_STATUS_SNOOP_COUNT0_SHIFT (28U)
- #define VHA_CR_SLC_CCM_STATUS_SNOOP_COUNT0_CLRMSK (IMG_UINT64_C(0XFFFFFFF00FFFFFFF))
- #define VHA_CR_SLC_CCM_STATUS_SPILLING_SHIFT (24U)
- #define VHA_CR_SLC_CCM_STATUS_SPILLING_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFEFFFFFF))
- #define VHA_CR_SLC_CCM_STATUS_SPILLING_EN (IMG_UINT64_C(0X0000000001000000))
- #define VHA_CR_SLC_CCM_STATUS_SPILL_ENTRIES_SHIFT (12U)
- #define VHA_CR_SLC_CCM_STATUS_SPILL_ENTRIES_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF00FFF))
- #define VHA_CR_SLC_CCM_STATUS_ACTIVE_ENTRIES_SHIFT (0U)
- #define VHA_CR_SLC_CCM_STATUS_ACTIVE_ENTRIES_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFF00))
- #endif /* _VHA_CR_MAGNA_H_ */
- /*****************************************************************************
- End of file (vha_cr_magna.h)
- *****************************************************************************/
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