vha_cr_magna.h 370 KB

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  1. /*************************************************************************/ /*!
  2. @Title Hardware definition file vha_cr_magna.h
  3. @Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved
  4. */ /**************************************************************************/
  5. /* **** Autogenerated C -- do not edit **** */
  6. /*
  7. */
  8. #ifndef _VHA_CR_MAGNA_H_
  9. #define _VHA_CR_MAGNA_H_
  10. #define VHA_CR_MAGNA_REVISION 1
  11. /*
  12. Register VHA_CR_TLC_WM_INDIRECT
  13. */
  14. #define VHA_CR_TLC_WM_INDIRECT (0x0908U)
  15. #define VHA_CR_TLC_WM_INDIRECT_MASKFULL (IMG_UINT64_C(0x0000000000000007))
  16. #define VHA_CR_TLC_WM_INDIRECT_ADDRESS_SHIFT (0U)
  17. #define VHA_CR_TLC_WM_INDIRECT_ADDRESS_CLRMSK (0XFFFFFFF8U)
  18. /*
  19. Register VHA_CR_TLC_MH_CORE_INDIRECT
  20. */
  21. #define VHA_CR_TLC_MH_CORE_INDIRECT (0x0900U)
  22. #define VHA_CR_TLC_MH_CORE_INDIRECT_MASKFULL (IMG_UINT64_C(0x00000000000000FF))
  23. #define VHA_CR_TLC_MH_CORE_INDIRECT_MASK_SHIFT (0U)
  24. #define VHA_CR_TLC_MH_CORE_INDIRECT_MASK_CLRMSK (0XFFFFFF00U)
  25. /*
  26. Register VHA_CR_IC_CORE_INDIRECT
  27. */
  28. #define VHA_CR_IC_CORE_INDIRECT (0x0900U)
  29. #define VHA_CR_IC_CORE_INDIRECT_MASKFULL (IMG_UINT64_C(0x00000000000000FF))
  30. #define VHA_CR_IC_CORE_INDIRECT_MASK_SHIFT (0U)
  31. #define VHA_CR_IC_CORE_INDIRECT_MASK_CLRMSK (0XFFFFFF00U)
  32. /*
  33. Register VHA_CR_CORE_CTRL_INDIRECT
  34. */
  35. #define VHA_CR_CORE_CTRL_INDIRECT (0x0900U)
  36. #define VHA_CR_CORE_CTRL_INDIRECT_MASKFULL (IMG_UINT64_C(0x00000000000000FF))
  37. #define VHA_CR_CORE_CTRL_INDIRECT_MASK_SHIFT (0U)
  38. #define VHA_CR_CORE_CTRL_INDIRECT_MASK_CLRMSK (0XFFFFFF00U)
  39. /*
  40. Register VHA_CR_CORE_MH_INDIRECT
  41. */
  42. #define VHA_CR_CORE_MH_INDIRECT (0x0900U)
  43. #define VHA_CR_CORE_MH_INDIRECT_MASKFULL (IMG_UINT64_C(0x00000000000000FF))
  44. #define VHA_CR_CORE_MH_INDIRECT_MASK_SHIFT (0U)
  45. #define VHA_CR_CORE_MH_INDIRECT_MASK_CLRMSK (0XFFFFFF00U)
  46. /*
  47. Register VHA_CR_CNN_TOP_INDIRECT
  48. */
  49. #define VHA_CR_CNN_TOP_INDIRECT (0x0900U)
  50. #define VHA_CR_CNN_TOP_INDIRECT_MASKFULL (IMG_UINT64_C(0x00000000000000FF))
  51. #define VHA_CR_CNN_TOP_INDIRECT_MASK_SHIFT (0U)
  52. #define VHA_CR_CNN_TOP_INDIRECT_MASK_CLRMSK (0XFFFFFF00U)
  53. /*
  54. Register VHA_CR_CNN_FE_INDIRECT
  55. */
  56. #define VHA_CR_CNN_FE_INDIRECT (0x0900U)
  57. #define VHA_CR_CNN_FE_INDIRECT_MASKFULL (IMG_UINT64_C(0x00000000000000FF))
  58. #define VHA_CR_CNN_FE_INDIRECT_MASK_SHIFT (0U)
  59. #define VHA_CR_CNN_FE_INDIRECT_MASK_CLRMSK (0XFFFFFF00U)
  60. /*
  61. Register VHA_CR_CNN_BE_INDIRECT
  62. */
  63. #define VHA_CR_CNN_BE_INDIRECT (0x0900U)
  64. #define VHA_CR_CNN_BE_INDIRECT_MASKFULL (IMG_UINT64_C(0x00000000000000FF))
  65. #define VHA_CR_CNN_BE_INDIRECT_MASK_SHIFT (0U)
  66. #define VHA_CR_CNN_BE_INDIRECT_MASK_CLRMSK (0XFFFFFF00U)
  67. #define VHA_CR_DOMAINSPLIT_TYPE_MASK (0x0000FFFFU)
  68. #define VHA_CR_DOMAINSPLIT_TYPE_RESERVED_SHIFT (9U)
  69. #define VHA_CR_DOMAINSPLIT_TYPE_RESERVED_CLRMSK (0XFFFF01FFU)
  70. #define VHA_CR_DOMAINSPLIT_TYPE_CORE7_SHIFT (8U)
  71. #define VHA_CR_DOMAINSPLIT_TYPE_CORE7_CLRMSK (0XFFFFFEFFU)
  72. #define VHA_CR_DOMAINSPLIT_TYPE_CORE7_EN (0X00000100U)
  73. #define VHA_CR_DOMAINSPLIT_TYPE_CORE6_SHIFT (7U)
  74. #define VHA_CR_DOMAINSPLIT_TYPE_CORE6_CLRMSK (0XFFFFFF7FU)
  75. #define VHA_CR_DOMAINSPLIT_TYPE_CORE6_EN (0X00000080U)
  76. #define VHA_CR_DOMAINSPLIT_TYPE_CORE5_SHIFT (6U)
  77. #define VHA_CR_DOMAINSPLIT_TYPE_CORE5_CLRMSK (0XFFFFFFBFU)
  78. #define VHA_CR_DOMAINSPLIT_TYPE_CORE5_EN (0X00000040U)
  79. #define VHA_CR_DOMAINSPLIT_TYPE_CORE4_SHIFT (5U)
  80. #define VHA_CR_DOMAINSPLIT_TYPE_CORE4_CLRMSK (0XFFFFFFDFU)
  81. #define VHA_CR_DOMAINSPLIT_TYPE_CORE4_EN (0X00000020U)
  82. #define VHA_CR_DOMAINSPLIT_TYPE_CORE3_SHIFT (4U)
  83. #define VHA_CR_DOMAINSPLIT_TYPE_CORE3_CLRMSK (0XFFFFFFEFU)
  84. #define VHA_CR_DOMAINSPLIT_TYPE_CORE3_EN (0X00000010U)
  85. #define VHA_CR_DOMAINSPLIT_TYPE_CORE2_SHIFT (3U)
  86. #define VHA_CR_DOMAINSPLIT_TYPE_CORE2_CLRMSK (0XFFFFFFF7U)
  87. #define VHA_CR_DOMAINSPLIT_TYPE_CORE2_EN (0X00000008U)
  88. #define VHA_CR_DOMAINSPLIT_TYPE_CORE1_SHIFT (2U)
  89. #define VHA_CR_DOMAINSPLIT_TYPE_CORE1_CLRMSK (0XFFFFFFFBU)
  90. #define VHA_CR_DOMAINSPLIT_TYPE_CORE1_EN (0X00000004U)
  91. #define VHA_CR_DOMAINSPLIT_TYPE_CORE0_SHIFT (1U)
  92. #define VHA_CR_DOMAINSPLIT_TYPE_CORE0_CLRMSK (0XFFFFFFFDU)
  93. #define VHA_CR_DOMAINSPLIT_TYPE_CORE0_EN (0X00000002U)
  94. #define VHA_CR_DOMAINSPLIT_TYPE_TLC_SHIFT (0U)
  95. #define VHA_CR_DOMAINSPLIT_TYPE_TLC_CLRMSK (0XFFFFFFFEU)
  96. #define VHA_CR_DOMAINSPLIT_TYPE_TLC_EN (0X00000001U)
  97. /*
  98. Register VHA_CR_PRODUCT_ID
  99. */
  100. #define VHA_CR_PRODUCT_ID (0x0018U)
  101. #define VHA_CR_PRODUCT_ID_MASKFULL (IMG_UINT64_C(0x00000000FFFF0000))
  102. #define VHA_CR_PRODUCT_ID_IMG_PRODUCT_ID_SHIFT (16U)
  103. #define VHA_CR_PRODUCT_ID_IMG_PRODUCT_ID_CLRMSK (IMG_UINT64_C(0XFFFFFFFF0000FFFF))
  104. /*
  105. Register VHA_CR_CORE_ID
  106. */
  107. #define VHA_CR_CORE_ID (0x0020U)
  108. #define VHA_CR_CORE_ID_MASKFULL (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
  109. #define VHA_CR_CORE_ID_BRANCH_ID_SHIFT (48U)
  110. #define VHA_CR_CORE_ID_BRANCH_ID_CLRMSK (IMG_UINT64_C(0X0000FFFFFFFFFFFF))
  111. #define VHA_CR_CORE_ID_VERSION_ID_SHIFT (32U)
  112. #define VHA_CR_CORE_ID_VERSION_ID_CLRMSK (IMG_UINT64_C(0XFFFF0000FFFFFFFF))
  113. #define VHA_CR_CORE_ID_NUMBER_OF_SCALABLE_UNITS_SHIFT (16U)
  114. #define VHA_CR_CORE_ID_NUMBER_OF_SCALABLE_UNITS_CLRMSK (IMG_UINT64_C(0XFFFFFFFF0000FFFF))
  115. #define VHA_CR_CORE_ID_CONFIG_ID_SHIFT (0U)
  116. #define VHA_CR_CORE_ID_CONFIG_ID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF0000))
  117. /*
  118. Register VHA_CR_CORE_IP_INTEGRATOR_ID
  119. */
  120. #define VHA_CR_CORE_IP_INTEGRATOR_ID (0x0028U)
  121. #define VHA_CR_CORE_IP_INTEGRATOR_ID_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  122. #define VHA_CR_CORE_IP_INTEGRATOR_ID_VALUE_SHIFT (0U)
  123. #define VHA_CR_CORE_IP_INTEGRATOR_ID_VALUE_CLRMSK (IMG_UINT64_C(0XFFFFFFFF00000000))
  124. /*
  125. Register VHA_CR_CORE_IP_CHANGELIST
  126. */
  127. #define VHA_CR_CORE_IP_CHANGELIST (0x0030U)
  128. #define VHA_CR_CORE_IP_CHANGELIST_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  129. #define VHA_CR_CORE_IP_CHANGELIST_VALUE_SHIFT (0U)
  130. #define VHA_CR_CORE_IP_CHANGELIST_VALUE_CLRMSK (IMG_UINT64_C(0XFFFFFFFF00000000))
  131. /*
  132. Register VHA_CR_CORE_IP_CONFIG
  133. */
  134. #define VHA_CR_CORE_IP_CONFIG (0x0038U)
  135. #define VHA_CR_CORE_IP_CONFIG_MASKFULL (IMG_UINT64_C(0x00000000000FFF01))
  136. #define VHA_CR_CORE_IP_CONFIG_SIGNATURES_SUPPORTED_SAFETY_SHIFT (19U)
  137. #define VHA_CR_CORE_IP_CONFIG_SIGNATURES_SUPPORTED_SAFETY_CLRMSK (0XFFF7FFFFU)
  138. #define VHA_CR_CORE_IP_CONFIG_SIGNATURES_SUPPORTED_SAFETY_EN (0X00080000U)
  139. #define VHA_CR_CORE_IP_CONFIG_OCM_SECURITY_SHIFT (18U)
  140. #define VHA_CR_CORE_IP_CONFIG_OCM_SECURITY_CLRMSK (0XFFFBFFFFU)
  141. #define VHA_CR_CORE_IP_CONFIG_OCM_SECURITY_EN (0X00040000U)
  142. #define VHA_CR_CORE_IP_CONFIG_ECC_RAMS_SHIFT (16U)
  143. #define VHA_CR_CORE_IP_CONFIG_ECC_RAMS_CLRMSK (0XFFFCFFFFU)
  144. #define VHA_CR_CORE_IP_CONFIG_PARITY_REGISTERS_SHIFT (15U)
  145. #define VHA_CR_CORE_IP_CONFIG_PARITY_REGISTERS_CLRMSK (0XFFFF7FFFU)
  146. #define VHA_CR_CORE_IP_CONFIG_PARITY_REGISTERS_EN (0X00008000U)
  147. #define VHA_CR_CORE_IP_CONFIG_MMU_VERSION_SHIFT (12U)
  148. #define VHA_CR_CORE_IP_CONFIG_MMU_VERSION_CLRMSK (0XFFFF8FFFU)
  149. #define VHA_CR_CORE_IP_CONFIG_SIGNATURES_SUPPORTED_SUBSET_SHIFT (11U)
  150. #define VHA_CR_CORE_IP_CONFIG_SIGNATURES_SUPPORTED_SUBSET_CLRMSK (0XFFFFF7FFU)
  151. #define VHA_CR_CORE_IP_CONFIG_SIGNATURES_SUPPORTED_SUBSET_EN (0X00000800U)
  152. #define VHA_CR_CORE_IP_CONFIG_SIGNATURES_SUPPORTED_ALL_SHIFT (10U)
  153. #define VHA_CR_CORE_IP_CONFIG_SIGNATURES_SUPPORTED_ALL_CLRMSK (0XFFFFFBFFU)
  154. #define VHA_CR_CORE_IP_CONFIG_SIGNATURES_SUPPORTED_ALL_EN (0X00000400U)
  155. #define VHA_CR_CORE_IP_CONFIG_RANDOM_STALLERS_SUPPORTED_SHIFT (9U)
  156. #define VHA_CR_CORE_IP_CONFIG_RANDOM_STALLERS_SUPPORTED_CLRMSK (0XFFFFFDFFU)
  157. #define VHA_CR_CORE_IP_CONFIG_RANDOM_STALLERS_SUPPORTED_EN (0X00000200U)
  158. #define VHA_CR_CORE_IP_CONFIG_RTM_SUPPORTED_SHIFT (8U)
  159. #define VHA_CR_CORE_IP_CONFIG_RTM_SUPPORTED_CLRMSK (0XFFFFFEFFU)
  160. #define VHA_CR_CORE_IP_CONFIG_RTM_SUPPORTED_EN (0X00000100U)
  161. #define VHA_CR_CORE_IP_CONFIG_CNN_SUPPORTED_SHIFT (0U)
  162. #define VHA_CR_CORE_IP_CONFIG_CNN_SUPPORTED_CLRMSK (0XFFFFFFFEU)
  163. #define VHA_CR_CORE_IP_CONFIG_CNN_SUPPORTED_EN (0X00000001U)
  164. #define VHA_CR_CORE_IP_CONFIG1_BUS_WIDTH_MASK (0x00000007U)
  165. /*
  166. 8-byte memory interface */
  167. #define VHA_CR_CORE_IP_CONFIG1_BUS_WIDTH_MEM_WORD_8_BYTES (0x00000000U)
  168. /*
  169. 16-byte memory interface */
  170. #define VHA_CR_CORE_IP_CONFIG1_BUS_WIDTH_MEM_WORD_16_BYTES (0x00000001U)
  171. /*
  172. 32-byte memory interface */
  173. #define VHA_CR_CORE_IP_CONFIG1_BUS_WIDTH_MEM_WORD_32_BYTES (0x00000002U)
  174. /*
  175. 64-byte memory interface */
  176. #define VHA_CR_CORE_IP_CONFIG1_BUS_WIDTH_MEM_WORD_64_BYTES (0x00000003U)
  177. /*
  178. 128-byte memory interface */
  179. #define VHA_CR_CORE_IP_CONFIG1_BUS_WIDTH_MEM_WORD_128_BYTES (0x00000004U)
  180. /*
  181. Register VHA_CR_CORE_IP_CONFIG1
  182. */
  183. #define VHA_CR_CORE_IP_CONFIG1 (0x0040U)
  184. #define VHA_CR_CORE_IP_CONFIG1_MASKFULL (IMG_UINT64_C(0x00001FFFCFFF9FFF))
  185. #define VHA_CR_CORE_IP_CONFIG1_EXT_MEM_BUS_WIDTH_SHIFT (42U)
  186. #define VHA_CR_CORE_IP_CONFIG1_EXT_MEM_BUS_WIDTH_CLRMSK (IMG_UINT64_C(0XFFFFE3FFFFFFFFFF))
  187. #define VHA_CR_CORE_IP_CONFIG1_EXT_MEM_BUS_WIDTH_MEM_WORD_8_BYTES (IMG_UINT64_C(0000000000000000))
  188. #define VHA_CR_CORE_IP_CONFIG1_EXT_MEM_BUS_WIDTH_MEM_WORD_16_BYTES (IMG_UINT64_C(0x0000040000000000))
  189. #define VHA_CR_CORE_IP_CONFIG1_EXT_MEM_BUS_WIDTH_MEM_WORD_32_BYTES (IMG_UINT64_C(0x0000080000000000))
  190. #define VHA_CR_CORE_IP_CONFIG1_EXT_MEM_BUS_WIDTH_MEM_WORD_64_BYTES (IMG_UINT64_C(0x00000c0000000000))
  191. #define VHA_CR_CORE_IP_CONFIG1_EXT_MEM_BUS_WIDTH_MEM_WORD_128_BYTES (IMG_UINT64_C(0x0000100000000000))
  192. #define VHA_CR_CORE_IP_CONFIG1_SYS_OCM_NUM_SUBBANKS_LOG2_SHIFT (39U)
  193. #define VHA_CR_CORE_IP_CONFIG1_SYS_OCM_NUM_SUBBANKS_LOG2_CLRMSK (IMG_UINT64_C(0XFFFFFC7FFFFFFFFF))
  194. #define VHA_CR_CORE_IP_CONFIG1_SYS_OCM_NUM_BANK_ARRAYS_MIN1_SHIFT (36U)
  195. #define VHA_CR_CORE_IP_CONFIG1_SYS_OCM_NUM_BANK_ARRAYS_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFF8FFFFFFFFF))
  196. #define VHA_CR_CORE_IP_CONFIG1_SYS_OCM_NUM_BANK_GROUPS_MIN1_SHIFT (33U)
  197. #define VHA_CR_CORE_IP_CONFIG1_SYS_OCM_NUM_BANK_GROUPS_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFF1FFFFFFFF))
  198. #define VHA_CR_CORE_IP_CONFIG1_NUM_CORES_MIN1_SHIFT (30U)
  199. #define VHA_CR_CORE_IP_CONFIG1_NUM_CORES_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFE3FFFFFFF))
  200. #define VHA_CR_CORE_IP_CONFIG1_CORE_OCM_RAM_SIZE_4KB_SHIFT (15U)
  201. #define VHA_CR_CORE_IP_CONFIG1_CORE_OCM_RAM_SIZE_4KB_CLRMSK (IMG_UINT64_C(0XFFFFFFFFF0007FFF))
  202. #define VHA_CR_CORE_IP_CONFIG1_SYS_OCM_RAM_SIZE_4KB_SHIFT (0U)
  203. #define VHA_CR_CORE_IP_CONFIG1_SYS_OCM_RAM_SIZE_4KB_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFE000))
  204. /*
  205. Register VHA_CR_CNN_IP_CONFIG0
  206. */
  207. #define VHA_CR_CNN_IP_CONFIG0 (0x0068U)
  208. #define VHA_CR_CNN_IP_CONFIG0_MASKFULL (IMG_UINT64_C(0x000000001FFFFFFF))
  209. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_CMD_CRC_FOOTER_SHIFT (28U)
  210. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_CMD_CRC_FOOTER_CLRMSK (IMG_UINT64_C(0XFFFFFFFFEFFFFFFF))
  211. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_CMD_CRC_FOOTER_EN (IMG_UINT64_C(0X0000000010000000))
  212. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_MEM_REQ_PRIORITISATION_SHIFT (27U)
  213. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_MEM_REQ_PRIORITISATION_CLRMSK (IMG_UINT64_C(0XFFFFFFFFF7FFFFFF))
  214. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_MEM_REQ_PRIORITISATION_EN (IMG_UINT64_C(0X0000000008000000))
  215. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_PIPELINE_ORDER_XBAR_SHIFT (26U)
  216. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_PIPELINE_ORDER_XBAR_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFBFFFFFF))
  217. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_PIPELINE_ORDER_XBAR_EN (IMG_UINT64_C(0X0000000004000000))
  218. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DEPTHWISE_POOLING_ENGINE_SHIFT (25U)
  219. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DEPTHWISE_POOLING_ENGINE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFDFFFFFF))
  220. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DEPTHWISE_POOLING_ENGINE_EN (IMG_UINT64_C(0X0000000002000000))
  221. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_PARALLEL_MMM_SUPPORTED_SHIFT (24U)
  222. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_PARALLEL_MMM_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFEFFFFFF))
  223. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_PARALLEL_MMM_SUPPORTED_EN (IMG_UINT64_C(0X0000000001000000))
  224. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_MMU_PRELOADS_SHIFT (23U)
  225. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_MMU_PRELOADS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF7FFFFF))
  226. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_MMU_PRELOADS_EN (IMG_UINT64_C(0X0000000000800000))
  227. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_MMM_SUPPORTED_SHIFT (22U)
  228. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_MMM_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFBFFFFF))
  229. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_MMM_SUPPORTED_EN (IMG_UINT64_C(0X0000000000400000))
  230. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_SCHEDULING_SUPPORTED_SHIFT (21U)
  231. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_SCHEDULING_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFDFFFFF))
  232. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_SCHEDULING_SUPPORTED_EN (IMG_UINT64_C(0X0000000000200000))
  233. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_SECURITY_SHIFT (20U)
  234. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_SECURITY_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFEFFFFF))
  235. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_SECURITY_EN (IMG_UINT64_C(0X0000000000100000))
  236. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_CBUF_DECOMPRESSION_SUPPORTED_SHIFT (19U)
  237. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_CBUF_DECOMPRESSION_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF7FFFF))
  238. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_CBUF_DECOMPRESSION_SUPPORTED_EN (IMG_UINT64_C(0X0000000000080000))
  239. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_POOL_MIN_SUPPORTED_SHIFT (18U)
  240. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_POOL_MIN_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFBFFFF))
  241. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_POOL_MIN_SUPPORTED_EN (IMG_UINT64_C(0X0000000000040000))
  242. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_UNSIGNED_SUPPORTED_SHIFT (17U)
  243. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_UNSIGNED_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFDFFFF))
  244. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_UNSIGNED_SUPPORTED_EN (IMG_UINT64_C(0X0000000000020000))
  245. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_MIRROR_PADDING_SUPPORTED_SHIFT (16U)
  246. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_MIRROR_PADDING_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFEFFFF))
  247. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_MIRROR_PADDING_SUPPORTED_EN (IMG_UINT64_C(0X0000000000010000))
  248. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_EWO_BROADCAST_SUPPORTED_SHIFT (15U)
  249. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_EWO_BROADCAST_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF7FFF))
  250. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_EWO_BROADCAST_SUPPORTED_EN (IMG_UINT64_C(0X0000000000008000))
  251. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_HALF_16BIT_CONV_SUPPORTED_SHIFT (14U)
  252. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_HALF_16BIT_CONV_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFBFFF))
  253. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_HALF_16BIT_CONV_SUPPORTED_EN (IMG_UINT64_C(0X0000000000004000))
  254. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_OUTPUT_FIXTOFIX_SUPPORTED_SHIFT (13U)
  255. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_OUTPUT_FIXTOFIX_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFDFFF))
  256. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_OUTPUT_FIXTOFIX_SUPPORTED_EN (IMG_UINT64_C(0X0000000000002000))
  257. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DUAL_8BIT_CONV_SUPPORTED_SHIFT (12U)
  258. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DUAL_8BIT_CONV_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFEFFF))
  259. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DUAL_8BIT_CONV_SUPPORTED_EN (IMG_UINT64_C(0X0000000000001000))
  260. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DATA_DECOMPRESSION_SUPPORTED_SHIFT (11U)
  261. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DATA_DECOMPRESSION_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF7FF))
  262. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DATA_DECOMPRESSION_SUPPORTED_EN (IMG_UINT64_C(0X0000000000000800))
  263. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DATA_COMPRESSION_SUPPORTED_SHIFT (10U)
  264. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DATA_COMPRESSION_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFBFF))
  265. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DATA_COMPRESSION_SUPPORTED_EN (IMG_UINT64_C(0X0000000000000400))
  266. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_ELEMENT_OPS_CALC_SUPPORTED_SHIFT (9U)
  267. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_ELEMENT_OPS_CALC_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFDFF))
  268. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_ELEMENT_OPS_CALC_SUPPORTED_EN (IMG_UINT64_C(0X0000000000000200))
  269. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_ELEMENT_OPS_FETCH_SUPPORTED_SHIFT (8U)
  270. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_ELEMENT_OPS_FETCH_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFEFF))
  271. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_ELEMENT_OPS_FETCH_SUPPORTED_EN (IMG_UINT64_C(0X0000000000000100))
  272. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_ELEMENT_OPS_SUPPORTED_SHIFT (7U)
  273. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_ELEMENT_OPS_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFF7F))
  274. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_ELEMENT_OPS_SUPPORTED_EN (IMG_UINT64_C(0X0000000000000080))
  275. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_POOL_AVG_SUPPORTED_SHIFT (6U)
  276. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_POOL_AVG_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFBF))
  277. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_POOL_AVG_SUPPORTED_EN (IMG_UINT64_C(0X0000000000000040))
  278. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_POOL_MAX_SUPPORTED_SHIFT (5U)
  279. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_POOL_MAX_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFDF))
  280. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_POOL_MAX_SUPPORTED_EN (IMG_UINT64_C(0X0000000000000020))
  281. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_NORM_ICN_SUPPORTED_SHIFT (4U)
  282. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_NORM_ICN_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFEF))
  283. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_NORM_ICN_SUPPORTED_EN (IMG_UINT64_C(0X0000000000000010))
  284. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_NORM_ACN_SUPPORTED_SHIFT (3U)
  285. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_NORM_ACN_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF7))
  286. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_NORM_ACN_SUPPORTED_EN (IMG_UINT64_C(0X0000000000000008))
  287. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_ACT_LUT_SUPPORTED_SHIFT (2U)
  288. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_ACT_LUT_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFB))
  289. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_ACT_LUT_SUPPORTED_EN (IMG_UINT64_C(0X0000000000000004))
  290. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DECONV_SUPPORTED_SHIFT (1U)
  291. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DECONV_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFD))
  292. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DECONV_SUPPORTED_EN (IMG_UINT64_C(0X0000000000000002))
  293. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_CONV_SUPPORTED_SHIFT (0U)
  294. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_CONV_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  295. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_CONV_SUPPORTED_EN (IMG_UINT64_C(0X0000000000000001))
  296. /*
  297. Register VHA_CR_CNN_IP_CONFIG1
  298. */
  299. #define VHA_CR_CNN_IP_CONFIG1 (0x0070U)
  300. #define VHA_CR_CNN_IP_CONFIG1_MASKFULL (IMG_UINT64_C(0xFFFFFFFF3F0FFFFF))
  301. #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_ADDRESS_ALIGNMENT_BYTES_LOG2_SHIFT (60U)
  302. #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_ADDRESS_ALIGNMENT_BYTES_LOG2_CLRMSK (IMG_UINT64_C(0X0FFFFFFFFFFFFFFF))
  303. #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_MAX_FILTERS_PER_SET_MIN1_SHIFT (52U)
  304. #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_MAX_FILTERS_PER_SET_MIN1_CLRMSK (IMG_UINT64_C(0XF00FFFFFFFFFFFFF))
  305. #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_MAX_FILTERS_MIN1_SHIFT (39U)
  306. #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_MAX_FILTERS_MIN1_CLRMSK (IMG_UINT64_C(0XFFF0007FFFFFFFFF))
  307. #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_SCHEDULING_NUM_PRIORITY_MIN1_SHIFT (37U)
  308. #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_SCHEDULING_NUM_PRIORITY_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFF9FFFFFFFFF))
  309. #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_CONV_ENGINE_CALC_BLOCKS_MIN1_SHIFT (32U)
  310. #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_CONV_ENGINE_CALC_BLOCKS_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFE0FFFFFFFF))
  311. #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_WEIGHT_DATA_WIDTH_MIN1_SHIFT (24U)
  312. #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_WEIGHT_DATA_WIDTH_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFC0FFFFFF))
  313. #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_ACTIVATION_DATA_WIDTH_MIN1_SHIFT (16U)
  314. #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_ACTIVATION_DATA_WIDTH_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF0FFFF))
  315. #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_CONV_ENGINE_NUM_FILTERS_MIN1_SHIFT (12U)
  316. #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_CONV_ENGINE_NUM_FILTERS_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF0FFF))
  317. #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_CONV_ENGINE_NUM_COEFFS_MIN1_SHIFT (4U)
  318. #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_CONV_ENGINE_NUM_COEFFS_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF00F))
  319. #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_SCHEDULING_NUM_HOSTS_MIN1_SHIFT (0U)
  320. #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_SCHEDULING_NUM_HOSTS_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF0))
  321. /*
  322. Register VHA_CR_CNN_IP_CONFIG2
  323. */
  324. #define VHA_CR_CNN_IP_CONFIG2 (0x0078U)
  325. #define VHA_CR_CNN_IP_CONFIG2_MASKFULL (IMG_UINT64_C(0x00FFFFFFFFFFFFFF))
  326. #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_TENSOR_CONCAT_MIN1_SHIFT (51U)
  327. #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_TENSOR_CONCAT_MIN1_CLRMSK (IMG_UINT64_C(0XFF07FFFFFFFFFFFF))
  328. #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_TENSOR_SPLIT_MIN1_SHIFT (48U)
  329. #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_TENSOR_SPLIT_MIN1_CLRMSK (IMG_UINT64_C(0XFFF8FFFFFFFFFFFF))
  330. #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_SHARED_BUFFER_BANKS_MIN1_SHIFT (44U)
  331. #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_SHARED_BUFFER_BANKS_MIN1_CLRMSK (IMG_UINT64_C(0XFFFF0FFFFFFFFFFF))
  332. #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_MAX_FILTERS_WITH_BIAS_MIN1_SHIFT (34U)
  333. #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_MAX_FILTERS_WITH_BIAS_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFF003FFFFFFFF))
  334. #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_NORM_UNITS_MIN1_SHIFT (28U)
  335. #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_NORM_UNITS_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFC0FFFFFFF))
  336. #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_SHARED_BUFFER_SIZE_MIN1_SHIFT (20U)
  337. #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_SHARED_BUFFER_SIZE_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFF00FFFFF))
  338. #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_COEFF_BUFFER_SIZE_MIN1_SHIFT (4U)
  339. #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_COEFF_BUFFER_SIZE_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF0000F))
  340. #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_COEFF_BUFFER_BANKS_MIN1_SHIFT (0U)
  341. #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_COEFF_BUFFER_BANKS_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF0))
  342. /*
  343. Register VHA_CR_CNN_IP_CONFIG3
  344. */
  345. #define VHA_CR_CNN_IP_CONFIG3 (0x0080U)
  346. #define VHA_CR_CNN_IP_CONFIG3_MASKFULL (IMG_UINT64_C(0x000001FFFFFFFFFF))
  347. #define VHA_CR_CNN_IP_CONFIG3_VHA_CNN_MMM_PARALLELISM_L1_MIN1_SHIFT (38U)
  348. #define VHA_CR_CNN_IP_CONFIG3_VHA_CNN_MMM_PARALLELISM_L1_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFE3FFFFFFFFF))
  349. #define VHA_CR_CNN_IP_CONFIG3_VHA_CNN_MMM_PARALLELISM_L0_MIN1_SHIFT (34U)
  350. #define VHA_CR_CNN_IP_CONFIG3_VHA_CNN_MMM_PARALLELISM_L0_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFC3FFFFFFFF))
  351. #define VHA_CR_CNN_IP_CONFIG3_VHA_CNN_MMM_BUFFER_SIZE_MIN1_SHIFT (29U)
  352. #define VHA_CR_CNN_IP_CONFIG3_VHA_CNN_MMM_BUFFER_SIZE_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFC1FFFFFFF))
  353. #define VHA_CR_CNN_IP_CONFIG3_VHA_CNN_MMM_BUFFER_BANKS_MIN1_SHIFT (24U)
  354. #define VHA_CR_CNN_IP_CONFIG3_VHA_CNN_MMM_BUFFER_BANKS_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFE0FFFFFF))
  355. #define VHA_CR_CNN_IP_CONFIG3_VHA_CNN_ACT_LUT_SIZE_MIN1_SHIFT (16U)
  356. #define VHA_CR_CNN_IP_CONFIG3_VHA_CNN_ACT_LUT_SIZE_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF00FFFF))
  357. #define VHA_CR_CNN_IP_CONFIG3_VHA_CNN_INPUT_BUFFER_SIZE_MIN1_SHIFT (8U)
  358. #define VHA_CR_CNN_IP_CONFIG3_VHA_CNN_INPUT_BUFFER_SIZE_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF00FF))
  359. #define VHA_CR_CNN_IP_CONFIG3_VHA_CNN_INPUT_BUFFER_BANKS_MIN1_SHIFT (0U)
  360. #define VHA_CR_CNN_IP_CONFIG3_VHA_CNN_INPUT_BUFFER_BANKS_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFF00))
  361. #define VHA_CR_SYS_CLK_CTRL0_MODE_MASK (0x00000003U)
  362. /*
  363. The domain clock is forced off */
  364. #define VHA_CR_SYS_CLK_CTRL0_MODE_OFF (0x00000000U)
  365. /*
  366. The domain clock is forced on */
  367. #define VHA_CR_SYS_CLK_CTRL0_MODE_ON (0x00000001U)
  368. /*
  369. Automatic clock gating is active, the domain clock is only on whilst data is being processed */
  370. #define VHA_CR_SYS_CLK_CTRL0_MODE_AUTO (0x00000002U)
  371. #define VHA_CR_SYS_CLK_CTRL0_MODE_NOTOFF_MASK (0x00000003U)
  372. /*
  373. The domain clock is forced on */
  374. #define VHA_CR_SYS_CLK_CTRL0_MODE_NOTOFF_ON (0x00000001U)
  375. /*
  376. Automatic clock gating is active, the domain clock is only on whilst data is being processed */
  377. #define VHA_CR_SYS_CLK_CTRL0_MODE_NOTOFF_AUTO (0x00000002U)
  378. /*
  379. Register VHA_CR_SYS_CLK_CTRL0
  380. */
  381. #define VHA_CR_SYS_CLK_CTRL0 (0x0200U)
  382. #define VHA_CR_SYS_CLK_CTRL0_MASKFULL (IMG_UINT64_C(0xFFFFFFFFFFFF0FFF))
  383. #define VHA_CR_SYS_CLK_CTRL0_CORE7_SHIFT (62U)
  384. #define VHA_CR_SYS_CLK_CTRL0_CORE7_CLRMSK (IMG_UINT64_C(0X3FFFFFFFFFFFFFFF))
  385. #define VHA_CR_SYS_CLK_CTRL0_CORE7_OFF (IMG_UINT64_C(0000000000000000))
  386. #define VHA_CR_SYS_CLK_CTRL0_CORE7_ON (IMG_UINT64_C(0x4000000000000000))
  387. #define VHA_CR_SYS_CLK_CTRL0_CORE7_AUTO (IMG_UINT64_C(0x8000000000000000))
  388. #define VHA_CR_SYS_CLK_CTRL0_CORE6_SHIFT (60U)
  389. #define VHA_CR_SYS_CLK_CTRL0_CORE6_CLRMSK (IMG_UINT64_C(0XCFFFFFFFFFFFFFFF))
  390. #define VHA_CR_SYS_CLK_CTRL0_CORE6_OFF (IMG_UINT64_C(0000000000000000))
  391. #define VHA_CR_SYS_CLK_CTRL0_CORE6_ON (IMG_UINT64_C(0x1000000000000000))
  392. #define VHA_CR_SYS_CLK_CTRL0_CORE6_AUTO (IMG_UINT64_C(0x2000000000000000))
  393. #define VHA_CR_SYS_CLK_CTRL0_CORE5_SHIFT (58U)
  394. #define VHA_CR_SYS_CLK_CTRL0_CORE5_CLRMSK (IMG_UINT64_C(0XF3FFFFFFFFFFFFFF))
  395. #define VHA_CR_SYS_CLK_CTRL0_CORE5_OFF (IMG_UINT64_C(0000000000000000))
  396. #define VHA_CR_SYS_CLK_CTRL0_CORE5_ON (IMG_UINT64_C(0x0400000000000000))
  397. #define VHA_CR_SYS_CLK_CTRL0_CORE5_AUTO (IMG_UINT64_C(0x0800000000000000))
  398. #define VHA_CR_SYS_CLK_CTRL0_CORE4_SHIFT (56U)
  399. #define VHA_CR_SYS_CLK_CTRL0_CORE4_CLRMSK (IMG_UINT64_C(0XFCFFFFFFFFFFFFFF))
  400. #define VHA_CR_SYS_CLK_CTRL0_CORE4_OFF (IMG_UINT64_C(0000000000000000))
  401. #define VHA_CR_SYS_CLK_CTRL0_CORE4_ON (IMG_UINT64_C(0x0100000000000000))
  402. #define VHA_CR_SYS_CLK_CTRL0_CORE4_AUTO (IMG_UINT64_C(0x0200000000000000))
  403. #define VHA_CR_SYS_CLK_CTRL0_CORE3_SHIFT (54U)
  404. #define VHA_CR_SYS_CLK_CTRL0_CORE3_CLRMSK (IMG_UINT64_C(0XFF3FFFFFFFFFFFFF))
  405. #define VHA_CR_SYS_CLK_CTRL0_CORE3_OFF (IMG_UINT64_C(0000000000000000))
  406. #define VHA_CR_SYS_CLK_CTRL0_CORE3_ON (IMG_UINT64_C(0x0040000000000000))
  407. #define VHA_CR_SYS_CLK_CTRL0_CORE3_AUTO (IMG_UINT64_C(0x0080000000000000))
  408. #define VHA_CR_SYS_CLK_CTRL0_CORE2_SHIFT (52U)
  409. #define VHA_CR_SYS_CLK_CTRL0_CORE2_CLRMSK (IMG_UINT64_C(0XFFCFFFFFFFFFFFFF))
  410. #define VHA_CR_SYS_CLK_CTRL0_CORE2_OFF (IMG_UINT64_C(0000000000000000))
  411. #define VHA_CR_SYS_CLK_CTRL0_CORE2_ON (IMG_UINT64_C(0x0010000000000000))
  412. #define VHA_CR_SYS_CLK_CTRL0_CORE2_AUTO (IMG_UINT64_C(0x0020000000000000))
  413. #define VHA_CR_SYS_CLK_CTRL0_CORE1_SHIFT (50U)
  414. #define VHA_CR_SYS_CLK_CTRL0_CORE1_CLRMSK (IMG_UINT64_C(0XFFF3FFFFFFFFFFFF))
  415. #define VHA_CR_SYS_CLK_CTRL0_CORE1_OFF (IMG_UINT64_C(0000000000000000))
  416. #define VHA_CR_SYS_CLK_CTRL0_CORE1_ON (IMG_UINT64_C(0x0004000000000000))
  417. #define VHA_CR_SYS_CLK_CTRL0_CORE1_AUTO (IMG_UINT64_C(0x0008000000000000))
  418. #define VHA_CR_SYS_CLK_CTRL0_CORE0_SHIFT (48U)
  419. #define VHA_CR_SYS_CLK_CTRL0_CORE0_CLRMSK (IMG_UINT64_C(0XFFFCFFFFFFFFFFFF))
  420. #define VHA_CR_SYS_CLK_CTRL0_CORE0_OFF (IMG_UINT64_C(0000000000000000))
  421. #define VHA_CR_SYS_CLK_CTRL0_CORE0_ON (IMG_UINT64_C(0x0001000000000000))
  422. #define VHA_CR_SYS_CLK_CTRL0_CORE0_AUTO (IMG_UINT64_C(0x0002000000000000))
  423. #define VHA_CR_SYS_CLK_CTRL0_NOC7_SHIFT (46U)
  424. #define VHA_CR_SYS_CLK_CTRL0_NOC7_CLRMSK (IMG_UINT64_C(0XFFFF3FFFFFFFFFFF))
  425. #define VHA_CR_SYS_CLK_CTRL0_NOC7_OFF (IMG_UINT64_C(0000000000000000))
  426. #define VHA_CR_SYS_CLK_CTRL0_NOC7_ON (IMG_UINT64_C(0x0000400000000000))
  427. #define VHA_CR_SYS_CLK_CTRL0_NOC7_AUTO (IMG_UINT64_C(0x0000800000000000))
  428. #define VHA_CR_SYS_CLK_CTRL0_NOC6_SHIFT (44U)
  429. #define VHA_CR_SYS_CLK_CTRL0_NOC6_CLRMSK (IMG_UINT64_C(0XFFFFCFFFFFFFFFFF))
  430. #define VHA_CR_SYS_CLK_CTRL0_NOC6_OFF (IMG_UINT64_C(0000000000000000))
  431. #define VHA_CR_SYS_CLK_CTRL0_NOC6_ON (IMG_UINT64_C(0x0000100000000000))
  432. #define VHA_CR_SYS_CLK_CTRL0_NOC6_AUTO (IMG_UINT64_C(0x0000200000000000))
  433. #define VHA_CR_SYS_CLK_CTRL0_NOC5_SHIFT (42U)
  434. #define VHA_CR_SYS_CLK_CTRL0_NOC5_CLRMSK (IMG_UINT64_C(0XFFFFF3FFFFFFFFFF))
  435. #define VHA_CR_SYS_CLK_CTRL0_NOC5_OFF (IMG_UINT64_C(0000000000000000))
  436. #define VHA_CR_SYS_CLK_CTRL0_NOC5_ON (IMG_UINT64_C(0x0000040000000000))
  437. #define VHA_CR_SYS_CLK_CTRL0_NOC5_AUTO (IMG_UINT64_C(0x0000080000000000))
  438. #define VHA_CR_SYS_CLK_CTRL0_NOC4_SHIFT (40U)
  439. #define VHA_CR_SYS_CLK_CTRL0_NOC4_CLRMSK (IMG_UINT64_C(0XFFFFFCFFFFFFFFFF))
  440. #define VHA_CR_SYS_CLK_CTRL0_NOC4_OFF (IMG_UINT64_C(0000000000000000))
  441. #define VHA_CR_SYS_CLK_CTRL0_NOC4_ON (IMG_UINT64_C(0x0000010000000000))
  442. #define VHA_CR_SYS_CLK_CTRL0_NOC4_AUTO (IMG_UINT64_C(0x0000020000000000))
  443. #define VHA_CR_SYS_CLK_CTRL0_NOC3_SHIFT (38U)
  444. #define VHA_CR_SYS_CLK_CTRL0_NOC3_CLRMSK (IMG_UINT64_C(0XFFFFFF3FFFFFFFFF))
  445. #define VHA_CR_SYS_CLK_CTRL0_NOC3_OFF (IMG_UINT64_C(0000000000000000))
  446. #define VHA_CR_SYS_CLK_CTRL0_NOC3_ON (IMG_UINT64_C(0x0000004000000000))
  447. #define VHA_CR_SYS_CLK_CTRL0_NOC3_AUTO (IMG_UINT64_C(0x0000008000000000))
  448. #define VHA_CR_SYS_CLK_CTRL0_NOC2_SHIFT (36U)
  449. #define VHA_CR_SYS_CLK_CTRL0_NOC2_CLRMSK (IMG_UINT64_C(0XFFFFFFCFFFFFFFFF))
  450. #define VHA_CR_SYS_CLK_CTRL0_NOC2_OFF (IMG_UINT64_C(0000000000000000))
  451. #define VHA_CR_SYS_CLK_CTRL0_NOC2_ON (IMG_UINT64_C(0x0000001000000000))
  452. #define VHA_CR_SYS_CLK_CTRL0_NOC2_AUTO (IMG_UINT64_C(0x0000002000000000))
  453. #define VHA_CR_SYS_CLK_CTRL0_NOC1_SHIFT (34U)
  454. #define VHA_CR_SYS_CLK_CTRL0_NOC1_CLRMSK (IMG_UINT64_C(0XFFFFFFF3FFFFFFFF))
  455. #define VHA_CR_SYS_CLK_CTRL0_NOC1_OFF (IMG_UINT64_C(0000000000000000))
  456. #define VHA_CR_SYS_CLK_CTRL0_NOC1_ON (IMG_UINT64_C(0x0000000400000000))
  457. #define VHA_CR_SYS_CLK_CTRL0_NOC1_AUTO (IMG_UINT64_C(0x0000000800000000))
  458. #define VHA_CR_SYS_CLK_CTRL0_NOC0_SHIFT (32U)
  459. #define VHA_CR_SYS_CLK_CTRL0_NOC0_CLRMSK (IMG_UINT64_C(0XFFFFFFFCFFFFFFFF))
  460. #define VHA_CR_SYS_CLK_CTRL0_NOC0_OFF (IMG_UINT64_C(0000000000000000))
  461. #define VHA_CR_SYS_CLK_CTRL0_NOC0_ON (IMG_UINT64_C(0x0000000100000000))
  462. #define VHA_CR_SYS_CLK_CTRL0_NOC0_AUTO (IMG_UINT64_C(0x0000000200000000))
  463. #define VHA_CR_SYS_CLK_CTRL0_WM7_SHIFT (30U)
  464. #define VHA_CR_SYS_CLK_CTRL0_WM7_CLRMSK (IMG_UINT64_C(0XFFFFFFFF3FFFFFFF))
  465. #define VHA_CR_SYS_CLK_CTRL0_WM7_OFF (IMG_UINT64_C(0000000000000000))
  466. #define VHA_CR_SYS_CLK_CTRL0_WM7_ON (IMG_UINT64_C(0x0000000040000000))
  467. #define VHA_CR_SYS_CLK_CTRL0_WM7_AUTO (IMG_UINT64_C(0x0000000080000000))
  468. #define VHA_CR_SYS_CLK_CTRL0_WM6_SHIFT (28U)
  469. #define VHA_CR_SYS_CLK_CTRL0_WM6_CLRMSK (IMG_UINT64_C(0XFFFFFFFFCFFFFFFF))
  470. #define VHA_CR_SYS_CLK_CTRL0_WM6_OFF (IMG_UINT64_C(0000000000000000))
  471. #define VHA_CR_SYS_CLK_CTRL0_WM6_ON (IMG_UINT64_C(0x0000000010000000))
  472. #define VHA_CR_SYS_CLK_CTRL0_WM6_AUTO (IMG_UINT64_C(0x0000000020000000))
  473. #define VHA_CR_SYS_CLK_CTRL0_WM5_SHIFT (26U)
  474. #define VHA_CR_SYS_CLK_CTRL0_WM5_CLRMSK (IMG_UINT64_C(0XFFFFFFFFF3FFFFFF))
  475. #define VHA_CR_SYS_CLK_CTRL0_WM5_OFF (IMG_UINT64_C(0000000000000000))
  476. #define VHA_CR_SYS_CLK_CTRL0_WM5_ON (IMG_UINT64_C(0x0000000004000000))
  477. #define VHA_CR_SYS_CLK_CTRL0_WM5_AUTO (IMG_UINT64_C(0x0000000008000000))
  478. #define VHA_CR_SYS_CLK_CTRL0_WM4_SHIFT (24U)
  479. #define VHA_CR_SYS_CLK_CTRL0_WM4_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFCFFFFFF))
  480. #define VHA_CR_SYS_CLK_CTRL0_WM4_OFF (IMG_UINT64_C(0000000000000000))
  481. #define VHA_CR_SYS_CLK_CTRL0_WM4_ON (IMG_UINT64_C(0x0000000001000000))
  482. #define VHA_CR_SYS_CLK_CTRL0_WM4_AUTO (IMG_UINT64_C(0x0000000002000000))
  483. #define VHA_CR_SYS_CLK_CTRL0_WM3_SHIFT (22U)
  484. #define VHA_CR_SYS_CLK_CTRL0_WM3_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF3FFFFF))
  485. #define VHA_CR_SYS_CLK_CTRL0_WM3_OFF (IMG_UINT64_C(0000000000000000))
  486. #define VHA_CR_SYS_CLK_CTRL0_WM3_ON (IMG_UINT64_C(0x0000000000400000))
  487. #define VHA_CR_SYS_CLK_CTRL0_WM3_AUTO (IMG_UINT64_C(0x0000000000800000))
  488. #define VHA_CR_SYS_CLK_CTRL0_WM2_SHIFT (20U)
  489. #define VHA_CR_SYS_CLK_CTRL0_WM2_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFCFFFFF))
  490. #define VHA_CR_SYS_CLK_CTRL0_WM2_OFF (IMG_UINT64_C(0000000000000000))
  491. #define VHA_CR_SYS_CLK_CTRL0_WM2_ON (IMG_UINT64_C(0x0000000000100000))
  492. #define VHA_CR_SYS_CLK_CTRL0_WM2_AUTO (IMG_UINT64_C(0x0000000000200000))
  493. #define VHA_CR_SYS_CLK_CTRL0_WM1_SHIFT (18U)
  494. #define VHA_CR_SYS_CLK_CTRL0_WM1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF3FFFF))
  495. #define VHA_CR_SYS_CLK_CTRL0_WM1_OFF (IMG_UINT64_C(0000000000000000))
  496. #define VHA_CR_SYS_CLK_CTRL0_WM1_ON (IMG_UINT64_C(0x0000000000040000))
  497. #define VHA_CR_SYS_CLK_CTRL0_WM1_AUTO (IMG_UINT64_C(0x0000000000080000))
  498. #define VHA_CR_SYS_CLK_CTRL0_WM0_SHIFT (16U)
  499. #define VHA_CR_SYS_CLK_CTRL0_WM0_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFCFFFF))
  500. #define VHA_CR_SYS_CLK_CTRL0_WM0_OFF (IMG_UINT64_C(0000000000000000))
  501. #define VHA_CR_SYS_CLK_CTRL0_WM0_ON (IMG_UINT64_C(0x0000000000010000))
  502. #define VHA_CR_SYS_CLK_CTRL0_WM0_AUTO (IMG_UINT64_C(0x0000000000020000))
  503. #define VHA_CR_SYS_CLK_CTRL0_INTERCONNECT_SHIFT (10U)
  504. #define VHA_CR_SYS_CLK_CTRL0_INTERCONNECT_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF3FF))
  505. #define VHA_CR_SYS_CLK_CTRL0_INTERCONNECT_OFF (IMG_UINT64_C(0000000000000000))
  506. #define VHA_CR_SYS_CLK_CTRL0_INTERCONNECT_ON (IMG_UINT64_C(0x0000000000000400))
  507. #define VHA_CR_SYS_CLK_CTRL0_INTERCONNECT_AUTO (IMG_UINT64_C(0x0000000000000800))
  508. #define VHA_CR_SYS_CLK_CTRL0_AXI_SHIFT (8U)
  509. #define VHA_CR_SYS_CLK_CTRL0_AXI_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFCFF))
  510. #define VHA_CR_SYS_CLK_CTRL0_AXI_OFF (IMG_UINT64_C(0000000000000000))
  511. #define VHA_CR_SYS_CLK_CTRL0_AXI_ON (IMG_UINT64_C(0x0000000000000100))
  512. #define VHA_CR_SYS_CLK_CTRL0_AXI_AUTO (IMG_UINT64_C(0x0000000000000200))
  513. #define VHA_CR_SYS_CLK_CTRL0_SLC_SHIFT (6U)
  514. #define VHA_CR_SYS_CLK_CTRL0_SLC_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFF3F))
  515. #define VHA_CR_SYS_CLK_CTRL0_SLC_OFF (IMG_UINT64_C(0000000000000000))
  516. #define VHA_CR_SYS_CLK_CTRL0_SLC_ON (IMG_UINT64_C(0x0000000000000040))
  517. #define VHA_CR_SYS_CLK_CTRL0_SLC_AUTO (IMG_UINT64_C(0x0000000000000080))
  518. #define VHA_CR_SYS_CLK_CTRL0_LSYNC_SHIFT (4U)
  519. #define VHA_CR_SYS_CLK_CTRL0_LSYNC_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFCF))
  520. #define VHA_CR_SYS_CLK_CTRL0_LSYNC_OFF (IMG_UINT64_C(0000000000000000))
  521. #define VHA_CR_SYS_CLK_CTRL0_LSYNC_ON (IMG_UINT64_C(0x0000000000000010))
  522. #define VHA_CR_SYS_CLK_CTRL0_LSYNC_AUTO (IMG_UINT64_C(0x0000000000000020))
  523. #define VHA_CR_SYS_CLK_CTRL0_SOCM_SHIFT (2U)
  524. #define VHA_CR_SYS_CLK_CTRL0_SOCM_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF3))
  525. #define VHA_CR_SYS_CLK_CTRL0_SOCM_OFF (IMG_UINT64_C(0000000000000000))
  526. #define VHA_CR_SYS_CLK_CTRL0_SOCM_ON (IMG_UINT64_C(0x0000000000000004))
  527. #define VHA_CR_SYS_CLK_CTRL0_SOCM_AUTO (IMG_UINT64_C(0x0000000000000008))
  528. #define VHA_CR_SYS_CLK_CTRL0_REGBANK_SHIFT (0U)
  529. #define VHA_CR_SYS_CLK_CTRL0_REGBANK_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFC))
  530. #define VHA_CR_SYS_CLK_CTRL0_REGBANK_ON (IMG_UINT64_C(0x0000000000000001))
  531. #define VHA_CR_SYS_CLK_CTRL0_REGBANK_AUTO (IMG_UINT64_C(0x0000000000000002))
  532. /*
  533. Clock is gated and the module is inactive */
  534. #define VHA_CR_SYS_CLK_STATUS0_MODE_GATED (0x00000000U)
  535. /*
  536. Clock is running */
  537. #define VHA_CR_SYS_CLK_STATUS0_MODE_RUNNING (0x00000001U)
  538. /*
  539. Register VHA_CR_SYS_CLK_STATUS0
  540. */
  541. #define VHA_CR_SYS_CLK_STATUS0 (0x0208U)
  542. #define VHA_CR_SYS_CLK_STATUS0_MASKFULL (IMG_UINT64_C(0x00000000FFFFFF3F))
  543. #define VHA_CR_SYS_CLK_STATUS0_CORE7_SHIFT (31U)
  544. #define VHA_CR_SYS_CLK_STATUS0_CORE7_CLRMSK (IMG_UINT64_C(0XFFFFFFFF7FFFFFFF))
  545. #define VHA_CR_SYS_CLK_STATUS0_CORE7_GATED (IMG_UINT64_C(0000000000000000))
  546. #define VHA_CR_SYS_CLK_STATUS0_CORE7_RUNNING (IMG_UINT64_C(0x0000000080000000))
  547. #define VHA_CR_SYS_CLK_STATUS0_CORE6_SHIFT (30U)
  548. #define VHA_CR_SYS_CLK_STATUS0_CORE6_CLRMSK (IMG_UINT64_C(0XFFFFFFFFBFFFFFFF))
  549. #define VHA_CR_SYS_CLK_STATUS0_CORE6_GATED (IMG_UINT64_C(0000000000000000))
  550. #define VHA_CR_SYS_CLK_STATUS0_CORE6_RUNNING (IMG_UINT64_C(0x0000000040000000))
  551. #define VHA_CR_SYS_CLK_STATUS0_CORE5_SHIFT (29U)
  552. #define VHA_CR_SYS_CLK_STATUS0_CORE5_CLRMSK (IMG_UINT64_C(0XFFFFFFFFDFFFFFFF))
  553. #define VHA_CR_SYS_CLK_STATUS0_CORE5_GATED (IMG_UINT64_C(0000000000000000))
  554. #define VHA_CR_SYS_CLK_STATUS0_CORE5_RUNNING (IMG_UINT64_C(0x0000000020000000))
  555. #define VHA_CR_SYS_CLK_STATUS0_CORE4_SHIFT (28U)
  556. #define VHA_CR_SYS_CLK_STATUS0_CORE4_CLRMSK (IMG_UINT64_C(0XFFFFFFFFEFFFFFFF))
  557. #define VHA_CR_SYS_CLK_STATUS0_CORE4_GATED (IMG_UINT64_C(0000000000000000))
  558. #define VHA_CR_SYS_CLK_STATUS0_CORE4_RUNNING (IMG_UINT64_C(0x0000000010000000))
  559. #define VHA_CR_SYS_CLK_STATUS0_CORE3_SHIFT (27U)
  560. #define VHA_CR_SYS_CLK_STATUS0_CORE3_CLRMSK (IMG_UINT64_C(0XFFFFFFFFF7FFFFFF))
  561. #define VHA_CR_SYS_CLK_STATUS0_CORE3_GATED (IMG_UINT64_C(0000000000000000))
  562. #define VHA_CR_SYS_CLK_STATUS0_CORE3_RUNNING (IMG_UINT64_C(0x0000000008000000))
  563. #define VHA_CR_SYS_CLK_STATUS0_CORE2_SHIFT (26U)
  564. #define VHA_CR_SYS_CLK_STATUS0_CORE2_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFBFFFFFF))
  565. #define VHA_CR_SYS_CLK_STATUS0_CORE2_GATED (IMG_UINT64_C(0000000000000000))
  566. #define VHA_CR_SYS_CLK_STATUS0_CORE2_RUNNING (IMG_UINT64_C(0x0000000004000000))
  567. #define VHA_CR_SYS_CLK_STATUS0_CORE1_SHIFT (25U)
  568. #define VHA_CR_SYS_CLK_STATUS0_CORE1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFDFFFFFF))
  569. #define VHA_CR_SYS_CLK_STATUS0_CORE1_GATED (IMG_UINT64_C(0000000000000000))
  570. #define VHA_CR_SYS_CLK_STATUS0_CORE1_RUNNING (IMG_UINT64_C(0x0000000002000000))
  571. #define VHA_CR_SYS_CLK_STATUS0_CORE0_SHIFT (24U)
  572. #define VHA_CR_SYS_CLK_STATUS0_CORE0_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFEFFFFFF))
  573. #define VHA_CR_SYS_CLK_STATUS0_CORE0_GATED (IMG_UINT64_C(0000000000000000))
  574. #define VHA_CR_SYS_CLK_STATUS0_CORE0_RUNNING (IMG_UINT64_C(0x0000000001000000))
  575. #define VHA_CR_SYS_CLK_STATUS0_NOC7_SHIFT (23U)
  576. #define VHA_CR_SYS_CLK_STATUS0_NOC7_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF7FFFFF))
  577. #define VHA_CR_SYS_CLK_STATUS0_NOC7_GATED (IMG_UINT64_C(0000000000000000))
  578. #define VHA_CR_SYS_CLK_STATUS0_NOC7_RUNNING (IMG_UINT64_C(0x0000000000800000))
  579. #define VHA_CR_SYS_CLK_STATUS0_NOC6_SHIFT (22U)
  580. #define VHA_CR_SYS_CLK_STATUS0_NOC6_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFBFFFFF))
  581. #define VHA_CR_SYS_CLK_STATUS0_NOC6_GATED (IMG_UINT64_C(0000000000000000))
  582. #define VHA_CR_SYS_CLK_STATUS0_NOC6_RUNNING (IMG_UINT64_C(0x0000000000400000))
  583. #define VHA_CR_SYS_CLK_STATUS0_NOC5_SHIFT (21U)
  584. #define VHA_CR_SYS_CLK_STATUS0_NOC5_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFDFFFFF))
  585. #define VHA_CR_SYS_CLK_STATUS0_NOC5_GATED (IMG_UINT64_C(0000000000000000))
  586. #define VHA_CR_SYS_CLK_STATUS0_NOC5_RUNNING (IMG_UINT64_C(0x0000000000200000))
  587. #define VHA_CR_SYS_CLK_STATUS0_NOC4_SHIFT (20U)
  588. #define VHA_CR_SYS_CLK_STATUS0_NOC4_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFEFFFFF))
  589. #define VHA_CR_SYS_CLK_STATUS0_NOC4_GATED (IMG_UINT64_C(0000000000000000))
  590. #define VHA_CR_SYS_CLK_STATUS0_NOC4_RUNNING (IMG_UINT64_C(0x0000000000100000))
  591. #define VHA_CR_SYS_CLK_STATUS0_NOC3_SHIFT (19U)
  592. #define VHA_CR_SYS_CLK_STATUS0_NOC3_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF7FFFF))
  593. #define VHA_CR_SYS_CLK_STATUS0_NOC3_GATED (IMG_UINT64_C(0000000000000000))
  594. #define VHA_CR_SYS_CLK_STATUS0_NOC3_RUNNING (IMG_UINT64_C(0x0000000000080000))
  595. #define VHA_CR_SYS_CLK_STATUS0_NOC2_SHIFT (18U)
  596. #define VHA_CR_SYS_CLK_STATUS0_NOC2_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFBFFFF))
  597. #define VHA_CR_SYS_CLK_STATUS0_NOC2_GATED (IMG_UINT64_C(0000000000000000))
  598. #define VHA_CR_SYS_CLK_STATUS0_NOC2_RUNNING (IMG_UINT64_C(0x0000000000040000))
  599. #define VHA_CR_SYS_CLK_STATUS0_NOC1_SHIFT (17U)
  600. #define VHA_CR_SYS_CLK_STATUS0_NOC1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFDFFFF))
  601. #define VHA_CR_SYS_CLK_STATUS0_NOC1_GATED (IMG_UINT64_C(0000000000000000))
  602. #define VHA_CR_SYS_CLK_STATUS0_NOC1_RUNNING (IMG_UINT64_C(0x0000000000020000))
  603. #define VHA_CR_SYS_CLK_STATUS0_NOC0_SHIFT (16U)
  604. #define VHA_CR_SYS_CLK_STATUS0_NOC0_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFEFFFF))
  605. #define VHA_CR_SYS_CLK_STATUS0_NOC0_GATED (IMG_UINT64_C(0000000000000000))
  606. #define VHA_CR_SYS_CLK_STATUS0_NOC0_RUNNING (IMG_UINT64_C(0x0000000000010000))
  607. #define VHA_CR_SYS_CLK_STATUS0_WM7_SHIFT (15U)
  608. #define VHA_CR_SYS_CLK_STATUS0_WM7_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF7FFF))
  609. #define VHA_CR_SYS_CLK_STATUS0_WM7_GATED (IMG_UINT64_C(0000000000000000))
  610. #define VHA_CR_SYS_CLK_STATUS0_WM7_RUNNING (IMG_UINT64_C(0x0000000000008000))
  611. #define VHA_CR_SYS_CLK_STATUS0_WM6_SHIFT (14U)
  612. #define VHA_CR_SYS_CLK_STATUS0_WM6_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFBFFF))
  613. #define VHA_CR_SYS_CLK_STATUS0_WM6_GATED (IMG_UINT64_C(0000000000000000))
  614. #define VHA_CR_SYS_CLK_STATUS0_WM6_RUNNING (IMG_UINT64_C(0x0000000000004000))
  615. #define VHA_CR_SYS_CLK_STATUS0_WM5_SHIFT (13U)
  616. #define VHA_CR_SYS_CLK_STATUS0_WM5_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFDFFF))
  617. #define VHA_CR_SYS_CLK_STATUS0_WM5_GATED (IMG_UINT64_C(0000000000000000))
  618. #define VHA_CR_SYS_CLK_STATUS0_WM5_RUNNING (IMG_UINT64_C(0x0000000000002000))
  619. #define VHA_CR_SYS_CLK_STATUS0_WM4_SHIFT (12U)
  620. #define VHA_CR_SYS_CLK_STATUS0_WM4_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFEFFF))
  621. #define VHA_CR_SYS_CLK_STATUS0_WM4_GATED (IMG_UINT64_C(0000000000000000))
  622. #define VHA_CR_SYS_CLK_STATUS0_WM4_RUNNING (IMG_UINT64_C(0x0000000000001000))
  623. #define VHA_CR_SYS_CLK_STATUS0_WM3_SHIFT (11U)
  624. #define VHA_CR_SYS_CLK_STATUS0_WM3_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF7FF))
  625. #define VHA_CR_SYS_CLK_STATUS0_WM3_GATED (IMG_UINT64_C(0000000000000000))
  626. #define VHA_CR_SYS_CLK_STATUS0_WM3_RUNNING (IMG_UINT64_C(0x0000000000000800))
  627. #define VHA_CR_SYS_CLK_STATUS0_WM2_SHIFT (10U)
  628. #define VHA_CR_SYS_CLK_STATUS0_WM2_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFBFF))
  629. #define VHA_CR_SYS_CLK_STATUS0_WM2_GATED (IMG_UINT64_C(0000000000000000))
  630. #define VHA_CR_SYS_CLK_STATUS0_WM2_RUNNING (IMG_UINT64_C(0x0000000000000400))
  631. #define VHA_CR_SYS_CLK_STATUS0_WM1_SHIFT (9U)
  632. #define VHA_CR_SYS_CLK_STATUS0_WM1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFDFF))
  633. #define VHA_CR_SYS_CLK_STATUS0_WM1_GATED (IMG_UINT64_C(0000000000000000))
  634. #define VHA_CR_SYS_CLK_STATUS0_WM1_RUNNING (IMG_UINT64_C(0x0000000000000200))
  635. #define VHA_CR_SYS_CLK_STATUS0_WM0_SHIFT (8U)
  636. #define VHA_CR_SYS_CLK_STATUS0_WM0_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFEFF))
  637. #define VHA_CR_SYS_CLK_STATUS0_WM0_GATED (IMG_UINT64_C(0000000000000000))
  638. #define VHA_CR_SYS_CLK_STATUS0_WM0_RUNNING (IMG_UINT64_C(0x0000000000000100))
  639. #define VHA_CR_SYS_CLK_STATUS0_INTERCONNECT_SHIFT (5U)
  640. #define VHA_CR_SYS_CLK_STATUS0_INTERCONNECT_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFDF))
  641. #define VHA_CR_SYS_CLK_STATUS0_INTERCONNECT_GATED (IMG_UINT64_C(0000000000000000))
  642. #define VHA_CR_SYS_CLK_STATUS0_INTERCONNECT_RUNNING (IMG_UINT64_C(0x0000000000000020))
  643. #define VHA_CR_SYS_CLK_STATUS0_AXI_SHIFT (4U)
  644. #define VHA_CR_SYS_CLK_STATUS0_AXI_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFEF))
  645. #define VHA_CR_SYS_CLK_STATUS0_AXI_GATED (IMG_UINT64_C(0000000000000000))
  646. #define VHA_CR_SYS_CLK_STATUS0_AXI_RUNNING (IMG_UINT64_C(0x0000000000000010))
  647. #define VHA_CR_SYS_CLK_STATUS0_SLC_SHIFT (3U)
  648. #define VHA_CR_SYS_CLK_STATUS0_SLC_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF7))
  649. #define VHA_CR_SYS_CLK_STATUS0_SLC_GATED (IMG_UINT64_C(0000000000000000))
  650. #define VHA_CR_SYS_CLK_STATUS0_SLC_RUNNING (IMG_UINT64_C(0x0000000000000008))
  651. #define VHA_CR_SYS_CLK_STATUS0_LSYNC_SHIFT (2U)
  652. #define VHA_CR_SYS_CLK_STATUS0_LSYNC_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFB))
  653. #define VHA_CR_SYS_CLK_STATUS0_LSYNC_GATED (IMG_UINT64_C(0000000000000000))
  654. #define VHA_CR_SYS_CLK_STATUS0_LSYNC_RUNNING (IMG_UINT64_C(0x0000000000000004))
  655. #define VHA_CR_SYS_CLK_STATUS0_SOCM_SHIFT (1U)
  656. #define VHA_CR_SYS_CLK_STATUS0_SOCM_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFD))
  657. #define VHA_CR_SYS_CLK_STATUS0_SOCM_GATED (IMG_UINT64_C(0000000000000000))
  658. #define VHA_CR_SYS_CLK_STATUS0_SOCM_RUNNING (IMG_UINT64_C(0x0000000000000002))
  659. #define VHA_CR_SYS_CLK_STATUS0_REGBANK_SHIFT (0U)
  660. #define VHA_CR_SYS_CLK_STATUS0_REGBANK_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  661. #define VHA_CR_SYS_CLK_STATUS0_REGBANK_GATED (IMG_UINT64_C(0000000000000000))
  662. #define VHA_CR_SYS_CLK_STATUS0_REGBANK_RUNNING (IMG_UINT64_C(0x0000000000000001))
  663. /*
  664. Register VHA_CR_SYS_RESET_CTRL
  665. */
  666. #define VHA_CR_SYS_RESET_CTRL (0x0210U)
  667. #define VHA_CR_SYS_RESET_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000FFFF1E))
  668. #define VHA_CR_SYS_RESET_CTRL_CORE_SHIFT (16U)
  669. #define VHA_CR_SYS_RESET_CTRL_CORE_CLRMSK (0XFF00FFFFU)
  670. #define VHA_CR_SYS_RESET_CTRL_WM_SHIFT (8U)
  671. #define VHA_CR_SYS_RESET_CTRL_WM_CLRMSK (0XFFFF00FFU)
  672. #define VHA_CR_SYS_RESET_CTRL_INTERCONNECT_SHIFT (4U)
  673. #define VHA_CR_SYS_RESET_CTRL_INTERCONNECT_CLRMSK (0XFFFFFFEFU)
  674. #define VHA_CR_SYS_RESET_CTRL_INTERCONNECT_EN (0X00000010U)
  675. #define VHA_CR_SYS_RESET_CTRL_SLC_SHIFT (3U)
  676. #define VHA_CR_SYS_RESET_CTRL_SLC_CLRMSK (0XFFFFFFF7U)
  677. #define VHA_CR_SYS_RESET_CTRL_SLC_EN (0X00000008U)
  678. #define VHA_CR_SYS_RESET_CTRL_MH_SHIFT (2U)
  679. #define VHA_CR_SYS_RESET_CTRL_MH_CLRMSK (0XFFFFFFFBU)
  680. #define VHA_CR_SYS_RESET_CTRL_MH_EN (0X00000004U)
  681. #define VHA_CR_SYS_RESET_CTRL_REGBANK_SHIFT (1U)
  682. #define VHA_CR_SYS_RESET_CTRL_REGBANK_CLRMSK (0XFFFFFFFDU)
  683. #define VHA_CR_SYS_RESET_CTRL_REGBANK_EN (0X00000002U)
  684. /*
  685. Register VHA_CR_HOST_EVENT_SOURCE
  686. */
  687. #define VHA_CR_HOST_EVENT_SOURCE (0x0218U)
  688. #define VHA_CR_HOST_EVENT_SOURCE_MASKFULL (IMG_UINT64_C(0x00000000FFFFFF01))
  689. #define VHA_CR_HOST_EVENT_SOURCE_IC_SHIFT (24U)
  690. #define VHA_CR_HOST_EVENT_SOURCE_IC_CLRMSK (0X00FFFFFFU)
  691. #define VHA_CR_HOST_EVENT_SOURCE_CORE_SHIFT (16U)
  692. #define VHA_CR_HOST_EVENT_SOURCE_CORE_CLRMSK (0XFF00FFFFU)
  693. #define VHA_CR_HOST_EVENT_SOURCE_WM_SHIFT (8U)
  694. #define VHA_CR_HOST_EVENT_SOURCE_WM_CLRMSK (0XFFFF00FFU)
  695. #define VHA_CR_HOST_EVENT_SOURCE_SYS_SHIFT (0U)
  696. #define VHA_CR_HOST_EVENT_SOURCE_SYS_CLRMSK (0XFFFFFFFEU)
  697. #define VHA_CR_HOST_EVENT_SOURCE_SYS_EN (0X00000001U)
  698. #define VHA_CR_SYS_EVENT_TYPE_LOGIC_ERROR_SHIFT (30U)
  699. #define VHA_CR_SYS_EVENT_TYPE_LOGIC_ERROR_CLRMSK (0XBFFFFFFFU)
  700. #define VHA_CR_SYS_EVENT_TYPE_LOGIC_ERROR_EN (0X40000000U)
  701. #define VHA_CR_SYS_EVENT_TYPE_RAM_CORRECTION_SHIFT (29U)
  702. #define VHA_CR_SYS_EVENT_TYPE_RAM_CORRECTION_CLRMSK (0XDFFFFFFFU)
  703. #define VHA_CR_SYS_EVENT_TYPE_RAM_CORRECTION_EN (0X20000000U)
  704. #define VHA_CR_SYS_EVENT_TYPE_RAM_DETECTION_SHIFT (28U)
  705. #define VHA_CR_SYS_EVENT_TYPE_RAM_DETECTION_CLRMSK (0XEFFFFFFFU)
  706. #define VHA_CR_SYS_EVENT_TYPE_RAM_DETECTION_EN (0X10000000U)
  707. #define VHA_CR_SYS_EVENT_TYPE_LSYNC_INV_REQ_SHIFT (27U)
  708. #define VHA_CR_SYS_EVENT_TYPE_LSYNC_INV_REQ_CLRMSK (0XF7FFFFFFU)
  709. #define VHA_CR_SYS_EVENT_TYPE_LSYNC_INV_REQ_EN (0X08000000U)
  710. #define VHA_CR_SYS_EVENT_TYPE_SOCM_SCRUB_DONE_SHIFT (26U)
  711. #define VHA_CR_SYS_EVENT_TYPE_SOCM_SCRUB_DONE_CLRMSK (0XFBFFFFFFU)
  712. #define VHA_CR_SYS_EVENT_TYPE_SOCM_SCRUB_DONE_EN (0X04000000U)
  713. #define VHA_CR_SYS_EVENT_TYPE_AXI_MEMORY_PARITY_ERROR_SHIFT (21U)
  714. #define VHA_CR_SYS_EVENT_TYPE_AXI_MEMORY_PARITY_ERROR_CLRMSK (0XFE1FFFFFU)
  715. #define VHA_CR_SYS_EVENT_TYPE_SYS_MEM_WDT_SHIFT (20U)
  716. #define VHA_CR_SYS_EVENT_TYPE_SYS_MEM_WDT_CLRMSK (0XFFEFFFFFU)
  717. #define VHA_CR_SYS_EVENT_TYPE_SYS_MEM_WDT_EN (0X00100000U)
  718. #define VHA_CR_SYS_EVENT_TYPE_MMU_PARITY_ERROR_SHIFT (16U)
  719. #define VHA_CR_SYS_EVENT_TYPE_MMU_PARITY_ERROR_CLRMSK (0XFFF0FFFFU)
  720. #define VHA_CR_SYS_EVENT_TYPE_MMU_PAGE_FAULT_SHIFT (8U)
  721. #define VHA_CR_SYS_EVENT_TYPE_MMU_PAGE_FAULT_CLRMSK (0XFFFF00FFU)
  722. #define VHA_CR_SYS_EVENT_TYPE_AXI_ERROR_SHIFT (4U)
  723. #define VHA_CR_SYS_EVENT_TYPE_AXI_ERROR_CLRMSK (0XFFFFFF0FU)
  724. #define VHA_CR_SYS_EVENT_TYPE_RAM_INIT_DONE_SHIFT (3U)
  725. #define VHA_CR_SYS_EVENT_TYPE_RAM_INIT_DONE_CLRMSK (0XFFFFFFF7U)
  726. #define VHA_CR_SYS_EVENT_TYPE_RAM_INIT_DONE_EN (0X00000008U)
  727. #define VHA_CR_SYS_EVENT_TYPE_MEMBUS_RESET_DONE_SHIFT (2U)
  728. #define VHA_CR_SYS_EVENT_TYPE_MEMBUS_RESET_DONE_CLRMSK (0XFFFFFFFBU)
  729. #define VHA_CR_SYS_EVENT_TYPE_MEMBUS_RESET_DONE_EN (0X00000004U)
  730. #define VHA_CR_SYS_EVENT_TYPE_POWER_ABORT_SHIFT (1U)
  731. #define VHA_CR_SYS_EVENT_TYPE_POWER_ABORT_CLRMSK (0XFFFFFFFDU)
  732. #define VHA_CR_SYS_EVENT_TYPE_POWER_ABORT_EN (0X00000002U)
  733. #define VHA_CR_SYS_EVENT_TYPE_POWER_COMPLETE_SHIFT (0U)
  734. #define VHA_CR_SYS_EVENT_TYPE_POWER_COMPLETE_CLRMSK (0XFFFFFFFEU)
  735. #define VHA_CR_SYS_EVENT_TYPE_POWER_COMPLETE_EN (0X00000001U)
  736. #define VHA_CR_SYS_EVENT_STATUS_TYPE_PARITY_SHIFT (31U)
  737. #define VHA_CR_SYS_EVENT_STATUS_TYPE_PARITY_CLRMSK (0X7FFFFFFFU)
  738. #define VHA_CR_SYS_EVENT_STATUS_TYPE_PARITY_EN (0X80000000U)
  739. #define VHA_CR_SYS_EVENT_STATUS_TYPE_LOGIC_ERROR_SHIFT (30U)
  740. #define VHA_CR_SYS_EVENT_STATUS_TYPE_LOGIC_ERROR_CLRMSK (0XBFFFFFFFU)
  741. #define VHA_CR_SYS_EVENT_STATUS_TYPE_LOGIC_ERROR_EN (0X40000000U)
  742. #define VHA_CR_SYS_EVENT_STATUS_TYPE_RAM_CORRECTION_SHIFT (29U)
  743. #define VHA_CR_SYS_EVENT_STATUS_TYPE_RAM_CORRECTION_CLRMSK (0XDFFFFFFFU)
  744. #define VHA_CR_SYS_EVENT_STATUS_TYPE_RAM_CORRECTION_EN (0X20000000U)
  745. #define VHA_CR_SYS_EVENT_STATUS_TYPE_RAM_DETECTION_SHIFT (28U)
  746. #define VHA_CR_SYS_EVENT_STATUS_TYPE_RAM_DETECTION_CLRMSK (0XEFFFFFFFU)
  747. #define VHA_CR_SYS_EVENT_STATUS_TYPE_RAM_DETECTION_EN (0X10000000U)
  748. #define VHA_CR_SYS_EVENT_STATUS_TYPE_LSYNC_INV_REQ_SHIFT (27U)
  749. #define VHA_CR_SYS_EVENT_STATUS_TYPE_LSYNC_INV_REQ_CLRMSK (0XF7FFFFFFU)
  750. #define VHA_CR_SYS_EVENT_STATUS_TYPE_LSYNC_INV_REQ_EN (0X08000000U)
  751. #define VHA_CR_SYS_EVENT_STATUS_TYPE_SOCM_SCRUB_DONE_SHIFT (26U)
  752. #define VHA_CR_SYS_EVENT_STATUS_TYPE_SOCM_SCRUB_DONE_CLRMSK (0XFBFFFFFFU)
  753. #define VHA_CR_SYS_EVENT_STATUS_TYPE_SOCM_SCRUB_DONE_EN (0X04000000U)
  754. #define VHA_CR_SYS_EVENT_STATUS_TYPE_AXI_MEMORY_PARITY_ERROR_SHIFT (21U)
  755. #define VHA_CR_SYS_EVENT_STATUS_TYPE_AXI_MEMORY_PARITY_ERROR_CLRMSK (0XFE1FFFFFU)
  756. #define VHA_CR_SYS_EVENT_STATUS_TYPE_SYS_MEM_WDT_SHIFT (20U)
  757. #define VHA_CR_SYS_EVENT_STATUS_TYPE_SYS_MEM_WDT_CLRMSK (0XFFEFFFFFU)
  758. #define VHA_CR_SYS_EVENT_STATUS_TYPE_SYS_MEM_WDT_EN (0X00100000U)
  759. #define VHA_CR_SYS_EVENT_STATUS_TYPE_MMU_PARITY_ERROR_SHIFT (16U)
  760. #define VHA_CR_SYS_EVENT_STATUS_TYPE_MMU_PARITY_ERROR_CLRMSK (0XFFF0FFFFU)
  761. #define VHA_CR_SYS_EVENT_STATUS_TYPE_MMU_PAGE_FAULT_SHIFT (8U)
  762. #define VHA_CR_SYS_EVENT_STATUS_TYPE_MMU_PAGE_FAULT_CLRMSK (0XFFFF00FFU)
  763. #define VHA_CR_SYS_EVENT_STATUS_TYPE_AXI_ERROR_SHIFT (4U)
  764. #define VHA_CR_SYS_EVENT_STATUS_TYPE_AXI_ERROR_CLRMSK (0XFFFFFF0FU)
  765. #define VHA_CR_SYS_EVENT_STATUS_TYPE_RAM_INIT_DONE_SHIFT (3U)
  766. #define VHA_CR_SYS_EVENT_STATUS_TYPE_RAM_INIT_DONE_CLRMSK (0XFFFFFFF7U)
  767. #define VHA_CR_SYS_EVENT_STATUS_TYPE_RAM_INIT_DONE_EN (0X00000008U)
  768. #define VHA_CR_SYS_EVENT_STATUS_TYPE_MEMBUS_RESET_DONE_SHIFT (2U)
  769. #define VHA_CR_SYS_EVENT_STATUS_TYPE_MEMBUS_RESET_DONE_CLRMSK (0XFFFFFFFBU)
  770. #define VHA_CR_SYS_EVENT_STATUS_TYPE_MEMBUS_RESET_DONE_EN (0X00000004U)
  771. #define VHA_CR_SYS_EVENT_STATUS_TYPE_POWER_ABORT_SHIFT (1U)
  772. #define VHA_CR_SYS_EVENT_STATUS_TYPE_POWER_ABORT_CLRMSK (0XFFFFFFFDU)
  773. #define VHA_CR_SYS_EVENT_STATUS_TYPE_POWER_ABORT_EN (0X00000002U)
  774. #define VHA_CR_SYS_EVENT_STATUS_TYPE_POWER_COMPLETE_SHIFT (0U)
  775. #define VHA_CR_SYS_EVENT_STATUS_TYPE_POWER_COMPLETE_CLRMSK (0XFFFFFFFEU)
  776. #define VHA_CR_SYS_EVENT_STATUS_TYPE_POWER_COMPLETE_EN (0X00000001U)
  777. /*
  778. Register VHA_CR_SYS_EVENT_ENABLE
  779. */
  780. #define VHA_CR_SYS_EVENT_ENABLE (0x0220U)
  781. #define VHA_CR_SYS_EVENT_ENABLE_MASKFULL (IMG_UINT64_C(0x000000007DFFFFFF))
  782. #define VHA_CR_SYS_EVENT_ENABLE_LOGIC_ERROR_SHIFT (30U)
  783. #define VHA_CR_SYS_EVENT_ENABLE_LOGIC_ERROR_CLRMSK (0XBFFFFFFFU)
  784. #define VHA_CR_SYS_EVENT_ENABLE_LOGIC_ERROR_EN (0X40000000U)
  785. #define VHA_CR_SYS_EVENT_ENABLE_RAM_CORRECTION_SHIFT (29U)
  786. #define VHA_CR_SYS_EVENT_ENABLE_RAM_CORRECTION_CLRMSK (0XDFFFFFFFU)
  787. #define VHA_CR_SYS_EVENT_ENABLE_RAM_CORRECTION_EN (0X20000000U)
  788. #define VHA_CR_SYS_EVENT_ENABLE_RAM_DETECTION_SHIFT (28U)
  789. #define VHA_CR_SYS_EVENT_ENABLE_RAM_DETECTION_CLRMSK (0XEFFFFFFFU)
  790. #define VHA_CR_SYS_EVENT_ENABLE_RAM_DETECTION_EN (0X10000000U)
  791. #define VHA_CR_SYS_EVENT_ENABLE_LSYNC_INV_REQ_SHIFT (27U)
  792. #define VHA_CR_SYS_EVENT_ENABLE_LSYNC_INV_REQ_CLRMSK (0XF7FFFFFFU)
  793. #define VHA_CR_SYS_EVENT_ENABLE_LSYNC_INV_REQ_EN (0X08000000U)
  794. #define VHA_CR_SYS_EVENT_ENABLE_SOCM_SCRUB_DONE_SHIFT (26U)
  795. #define VHA_CR_SYS_EVENT_ENABLE_SOCM_SCRUB_DONE_CLRMSK (0XFBFFFFFFU)
  796. #define VHA_CR_SYS_EVENT_ENABLE_SOCM_SCRUB_DONE_EN (0X04000000U)
  797. #define VHA_CR_SYS_EVENT_ENABLE_AXI_MEMORY_PARITY_ERROR_SHIFT (21U)
  798. #define VHA_CR_SYS_EVENT_ENABLE_AXI_MEMORY_PARITY_ERROR_CLRMSK (0XFE1FFFFFU)
  799. #define VHA_CR_SYS_EVENT_ENABLE_SYS_MEM_WDT_SHIFT (20U)
  800. #define VHA_CR_SYS_EVENT_ENABLE_SYS_MEM_WDT_CLRMSK (0XFFEFFFFFU)
  801. #define VHA_CR_SYS_EVENT_ENABLE_SYS_MEM_WDT_EN (0X00100000U)
  802. #define VHA_CR_SYS_EVENT_ENABLE_MMU_PARITY_ERROR_SHIFT (16U)
  803. #define VHA_CR_SYS_EVENT_ENABLE_MMU_PARITY_ERROR_CLRMSK (0XFFF0FFFFU)
  804. #define VHA_CR_SYS_EVENT_ENABLE_MMU_PAGE_FAULT_SHIFT (8U)
  805. #define VHA_CR_SYS_EVENT_ENABLE_MMU_PAGE_FAULT_CLRMSK (0XFFFF00FFU)
  806. #define VHA_CR_SYS_EVENT_ENABLE_AXI_ERROR_SHIFT (4U)
  807. #define VHA_CR_SYS_EVENT_ENABLE_AXI_ERROR_CLRMSK (0XFFFFFF0FU)
  808. #define VHA_CR_SYS_EVENT_ENABLE_RAM_INIT_DONE_SHIFT (3U)
  809. #define VHA_CR_SYS_EVENT_ENABLE_RAM_INIT_DONE_CLRMSK (0XFFFFFFF7U)
  810. #define VHA_CR_SYS_EVENT_ENABLE_RAM_INIT_DONE_EN (0X00000008U)
  811. #define VHA_CR_SYS_EVENT_ENABLE_MEMBUS_RESET_DONE_SHIFT (2U)
  812. #define VHA_CR_SYS_EVENT_ENABLE_MEMBUS_RESET_DONE_CLRMSK (0XFFFFFFFBU)
  813. #define VHA_CR_SYS_EVENT_ENABLE_MEMBUS_RESET_DONE_EN (0X00000004U)
  814. #define VHA_CR_SYS_EVENT_ENABLE_POWER_ABORT_SHIFT (1U)
  815. #define VHA_CR_SYS_EVENT_ENABLE_POWER_ABORT_CLRMSK (0XFFFFFFFDU)
  816. #define VHA_CR_SYS_EVENT_ENABLE_POWER_ABORT_EN (0X00000002U)
  817. #define VHA_CR_SYS_EVENT_ENABLE_POWER_COMPLETE_SHIFT (0U)
  818. #define VHA_CR_SYS_EVENT_ENABLE_POWER_COMPLETE_CLRMSK (0XFFFFFFFEU)
  819. #define VHA_CR_SYS_EVENT_ENABLE_POWER_COMPLETE_EN (0X00000001U)
  820. /*
  821. Register VHA_CR_SYS_EVENT_STATUS
  822. */
  823. #define VHA_CR_SYS_EVENT_STATUS (0x0228U)
  824. #define VHA_CR_SYS_EVENT_STATUS_MASKFULL (IMG_UINT64_C(0x00000000FDFFFFFF))
  825. #define VHA_CR_SYS_EVENT_STATUS_PARITY_SHIFT (31U)
  826. #define VHA_CR_SYS_EVENT_STATUS_PARITY_CLRMSK (0X7FFFFFFFU)
  827. #define VHA_CR_SYS_EVENT_STATUS_PARITY_EN (0X80000000U)
  828. #define VHA_CR_SYS_EVENT_STATUS_LOGIC_ERROR_SHIFT (30U)
  829. #define VHA_CR_SYS_EVENT_STATUS_LOGIC_ERROR_CLRMSK (0XBFFFFFFFU)
  830. #define VHA_CR_SYS_EVENT_STATUS_LOGIC_ERROR_EN (0X40000000U)
  831. #define VHA_CR_SYS_EVENT_STATUS_RAM_CORRECTION_SHIFT (29U)
  832. #define VHA_CR_SYS_EVENT_STATUS_RAM_CORRECTION_CLRMSK (0XDFFFFFFFU)
  833. #define VHA_CR_SYS_EVENT_STATUS_RAM_CORRECTION_EN (0X20000000U)
  834. #define VHA_CR_SYS_EVENT_STATUS_RAM_DETECTION_SHIFT (28U)
  835. #define VHA_CR_SYS_EVENT_STATUS_RAM_DETECTION_CLRMSK (0XEFFFFFFFU)
  836. #define VHA_CR_SYS_EVENT_STATUS_RAM_DETECTION_EN (0X10000000U)
  837. #define VHA_CR_SYS_EVENT_STATUS_LSYNC_INV_REQ_SHIFT (27U)
  838. #define VHA_CR_SYS_EVENT_STATUS_LSYNC_INV_REQ_CLRMSK (0XF7FFFFFFU)
  839. #define VHA_CR_SYS_EVENT_STATUS_LSYNC_INV_REQ_EN (0X08000000U)
  840. #define VHA_CR_SYS_EVENT_STATUS_SOCM_SCRUB_DONE_SHIFT (26U)
  841. #define VHA_CR_SYS_EVENT_STATUS_SOCM_SCRUB_DONE_CLRMSK (0XFBFFFFFFU)
  842. #define VHA_CR_SYS_EVENT_STATUS_SOCM_SCRUB_DONE_EN (0X04000000U)
  843. #define VHA_CR_SYS_EVENT_STATUS_AXI_MEMORY_PARITY_ERROR_SHIFT (21U)
  844. #define VHA_CR_SYS_EVENT_STATUS_AXI_MEMORY_PARITY_ERROR_CLRMSK (0XFE1FFFFFU)
  845. #define VHA_CR_SYS_EVENT_STATUS_SYS_MEM_WDT_SHIFT (20U)
  846. #define VHA_CR_SYS_EVENT_STATUS_SYS_MEM_WDT_CLRMSK (0XFFEFFFFFU)
  847. #define VHA_CR_SYS_EVENT_STATUS_SYS_MEM_WDT_EN (0X00100000U)
  848. #define VHA_CR_SYS_EVENT_STATUS_MMU_PARITY_ERROR_SHIFT (16U)
  849. #define VHA_CR_SYS_EVENT_STATUS_MMU_PARITY_ERROR_CLRMSK (0XFFF0FFFFU)
  850. #define VHA_CR_SYS_EVENT_STATUS_MMU_PAGE_FAULT_SHIFT (8U)
  851. #define VHA_CR_SYS_EVENT_STATUS_MMU_PAGE_FAULT_CLRMSK (0XFFFF00FFU)
  852. #define VHA_CR_SYS_EVENT_STATUS_AXI_ERROR_SHIFT (4U)
  853. #define VHA_CR_SYS_EVENT_STATUS_AXI_ERROR_CLRMSK (0XFFFFFF0FU)
  854. #define VHA_CR_SYS_EVENT_STATUS_RAM_INIT_DONE_SHIFT (3U)
  855. #define VHA_CR_SYS_EVENT_STATUS_RAM_INIT_DONE_CLRMSK (0XFFFFFFF7U)
  856. #define VHA_CR_SYS_EVENT_STATUS_RAM_INIT_DONE_EN (0X00000008U)
  857. #define VHA_CR_SYS_EVENT_STATUS_MEMBUS_RESET_DONE_SHIFT (2U)
  858. #define VHA_CR_SYS_EVENT_STATUS_MEMBUS_RESET_DONE_CLRMSK (0XFFFFFFFBU)
  859. #define VHA_CR_SYS_EVENT_STATUS_MEMBUS_RESET_DONE_EN (0X00000004U)
  860. #define VHA_CR_SYS_EVENT_STATUS_POWER_ABORT_SHIFT (1U)
  861. #define VHA_CR_SYS_EVENT_STATUS_POWER_ABORT_CLRMSK (0XFFFFFFFDU)
  862. #define VHA_CR_SYS_EVENT_STATUS_POWER_ABORT_EN (0X00000002U)
  863. #define VHA_CR_SYS_EVENT_STATUS_POWER_COMPLETE_SHIFT (0U)
  864. #define VHA_CR_SYS_EVENT_STATUS_POWER_COMPLETE_CLRMSK (0XFFFFFFFEU)
  865. #define VHA_CR_SYS_EVENT_STATUS_POWER_COMPLETE_EN (0X00000001U)
  866. /*
  867. Register VHA_CR_SYS_EVENT_STATUS_DISABLE
  868. */
  869. #define VHA_CR_SYS_EVENT_STATUS_DISABLE (0x0290U)
  870. #define VHA_CR_SYS_EVENT_STATUS_DISABLE_MASKFULL (IMG_UINT64_C(0x000000007DFFFFFF))
  871. #define VHA_CR_SYS_EVENT_STATUS_DISABLE_LOGIC_ERROR_SHIFT (30U)
  872. #define VHA_CR_SYS_EVENT_STATUS_DISABLE_LOGIC_ERROR_CLRMSK (0XBFFFFFFFU)
  873. #define VHA_CR_SYS_EVENT_STATUS_DISABLE_LOGIC_ERROR_EN (0X40000000U)
  874. #define VHA_CR_SYS_EVENT_STATUS_DISABLE_RAM_CORRECTION_SHIFT (29U)
  875. #define VHA_CR_SYS_EVENT_STATUS_DISABLE_RAM_CORRECTION_CLRMSK (0XDFFFFFFFU)
  876. #define VHA_CR_SYS_EVENT_STATUS_DISABLE_RAM_CORRECTION_EN (0X20000000U)
  877. #define VHA_CR_SYS_EVENT_STATUS_DISABLE_RAM_DETECTION_SHIFT (28U)
  878. #define VHA_CR_SYS_EVENT_STATUS_DISABLE_RAM_DETECTION_CLRMSK (0XEFFFFFFFU)
  879. #define VHA_CR_SYS_EVENT_STATUS_DISABLE_RAM_DETECTION_EN (0X10000000U)
  880. #define VHA_CR_SYS_EVENT_STATUS_DISABLE_LSYNC_INV_REQ_SHIFT (27U)
  881. #define VHA_CR_SYS_EVENT_STATUS_DISABLE_LSYNC_INV_REQ_CLRMSK (0XF7FFFFFFU)
  882. #define VHA_CR_SYS_EVENT_STATUS_DISABLE_LSYNC_INV_REQ_EN (0X08000000U)
  883. #define VHA_CR_SYS_EVENT_STATUS_DISABLE_SOCM_SCRUB_DONE_SHIFT (26U)
  884. #define VHA_CR_SYS_EVENT_STATUS_DISABLE_SOCM_SCRUB_DONE_CLRMSK (0XFBFFFFFFU)
  885. #define VHA_CR_SYS_EVENT_STATUS_DISABLE_SOCM_SCRUB_DONE_EN (0X04000000U)
  886. #define VHA_CR_SYS_EVENT_STATUS_DISABLE_AXI_MEMORY_PARITY_ERROR_SHIFT (21U)
  887. #define VHA_CR_SYS_EVENT_STATUS_DISABLE_AXI_MEMORY_PARITY_ERROR_CLRMSK (0XFE1FFFFFU)
  888. #define VHA_CR_SYS_EVENT_STATUS_DISABLE_SYS_MEM_WDT_SHIFT (20U)
  889. #define VHA_CR_SYS_EVENT_STATUS_DISABLE_SYS_MEM_WDT_CLRMSK (0XFFEFFFFFU)
  890. #define VHA_CR_SYS_EVENT_STATUS_DISABLE_SYS_MEM_WDT_EN (0X00100000U)
  891. #define VHA_CR_SYS_EVENT_STATUS_DISABLE_MMU_PARITY_ERROR_SHIFT (16U)
  892. #define VHA_CR_SYS_EVENT_STATUS_DISABLE_MMU_PARITY_ERROR_CLRMSK (0XFFF0FFFFU)
  893. #define VHA_CR_SYS_EVENT_STATUS_DISABLE_MMU_PAGE_FAULT_SHIFT (8U)
  894. #define VHA_CR_SYS_EVENT_STATUS_DISABLE_MMU_PAGE_FAULT_CLRMSK (0XFFFF00FFU)
  895. #define VHA_CR_SYS_EVENT_STATUS_DISABLE_AXI_ERROR_SHIFT (4U)
  896. #define VHA_CR_SYS_EVENT_STATUS_DISABLE_AXI_ERROR_CLRMSK (0XFFFFFF0FU)
  897. #define VHA_CR_SYS_EVENT_STATUS_DISABLE_RAM_INIT_DONE_SHIFT (3U)
  898. #define VHA_CR_SYS_EVENT_STATUS_DISABLE_RAM_INIT_DONE_CLRMSK (0XFFFFFFF7U)
  899. #define VHA_CR_SYS_EVENT_STATUS_DISABLE_RAM_INIT_DONE_EN (0X00000008U)
  900. #define VHA_CR_SYS_EVENT_STATUS_DISABLE_MEMBUS_RESET_DONE_SHIFT (2U)
  901. #define VHA_CR_SYS_EVENT_STATUS_DISABLE_MEMBUS_RESET_DONE_CLRMSK (0XFFFFFFFBU)
  902. #define VHA_CR_SYS_EVENT_STATUS_DISABLE_MEMBUS_RESET_DONE_EN (0X00000004U)
  903. #define VHA_CR_SYS_EVENT_STATUS_DISABLE_POWER_ABORT_SHIFT (1U)
  904. #define VHA_CR_SYS_EVENT_STATUS_DISABLE_POWER_ABORT_CLRMSK (0XFFFFFFFDU)
  905. #define VHA_CR_SYS_EVENT_STATUS_DISABLE_POWER_ABORT_EN (0X00000002U)
  906. #define VHA_CR_SYS_EVENT_STATUS_DISABLE_POWER_COMPLETE_SHIFT (0U)
  907. #define VHA_CR_SYS_EVENT_STATUS_DISABLE_POWER_COMPLETE_CLRMSK (0XFFFFFFFEU)
  908. #define VHA_CR_SYS_EVENT_STATUS_DISABLE_POWER_COMPLETE_EN (0X00000001U)
  909. /*
  910. Register VHA_CR_SYS_EVENT_CLEAR
  911. */
  912. #define VHA_CR_SYS_EVENT_CLEAR (0x0230U)
  913. #define VHA_CR_SYS_EVENT_CLEAR_MASKFULL (IMG_UINT64_C(0x000000007DFFFFFF))
  914. #define VHA_CR_SYS_EVENT_CLEAR_LOGIC_ERROR_SHIFT (30U)
  915. #define VHA_CR_SYS_EVENT_CLEAR_LOGIC_ERROR_CLRMSK (0XBFFFFFFFU)
  916. #define VHA_CR_SYS_EVENT_CLEAR_LOGIC_ERROR_EN (0X40000000U)
  917. #define VHA_CR_SYS_EVENT_CLEAR_RAM_CORRECTION_SHIFT (29U)
  918. #define VHA_CR_SYS_EVENT_CLEAR_RAM_CORRECTION_CLRMSK (0XDFFFFFFFU)
  919. #define VHA_CR_SYS_EVENT_CLEAR_RAM_CORRECTION_EN (0X20000000U)
  920. #define VHA_CR_SYS_EVENT_CLEAR_RAM_DETECTION_SHIFT (28U)
  921. #define VHA_CR_SYS_EVENT_CLEAR_RAM_DETECTION_CLRMSK (0XEFFFFFFFU)
  922. #define VHA_CR_SYS_EVENT_CLEAR_RAM_DETECTION_EN (0X10000000U)
  923. #define VHA_CR_SYS_EVENT_CLEAR_LSYNC_INV_REQ_SHIFT (27U)
  924. #define VHA_CR_SYS_EVENT_CLEAR_LSYNC_INV_REQ_CLRMSK (0XF7FFFFFFU)
  925. #define VHA_CR_SYS_EVENT_CLEAR_LSYNC_INV_REQ_EN (0X08000000U)
  926. #define VHA_CR_SYS_EVENT_CLEAR_SOCM_SCRUB_DONE_SHIFT (26U)
  927. #define VHA_CR_SYS_EVENT_CLEAR_SOCM_SCRUB_DONE_CLRMSK (0XFBFFFFFFU)
  928. #define VHA_CR_SYS_EVENT_CLEAR_SOCM_SCRUB_DONE_EN (0X04000000U)
  929. #define VHA_CR_SYS_EVENT_CLEAR_AXI_MEMORY_PARITY_ERROR_SHIFT (21U)
  930. #define VHA_CR_SYS_EVENT_CLEAR_AXI_MEMORY_PARITY_ERROR_CLRMSK (0XFE1FFFFFU)
  931. #define VHA_CR_SYS_EVENT_CLEAR_SYS_MEM_WDT_SHIFT (20U)
  932. #define VHA_CR_SYS_EVENT_CLEAR_SYS_MEM_WDT_CLRMSK (0XFFEFFFFFU)
  933. #define VHA_CR_SYS_EVENT_CLEAR_SYS_MEM_WDT_EN (0X00100000U)
  934. #define VHA_CR_SYS_EVENT_CLEAR_MMU_PARITY_ERROR_SHIFT (16U)
  935. #define VHA_CR_SYS_EVENT_CLEAR_MMU_PARITY_ERROR_CLRMSK (0XFFF0FFFFU)
  936. #define VHA_CR_SYS_EVENT_CLEAR_MMU_PAGE_FAULT_SHIFT (8U)
  937. #define VHA_CR_SYS_EVENT_CLEAR_MMU_PAGE_FAULT_CLRMSK (0XFFFF00FFU)
  938. #define VHA_CR_SYS_EVENT_CLEAR_AXI_ERROR_SHIFT (4U)
  939. #define VHA_CR_SYS_EVENT_CLEAR_AXI_ERROR_CLRMSK (0XFFFFFF0FU)
  940. #define VHA_CR_SYS_EVENT_CLEAR_RAM_INIT_DONE_SHIFT (3U)
  941. #define VHA_CR_SYS_EVENT_CLEAR_RAM_INIT_DONE_CLRMSK (0XFFFFFFF7U)
  942. #define VHA_CR_SYS_EVENT_CLEAR_RAM_INIT_DONE_EN (0X00000008U)
  943. #define VHA_CR_SYS_EVENT_CLEAR_MEMBUS_RESET_DONE_SHIFT (2U)
  944. #define VHA_CR_SYS_EVENT_CLEAR_MEMBUS_RESET_DONE_CLRMSK (0XFFFFFFFBU)
  945. #define VHA_CR_SYS_EVENT_CLEAR_MEMBUS_RESET_DONE_EN (0X00000004U)
  946. #define VHA_CR_SYS_EVENT_CLEAR_POWER_ABORT_SHIFT (1U)
  947. #define VHA_CR_SYS_EVENT_CLEAR_POWER_ABORT_CLRMSK (0XFFFFFFFDU)
  948. #define VHA_CR_SYS_EVENT_CLEAR_POWER_ABORT_EN (0X00000002U)
  949. #define VHA_CR_SYS_EVENT_CLEAR_POWER_COMPLETE_SHIFT (0U)
  950. #define VHA_CR_SYS_EVENT_CLEAR_POWER_COMPLETE_CLRMSK (0XFFFFFFFEU)
  951. #define VHA_CR_SYS_EVENT_CLEAR_POWER_COMPLETE_EN (0X00000001U)
  952. /*
  953. Register VHA_CR_SYS_EVENT_INJECT
  954. */
  955. #define VHA_CR_SYS_EVENT_INJECT (0x0288U)
  956. #define VHA_CR_SYS_EVENT_INJECT_MASKFULL (IMG_UINT64_C(0x000000007DFFFFFF))
  957. #define VHA_CR_SYS_EVENT_INJECT_LOGIC_ERROR_SHIFT (30U)
  958. #define VHA_CR_SYS_EVENT_INJECT_LOGIC_ERROR_CLRMSK (0XBFFFFFFFU)
  959. #define VHA_CR_SYS_EVENT_INJECT_LOGIC_ERROR_EN (0X40000000U)
  960. #define VHA_CR_SYS_EVENT_INJECT_RAM_CORRECTION_SHIFT (29U)
  961. #define VHA_CR_SYS_EVENT_INJECT_RAM_CORRECTION_CLRMSK (0XDFFFFFFFU)
  962. #define VHA_CR_SYS_EVENT_INJECT_RAM_CORRECTION_EN (0X20000000U)
  963. #define VHA_CR_SYS_EVENT_INJECT_RAM_DETECTION_SHIFT (28U)
  964. #define VHA_CR_SYS_EVENT_INJECT_RAM_DETECTION_CLRMSK (0XEFFFFFFFU)
  965. #define VHA_CR_SYS_EVENT_INJECT_RAM_DETECTION_EN (0X10000000U)
  966. #define VHA_CR_SYS_EVENT_INJECT_LSYNC_INV_REQ_SHIFT (27U)
  967. #define VHA_CR_SYS_EVENT_INJECT_LSYNC_INV_REQ_CLRMSK (0XF7FFFFFFU)
  968. #define VHA_CR_SYS_EVENT_INJECT_LSYNC_INV_REQ_EN (0X08000000U)
  969. #define VHA_CR_SYS_EVENT_INJECT_SOCM_SCRUB_DONE_SHIFT (26U)
  970. #define VHA_CR_SYS_EVENT_INJECT_SOCM_SCRUB_DONE_CLRMSK (0XFBFFFFFFU)
  971. #define VHA_CR_SYS_EVENT_INJECT_SOCM_SCRUB_DONE_EN (0X04000000U)
  972. #define VHA_CR_SYS_EVENT_INJECT_AXI_MEMORY_PARITY_ERROR_SHIFT (21U)
  973. #define VHA_CR_SYS_EVENT_INJECT_AXI_MEMORY_PARITY_ERROR_CLRMSK (0XFE1FFFFFU)
  974. #define VHA_CR_SYS_EVENT_INJECT_SYS_MEM_WDT_SHIFT (20U)
  975. #define VHA_CR_SYS_EVENT_INJECT_SYS_MEM_WDT_CLRMSK (0XFFEFFFFFU)
  976. #define VHA_CR_SYS_EVENT_INJECT_SYS_MEM_WDT_EN (0X00100000U)
  977. #define VHA_CR_SYS_EVENT_INJECT_MMU_PARITY_ERROR_SHIFT (16U)
  978. #define VHA_CR_SYS_EVENT_INJECT_MMU_PARITY_ERROR_CLRMSK (0XFFF0FFFFU)
  979. #define VHA_CR_SYS_EVENT_INJECT_MMU_PAGE_FAULT_SHIFT (8U)
  980. #define VHA_CR_SYS_EVENT_INJECT_MMU_PAGE_FAULT_CLRMSK (0XFFFF00FFU)
  981. #define VHA_CR_SYS_EVENT_INJECT_AXI_ERROR_SHIFT (4U)
  982. #define VHA_CR_SYS_EVENT_INJECT_AXI_ERROR_CLRMSK (0XFFFFFF0FU)
  983. #define VHA_CR_SYS_EVENT_INJECT_RAM_INIT_DONE_SHIFT (3U)
  984. #define VHA_CR_SYS_EVENT_INJECT_RAM_INIT_DONE_CLRMSK (0XFFFFFFF7U)
  985. #define VHA_CR_SYS_EVENT_INJECT_RAM_INIT_DONE_EN (0X00000008U)
  986. #define VHA_CR_SYS_EVENT_INJECT_MEMBUS_RESET_DONE_SHIFT (2U)
  987. #define VHA_CR_SYS_EVENT_INJECT_MEMBUS_RESET_DONE_CLRMSK (0XFFFFFFFBU)
  988. #define VHA_CR_SYS_EVENT_INJECT_MEMBUS_RESET_DONE_EN (0X00000004U)
  989. #define VHA_CR_SYS_EVENT_INJECT_POWER_ABORT_SHIFT (1U)
  990. #define VHA_CR_SYS_EVENT_INJECT_POWER_ABORT_CLRMSK (0XFFFFFFFDU)
  991. #define VHA_CR_SYS_EVENT_INJECT_POWER_ABORT_EN (0X00000002U)
  992. #define VHA_CR_SYS_EVENT_INJECT_POWER_COMPLETE_SHIFT (0U)
  993. #define VHA_CR_SYS_EVENT_INJECT_POWER_COMPLETE_CLRMSK (0XFFFFFFFEU)
  994. #define VHA_CR_SYS_EVENT_INJECT_POWER_COMPLETE_EN (0X00000001U)
  995. /*
  996. Register VHA_CR_SYS_EVENT_THRESHOLD
  997. */
  998. #define VHA_CR_SYS_EVENT_THRESHOLD (0x0238U)
  999. #define VHA_CR_SYS_EVENT_THRESHOLD_MASKFULL (IMG_UINT64_C(0x000000000000FFFF))
  1000. #define VHA_CR_SYS_EVENT_THRESHOLD_RAM_CORRECTION_SHIFT (0U)
  1001. #define VHA_CR_SYS_EVENT_THRESHOLD_RAM_CORRECTION_CLRMSK (0XFFFF0000U)
  1002. /*
  1003. Register VHA_CR_SYS_EVENT_THRESHOLD_VAL
  1004. */
  1005. #define VHA_CR_SYS_EVENT_THRESHOLD_VAL (0x0240U)
  1006. #define VHA_CR_SYS_EVENT_THRESHOLD_VAL_MASKFULL (IMG_UINT64_C(0x000000000000FFFF))
  1007. #define VHA_CR_SYS_EVENT_THRESHOLD_VAL_RAM_CORRECTION_SHIFT (0U)
  1008. #define VHA_CR_SYS_EVENT_THRESHOLD_VAL_RAM_CORRECTION_CLRMSK (0XFFFF0000U)
  1009. /*
  1010. Register VHA_CR_POWER_EVENT
  1011. */
  1012. #define VHA_CR_POWER_EVENT (0x0248U)
  1013. #define VHA_CR_POWER_EVENT_MASKFULL (IMG_UINT64_C(0x0000000000FFFF03))
  1014. #define VHA_CR_POWER_EVENT_DOMAIN_SHIFT (8U)
  1015. #define VHA_CR_POWER_EVENT_DOMAIN_CLRMSK (0XFF0000FFU)
  1016. #define VHA_CR_POWER_EVENT_DOMAIN_RESERVED_SHIFT (17U)
  1017. #define VHA_CR_POWER_EVENT_DOMAIN_RESERVED_CLRMSK (0xff01ffff)
  1018. #define VHA_CR_POWER_EVENT_DOMAIN_CORE7_SHIFT (16U)
  1019. #define VHA_CR_POWER_EVENT_DOMAIN_CORE7_CLRMSK (0xfffeffff)
  1020. #define VHA_CR_POWER_EVENT_DOMAIN_CORE6_SHIFT (15U)
  1021. #define VHA_CR_POWER_EVENT_DOMAIN_CORE6_CLRMSK (0xffff7fff)
  1022. #define VHA_CR_POWER_EVENT_DOMAIN_CORE5_SHIFT (14U)
  1023. #define VHA_CR_POWER_EVENT_DOMAIN_CORE5_CLRMSK (0xffffbfff)
  1024. #define VHA_CR_POWER_EVENT_DOMAIN_CORE4_SHIFT (13U)
  1025. #define VHA_CR_POWER_EVENT_DOMAIN_CORE4_CLRMSK (0xffffdfff)
  1026. #define VHA_CR_POWER_EVENT_DOMAIN_CORE3_SHIFT (12U)
  1027. #define VHA_CR_POWER_EVENT_DOMAIN_CORE3_CLRMSK (0xffffefff)
  1028. #define VHA_CR_POWER_EVENT_DOMAIN_CORE2_SHIFT (11U)
  1029. #define VHA_CR_POWER_EVENT_DOMAIN_CORE2_CLRMSK (0xfffff7ff)
  1030. #define VHA_CR_POWER_EVENT_DOMAIN_CORE1_SHIFT (10U)
  1031. #define VHA_CR_POWER_EVENT_DOMAIN_CORE1_CLRMSK (0xfffffbff)
  1032. #define VHA_CR_POWER_EVENT_DOMAIN_CORE0_SHIFT (9U)
  1033. #define VHA_CR_POWER_EVENT_DOMAIN_CORE0_CLRMSK (0xfffffdff)
  1034. #define VHA_CR_POWER_EVENT_DOMAIN_TLC_SHIFT (8U)
  1035. #define VHA_CR_POWER_EVENT_DOMAIN_TLC_CLRMSK (0xfffffeff)
  1036. #define VHA_CR_POWER_EVENT_REQ_SHIFT (1U)
  1037. #define VHA_CR_POWER_EVENT_REQ_CLRMSK (0XFFFFFFFDU)
  1038. #define VHA_CR_POWER_EVENT_REQ_EN (0X00000002U)
  1039. #define VHA_CR_POWER_EVENT_TYPE_SHIFT (0U)
  1040. #define VHA_CR_POWER_EVENT_TYPE_CLRMSK (0XFFFFFFFEU)
  1041. #define VHA_CR_POWER_EVENT_TYPE_POWER_DOWN (00000000U)
  1042. #define VHA_CR_POWER_EVENT_TYPE_POWER_UP (0X00000001U)
  1043. /*
  1044. Register VHA_CR_IDLE_HYSTERESIS_COUNT
  1045. */
  1046. #define VHA_CR_IDLE_HYSTERESIS_COUNT (0x0250U)
  1047. #define VHA_CR_IDLE_HYSTERESIS_COUNT_MASKFULL (IMG_UINT64_C(0x000000000000001F))
  1048. #define VHA_CR_IDLE_HYSTERESIS_COUNT_VALUE_SHIFT (0U)
  1049. #define VHA_CR_IDLE_HYSTERESIS_COUNT_VALUE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFE0))
  1050. #define VHA_CR_RESET_CLK_CTRL_MODE_MASK (0x00000003U)
  1051. /*
  1052. Clock always OFF during reset. */
  1053. #define VHA_CR_RESET_CLK_CTRL_MODE_OFF (0x00000000U)
  1054. /*
  1055. Clock ON for 16 clock cycles during reset. */
  1056. #define VHA_CR_RESET_CLK_CTRL_MODE_ON_16 (0x00000001U)
  1057. /*
  1058. Clock ON for 64 clock cycles during reset. */
  1059. #define VHA_CR_RESET_CLK_CTRL_MODE_ON_64 (0x00000002U)
  1060. /*
  1061. Clock always ON during reset. */
  1062. #define VHA_CR_RESET_CLK_CTRL_MODE_ON (0x00000003U)
  1063. /*
  1064. Register VHA_CR_RESET_CLK_CTRL
  1065. */
  1066. #define VHA_CR_RESET_CLK_CTRL (0x0258U)
  1067. #define VHA_CR_RESET_CLK_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000000003))
  1068. #define VHA_CR_RESET_CLK_CTRL_CTRL_SHIFT (0U)
  1069. #define VHA_CR_RESET_CLK_CTRL_CTRL_CLRMSK (0XFFFFFFFCU)
  1070. #define VHA_CR_RESET_CLK_CTRL_CTRL_OFF (00000000U)
  1071. #define VHA_CR_RESET_CLK_CTRL_CTRL_ON_16 (0X00000001U)
  1072. #define VHA_CR_RESET_CLK_CTRL_CTRL_ON_64 (0X00000002U)
  1073. #define VHA_CR_RESET_CLK_CTRL_CTRL_ON (0X00000003U)
  1074. /*
  1075. Register VHA_CR_VHA_AXI_RESET_CTRL
  1076. */
  1077. #define VHA_CR_VHA_AXI_RESET_CTRL (0x0260U)
  1078. #define VHA_CR_VHA_AXI_RESET_CTRL_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  1079. #define VHA_CR_VHA_AXI_RESET_CTRL_SOFT_RESET_CYCLES_SHIFT (0U)
  1080. #define VHA_CR_VHA_AXI_RESET_CTRL_SOFT_RESET_CYCLES_CLRMSK (00000000U)
  1081. /*
  1082. Register VHA_CR_SYS_RAM_INIT
  1083. */
  1084. #define VHA_CR_SYS_RAM_INIT (0x0268U)
  1085. #define VHA_CR_SYS_RAM_INIT_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  1086. #define VHA_CR_SYS_RAM_INIT_KICK_SHIFT (0U)
  1087. #define VHA_CR_SYS_RAM_INIT_KICK_CLRMSK (0XFFFFFFFEU)
  1088. #define VHA_CR_SYS_RAM_INIT_KICK_EN (0X00000001U)
  1089. /*
  1090. Register VHA_CR_WM_EVENT_SOURCE
  1091. */
  1092. #define VHA_CR_WM_EVENT_SOURCE (0x0270U)
  1093. #define VHA_CR_WM_EVENT_SOURCE_MASKFULL (IMG_UINT64_C(0x00000000FFFF0000))
  1094. #define VHA_CR_WM_EVENT_SOURCE_IC_SHIFT (24U)
  1095. #define VHA_CR_WM_EVENT_SOURCE_IC_CLRMSK (0X00FFFFFFU)
  1096. #define VHA_CR_WM_EVENT_SOURCE_CORE_SHIFT (16U)
  1097. #define VHA_CR_WM_EVENT_SOURCE_CORE_CLRMSK (0XFF00FFFFU)
  1098. /*
  1099. Register VHA_CR_SYS_RTM_CTRL
  1100. */
  1101. #define VHA_CR_SYS_RTM_CTRL (0x0278U)
  1102. #define VHA_CR_SYS_RTM_CTRL_MASKFULL (IMG_UINT64_C(0x00000000C0FFFFF8))
  1103. #define VHA_CR_SYS_RTM_CTRL_RTM_ENABLE_SHIFT (31U)
  1104. #define VHA_CR_SYS_RTM_CTRL_RTM_ENABLE_CLRMSK (0X7FFFFFFFU)
  1105. #define VHA_CR_SYS_RTM_CTRL_RTM_ENABLE_EN (0X80000000U)
  1106. #define VHA_CR_SYS_RTM_CTRL_RTM_CHECK_SHIFT (30U)
  1107. #define VHA_CR_SYS_RTM_CTRL_RTM_CHECK_CLRMSK (0XBFFFFFFFU)
  1108. #define VHA_CR_SYS_RTM_CTRL_RTM_CHECK_EN (0X40000000U)
  1109. #define VHA_CR_SYS_RTM_CTRL_RTM_SELECTOR_SHIFT (3U)
  1110. #define VHA_CR_SYS_RTM_CTRL_RTM_SELECTOR_CLRMSK (0XFF000007U)
  1111. /*
  1112. Register VHA_CR_SYS_RTM_DATA
  1113. */
  1114. #define VHA_CR_SYS_RTM_DATA (0x0280U)
  1115. #define VHA_CR_SYS_RTM_DATA_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  1116. #define VHA_CR_SYS_RTM_DATA_RTM_DATA_SHIFT (0U)
  1117. #define VHA_CR_SYS_RTM_DATA_RTM_DATA_CLRMSK (00000000U)
  1118. /*
  1119. Register VHA_CR_SOCIF_WAKEUP_ENABLE
  1120. */
  1121. #define VHA_CR_SOCIF_WAKEUP_ENABLE (0x0400U)
  1122. #define VHA_CR_SOCIF_WAKEUP_ENABLE_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  1123. #define VHA_CR_SOCIF_WAKEUP_ENABLE_ALWAYS_SHIFT (0U)
  1124. #define VHA_CR_SOCIF_WAKEUP_ENABLE_ALWAYS_CLRMSK (0XFFFFFFFEU)
  1125. #define VHA_CR_SOCIF_WAKEUP_ENABLE_ALWAYS_EN (0X00000001U)
  1126. /*
  1127. Register VHA_CR_AXI_EXACCESS
  1128. */
  1129. #define VHA_CR_AXI_EXACCESS (0x0408U)
  1130. #define VHA_CR_AXI_EXACCESS_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  1131. #define VHA_CR_AXI_EXACCESS_SOCIF_ENABLE_SHIFT (0U)
  1132. #define VHA_CR_AXI_EXACCESS_SOCIF_ENABLE_CLRMSK (0XFFFFFFFEU)
  1133. #define VHA_CR_AXI_EXACCESS_SOCIF_ENABLE_EN (0X00000001U)
  1134. /*
  1135. Register VHA_CR_REGBANK_REQUEST_INVALID
  1136. */
  1137. #define VHA_CR_REGBANK_REQUEST_INVALID (0x0410U)
  1138. #define VHA_CR_REGBANK_REQUEST_INVALID_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  1139. #define VHA_CR_REGBANK_REQUEST_INVALID_FLAG_SHIFT (0U)
  1140. #define VHA_CR_REGBANK_REQUEST_INVALID_FLAG_CLRMSK (0XFFFFFFFEU)
  1141. #define VHA_CR_REGBANK_REQUEST_INVALID_FLAG_EN (0X00000001U)
  1142. #define VHA_CR_CORE_MAPPING_MASK (0x0000000FU)
  1143. /*
  1144. Core mapped to Workload Manager 0 */
  1145. #define VHA_CR_CORE_MAPPING_WM0 (0x00000000U)
  1146. /*
  1147. Core mapped to Workload Manager 1 */
  1148. #define VHA_CR_CORE_MAPPING_WM1 (0x00000001U)
  1149. /*
  1150. Core mapped to Workload Manager 2 */
  1151. #define VHA_CR_CORE_MAPPING_WM2 (0x00000002U)
  1152. /*
  1153. Core mapped to Workload Manager 3 */
  1154. #define VHA_CR_CORE_MAPPING_WM3 (0x00000003U)
  1155. /*
  1156. Core mapped to Workload Manager 4 */
  1157. #define VHA_CR_CORE_MAPPING_WM4 (0x00000004U)
  1158. /*
  1159. Core mapped to Workload Manager 5 */
  1160. #define VHA_CR_CORE_MAPPING_WM5 (0x00000005U)
  1161. /*
  1162. Core mapped to Workload Manager 6 */
  1163. #define VHA_CR_CORE_MAPPING_WM6 (0x00000006U)
  1164. /*
  1165. Core mapped to Workload Manager 7 */
  1166. #define VHA_CR_CORE_MAPPING_WM7 (0x00000007U)
  1167. /*
  1168. Dual lockstep with Core N-1 */
  1169. #define VHA_CR_CORE_MAPPING_LOCKSTEP (0x00000008U)
  1170. /*
  1171. Unallocated */
  1172. #define VHA_CR_CORE_MAPPING_UNALLOCATED (0x00000009U)
  1173. /*
  1174. Register VHA_CR_CORE_ASSIGNMENT
  1175. */
  1176. #define VHA_CR_CORE_ASSIGNMENT (0x0418U)
  1177. #define VHA_CR_CORE_ASSIGNMENT_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  1178. #define VHA_CR_CORE_ASSIGNMENT_CORE_7_WM_MAPPING_SHIFT (28U)
  1179. #define VHA_CR_CORE_ASSIGNMENT_CORE_7_WM_MAPPING_CLRMSK (0X0FFFFFFFU)
  1180. #define VHA_CR_CORE_ASSIGNMENT_CORE_7_WM_MAPPING_WM0 (00000000U)
  1181. #define VHA_CR_CORE_ASSIGNMENT_CORE_7_WM_MAPPING_WM1 (0X10000000U)
  1182. #define VHA_CR_CORE_ASSIGNMENT_CORE_7_WM_MAPPING_WM2 (0X20000000U)
  1183. #define VHA_CR_CORE_ASSIGNMENT_CORE_7_WM_MAPPING_WM3 (0X30000000U)
  1184. #define VHA_CR_CORE_ASSIGNMENT_CORE_7_WM_MAPPING_WM4 (0X40000000U)
  1185. #define VHA_CR_CORE_ASSIGNMENT_CORE_7_WM_MAPPING_WM5 (0X50000000U)
  1186. #define VHA_CR_CORE_ASSIGNMENT_CORE_7_WM_MAPPING_WM6 (0X60000000U)
  1187. #define VHA_CR_CORE_ASSIGNMENT_CORE_7_WM_MAPPING_WM7 (0X70000000U)
  1188. #define VHA_CR_CORE_ASSIGNMENT_CORE_7_WM_MAPPING_LOCKSTEP (0X80000000U)
  1189. #define VHA_CR_CORE_ASSIGNMENT_CORE_7_WM_MAPPING_UNALLOCATED (0X90000000U)
  1190. #define VHA_CR_CORE_ASSIGNMENT_CORE_6_WM_MAPPING_SHIFT (24U)
  1191. #define VHA_CR_CORE_ASSIGNMENT_CORE_6_WM_MAPPING_CLRMSK (0XF0FFFFFFU)
  1192. #define VHA_CR_CORE_ASSIGNMENT_CORE_6_WM_MAPPING_WM0 (00000000U)
  1193. #define VHA_CR_CORE_ASSIGNMENT_CORE_6_WM_MAPPING_WM1 (0X01000000U)
  1194. #define VHA_CR_CORE_ASSIGNMENT_CORE_6_WM_MAPPING_WM2 (0X02000000U)
  1195. #define VHA_CR_CORE_ASSIGNMENT_CORE_6_WM_MAPPING_WM3 (0X03000000U)
  1196. #define VHA_CR_CORE_ASSIGNMENT_CORE_6_WM_MAPPING_WM4 (0X04000000U)
  1197. #define VHA_CR_CORE_ASSIGNMENT_CORE_6_WM_MAPPING_WM5 (0X05000000U)
  1198. #define VHA_CR_CORE_ASSIGNMENT_CORE_6_WM_MAPPING_WM6 (0X06000000U)
  1199. #define VHA_CR_CORE_ASSIGNMENT_CORE_6_WM_MAPPING_WM7 (0X07000000U)
  1200. #define VHA_CR_CORE_ASSIGNMENT_CORE_6_WM_MAPPING_LOCKSTEP (0X08000000U)
  1201. #define VHA_CR_CORE_ASSIGNMENT_CORE_6_WM_MAPPING_UNALLOCATED (0X09000000U)
  1202. #define VHA_CR_CORE_ASSIGNMENT_CORE_5_WM_MAPPING_SHIFT (20U)
  1203. #define VHA_CR_CORE_ASSIGNMENT_CORE_5_WM_MAPPING_CLRMSK (0XFF0FFFFFU)
  1204. #define VHA_CR_CORE_ASSIGNMENT_CORE_5_WM_MAPPING_WM0 (00000000U)
  1205. #define VHA_CR_CORE_ASSIGNMENT_CORE_5_WM_MAPPING_WM1 (0X00100000U)
  1206. #define VHA_CR_CORE_ASSIGNMENT_CORE_5_WM_MAPPING_WM2 (0X00200000U)
  1207. #define VHA_CR_CORE_ASSIGNMENT_CORE_5_WM_MAPPING_WM3 (0X00300000U)
  1208. #define VHA_CR_CORE_ASSIGNMENT_CORE_5_WM_MAPPING_WM4 (0X00400000U)
  1209. #define VHA_CR_CORE_ASSIGNMENT_CORE_5_WM_MAPPING_WM5 (0X00500000U)
  1210. #define VHA_CR_CORE_ASSIGNMENT_CORE_5_WM_MAPPING_WM6 (0X00600000U)
  1211. #define VHA_CR_CORE_ASSIGNMENT_CORE_5_WM_MAPPING_WM7 (0X00700000U)
  1212. #define VHA_CR_CORE_ASSIGNMENT_CORE_5_WM_MAPPING_LOCKSTEP (0X00800000U)
  1213. #define VHA_CR_CORE_ASSIGNMENT_CORE_5_WM_MAPPING_UNALLOCATED (0X00900000U)
  1214. #define VHA_CR_CORE_ASSIGNMENT_CORE_4_WM_MAPPING_SHIFT (16U)
  1215. #define VHA_CR_CORE_ASSIGNMENT_CORE_4_WM_MAPPING_CLRMSK (0XFFF0FFFFU)
  1216. #define VHA_CR_CORE_ASSIGNMENT_CORE_4_WM_MAPPING_WM0 (00000000U)
  1217. #define VHA_CR_CORE_ASSIGNMENT_CORE_4_WM_MAPPING_WM1 (0X00010000U)
  1218. #define VHA_CR_CORE_ASSIGNMENT_CORE_4_WM_MAPPING_WM2 (0X00020000U)
  1219. #define VHA_CR_CORE_ASSIGNMENT_CORE_4_WM_MAPPING_WM3 (0X00030000U)
  1220. #define VHA_CR_CORE_ASSIGNMENT_CORE_4_WM_MAPPING_WM4 (0X00040000U)
  1221. #define VHA_CR_CORE_ASSIGNMENT_CORE_4_WM_MAPPING_WM5 (0X00050000U)
  1222. #define VHA_CR_CORE_ASSIGNMENT_CORE_4_WM_MAPPING_WM6 (0X00060000U)
  1223. #define VHA_CR_CORE_ASSIGNMENT_CORE_4_WM_MAPPING_WM7 (0X00070000U)
  1224. #define VHA_CR_CORE_ASSIGNMENT_CORE_4_WM_MAPPING_LOCKSTEP (0X00080000U)
  1225. #define VHA_CR_CORE_ASSIGNMENT_CORE_4_WM_MAPPING_UNALLOCATED (0X00090000U)
  1226. #define VHA_CR_CORE_ASSIGNMENT_CORE_3_WM_MAPPING_SHIFT (12U)
  1227. #define VHA_CR_CORE_ASSIGNMENT_CORE_3_WM_MAPPING_CLRMSK (0XFFFF0FFFU)
  1228. #define VHA_CR_CORE_ASSIGNMENT_CORE_3_WM_MAPPING_WM0 (00000000U)
  1229. #define VHA_CR_CORE_ASSIGNMENT_CORE_3_WM_MAPPING_WM1 (0X00001000U)
  1230. #define VHA_CR_CORE_ASSIGNMENT_CORE_3_WM_MAPPING_WM2 (0X00002000U)
  1231. #define VHA_CR_CORE_ASSIGNMENT_CORE_3_WM_MAPPING_WM3 (0X00003000U)
  1232. #define VHA_CR_CORE_ASSIGNMENT_CORE_3_WM_MAPPING_WM4 (0X00004000U)
  1233. #define VHA_CR_CORE_ASSIGNMENT_CORE_3_WM_MAPPING_WM5 (0X00005000U)
  1234. #define VHA_CR_CORE_ASSIGNMENT_CORE_3_WM_MAPPING_WM6 (0X00006000U)
  1235. #define VHA_CR_CORE_ASSIGNMENT_CORE_3_WM_MAPPING_WM7 (0X00007000U)
  1236. #define VHA_CR_CORE_ASSIGNMENT_CORE_3_WM_MAPPING_LOCKSTEP (0X00008000U)
  1237. #define VHA_CR_CORE_ASSIGNMENT_CORE_3_WM_MAPPING_UNALLOCATED (0X00009000U)
  1238. #define VHA_CR_CORE_ASSIGNMENT_CORE_2_WM_MAPPING_SHIFT (8U)
  1239. #define VHA_CR_CORE_ASSIGNMENT_CORE_2_WM_MAPPING_CLRMSK (0XFFFFF0FFU)
  1240. #define VHA_CR_CORE_ASSIGNMENT_CORE_2_WM_MAPPING_WM0 (00000000U)
  1241. #define VHA_CR_CORE_ASSIGNMENT_CORE_2_WM_MAPPING_WM1 (0X00000100U)
  1242. #define VHA_CR_CORE_ASSIGNMENT_CORE_2_WM_MAPPING_WM2 (0X00000200U)
  1243. #define VHA_CR_CORE_ASSIGNMENT_CORE_2_WM_MAPPING_WM3 (0X00000300U)
  1244. #define VHA_CR_CORE_ASSIGNMENT_CORE_2_WM_MAPPING_WM4 (0X00000400U)
  1245. #define VHA_CR_CORE_ASSIGNMENT_CORE_2_WM_MAPPING_WM5 (0X00000500U)
  1246. #define VHA_CR_CORE_ASSIGNMENT_CORE_2_WM_MAPPING_WM6 (0X00000600U)
  1247. #define VHA_CR_CORE_ASSIGNMENT_CORE_2_WM_MAPPING_WM7 (0X00000700U)
  1248. #define VHA_CR_CORE_ASSIGNMENT_CORE_2_WM_MAPPING_LOCKSTEP (0X00000800U)
  1249. #define VHA_CR_CORE_ASSIGNMENT_CORE_2_WM_MAPPING_UNALLOCATED (0X00000900U)
  1250. #define VHA_CR_CORE_ASSIGNMENT_CORE_1_WM_MAPPING_SHIFT (4U)
  1251. #define VHA_CR_CORE_ASSIGNMENT_CORE_1_WM_MAPPING_CLRMSK (0XFFFFFF0FU)
  1252. #define VHA_CR_CORE_ASSIGNMENT_CORE_1_WM_MAPPING_WM0 (00000000U)
  1253. #define VHA_CR_CORE_ASSIGNMENT_CORE_1_WM_MAPPING_WM1 (0X00000010U)
  1254. #define VHA_CR_CORE_ASSIGNMENT_CORE_1_WM_MAPPING_WM2 (0X00000020U)
  1255. #define VHA_CR_CORE_ASSIGNMENT_CORE_1_WM_MAPPING_WM3 (0X00000030U)
  1256. #define VHA_CR_CORE_ASSIGNMENT_CORE_1_WM_MAPPING_WM4 (0X00000040U)
  1257. #define VHA_CR_CORE_ASSIGNMENT_CORE_1_WM_MAPPING_WM5 (0X00000050U)
  1258. #define VHA_CR_CORE_ASSIGNMENT_CORE_1_WM_MAPPING_WM6 (0X00000060U)
  1259. #define VHA_CR_CORE_ASSIGNMENT_CORE_1_WM_MAPPING_WM7 (0X00000070U)
  1260. #define VHA_CR_CORE_ASSIGNMENT_CORE_1_WM_MAPPING_LOCKSTEP (0X00000080U)
  1261. #define VHA_CR_CORE_ASSIGNMENT_CORE_1_WM_MAPPING_UNALLOCATED (0X00000090U)
  1262. #define VHA_CR_CORE_ASSIGNMENT_CORE_0_WM_MAPPING_SHIFT (0U)
  1263. #define VHA_CR_CORE_ASSIGNMENT_CORE_0_WM_MAPPING_CLRMSK (0XFFFFFFF0U)
  1264. #define VHA_CR_CORE_ASSIGNMENT_CORE_0_WM_MAPPING_WM0 (00000000U)
  1265. #define VHA_CR_CORE_ASSIGNMENT_CORE_0_WM_MAPPING_WM1 (0X00000001U)
  1266. #define VHA_CR_CORE_ASSIGNMENT_CORE_0_WM_MAPPING_WM2 (0X00000002U)
  1267. #define VHA_CR_CORE_ASSIGNMENT_CORE_0_WM_MAPPING_WM3 (0X00000003U)
  1268. #define VHA_CR_CORE_ASSIGNMENT_CORE_0_WM_MAPPING_WM4 (0X00000004U)
  1269. #define VHA_CR_CORE_ASSIGNMENT_CORE_0_WM_MAPPING_WM5 (0X00000005U)
  1270. #define VHA_CR_CORE_ASSIGNMENT_CORE_0_WM_MAPPING_WM6 (0X00000006U)
  1271. #define VHA_CR_CORE_ASSIGNMENT_CORE_0_WM_MAPPING_WM7 (0X00000007U)
  1272. #define VHA_CR_CORE_ASSIGNMENT_CORE_0_WM_MAPPING_LOCKSTEP (0X00000008U)
  1273. #define VHA_CR_CORE_ASSIGNMENT_CORE_0_WM_MAPPING_UNALLOCATED (0X00000009U)
  1274. /*
  1275. Register VHA_CR_SOCM_BUF_ASSIGNMENT
  1276. */
  1277. #define VHA_CR_SOCM_BUF_ASSIGNMENT (0x0420U)
  1278. #define VHA_CR_SOCM_BUF_ASSIGNMENT_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  1279. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_7_WM_MAPPING_SHIFT (28U)
  1280. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_7_WM_MAPPING_CLRMSK (0X0FFFFFFFU)
  1281. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_7_WM_MAPPING_WM0 (00000000U)
  1282. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_7_WM_MAPPING_WM1 (0X10000000U)
  1283. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_7_WM_MAPPING_WM2 (0X20000000U)
  1284. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_7_WM_MAPPING_WM3 (0X30000000U)
  1285. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_7_WM_MAPPING_WM4 (0X40000000U)
  1286. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_7_WM_MAPPING_WM5 (0X50000000U)
  1287. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_7_WM_MAPPING_WM6 (0X60000000U)
  1288. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_7_WM_MAPPING_WM7 (0X70000000U)
  1289. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_7_WM_MAPPING_LOCKSTEP (0X80000000U)
  1290. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_7_WM_MAPPING_UNALLOCATED (0X90000000U)
  1291. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_6_WM_MAPPING_SHIFT (24U)
  1292. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_6_WM_MAPPING_CLRMSK (0XF0FFFFFFU)
  1293. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_6_WM_MAPPING_WM0 (00000000U)
  1294. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_6_WM_MAPPING_WM1 (0X01000000U)
  1295. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_6_WM_MAPPING_WM2 (0X02000000U)
  1296. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_6_WM_MAPPING_WM3 (0X03000000U)
  1297. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_6_WM_MAPPING_WM4 (0X04000000U)
  1298. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_6_WM_MAPPING_WM5 (0X05000000U)
  1299. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_6_WM_MAPPING_WM6 (0X06000000U)
  1300. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_6_WM_MAPPING_WM7 (0X07000000U)
  1301. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_6_WM_MAPPING_LOCKSTEP (0X08000000U)
  1302. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_6_WM_MAPPING_UNALLOCATED (0X09000000U)
  1303. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_5_WM_MAPPING_SHIFT (20U)
  1304. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_5_WM_MAPPING_CLRMSK (0XFF0FFFFFU)
  1305. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_5_WM_MAPPING_WM0 (00000000U)
  1306. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_5_WM_MAPPING_WM1 (0X00100000U)
  1307. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_5_WM_MAPPING_WM2 (0X00200000U)
  1308. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_5_WM_MAPPING_WM3 (0X00300000U)
  1309. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_5_WM_MAPPING_WM4 (0X00400000U)
  1310. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_5_WM_MAPPING_WM5 (0X00500000U)
  1311. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_5_WM_MAPPING_WM6 (0X00600000U)
  1312. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_5_WM_MAPPING_WM7 (0X00700000U)
  1313. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_5_WM_MAPPING_LOCKSTEP (0X00800000U)
  1314. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_5_WM_MAPPING_UNALLOCATED (0X00900000U)
  1315. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_4_WM_MAPPING_SHIFT (16U)
  1316. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_4_WM_MAPPING_CLRMSK (0XFFF0FFFFU)
  1317. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_4_WM_MAPPING_WM0 (00000000U)
  1318. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_4_WM_MAPPING_WM1 (0X00010000U)
  1319. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_4_WM_MAPPING_WM2 (0X00020000U)
  1320. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_4_WM_MAPPING_WM3 (0X00030000U)
  1321. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_4_WM_MAPPING_WM4 (0X00040000U)
  1322. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_4_WM_MAPPING_WM5 (0X00050000U)
  1323. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_4_WM_MAPPING_WM6 (0X00060000U)
  1324. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_4_WM_MAPPING_WM7 (0X00070000U)
  1325. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_4_WM_MAPPING_LOCKSTEP (0X00080000U)
  1326. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_4_WM_MAPPING_UNALLOCATED (0X00090000U)
  1327. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_3_WM_MAPPING_SHIFT (12U)
  1328. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_3_WM_MAPPING_CLRMSK (0XFFFF0FFFU)
  1329. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_3_WM_MAPPING_WM0 (00000000U)
  1330. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_3_WM_MAPPING_WM1 (0X00001000U)
  1331. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_3_WM_MAPPING_WM2 (0X00002000U)
  1332. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_3_WM_MAPPING_WM3 (0X00003000U)
  1333. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_3_WM_MAPPING_WM4 (0X00004000U)
  1334. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_3_WM_MAPPING_WM5 (0X00005000U)
  1335. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_3_WM_MAPPING_WM6 (0X00006000U)
  1336. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_3_WM_MAPPING_WM7 (0X00007000U)
  1337. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_3_WM_MAPPING_LOCKSTEP (0X00008000U)
  1338. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_3_WM_MAPPING_UNALLOCATED (0X00009000U)
  1339. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_2_WM_MAPPING_SHIFT (8U)
  1340. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_2_WM_MAPPING_CLRMSK (0XFFFFF0FFU)
  1341. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_2_WM_MAPPING_WM0 (00000000U)
  1342. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_2_WM_MAPPING_WM1 (0X00000100U)
  1343. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_2_WM_MAPPING_WM2 (0X00000200U)
  1344. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_2_WM_MAPPING_WM3 (0X00000300U)
  1345. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_2_WM_MAPPING_WM4 (0X00000400U)
  1346. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_2_WM_MAPPING_WM5 (0X00000500U)
  1347. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_2_WM_MAPPING_WM6 (0X00000600U)
  1348. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_2_WM_MAPPING_WM7 (0X00000700U)
  1349. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_2_WM_MAPPING_LOCKSTEP (0X00000800U)
  1350. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_2_WM_MAPPING_UNALLOCATED (0X00000900U)
  1351. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_1_WM_MAPPING_SHIFT (4U)
  1352. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_1_WM_MAPPING_CLRMSK (0XFFFFFF0FU)
  1353. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_1_WM_MAPPING_WM0 (00000000U)
  1354. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_1_WM_MAPPING_WM1 (0X00000010U)
  1355. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_1_WM_MAPPING_WM2 (0X00000020U)
  1356. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_1_WM_MAPPING_WM3 (0X00000030U)
  1357. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_1_WM_MAPPING_WM4 (0X00000040U)
  1358. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_1_WM_MAPPING_WM5 (0X00000050U)
  1359. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_1_WM_MAPPING_WM6 (0X00000060U)
  1360. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_1_WM_MAPPING_WM7 (0X00000070U)
  1361. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_1_WM_MAPPING_LOCKSTEP (0X00000080U)
  1362. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_1_WM_MAPPING_UNALLOCATED (0X00000090U)
  1363. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_0_WM_MAPPING_SHIFT (0U)
  1364. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_0_WM_MAPPING_CLRMSK (0XFFFFFFF0U)
  1365. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_0_WM_MAPPING_WM0 (00000000U)
  1366. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_0_WM_MAPPING_WM1 (0X00000001U)
  1367. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_0_WM_MAPPING_WM2 (0X00000002U)
  1368. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_0_WM_MAPPING_WM3 (0X00000003U)
  1369. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_0_WM_MAPPING_WM4 (0X00000004U)
  1370. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_0_WM_MAPPING_WM5 (0X00000005U)
  1371. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_0_WM_MAPPING_WM6 (0X00000006U)
  1372. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_0_WM_MAPPING_WM7 (0X00000007U)
  1373. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_0_WM_MAPPING_LOCKSTEP (0X00000008U)
  1374. #define VHA_CR_SOCM_BUF_ASSIGNMENT_SOCM_BUF_0_WM_MAPPING_UNALLOCATED (0X00000009U)
  1375. /*
  1376. Host gets assigned the same priority level as the rest of internal system bus requestors */
  1377. #define VHA_CR_SOCIF_ARBITER_CONFIG_ENUM_SOCIF_PRIORITIES_EQUAL (0x00000000U)
  1378. /*
  1379. Host gets assigned the higher priority level than the rest of internal system bus requestors */
  1380. #define VHA_CR_SOCIF_ARBITER_CONFIG_ENUM_SOCIF_PRIORITIES_HIGHEST (0x00000001U)
  1381. /*
  1382. Register VHA_CR_SOCIF_ARBITER_CONFIG
  1383. */
  1384. #define VHA_CR_SOCIF_ARBITER_CONFIG (0x0428U)
  1385. #define VHA_CR_SOCIF_ARBITER_CONFIG_MASKFULL (IMG_UINT64_C(0x000000000000001F))
  1386. #define VHA_CR_SOCIF_ARBITER_CONFIG_SOCIF_HOST_EXTRA_ALLOC_SHIFT (1U)
  1387. #define VHA_CR_SOCIF_ARBITER_CONFIG_SOCIF_HOST_EXTRA_ALLOC_CLRMSK (0XFFFFFFE1U)
  1388. #define VHA_CR_SOCIF_ARBITER_CONFIG_SOCIF_HOST_PRIORITY_SHIFT (0U)
  1389. #define VHA_CR_SOCIF_ARBITER_CONFIG_SOCIF_HOST_PRIORITY_CLRMSK (0XFFFFFFFEU)
  1390. #define VHA_CR_SOCIF_ARBITER_CONFIG_SOCIF_HOST_PRIORITY_EQUAL (00000000U)
  1391. #define VHA_CR_SOCIF_ARBITER_CONFIG_SOCIF_HOST_PRIORITY_HIGHEST (0X00000001U)
  1392. #define VHA_CR_INTERCONNECT_EVENT_TYPE_LOGIC_ERROR_SHIFT (30U)
  1393. #define VHA_CR_INTERCONNECT_EVENT_TYPE_LOGIC_ERROR_CLRMSK (0XBFFFFFFFU)
  1394. #define VHA_CR_INTERCONNECT_EVENT_TYPE_LOGIC_ERROR_EN (0X40000000U)
  1395. #define VHA_CR_INTERCONNECT_EVENT_TYPE_SOCIF_READ_MISMATCH_SHIFT (8U)
  1396. #define VHA_CR_INTERCONNECT_EVENT_TYPE_SOCIF_READ_MISMATCH_CLRMSK (0XFFFFFEFFU)
  1397. #define VHA_CR_INTERCONNECT_EVENT_TYPE_SOCIF_READ_MISMATCH_EN (0X00000100U)
  1398. #define VHA_CR_INTERCONNECT_EVENT_TYPE_SOCIF_READ_UNRESPONSIVE_SHIFT (4U)
  1399. #define VHA_CR_INTERCONNECT_EVENT_TYPE_SOCIF_READ_UNRESPONSIVE_CLRMSK (0XFFFFFFEFU)
  1400. #define VHA_CR_INTERCONNECT_EVENT_TYPE_SOCIF_READ_UNRESPONSIVE_EN (0X00000010U)
  1401. #define VHA_CR_INTERCONNECT_EVENT_TYPE_LOCKSTEP_ERROR_SHIFT (0U)
  1402. #define VHA_CR_INTERCONNECT_EVENT_TYPE_LOCKSTEP_ERROR_CLRMSK (0XFFFFFFFEU)
  1403. #define VHA_CR_INTERCONNECT_EVENT_TYPE_LOCKSTEP_ERROR_EN (0X00000001U)
  1404. #define VHA_CR_INTERCONNECT_EVENT_STATUS_TYPE_PARITY_SHIFT (31U)
  1405. #define VHA_CR_INTERCONNECT_EVENT_STATUS_TYPE_PARITY_CLRMSK (0X7FFFFFFFU)
  1406. #define VHA_CR_INTERCONNECT_EVENT_STATUS_TYPE_PARITY_EN (0X80000000U)
  1407. #define VHA_CR_INTERCONNECT_EVENT_STATUS_TYPE_LOGIC_ERROR_SHIFT (30U)
  1408. #define VHA_CR_INTERCONNECT_EVENT_STATUS_TYPE_LOGIC_ERROR_CLRMSK (0XBFFFFFFFU)
  1409. #define VHA_CR_INTERCONNECT_EVENT_STATUS_TYPE_LOGIC_ERROR_EN (0X40000000U)
  1410. #define VHA_CR_INTERCONNECT_EVENT_STATUS_TYPE_SOCIF_READ_MISMATCH_SHIFT (8U)
  1411. #define VHA_CR_INTERCONNECT_EVENT_STATUS_TYPE_SOCIF_READ_MISMATCH_CLRMSK (0XFFFFFEFFU)
  1412. #define VHA_CR_INTERCONNECT_EVENT_STATUS_TYPE_SOCIF_READ_MISMATCH_EN (0X00000100U)
  1413. #define VHA_CR_INTERCONNECT_EVENT_STATUS_TYPE_SOCIF_READ_UNRESPONSIVE_SHIFT (4U)
  1414. #define VHA_CR_INTERCONNECT_EVENT_STATUS_TYPE_SOCIF_READ_UNRESPONSIVE_CLRMSK (0XFFFFFFEFU)
  1415. #define VHA_CR_INTERCONNECT_EVENT_STATUS_TYPE_SOCIF_READ_UNRESPONSIVE_EN (0X00000010U)
  1416. #define VHA_CR_INTERCONNECT_EVENT_STATUS_TYPE_LOCKSTEP_ERROR_SHIFT (0U)
  1417. #define VHA_CR_INTERCONNECT_EVENT_STATUS_TYPE_LOCKSTEP_ERROR_CLRMSK (0XFFFFFFFEU)
  1418. #define VHA_CR_INTERCONNECT_EVENT_STATUS_TYPE_LOCKSTEP_ERROR_EN (0X00000001U)
  1419. /*
  1420. Register VHA_CR_INTERCONNECT_EVENT_HOST_ENABLE
  1421. */
  1422. #define VHA_CR_INTERCONNECT_EVENT_HOST_ENABLE (0x0500U)
  1423. #define VHA_CR_INTERCONNECT_EVENT_HOST_ENABLE_MASKFULL (IMG_UINT64_C(0x0000000040000111))
  1424. #define VHA_CR_INTERCONNECT_EVENT_HOST_ENABLE_LOGIC_ERROR_SHIFT (30U)
  1425. #define VHA_CR_INTERCONNECT_EVENT_HOST_ENABLE_LOGIC_ERROR_CLRMSK (0XBFFFFFFFU)
  1426. #define VHA_CR_INTERCONNECT_EVENT_HOST_ENABLE_LOGIC_ERROR_EN (0X40000000U)
  1427. #define VHA_CR_INTERCONNECT_EVENT_HOST_ENABLE_SOCIF_READ_MISMATCH_SHIFT (8U)
  1428. #define VHA_CR_INTERCONNECT_EVENT_HOST_ENABLE_SOCIF_READ_MISMATCH_CLRMSK (0XFFFFFEFFU)
  1429. #define VHA_CR_INTERCONNECT_EVENT_HOST_ENABLE_SOCIF_READ_MISMATCH_EN (0X00000100U)
  1430. #define VHA_CR_INTERCONNECT_EVENT_HOST_ENABLE_SOCIF_READ_UNRESPONSIVE_SHIFT (4U)
  1431. #define VHA_CR_INTERCONNECT_EVENT_HOST_ENABLE_SOCIF_READ_UNRESPONSIVE_CLRMSK (0XFFFFFFEFU)
  1432. #define VHA_CR_INTERCONNECT_EVENT_HOST_ENABLE_SOCIF_READ_UNRESPONSIVE_EN (0X00000010U)
  1433. #define VHA_CR_INTERCONNECT_EVENT_HOST_ENABLE_LOCKSTEP_ERROR_SHIFT (0U)
  1434. #define VHA_CR_INTERCONNECT_EVENT_HOST_ENABLE_LOCKSTEP_ERROR_CLRMSK (0XFFFFFFFEU)
  1435. #define VHA_CR_INTERCONNECT_EVENT_HOST_ENABLE_LOCKSTEP_ERROR_EN (0X00000001U)
  1436. /*
  1437. Register VHA_CR_INTERCONNECT_EVENT_HOST_STATUS
  1438. */
  1439. #define VHA_CR_INTERCONNECT_EVENT_HOST_STATUS (0x0508U)
  1440. #define VHA_CR_INTERCONNECT_EVENT_HOST_STATUS_MASKFULL (IMG_UINT64_C(0x00000000C0000111))
  1441. #define VHA_CR_INTERCONNECT_EVENT_HOST_STATUS_PARITY_SHIFT (31U)
  1442. #define VHA_CR_INTERCONNECT_EVENT_HOST_STATUS_PARITY_CLRMSK (0X7FFFFFFFU)
  1443. #define VHA_CR_INTERCONNECT_EVENT_HOST_STATUS_PARITY_EN (0X80000000U)
  1444. #define VHA_CR_INTERCONNECT_EVENT_HOST_STATUS_LOGIC_ERROR_SHIFT (30U)
  1445. #define VHA_CR_INTERCONNECT_EVENT_HOST_STATUS_LOGIC_ERROR_CLRMSK (0XBFFFFFFFU)
  1446. #define VHA_CR_INTERCONNECT_EVENT_HOST_STATUS_LOGIC_ERROR_EN (0X40000000U)
  1447. #define VHA_CR_INTERCONNECT_EVENT_HOST_STATUS_SOCIF_READ_MISMATCH_SHIFT (8U)
  1448. #define VHA_CR_INTERCONNECT_EVENT_HOST_STATUS_SOCIF_READ_MISMATCH_CLRMSK (0XFFFFFEFFU)
  1449. #define VHA_CR_INTERCONNECT_EVENT_HOST_STATUS_SOCIF_READ_MISMATCH_EN (0X00000100U)
  1450. #define VHA_CR_INTERCONNECT_EVENT_HOST_STATUS_SOCIF_READ_UNRESPONSIVE_SHIFT (4U)
  1451. #define VHA_CR_INTERCONNECT_EVENT_HOST_STATUS_SOCIF_READ_UNRESPONSIVE_CLRMSK (0XFFFFFFEFU)
  1452. #define VHA_CR_INTERCONNECT_EVENT_HOST_STATUS_SOCIF_READ_UNRESPONSIVE_EN (0X00000010U)
  1453. #define VHA_CR_INTERCONNECT_EVENT_HOST_STATUS_LOCKSTEP_ERROR_SHIFT (0U)
  1454. #define VHA_CR_INTERCONNECT_EVENT_HOST_STATUS_LOCKSTEP_ERROR_CLRMSK (0XFFFFFFFEU)
  1455. #define VHA_CR_INTERCONNECT_EVENT_HOST_STATUS_LOCKSTEP_ERROR_EN (0X00000001U)
  1456. /*
  1457. Register VHA_CR_INTERCONNECT_EVENT_HOST_STATUS_DISABLE
  1458. */
  1459. #define VHA_CR_INTERCONNECT_EVENT_HOST_STATUS_DISABLE (0x0530U)
  1460. #define VHA_CR_INTERCONNECT_EVENT_HOST_STATUS_DISABLE_MASKFULL (IMG_UINT64_C(0x0000000040000111))
  1461. #define VHA_CR_INTERCONNECT_EVENT_HOST_STATUS_DISABLE_LOGIC_ERROR_SHIFT (30U)
  1462. #define VHA_CR_INTERCONNECT_EVENT_HOST_STATUS_DISABLE_LOGIC_ERROR_CLRMSK (0XBFFFFFFFU)
  1463. #define VHA_CR_INTERCONNECT_EVENT_HOST_STATUS_DISABLE_LOGIC_ERROR_EN (0X40000000U)
  1464. #define VHA_CR_INTERCONNECT_EVENT_HOST_STATUS_DISABLE_SOCIF_READ_MISMATCH_SHIFT (8U)
  1465. #define VHA_CR_INTERCONNECT_EVENT_HOST_STATUS_DISABLE_SOCIF_READ_MISMATCH_CLRMSK (0XFFFFFEFFU)
  1466. #define VHA_CR_INTERCONNECT_EVENT_HOST_STATUS_DISABLE_SOCIF_READ_MISMATCH_EN (0X00000100U)
  1467. #define VHA_CR_INTERCONNECT_EVENT_HOST_STATUS_DISABLE_SOCIF_READ_UNRESPONSIVE_SHIFT (4U)
  1468. #define VHA_CR_INTERCONNECT_EVENT_HOST_STATUS_DISABLE_SOCIF_READ_UNRESPONSIVE_CLRMSK (0XFFFFFFEFU)
  1469. #define VHA_CR_INTERCONNECT_EVENT_HOST_STATUS_DISABLE_SOCIF_READ_UNRESPONSIVE_EN (0X00000010U)
  1470. #define VHA_CR_INTERCONNECT_EVENT_HOST_STATUS_DISABLE_LOCKSTEP_ERROR_SHIFT (0U)
  1471. #define VHA_CR_INTERCONNECT_EVENT_HOST_STATUS_DISABLE_LOCKSTEP_ERROR_CLRMSK (0XFFFFFFFEU)
  1472. #define VHA_CR_INTERCONNECT_EVENT_HOST_STATUS_DISABLE_LOCKSTEP_ERROR_EN (0X00000001U)
  1473. /*
  1474. Register VHA_CR_INTERCONNECT_EVENT_HOST_CLEAR
  1475. */
  1476. #define VHA_CR_INTERCONNECT_EVENT_HOST_CLEAR (0x0510U)
  1477. #define VHA_CR_INTERCONNECT_EVENT_HOST_CLEAR_MASKFULL (IMG_UINT64_C(0x0000000040000111))
  1478. #define VHA_CR_INTERCONNECT_EVENT_HOST_CLEAR_LOGIC_ERROR_SHIFT (30U)
  1479. #define VHA_CR_INTERCONNECT_EVENT_HOST_CLEAR_LOGIC_ERROR_CLRMSK (0XBFFFFFFFU)
  1480. #define VHA_CR_INTERCONNECT_EVENT_HOST_CLEAR_LOGIC_ERROR_EN (0X40000000U)
  1481. #define VHA_CR_INTERCONNECT_EVENT_HOST_CLEAR_SOCIF_READ_MISMATCH_SHIFT (8U)
  1482. #define VHA_CR_INTERCONNECT_EVENT_HOST_CLEAR_SOCIF_READ_MISMATCH_CLRMSK (0XFFFFFEFFU)
  1483. #define VHA_CR_INTERCONNECT_EVENT_HOST_CLEAR_SOCIF_READ_MISMATCH_EN (0X00000100U)
  1484. #define VHA_CR_INTERCONNECT_EVENT_HOST_CLEAR_SOCIF_READ_UNRESPONSIVE_SHIFT (4U)
  1485. #define VHA_CR_INTERCONNECT_EVENT_HOST_CLEAR_SOCIF_READ_UNRESPONSIVE_CLRMSK (0XFFFFFFEFU)
  1486. #define VHA_CR_INTERCONNECT_EVENT_HOST_CLEAR_SOCIF_READ_UNRESPONSIVE_EN (0X00000010U)
  1487. #define VHA_CR_INTERCONNECT_EVENT_HOST_CLEAR_LOCKSTEP_ERROR_SHIFT (0U)
  1488. #define VHA_CR_INTERCONNECT_EVENT_HOST_CLEAR_LOCKSTEP_ERROR_CLRMSK (0XFFFFFFFEU)
  1489. #define VHA_CR_INTERCONNECT_EVENT_HOST_CLEAR_LOCKSTEP_ERROR_EN (0X00000001U)
  1490. /*
  1491. Register VHA_CR_INTERCONNECT_EVENT_WM_ENABLE
  1492. */
  1493. #define VHA_CR_INTERCONNECT_EVENT_WM_ENABLE (0x0518U)
  1494. #define VHA_CR_INTERCONNECT_EVENT_WM_ENABLE_MASKFULL (IMG_UINT64_C(0x0000000040000111))
  1495. #define VHA_CR_INTERCONNECT_EVENT_WM_ENABLE_LOGIC_ERROR_SHIFT (30U)
  1496. #define VHA_CR_INTERCONNECT_EVENT_WM_ENABLE_LOGIC_ERROR_CLRMSK (0XBFFFFFFFU)
  1497. #define VHA_CR_INTERCONNECT_EVENT_WM_ENABLE_LOGIC_ERROR_EN (0X40000000U)
  1498. #define VHA_CR_INTERCONNECT_EVENT_WM_ENABLE_SOCIF_READ_MISMATCH_SHIFT (8U)
  1499. #define VHA_CR_INTERCONNECT_EVENT_WM_ENABLE_SOCIF_READ_MISMATCH_CLRMSK (0XFFFFFEFFU)
  1500. #define VHA_CR_INTERCONNECT_EVENT_WM_ENABLE_SOCIF_READ_MISMATCH_EN (0X00000100U)
  1501. #define VHA_CR_INTERCONNECT_EVENT_WM_ENABLE_SOCIF_READ_UNRESPONSIVE_SHIFT (4U)
  1502. #define VHA_CR_INTERCONNECT_EVENT_WM_ENABLE_SOCIF_READ_UNRESPONSIVE_CLRMSK (0XFFFFFFEFU)
  1503. #define VHA_CR_INTERCONNECT_EVENT_WM_ENABLE_SOCIF_READ_UNRESPONSIVE_EN (0X00000010U)
  1504. #define VHA_CR_INTERCONNECT_EVENT_WM_ENABLE_LOCKSTEP_ERROR_SHIFT (0U)
  1505. #define VHA_CR_INTERCONNECT_EVENT_WM_ENABLE_LOCKSTEP_ERROR_CLRMSK (0XFFFFFFFEU)
  1506. #define VHA_CR_INTERCONNECT_EVENT_WM_ENABLE_LOCKSTEP_ERROR_EN (0X00000001U)
  1507. /*
  1508. Register VHA_CR_INTERCONNECT_EVENT_WM_STATUS
  1509. */
  1510. #define VHA_CR_INTERCONNECT_EVENT_WM_STATUS (0x0520U)
  1511. #define VHA_CR_INTERCONNECT_EVENT_WM_STATUS_MASKFULL (IMG_UINT64_C(0x00000000C0000111))
  1512. #define VHA_CR_INTERCONNECT_EVENT_WM_STATUS_PARITY_SHIFT (31U)
  1513. #define VHA_CR_INTERCONNECT_EVENT_WM_STATUS_PARITY_CLRMSK (0X7FFFFFFFU)
  1514. #define VHA_CR_INTERCONNECT_EVENT_WM_STATUS_PARITY_EN (0X80000000U)
  1515. #define VHA_CR_INTERCONNECT_EVENT_WM_STATUS_LOGIC_ERROR_SHIFT (30U)
  1516. #define VHA_CR_INTERCONNECT_EVENT_WM_STATUS_LOGIC_ERROR_CLRMSK (0XBFFFFFFFU)
  1517. #define VHA_CR_INTERCONNECT_EVENT_WM_STATUS_LOGIC_ERROR_EN (0X40000000U)
  1518. #define VHA_CR_INTERCONNECT_EVENT_WM_STATUS_SOCIF_READ_MISMATCH_SHIFT (8U)
  1519. #define VHA_CR_INTERCONNECT_EVENT_WM_STATUS_SOCIF_READ_MISMATCH_CLRMSK (0XFFFFFEFFU)
  1520. #define VHA_CR_INTERCONNECT_EVENT_WM_STATUS_SOCIF_READ_MISMATCH_EN (0X00000100U)
  1521. #define VHA_CR_INTERCONNECT_EVENT_WM_STATUS_SOCIF_READ_UNRESPONSIVE_SHIFT (4U)
  1522. #define VHA_CR_INTERCONNECT_EVENT_WM_STATUS_SOCIF_READ_UNRESPONSIVE_CLRMSK (0XFFFFFFEFU)
  1523. #define VHA_CR_INTERCONNECT_EVENT_WM_STATUS_SOCIF_READ_UNRESPONSIVE_EN (0X00000010U)
  1524. #define VHA_CR_INTERCONNECT_EVENT_WM_STATUS_LOCKSTEP_ERROR_SHIFT (0U)
  1525. #define VHA_CR_INTERCONNECT_EVENT_WM_STATUS_LOCKSTEP_ERROR_CLRMSK (0XFFFFFFFEU)
  1526. #define VHA_CR_INTERCONNECT_EVENT_WM_STATUS_LOCKSTEP_ERROR_EN (0X00000001U)
  1527. /*
  1528. Register VHA_CR_INTERCONNECT_EVENT_WM_STATUS_DISABLE
  1529. */
  1530. #define VHA_CR_INTERCONNECT_EVENT_WM_STATUS_DISABLE (0x0538U)
  1531. #define VHA_CR_INTERCONNECT_EVENT_WM_STATUS_DISABLE_MASKFULL (IMG_UINT64_C(0x0000000040000111))
  1532. #define VHA_CR_INTERCONNECT_EVENT_WM_STATUS_DISABLE_LOGIC_ERROR_SHIFT (30U)
  1533. #define VHA_CR_INTERCONNECT_EVENT_WM_STATUS_DISABLE_LOGIC_ERROR_CLRMSK (0XBFFFFFFFU)
  1534. #define VHA_CR_INTERCONNECT_EVENT_WM_STATUS_DISABLE_LOGIC_ERROR_EN (0X40000000U)
  1535. #define VHA_CR_INTERCONNECT_EVENT_WM_STATUS_DISABLE_SOCIF_READ_MISMATCH_SHIFT (8U)
  1536. #define VHA_CR_INTERCONNECT_EVENT_WM_STATUS_DISABLE_SOCIF_READ_MISMATCH_CLRMSK (0XFFFFFEFFU)
  1537. #define VHA_CR_INTERCONNECT_EVENT_WM_STATUS_DISABLE_SOCIF_READ_MISMATCH_EN (0X00000100U)
  1538. #define VHA_CR_INTERCONNECT_EVENT_WM_STATUS_DISABLE_SOCIF_READ_UNRESPONSIVE_SHIFT (4U)
  1539. #define VHA_CR_INTERCONNECT_EVENT_WM_STATUS_DISABLE_SOCIF_READ_UNRESPONSIVE_CLRMSK (0XFFFFFFEFU)
  1540. #define VHA_CR_INTERCONNECT_EVENT_WM_STATUS_DISABLE_SOCIF_READ_UNRESPONSIVE_EN (0X00000010U)
  1541. #define VHA_CR_INTERCONNECT_EVENT_WM_STATUS_DISABLE_LOCKSTEP_ERROR_SHIFT (0U)
  1542. #define VHA_CR_INTERCONNECT_EVENT_WM_STATUS_DISABLE_LOCKSTEP_ERROR_CLRMSK (0XFFFFFFFEU)
  1543. #define VHA_CR_INTERCONNECT_EVENT_WM_STATUS_DISABLE_LOCKSTEP_ERROR_EN (0X00000001U)
  1544. /*
  1545. Register VHA_CR_INTERCONNECT_EVENT_WM_CLEAR
  1546. */
  1547. #define VHA_CR_INTERCONNECT_EVENT_WM_CLEAR (0x0528U)
  1548. #define VHA_CR_INTERCONNECT_EVENT_WM_CLEAR_MASKFULL (IMG_UINT64_C(0x0000000040000111))
  1549. #define VHA_CR_INTERCONNECT_EVENT_WM_CLEAR_LOGIC_ERROR_SHIFT (30U)
  1550. #define VHA_CR_INTERCONNECT_EVENT_WM_CLEAR_LOGIC_ERROR_CLRMSK (0XBFFFFFFFU)
  1551. #define VHA_CR_INTERCONNECT_EVENT_WM_CLEAR_LOGIC_ERROR_EN (0X40000000U)
  1552. #define VHA_CR_INTERCONNECT_EVENT_WM_CLEAR_SOCIF_READ_MISMATCH_SHIFT (8U)
  1553. #define VHA_CR_INTERCONNECT_EVENT_WM_CLEAR_SOCIF_READ_MISMATCH_CLRMSK (0XFFFFFEFFU)
  1554. #define VHA_CR_INTERCONNECT_EVENT_WM_CLEAR_SOCIF_READ_MISMATCH_EN (0X00000100U)
  1555. #define VHA_CR_INTERCONNECT_EVENT_WM_CLEAR_SOCIF_READ_UNRESPONSIVE_SHIFT (4U)
  1556. #define VHA_CR_INTERCONNECT_EVENT_WM_CLEAR_SOCIF_READ_UNRESPONSIVE_CLRMSK (0XFFFFFFEFU)
  1557. #define VHA_CR_INTERCONNECT_EVENT_WM_CLEAR_SOCIF_READ_UNRESPONSIVE_EN (0X00000010U)
  1558. #define VHA_CR_INTERCONNECT_EVENT_WM_CLEAR_LOCKSTEP_ERROR_SHIFT (0U)
  1559. #define VHA_CR_INTERCONNECT_EVENT_WM_CLEAR_LOCKSTEP_ERROR_CLRMSK (0XFFFFFFFEU)
  1560. #define VHA_CR_INTERCONNECT_EVENT_WM_CLEAR_LOCKSTEP_ERROR_EN (0X00000001U)
  1561. /*
  1562. Register VHA_CR_INTERCONNECT_EVENT_INJECT
  1563. */
  1564. #define VHA_CR_INTERCONNECT_EVENT_INJECT (0x0540U)
  1565. #define VHA_CR_INTERCONNECT_EVENT_INJECT_MASKFULL (IMG_UINT64_C(0x0000000040000111))
  1566. #define VHA_CR_INTERCONNECT_EVENT_INJECT_LOGIC_ERROR_SHIFT (30U)
  1567. #define VHA_CR_INTERCONNECT_EVENT_INJECT_LOGIC_ERROR_CLRMSK (0XBFFFFFFFU)
  1568. #define VHA_CR_INTERCONNECT_EVENT_INJECT_LOGIC_ERROR_EN (0X40000000U)
  1569. #define VHA_CR_INTERCONNECT_EVENT_INJECT_SOCIF_READ_MISMATCH_SHIFT (8U)
  1570. #define VHA_CR_INTERCONNECT_EVENT_INJECT_SOCIF_READ_MISMATCH_CLRMSK (0XFFFFFEFFU)
  1571. #define VHA_CR_INTERCONNECT_EVENT_INJECT_SOCIF_READ_MISMATCH_EN (0X00000100U)
  1572. #define VHA_CR_INTERCONNECT_EVENT_INJECT_SOCIF_READ_UNRESPONSIVE_SHIFT (4U)
  1573. #define VHA_CR_INTERCONNECT_EVENT_INJECT_SOCIF_READ_UNRESPONSIVE_CLRMSK (0XFFFFFFEFU)
  1574. #define VHA_CR_INTERCONNECT_EVENT_INJECT_SOCIF_READ_UNRESPONSIVE_EN (0X00000010U)
  1575. #define VHA_CR_INTERCONNECT_EVENT_INJECT_LOCKSTEP_ERROR_SHIFT (0U)
  1576. #define VHA_CR_INTERCONNECT_EVENT_INJECT_LOCKSTEP_ERROR_CLRMSK (0XFFFFFFFEU)
  1577. #define VHA_CR_INTERCONNECT_EVENT_INJECT_LOCKSTEP_ERROR_EN (0X00000001U)
  1578. /*
  1579. Register VHA_CR_IC_VHA_FLOP_ERR_INJ_CTRL
  1580. */
  1581. #define VHA_CR_IC_VHA_FLOP_ERR_INJ_CTRL (0x0800U)
  1582. #define VHA_CR_IC_VHA_FLOP_ERR_INJ_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  1583. #define VHA_CR_IC_VHA_FLOP_ERR_INJ_CTRL_ERR_INJ_CTRL_SHIFT (0U)
  1584. #define VHA_CR_IC_VHA_FLOP_ERR_INJ_CTRL_ERR_INJ_CTRL_CLRMSK (0XFFFFFFFEU)
  1585. #define VHA_CR_IC_VHA_FLOP_ERR_INJ_CTRL_ERR_INJ_CTRL_EN (0X00000001U)
  1586. /*
  1587. Register VHA_CR_IC_VHA_FLOP_ERR_INJ_STATUS
  1588. */
  1589. #define VHA_CR_IC_VHA_FLOP_ERR_INJ_STATUS (0x0808U)
  1590. #define VHA_CR_IC_VHA_FLOP_ERR_INJ_STATUS_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  1591. #define VHA_CR_IC_VHA_FLOP_ERR_INJ_STATUS_ERR_INJ_STATUS_SHIFT (0U)
  1592. #define VHA_CR_IC_VHA_FLOP_ERR_INJ_STATUS_ERR_INJ_STATUS_CLRMSK (0XFFFFFFFEU)
  1593. #define VHA_CR_IC_VHA_FLOP_ERR_INJ_STATUS_ERR_INJ_STATUS_EN (0X00000001U)
  1594. /*
  1595. Register VHA_CR_NN_SYS2_SYSBUS_HOST_STALL_RATIO
  1596. */
  1597. #define VHA_CR_NN_SYS2_SYSBUS_HOST_STALL_RATIO (0x1000U)
  1598. #define VHA_CR_NN_SYS2_SYSBUS_HOST_STALL_RATIO_MASKFULL (IMG_UINT64_C(0x000000000000FFFF))
  1599. #define VHA_CR_NN_SYS2_SYSBUS_HOST_STALL_RATIO_LSYNC_SOCIF_RTN_SHIFT (12U)
  1600. #define VHA_CR_NN_SYS2_SYSBUS_HOST_STALL_RATIO_LSYNC_SOCIF_RTN_CLRMSK (0XFFFF0FFFU)
  1601. #define VHA_CR_NN_SYS2_SYSBUS_HOST_STALL_RATIO_LSYNC_SOCIF_SHIFT (8U)
  1602. #define VHA_CR_NN_SYS2_SYSBUS_HOST_STALL_RATIO_LSYNC_SOCIF_CLRMSK (0XFFFFF0FFU)
  1603. #define VHA_CR_NN_SYS2_SYSBUS_HOST_STALL_RATIO_HOST_SOCIF_RTN_SHIFT (4U)
  1604. #define VHA_CR_NN_SYS2_SYSBUS_HOST_STALL_RATIO_HOST_SOCIF_RTN_CLRMSK (0XFFFFFF0FU)
  1605. #define VHA_CR_NN_SYS2_SYSBUS_HOST_STALL_RATIO_HOST_SOCIF_SHIFT (0U)
  1606. #define VHA_CR_NN_SYS2_SYSBUS_HOST_STALL_RATIO_HOST_SOCIF_CLRMSK (0XFFFFFFF0U)
  1607. /*
  1608. Register VHA_CR_NN_SYS2_SYSBUS_WM_STALL_RATIO
  1609. */
  1610. #define VHA_CR_NN_SYS2_SYSBUS_WM_STALL_RATIO (0x1008U)
  1611. #define VHA_CR_NN_SYS2_SYSBUS_WM_STALL_RATIO_MASKFULL (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
  1612. #define VHA_CR_NN_SYS2_SYSBUS_WM_STALL_RATIO_WM7_SOCIF_RTN_SHIFT (60U)
  1613. #define VHA_CR_NN_SYS2_SYSBUS_WM_STALL_RATIO_WM7_SOCIF_RTN_CLRMSK (IMG_UINT64_C(0X0FFFFFFFFFFFFFFF))
  1614. #define VHA_CR_NN_SYS2_SYSBUS_WM_STALL_RATIO_WM7_SOCIF_SHIFT (56U)
  1615. #define VHA_CR_NN_SYS2_SYSBUS_WM_STALL_RATIO_WM7_SOCIF_CLRMSK (IMG_UINT64_C(0XF0FFFFFFFFFFFFFF))
  1616. #define VHA_CR_NN_SYS2_SYSBUS_WM_STALL_RATIO_WM6_SOCIF_RTN_SHIFT (52U)
  1617. #define VHA_CR_NN_SYS2_SYSBUS_WM_STALL_RATIO_WM6_SOCIF_RTN_CLRMSK (IMG_UINT64_C(0XFF0FFFFFFFFFFFFF))
  1618. #define VHA_CR_NN_SYS2_SYSBUS_WM_STALL_RATIO_WM6_SOCIF_SHIFT (48U)
  1619. #define VHA_CR_NN_SYS2_SYSBUS_WM_STALL_RATIO_WM6_SOCIF_CLRMSK (IMG_UINT64_C(0XFFF0FFFFFFFFFFFF))
  1620. #define VHA_CR_NN_SYS2_SYSBUS_WM_STALL_RATIO_WM5_SOCIF_RTN_SHIFT (44U)
  1621. #define VHA_CR_NN_SYS2_SYSBUS_WM_STALL_RATIO_WM5_SOCIF_RTN_CLRMSK (IMG_UINT64_C(0XFFFF0FFFFFFFFFFF))
  1622. #define VHA_CR_NN_SYS2_SYSBUS_WM_STALL_RATIO_WM5_SOCIF_SHIFT (40U)
  1623. #define VHA_CR_NN_SYS2_SYSBUS_WM_STALL_RATIO_WM5_SOCIF_CLRMSK (IMG_UINT64_C(0XFFFFF0FFFFFFFFFF))
  1624. #define VHA_CR_NN_SYS2_SYSBUS_WM_STALL_RATIO_WM4_SOCIF_RTN_SHIFT (36U)
  1625. #define VHA_CR_NN_SYS2_SYSBUS_WM_STALL_RATIO_WM4_SOCIF_RTN_CLRMSK (IMG_UINT64_C(0XFFFFFF0FFFFFFFFF))
  1626. #define VHA_CR_NN_SYS2_SYSBUS_WM_STALL_RATIO_WM4_SOCIF_SHIFT (32U)
  1627. #define VHA_CR_NN_SYS2_SYSBUS_WM_STALL_RATIO_WM4_SOCIF_CLRMSK (IMG_UINT64_C(0XFFFFFFF0FFFFFFFF))
  1628. #define VHA_CR_NN_SYS2_SYSBUS_WM_STALL_RATIO_WM3_SOCIF_RTN_SHIFT (28U)
  1629. #define VHA_CR_NN_SYS2_SYSBUS_WM_STALL_RATIO_WM3_SOCIF_RTN_CLRMSK (IMG_UINT64_C(0XFFFFFFFF0FFFFFFF))
  1630. #define VHA_CR_NN_SYS2_SYSBUS_WM_STALL_RATIO_WM3_SOCIF_SHIFT (24U)
  1631. #define VHA_CR_NN_SYS2_SYSBUS_WM_STALL_RATIO_WM3_SOCIF_CLRMSK (IMG_UINT64_C(0XFFFFFFFFF0FFFFFF))
  1632. #define VHA_CR_NN_SYS2_SYSBUS_WM_STALL_RATIO_WM2_SOCIF_RTN_SHIFT (20U)
  1633. #define VHA_CR_NN_SYS2_SYSBUS_WM_STALL_RATIO_WM2_SOCIF_RTN_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF0FFFFF))
  1634. #define VHA_CR_NN_SYS2_SYSBUS_WM_STALL_RATIO_WM2_SOCIF_SHIFT (16U)
  1635. #define VHA_CR_NN_SYS2_SYSBUS_WM_STALL_RATIO_WM2_SOCIF_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF0FFFF))
  1636. #define VHA_CR_NN_SYS2_SYSBUS_WM_STALL_RATIO_WM1_SOCIF_RTN_SHIFT (12U)
  1637. #define VHA_CR_NN_SYS2_SYSBUS_WM_STALL_RATIO_WM1_SOCIF_RTN_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF0FFF))
  1638. #define VHA_CR_NN_SYS2_SYSBUS_WM_STALL_RATIO_WM1_SOCIF_SHIFT (8U)
  1639. #define VHA_CR_NN_SYS2_SYSBUS_WM_STALL_RATIO_WM1_SOCIF_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF0FF))
  1640. #define VHA_CR_NN_SYS2_SYSBUS_WM_STALL_RATIO_WM0_SOCIF_RTN_SHIFT (4U)
  1641. #define VHA_CR_NN_SYS2_SYSBUS_WM_STALL_RATIO_WM0_SOCIF_RTN_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFF0F))
  1642. #define VHA_CR_NN_SYS2_SYSBUS_WM_STALL_RATIO_WM0_SOCIF_SHIFT (0U)
  1643. #define VHA_CR_NN_SYS2_SYSBUS_WM_STALL_RATIO_WM0_SOCIF_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF0))
  1644. /*
  1645. Register VHA_CR_TLC_VHA_FLOP_ERR_INJ_CTRL
  1646. */
  1647. #define VHA_CR_TLC_VHA_FLOP_ERR_INJ_CTRL (0x1200U)
  1648. #define VHA_CR_TLC_VHA_FLOP_ERR_INJ_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  1649. #define VHA_CR_TLC_VHA_FLOP_ERR_INJ_CTRL_ERR_INJ_CTRL_SHIFT (0U)
  1650. #define VHA_CR_TLC_VHA_FLOP_ERR_INJ_CTRL_ERR_INJ_CTRL_CLRMSK (0XFFFFFFFEU)
  1651. #define VHA_CR_TLC_VHA_FLOP_ERR_INJ_CTRL_ERR_INJ_CTRL_EN (0X00000001U)
  1652. /*
  1653. Register VHA_CR_TLC_VHA_FLOP_ERR_INJ_STATUS
  1654. */
  1655. #define VHA_CR_TLC_VHA_FLOP_ERR_INJ_STATUS (0x1208U)
  1656. #define VHA_CR_TLC_VHA_FLOP_ERR_INJ_STATUS_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  1657. #define VHA_CR_TLC_VHA_FLOP_ERR_INJ_STATUS_ERR_INJ_STATUS_SHIFT (0U)
  1658. #define VHA_CR_TLC_VHA_FLOP_ERR_INJ_STATUS_ERR_INJ_STATUS_CLRMSK (0XFFFFFFFEU)
  1659. #define VHA_CR_TLC_VHA_FLOP_ERR_INJ_STATUS_ERR_INJ_STATUS_EN (0X00000001U)
  1660. /*
  1661. Register VHA_CR_LOW_LEVEL_SYNC_BASE_ADDR
  1662. */
  1663. #define VHA_CR_LOW_LEVEL_SYNC_BASE_ADDR (0x3000U)
  1664. #define VHA_CR_LOW_LEVEL_SYNC_BASE_ADDR_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFE0))
  1665. #define VHA_CR_LOW_LEVEL_SYNC_BASE_ADDR_BASE_ADDR_SHIFT (5U)
  1666. #define VHA_CR_LOW_LEVEL_SYNC_BASE_ADDR_BASE_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF000000001F))
  1667. /*
  1668. Register VHA_CR_SOCM_BASE_ADDR
  1669. */
  1670. #define VHA_CR_SOCM_BASE_ADDR (0x3008U)
  1671. #define VHA_CR_SOCM_BASE_ADDR_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFE0))
  1672. #define VHA_CR_SOCM_BASE_ADDR_BASE_ADDR_SHIFT (5U)
  1673. #define VHA_CR_SOCM_BASE_ADDR_BASE_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF000000001F))
  1674. /*
  1675. Register VHA_CR_SOCM_CIRCULAR_BUFFER_SIZE
  1676. */
  1677. #define VHA_CR_SOCM_CIRCULAR_BUFFER_SIZE (0x3010U)
  1678. #define VHA_CR_SOCM_CIRCULAR_BUFFER_SIZE_MASKFULL (IMG_UINT64_C(0x00000000FFFFFF80))
  1679. #define VHA_CR_SOCM_CIRCULAR_BUFFER_SIZE_SOCM_CIRCULAR_BUFFER_SIZE_SHIFT (7U)
  1680. #define VHA_CR_SOCM_CIRCULAR_BUFFER_SIZE_SOCM_CIRCULAR_BUFFER_SIZE_CLRMSK (IMG_UINT64_C(0XFFFFFFFF0000007F))
  1681. #define VHA_CR_SOCM_CIRCULAR_BUFFER_SIZE_SOCM_CIRCULAR_BUFFER_SIZE_ALIGNSHIFT (7U)
  1682. #define VHA_CR_SOCM_CIRCULAR_BUFFER_SIZE_SOCM_CIRCULAR_BUFFER_SIZE_ALIGNSIZE (128U)
  1683. /*
  1684. Register VHA_CR_SOCM_B7_XOR_BITS
  1685. */
  1686. #define VHA_CR_SOCM_B7_XOR_BITS (0x3018U)
  1687. #define VHA_CR_SOCM_B7_XOR_BITS_MASKFULL (IMG_UINT64_C(0x0000000001FFFE00))
  1688. #define VHA_CR_SOCM_B7_XOR_BITS_SOCM_B7_XOR_BITS_SHIFT (9U)
  1689. #define VHA_CR_SOCM_B7_XOR_BITS_SOCM_B7_XOR_BITS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFE0001FF))
  1690. /*
  1691. Register VHA_CR_SOCM_B8_XOR_BITS
  1692. */
  1693. #define VHA_CR_SOCM_B8_XOR_BITS (0x3020U)
  1694. #define VHA_CR_SOCM_B8_XOR_BITS_MASKFULL (IMG_UINT64_C(0x0000000001FFFE00))
  1695. #define VHA_CR_SOCM_B8_XOR_BITS_SOCM_B8_XOR_BITS_SHIFT (9U)
  1696. #define VHA_CR_SOCM_B8_XOR_BITS_SOCM_B8_XOR_BITS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFE0001FF))
  1697. /*
  1698. Register VHA_CR_SOCM_MASKEDWRITE_STALL
  1699. */
  1700. #define VHA_CR_SOCM_MASKEDWRITE_STALL (0x3028U)
  1701. #define VHA_CR_SOCM_MASKEDWRITE_STALL_MASKFULL (IMG_UINT64_C(0x0000000000000FFF))
  1702. #define VHA_CR_SOCM_MASKEDWRITE_STALL_IDLE_SHIFT (6U)
  1703. #define VHA_CR_SOCM_MASKEDWRITE_STALL_IDLE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF03F))
  1704. #define VHA_CR_SOCM_MASKEDWRITE_STALL_BUSY_SHIFT (0U)
  1705. #define VHA_CR_SOCM_MASKEDWRITE_STALL_BUSY_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFC0))
  1706. /*
  1707. Register VHA_CR_BW_LIMIT_CTRL
  1708. */
  1709. #define VHA_CR_BW_LIMIT_CTRL (0x3030U)
  1710. #define VHA_CR_BW_LIMIT_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  1711. #define VHA_CR_BW_LIMIT_CTRL_BW_LIMIT_ENABLE_SHIFT (0U)
  1712. #define VHA_CR_BW_LIMIT_CTRL_BW_LIMIT_ENABLE_CLRMSK (0XFFFFFFFEU)
  1713. #define VHA_CR_BW_LIMIT_CTRL_BW_LIMIT_ENABLE_EN (0X00000001U)
  1714. /*
  1715. Register VHA_CR_BW_LIMIT_CTRL1
  1716. */
  1717. #define VHA_CR_BW_LIMIT_CTRL1 (0x3038U)
  1718. #define VHA_CR_BW_LIMIT_CTRL1_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  1719. #define VHA_CR_BW_LIMIT_CTRL1_BW_LIMIT_MAX_FLEX_SHIFT (24U)
  1720. #define VHA_CR_BW_LIMIT_CTRL1_BW_LIMIT_MAX_FLEX_CLRMSK (IMG_UINT64_C(0XFFFFFF0000FFFFFF))
  1721. #define VHA_CR_BW_LIMIT_CTRL1_BW_LIMIT_MAX_SLOPE_SHIFT (16U)
  1722. #define VHA_CR_BW_LIMIT_CTRL1_BW_LIMIT_MAX_SLOPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF00FFFF))
  1723. #define VHA_CR_BW_LIMIT_CTRL1_BW_LIMIT_REQ_INCR_SHIFT (8U)
  1724. #define VHA_CR_BW_LIMIT_CTRL1_BW_LIMIT_REQ_INCR_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF00FF))
  1725. #define VHA_CR_BW_LIMIT_CTRL1_BW_LIMIT_PERIOD_MIN1_SHIFT (0U)
  1726. #define VHA_CR_BW_LIMIT_CTRL1_BW_LIMIT_PERIOD_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFF00))
  1727. /*
  1728. Register VHA_CR_NOC_BWM_CONTROL
  1729. */
  1730. #define VHA_CR_NOC_BWM_CONTROL (0x3040U)
  1731. #define VHA_CR_NOC_BWM_CONTROL_MASKFULL (IMG_UINT64_C(0x00000000000000FF))
  1732. #define VHA_CR_NOC_BWM_CONTROL_NOC_BWM_REQUESTER_SHIFT (1U)
  1733. #define VHA_CR_NOC_BWM_CONTROL_NOC_BWM_REQUESTER_CLRMSK (0XFFFFFF01U)
  1734. #define VHA_CR_NOC_BWM_CONTROL_NOC_BWM_ENABLE_SHIFT (0U)
  1735. #define VHA_CR_NOC_BWM_CONTROL_NOC_BWM_ENABLE_CLRMSK (0XFFFFFFFEU)
  1736. #define VHA_CR_NOC_BWM_CONTROL_NOC_BWM_ENABLE_EN (0X00000001U)
  1737. /*
  1738. Register VHA_CR_CORE_BW_SOCM_RD
  1739. */
  1740. #define VHA_CR_CORE_BW_SOCM_RD (0x3100U)
  1741. #define VHA_CR_CORE_BW_SOCM_RD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  1742. #define VHA_CR_CORE_BW_SOCM_RD_BW_SHIFT (0U)
  1743. #define VHA_CR_CORE_BW_SOCM_RD_BW_CLRMSK (00000000U)
  1744. /*
  1745. Register VHA_CR_CORE_BW_SOCM_WR
  1746. */
  1747. #define VHA_CR_CORE_BW_SOCM_WR (0x3108U)
  1748. #define VHA_CR_CORE_BW_SOCM_WR_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  1749. #define VHA_CR_CORE_BW_SOCM_WR_BW_SHIFT (0U)
  1750. #define VHA_CR_CORE_BW_SOCM_WR_BW_CLRMSK (00000000U)
  1751. /*
  1752. Register VHA_CR_CORE_BW_SOCM_MWR
  1753. */
  1754. #define VHA_CR_CORE_BW_SOCM_MWR (0x3110U)
  1755. #define VHA_CR_CORE_BW_SOCM_MWR_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  1756. #define VHA_CR_CORE_BW_SOCM_MWR_BW_SHIFT (0U)
  1757. #define VHA_CR_CORE_BW_SOCM_MWR_BW_CLRMSK (00000000U)
  1758. /*
  1759. Register VHA_CR_CORE_BW_DDR_RD
  1760. */
  1761. #define VHA_CR_CORE_BW_DDR_RD (0x3118U)
  1762. #define VHA_CR_CORE_BW_DDR_RD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  1763. #define VHA_CR_CORE_BW_DDR_RD_BW_SHIFT (0U)
  1764. #define VHA_CR_CORE_BW_DDR_RD_BW_CLRMSK (00000000U)
  1765. /*
  1766. Register VHA_CR_CORE_BW_DDR_WR
  1767. */
  1768. #define VHA_CR_CORE_BW_DDR_WR (0x3120U)
  1769. #define VHA_CR_CORE_BW_DDR_WR_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  1770. #define VHA_CR_CORE_BW_DDR_WR_BW_SHIFT (0U)
  1771. #define VHA_CR_CORE_BW_DDR_WR_BW_CLRMSK (00000000U)
  1772. /*
  1773. Register VHA_CR_CORE_BW_DDR_MWR
  1774. */
  1775. #define VHA_CR_CORE_BW_DDR_MWR (0x3128U)
  1776. #define VHA_CR_CORE_BW_DDR_MWR_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  1777. #define VHA_CR_CORE_BW_DDR_MWR_BW_SHIFT (0U)
  1778. #define VHA_CR_CORE_BW_DDR_MWR_BW_CLRMSK (00000000U)
  1779. /*
  1780. Register VHA_CR_CORE_BW_SOCM_RD_WORD
  1781. */
  1782. #define VHA_CR_CORE_BW_SOCM_RD_WORD (0x3130U)
  1783. #define VHA_CR_CORE_BW_SOCM_RD_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  1784. #define VHA_CR_CORE_BW_SOCM_RD_WORD_BW_SHIFT (0U)
  1785. #define VHA_CR_CORE_BW_SOCM_RD_WORD_BW_CLRMSK (00000000U)
  1786. /*
  1787. Register VHA_CR_CORE_BW_SOCM_WR_WORD
  1788. */
  1789. #define VHA_CR_CORE_BW_SOCM_WR_WORD (0x3138U)
  1790. #define VHA_CR_CORE_BW_SOCM_WR_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  1791. #define VHA_CR_CORE_BW_SOCM_WR_WORD_BW_SHIFT (0U)
  1792. #define VHA_CR_CORE_BW_SOCM_WR_WORD_BW_CLRMSK (00000000U)
  1793. /*
  1794. Register VHA_CR_CORE_BW_DDR_RD_WORD
  1795. */
  1796. #define VHA_CR_CORE_BW_DDR_RD_WORD (0x3140U)
  1797. #define VHA_CR_CORE_BW_DDR_RD_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  1798. #define VHA_CR_CORE_BW_DDR_RD_WORD_BW_SHIFT (0U)
  1799. #define VHA_CR_CORE_BW_DDR_RD_WORD_BW_CLRMSK (00000000U)
  1800. /*
  1801. Register VHA_CR_CORE_BW_DDR_WR_WORD
  1802. */
  1803. #define VHA_CR_CORE_BW_DDR_WR_WORD (0x3148U)
  1804. #define VHA_CR_CORE_BW_DDR_WR_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  1805. #define VHA_CR_CORE_BW_DDR_WR_WORD_BW_SHIFT (0U)
  1806. #define VHA_CR_CORE_BW_DDR_WR_WORD_BW_CLRMSK (00000000U)
  1807. /*
  1808. Register VHA_CR_NN_SYS2_MEMBUS_SYS_STALL_RATIO
  1809. */
  1810. #define VHA_CR_NN_SYS2_MEMBUS_SYS_STALL_RATIO (0x3150U)
  1811. #define VHA_CR_NN_SYS2_MEMBUS_SYS_STALL_RATIO_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  1812. #define VHA_CR_NN_SYS2_MEMBUS_SYS_STALL_RATIO_SYS_NOC_LSYNC_RTN_SHIFT (28U)
  1813. #define VHA_CR_NN_SYS2_MEMBUS_SYS_STALL_RATIO_SYS_NOC_LSYNC_RTN_CLRMSK (0X0FFFFFFFU)
  1814. #define VHA_CR_NN_SYS2_MEMBUS_SYS_STALL_RATIO_SYS_NOC_LSYNC_SHIFT (24U)
  1815. #define VHA_CR_NN_SYS2_MEMBUS_SYS_STALL_RATIO_SYS_NOC_LSYNC_CLRMSK (0XF0FFFFFFU)
  1816. #define VHA_CR_NN_SYS2_MEMBUS_SYS_STALL_RATIO_SYS_NOC_SOCM_RTN_SHIFT (20U)
  1817. #define VHA_CR_NN_SYS2_MEMBUS_SYS_STALL_RATIO_SYS_NOC_SOCM_RTN_CLRMSK (0XFF0FFFFFU)
  1818. #define VHA_CR_NN_SYS2_MEMBUS_SYS_STALL_RATIO_SYS_NOC_SOCM_SHIFT (16U)
  1819. #define VHA_CR_NN_SYS2_MEMBUS_SYS_STALL_RATIO_SYS_NOC_SOCM_CLRMSK (0XFFF0FFFFU)
  1820. #define VHA_CR_NN_SYS2_MEMBUS_SYS_STALL_RATIO_SYS_NOC_SLC_RTN_SHIFT (12U)
  1821. #define VHA_CR_NN_SYS2_MEMBUS_SYS_STALL_RATIO_SYS_NOC_SLC_RTN_CLRMSK (0XFFFF0FFFU)
  1822. #define VHA_CR_NN_SYS2_MEMBUS_SYS_STALL_RATIO_SYS_NOC_SLC_SHIFT (8U)
  1823. #define VHA_CR_NN_SYS2_MEMBUS_SYS_STALL_RATIO_SYS_NOC_SLC_CLRMSK (0XFFFFF0FFU)
  1824. #define VHA_CR_NN_SYS2_MEMBUS_SYS_STALL_RATIO_CORE_SYS_NOC_RTN_SHIFT (4U)
  1825. #define VHA_CR_NN_SYS2_MEMBUS_SYS_STALL_RATIO_CORE_SYS_NOC_RTN_CLRMSK (0XFFFFFF0FU)
  1826. #define VHA_CR_NN_SYS2_MEMBUS_SYS_STALL_RATIO_CORE_SYS_NOC_SHIFT (0U)
  1827. #define VHA_CR_NN_SYS2_MEMBUS_SYS_STALL_RATIO_CORE_SYS_NOC_CLRMSK (0XFFFFFFF0U)
  1828. /*
  1829. SYS_MEM_WDT is Disabled */
  1830. #define VHA_CR_SYS_MEM_WDT_CTRL_SYS_MEM_WDT_CTRL_NONE (0x00000000U)
  1831. /*
  1832. SYS_MEM_WDT is Cleared when WM is running */
  1833. #define VHA_CR_SYS_MEM_WDT_CTRL_SYS_MEM_WDT_CTRL_KICK_WL (0x00000001U)
  1834. /*
  1835. Register VHA_CR_SYS_MEM_WDT_CTRL
  1836. */
  1837. #define VHA_CR_SYS_MEM_WDT_CTRL (0x5000U)
  1838. #define VHA_CR_SYS_MEM_WDT_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  1839. #define VHA_CR_SYS_MEM_WDT_CTRL_MODE_SHIFT (0U)
  1840. #define VHA_CR_SYS_MEM_WDT_CTRL_MODE_CLRMSK (0XFFFFFFFEU)
  1841. #define VHA_CR_SYS_MEM_WDT_CTRL_MODE_NONE (00000000U)
  1842. #define VHA_CR_SYS_MEM_WDT_CTRL_MODE_KICK_WL (0X00000001U)
  1843. /*
  1844. Register VHA_CR_SYS_MEM_WDT_COMPAREMATCH
  1845. */
  1846. #define VHA_CR_SYS_MEM_WDT_COMPAREMATCH (0x5008U)
  1847. #define VHA_CR_SYS_MEM_WDT_COMPAREMATCH_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  1848. #define VHA_CR_SYS_MEM_WDT_COMPAREMATCH_VALUE_SHIFT (0U)
  1849. #define VHA_CR_SYS_MEM_WDT_COMPAREMATCH_VALUE_CLRMSK (00000000U)
  1850. /*
  1851. Register VHA_CR_SYS_MEM_WDT_TIMER
  1852. */
  1853. #define VHA_CR_SYS_MEM_WDT_TIMER (0x5010U)
  1854. #define VHA_CR_SYS_MEM_WDT_TIMER_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  1855. #define VHA_CR_SYS_MEM_WDT_TIMER_VALUE_SHIFT (0U)
  1856. #define VHA_CR_SYS_MEM_WDT_TIMER_VALUE_CLRMSK (00000000U)
  1857. /*
  1858. Register VHA_CR_LOW_LEVEL_SYNC_STATUS
  1859. */
  1860. #define VHA_CR_LOW_LEVEL_SYNC_STATUS (0x5018U)
  1861. #define VHA_CR_LOW_LEVEL_SYNC_STATUS_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  1862. #define VHA_CR_LOW_LEVEL_SYNC_STATUS_CORE7_SHIFT (28U)
  1863. #define VHA_CR_LOW_LEVEL_SYNC_STATUS_CORE7_CLRMSK (0X0FFFFFFFU)
  1864. #define VHA_CR_LOW_LEVEL_SYNC_STATUS_CORE6_SHIFT (24U)
  1865. #define VHA_CR_LOW_LEVEL_SYNC_STATUS_CORE6_CLRMSK (0XF0FFFFFFU)
  1866. #define VHA_CR_LOW_LEVEL_SYNC_STATUS_CORE5_SHIFT (20U)
  1867. #define VHA_CR_LOW_LEVEL_SYNC_STATUS_CORE5_CLRMSK (0XFF0FFFFFU)
  1868. #define VHA_CR_LOW_LEVEL_SYNC_STATUS_CORE4_SHIFT (16U)
  1869. #define VHA_CR_LOW_LEVEL_SYNC_STATUS_CORE4_CLRMSK (0XFFF0FFFFU)
  1870. #define VHA_CR_LOW_LEVEL_SYNC_STATUS_CORE3_SHIFT (12U)
  1871. #define VHA_CR_LOW_LEVEL_SYNC_STATUS_CORE3_CLRMSK (0XFFFF0FFFU)
  1872. #define VHA_CR_LOW_LEVEL_SYNC_STATUS_CORE2_SHIFT (8U)
  1873. #define VHA_CR_LOW_LEVEL_SYNC_STATUS_CORE2_CLRMSK (0XFFFFF0FFU)
  1874. #define VHA_CR_LOW_LEVEL_SYNC_STATUS_CORE1_SHIFT (4U)
  1875. #define VHA_CR_LOW_LEVEL_SYNC_STATUS_CORE1_CLRMSK (0XFFFFFF0FU)
  1876. #define VHA_CR_LOW_LEVEL_SYNC_STATUS_CORE0_SHIFT (0U)
  1877. #define VHA_CR_LOW_LEVEL_SYNC_STATUS_CORE0_CLRMSK (0XFFFFFFF0U)
  1878. /*
  1879. Register VHA_CR_LOW_LEVEL_SYNC_CLEAR
  1880. */
  1881. #define VHA_CR_LOW_LEVEL_SYNC_CLEAR (0x5020U)
  1882. #define VHA_CR_LOW_LEVEL_SYNC_CLEAR_MASKFULL (IMG_UINT64_C(0x00000000000000FF))
  1883. #define VHA_CR_LOW_LEVEL_SYNC_CLEAR_CORE7_SHIFT (7U)
  1884. #define VHA_CR_LOW_LEVEL_SYNC_CLEAR_CORE7_CLRMSK (0XFFFFFF7FU)
  1885. #define VHA_CR_LOW_LEVEL_SYNC_CLEAR_CORE7_EN (0X00000080U)
  1886. #define VHA_CR_LOW_LEVEL_SYNC_CLEAR_CORE6_SHIFT (6U)
  1887. #define VHA_CR_LOW_LEVEL_SYNC_CLEAR_CORE6_CLRMSK (0XFFFFFFBFU)
  1888. #define VHA_CR_LOW_LEVEL_SYNC_CLEAR_CORE6_EN (0X00000040U)
  1889. #define VHA_CR_LOW_LEVEL_SYNC_CLEAR_CORE5_SHIFT (5U)
  1890. #define VHA_CR_LOW_LEVEL_SYNC_CLEAR_CORE5_CLRMSK (0XFFFFFFDFU)
  1891. #define VHA_CR_LOW_LEVEL_SYNC_CLEAR_CORE5_EN (0X00000020U)
  1892. #define VHA_CR_LOW_LEVEL_SYNC_CLEAR_CORE4_SHIFT (4U)
  1893. #define VHA_CR_LOW_LEVEL_SYNC_CLEAR_CORE4_CLRMSK (0XFFFFFFEFU)
  1894. #define VHA_CR_LOW_LEVEL_SYNC_CLEAR_CORE4_EN (0X00000010U)
  1895. #define VHA_CR_LOW_LEVEL_SYNC_CLEAR_CORE3_SHIFT (3U)
  1896. #define VHA_CR_LOW_LEVEL_SYNC_CLEAR_CORE3_CLRMSK (0XFFFFFFF7U)
  1897. #define VHA_CR_LOW_LEVEL_SYNC_CLEAR_CORE3_EN (0X00000008U)
  1898. #define VHA_CR_LOW_LEVEL_SYNC_CLEAR_CORE2_SHIFT (2U)
  1899. #define VHA_CR_LOW_LEVEL_SYNC_CLEAR_CORE2_CLRMSK (0XFFFFFFFBU)
  1900. #define VHA_CR_LOW_LEVEL_SYNC_CLEAR_CORE2_EN (0X00000004U)
  1901. #define VHA_CR_LOW_LEVEL_SYNC_CLEAR_CORE1_SHIFT (1U)
  1902. #define VHA_CR_LOW_LEVEL_SYNC_CLEAR_CORE1_CLRMSK (0XFFFFFFFDU)
  1903. #define VHA_CR_LOW_LEVEL_SYNC_CLEAR_CORE1_EN (0X00000002U)
  1904. #define VHA_CR_LOW_LEVEL_SYNC_CLEAR_CORE0_SHIFT (0U)
  1905. #define VHA_CR_LOW_LEVEL_SYNC_CLEAR_CORE0_CLRMSK (0XFFFFFFFEU)
  1906. #define VHA_CR_LOW_LEVEL_SYNC_CLEAR_CORE0_EN (0X00000001U)
  1907. /*
  1908. Register VHA_CR_SOCM_SCRUB_CTRL
  1909. */
  1910. #define VHA_CR_SOCM_SCRUB_CTRL (0x5028U)
  1911. #define VHA_CR_SOCM_SCRUB_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000000011))
  1912. #define VHA_CR_SOCM_SCRUB_CTRL_MODE_SHIFT (4U)
  1913. #define VHA_CR_SOCM_SCRUB_CTRL_MODE_CLRMSK (0XFFFFFFEFU)
  1914. #define VHA_CR_SOCM_SCRUB_CTRL_MODE_EN (0X00000010U)
  1915. #define VHA_CR_SOCM_SCRUB_CTRL_KICK_SHIFT (0U)
  1916. #define VHA_CR_SOCM_SCRUB_CTRL_KICK_CLRMSK (0XFFFFFFFEU)
  1917. #define VHA_CR_SOCM_SCRUB_CTRL_KICK_EN (0X00000001U)
  1918. /*
  1919. Register VHA_CR_PERF_SLC0_READ
  1920. */
  1921. #define VHA_CR_PERF_SLC0_READ (0x7000U)
  1922. #define VHA_CR_PERF_SLC0_READ_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  1923. #define VHA_CR_PERF_SLC0_READ_COUNT_SHIFT (0U)
  1924. #define VHA_CR_PERF_SLC0_READ_COUNT_CLRMSK (00000000U)
  1925. /*
  1926. Register VHA_CR_PERF_SLC0_WRITE
  1927. */
  1928. #define VHA_CR_PERF_SLC0_WRITE (0x7008U)
  1929. #define VHA_CR_PERF_SLC0_WRITE_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  1930. #define VHA_CR_PERF_SLC0_WRITE_COUNT_SHIFT (0U)
  1931. #define VHA_CR_PERF_SLC0_WRITE_COUNT_CLRMSK (00000000U)
  1932. /*
  1933. Register VHA_CR_PERF_SLC0_WRITE_DATA_STALL
  1934. */
  1935. #define VHA_CR_PERF_SLC0_WRITE_DATA_STALL (0x7010U)
  1936. #define VHA_CR_PERF_SLC0_WRITE_DATA_STALL_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  1937. #define VHA_CR_PERF_SLC0_WRITE_DATA_STALL_COUNT_SHIFT (0U)
  1938. #define VHA_CR_PERF_SLC0_WRITE_DATA_STALL_COUNT_CLRMSK (00000000U)
  1939. /*
  1940. Register VHA_CR_PERF_SLC0_READ_STALL
  1941. */
  1942. #define VHA_CR_PERF_SLC0_READ_STALL (0x7018U)
  1943. #define VHA_CR_PERF_SLC0_READ_STALL_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  1944. #define VHA_CR_PERF_SLC0_READ_STALL_COUNT_SHIFT (0U)
  1945. #define VHA_CR_PERF_SLC0_READ_STALL_COUNT_CLRMSK (00000000U)
  1946. /*
  1947. Register VHA_CR_PERF_SLC0_WRITE_STALL
  1948. */
  1949. #define VHA_CR_PERF_SLC0_WRITE_STALL (0x7020U)
  1950. #define VHA_CR_PERF_SLC0_WRITE_STALL_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  1951. #define VHA_CR_PERF_SLC0_WRITE_STALL_COUNT_SHIFT (0U)
  1952. #define VHA_CR_PERF_SLC0_WRITE_STALL_COUNT_CLRMSK (00000000U)
  1953. /*
  1954. Register VHA_CR_PERF_SLC0_READ_ID_STALL
  1955. */
  1956. #define VHA_CR_PERF_SLC0_READ_ID_STALL (0x7028U)
  1957. #define VHA_CR_PERF_SLC0_READ_ID_STALL_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  1958. #define VHA_CR_PERF_SLC0_READ_ID_STALL_COUNT_SHIFT (0U)
  1959. #define VHA_CR_PERF_SLC0_READ_ID_STALL_COUNT_CLRMSK (00000000U)
  1960. /*
  1961. Register VHA_CR_PERF_SLC0_WRITE_ID_STALL
  1962. */
  1963. #define VHA_CR_PERF_SLC0_WRITE_ID_STALL (0x7030U)
  1964. #define VHA_CR_PERF_SLC0_WRITE_ID_STALL_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  1965. #define VHA_CR_PERF_SLC0_WRITE_ID_STALL_COUNT_SHIFT (0U)
  1966. #define VHA_CR_PERF_SLC0_WRITE_ID_STALL_COUNT_CLRMSK (00000000U)
  1967. /*
  1968. Register VHA_CR_PERF_SLC0_RD_BURST_SIZE1
  1969. */
  1970. #define VHA_CR_PERF_SLC0_RD_BURST_SIZE1 (0x7038U)
  1971. #define VHA_CR_PERF_SLC0_RD_BURST_SIZE1_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  1972. #define VHA_CR_PERF_SLC0_RD_BURST_SIZE1_COUNT_SHIFT (0U)
  1973. #define VHA_CR_PERF_SLC0_RD_BURST_SIZE1_COUNT_CLRMSK (00000000U)
  1974. /*
  1975. Register VHA_CR_PERF_SLC0_WR_BURST_SIZE1
  1976. */
  1977. #define VHA_CR_PERF_SLC0_WR_BURST_SIZE1 (0x7040U)
  1978. #define VHA_CR_PERF_SLC0_WR_BURST_SIZE1_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  1979. #define VHA_CR_PERF_SLC0_WR_BURST_SIZE1_COUNT_SHIFT (0U)
  1980. #define VHA_CR_PERF_SLC0_WR_BURST_SIZE1_COUNT_CLRMSK (00000000U)
  1981. /*
  1982. Register VHA_CR_PERF_SLC0_RD_BURST_SIZE2
  1983. */
  1984. #define VHA_CR_PERF_SLC0_RD_BURST_SIZE2 (0x7048U)
  1985. #define VHA_CR_PERF_SLC0_RD_BURST_SIZE2_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  1986. #define VHA_CR_PERF_SLC0_RD_BURST_SIZE2_COUNT_SHIFT (0U)
  1987. #define VHA_CR_PERF_SLC0_RD_BURST_SIZE2_COUNT_CLRMSK (00000000U)
  1988. /*
  1989. Register VHA_CR_PERF_SLC0_WR_BURST_SIZE2
  1990. */
  1991. #define VHA_CR_PERF_SLC0_WR_BURST_SIZE2 (0x7050U)
  1992. #define VHA_CR_PERF_SLC0_WR_BURST_SIZE2_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  1993. #define VHA_CR_PERF_SLC0_WR_BURST_SIZE2_COUNT_SHIFT (0U)
  1994. #define VHA_CR_PERF_SLC0_WR_BURST_SIZE2_COUNT_CLRMSK (00000000U)
  1995. /*
  1996. Register VHA_CR_PERF_SLC0_RD_BURST_SIZE3
  1997. */
  1998. #define VHA_CR_PERF_SLC0_RD_BURST_SIZE3 (0x7058U)
  1999. #define VHA_CR_PERF_SLC0_RD_BURST_SIZE3_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  2000. #define VHA_CR_PERF_SLC0_RD_BURST_SIZE3_COUNT_SHIFT (0U)
  2001. #define VHA_CR_PERF_SLC0_RD_BURST_SIZE3_COUNT_CLRMSK (00000000U)
  2002. /*
  2003. Register VHA_CR_PERF_SLC0_WR_BURST_SIZE3
  2004. */
  2005. #define VHA_CR_PERF_SLC0_WR_BURST_SIZE3 (0x7060U)
  2006. #define VHA_CR_PERF_SLC0_WR_BURST_SIZE3_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  2007. #define VHA_CR_PERF_SLC0_WR_BURST_SIZE3_COUNT_SHIFT (0U)
  2008. #define VHA_CR_PERF_SLC0_WR_BURST_SIZE3_COUNT_CLRMSK (00000000U)
  2009. /*
  2010. Register VHA_CR_PERF_SLC0_RD_BURST_SIZE4
  2011. */
  2012. #define VHA_CR_PERF_SLC0_RD_BURST_SIZE4 (0x7068U)
  2013. #define VHA_CR_PERF_SLC0_RD_BURST_SIZE4_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  2014. #define VHA_CR_PERF_SLC0_RD_BURST_SIZE4_COUNT_SHIFT (0U)
  2015. #define VHA_CR_PERF_SLC0_RD_BURST_SIZE4_COUNT_CLRMSK (00000000U)
  2016. /*
  2017. Register VHA_CR_PERF_SLC0_WR_BURST_SIZE4
  2018. */
  2019. #define VHA_CR_PERF_SLC0_WR_BURST_SIZE4 (0x7070U)
  2020. #define VHA_CR_PERF_SLC0_WR_BURST_SIZE4_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  2021. #define VHA_CR_PERF_SLC0_WR_BURST_SIZE4_COUNT_SHIFT (0U)
  2022. #define VHA_CR_PERF_SLC0_WR_BURST_SIZE4_COUNT_CLRMSK (00000000U)
  2023. /*
  2024. Register VHA_CR_PERF_RESET_FULL
  2025. */
  2026. #define VHA_CR_PERF_RESET_FULL (0x7078U)
  2027. #define VHA_CR_PERF_RESET_FULL_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  2028. #define VHA_CR_PERF_RESET_FULL_RANGE_SHIFT (0U)
  2029. #define VHA_CR_PERF_RESET_FULL_RANGE_CLRMSK (0XFFFFFFFEU)
  2030. #define VHA_CR_PERF_RESET_FULL_RANGE_EN (0X00000001U)
  2031. /*
  2032. Register VHA_CR_PERF_ENABLE_FULL
  2033. */
  2034. #define VHA_CR_PERF_ENABLE_FULL (0x7080U)
  2035. #define VHA_CR_PERF_ENABLE_FULL_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  2036. #define VHA_CR_PERF_ENABLE_FULL_RANGE_SHIFT (0U)
  2037. #define VHA_CR_PERF_ENABLE_FULL_RANGE_CLRMSK (0XFFFFFFFEU)
  2038. #define VHA_CR_PERF_ENABLE_FULL_RANGE_EN (0X00000001U)
  2039. /*
  2040. Register VHA_CR_MMU_STATUS
  2041. */
  2042. #define VHA_CR_MMU_STATUS (0x7088U)
  2043. #define VHA_CR_MMU_STATUS_MASKFULL (IMG_UINT64_C(0x000001FFFFFFFFFF))
  2044. #define VHA_CR_MMU_STATUS_MMU_STALLED_SHIFT (40U)
  2045. #define VHA_CR_MMU_STATUS_MMU_STALLED_CLRMSK (IMG_UINT64_C(0XFFFFFEFFFFFFFFFF))
  2046. #define VHA_CR_MMU_STATUS_MMU_STALLED_EN (IMG_UINT64_C(0X0000010000000000))
  2047. #define VHA_CR_MMU_STATUS_PM_WRITES_SHIFT (38U)
  2048. #define VHA_CR_MMU_STATUS_PM_WRITES_CLRMSK (IMG_UINT64_C(0XFFFFFF3FFFFFFFFF))
  2049. #define VHA_CR_MMU_STATUS_PM_READS_SHIFT (36U)
  2050. #define VHA_CR_MMU_STATUS_PM_READS_CLRMSK (IMG_UINT64_C(0XFFFFFFCFFFFFFFFF))
  2051. #define VHA_CR_MMU_STATUS_PC_READS_SHIFT (24U)
  2052. #define VHA_CR_MMU_STATUS_PC_READS_CLRMSK (IMG_UINT64_C(0XFFFFFFF000FFFFFF))
  2053. #define VHA_CR_MMU_STATUS_PD_READS_SHIFT (12U)
  2054. #define VHA_CR_MMU_STATUS_PD_READS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF000FFF))
  2055. #define VHA_CR_MMU_STATUS_PT_READS_SHIFT (0U)
  2056. #define VHA_CR_MMU_STATUS_PT_READS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF000))
  2057. /*
  2058. Register VHA_CR_SLC_STATUS1
  2059. */
  2060. #define VHA_CR_SLC_STATUS1 (0x7090U)
  2061. #define VHA_CR_SLC_STATUS1_MASKFULL (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
  2062. #define VHA_CR_SLC_STATUS1_RESERVED_SHIFT (48U)
  2063. #define VHA_CR_SLC_STATUS1_RESERVED_CLRMSK (IMG_UINT64_C(0X0000FFFFFFFFFFFF))
  2064. #define VHA_CR_SLC_STATUS1_BUS1_OUTSTANDING_WRITES_SHIFT (36U)
  2065. #define VHA_CR_SLC_STATUS1_BUS1_OUTSTANDING_WRITES_CLRMSK (IMG_UINT64_C(0XFFFF000FFFFFFFFF))
  2066. #define VHA_CR_SLC_STATUS1_BUS0_OUTSTANDING_WRITES_SHIFT (24U)
  2067. #define VHA_CR_SLC_STATUS1_BUS0_OUTSTANDING_WRITES_CLRMSK (IMG_UINT64_C(0XFFFFFFF000FFFFFF))
  2068. #define VHA_CR_SLC_STATUS1_BUS1_OUTSTANDING_READS_SHIFT (12U)
  2069. #define VHA_CR_SLC_STATUS1_BUS1_OUTSTANDING_READS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF000FFF))
  2070. #define VHA_CR_SLC_STATUS1_BUS0_OUTSTANDING_READS_SHIFT (0U)
  2071. #define VHA_CR_SLC_STATUS1_BUS0_OUTSTANDING_READS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF000))
  2072. /*
  2073. Register VHA_CR_SLC_STATUS2
  2074. */
  2075. #define VHA_CR_SLC_STATUS2 (0x7098U)
  2076. #define VHA_CR_SLC_STATUS2_MASKFULL (IMG_UINT64_C(0x0000FFFFFFFFFFFF))
  2077. #define VHA_CR_SLC_STATUS2_BUS3_OUTSTANDING_WRITES_SHIFT (36U)
  2078. #define VHA_CR_SLC_STATUS2_BUS3_OUTSTANDING_WRITES_CLRMSK (IMG_UINT64_C(0XFFFF000FFFFFFFFF))
  2079. #define VHA_CR_SLC_STATUS2_BUS2_OUTSTANDING_WRITES_SHIFT (24U)
  2080. #define VHA_CR_SLC_STATUS2_BUS2_OUTSTANDING_WRITES_CLRMSK (IMG_UINT64_C(0XFFFFFFF000FFFFFF))
  2081. #define VHA_CR_SLC_STATUS2_BUS3_OUTSTANDING_READS_SHIFT (12U)
  2082. #define VHA_CR_SLC_STATUS2_BUS3_OUTSTANDING_READS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF000FFF))
  2083. #define VHA_CR_SLC_STATUS2_BUS2_OUTSTANDING_READS_SHIFT (0U)
  2084. #define VHA_CR_SLC_STATUS2_BUS2_OUTSTANDING_READS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF000))
  2085. /*
  2086. Register VHA_CR_SLC_IDLE
  2087. */
  2088. #define VHA_CR_SLC_IDLE (0x70A0U)
  2089. #define VHA_CR_SLC_IDLE_MASKFULL (IMG_UINT64_C(0x000000000000FFFF))
  2090. #define VHA_CR_SLC_IDLE_ACE_CONVERTERS_SHIFT (12U)
  2091. #define VHA_CR_SLC_IDLE_ACE_CONVERTERS_CLRMSK (0XFFFF0FFFU)
  2092. #define VHA_CR_SLC_IDLE_CACHE_BANKS_SHIFT (4U)
  2093. #define VHA_CR_SLC_IDLE_CACHE_BANKS_CLRMSK (0XFFFFF00FU)
  2094. #define VHA_CR_SLC_IDLE_MMU_SHIFT (3U)
  2095. #define VHA_CR_SLC_IDLE_MMU_CLRMSK (0XFFFFFFF7U)
  2096. #define VHA_CR_SLC_IDLE_MMU_EN (0X00000008U)
  2097. #define VHA_CR_SLC_IDLE_CCM_SHIFT (2U)
  2098. #define VHA_CR_SLC_IDLE_CCM_CLRMSK (0XFFFFFFFBU)
  2099. #define VHA_CR_SLC_IDLE_CCM_EN (0X00000004U)
  2100. #define VHA_CR_SLC_IDLE_RDI_SHIFT (1U)
  2101. #define VHA_CR_SLC_IDLE_RDI_CLRMSK (0XFFFFFFFDU)
  2102. #define VHA_CR_SLC_IDLE_RDI_EN (0X00000002U)
  2103. #define VHA_CR_SLC_IDLE_XBAR_SHIFT (0U)
  2104. #define VHA_CR_SLC_IDLE_XBAR_CLRMSK (0XFFFFFFFEU)
  2105. #define VHA_CR_SLC_IDLE_XBAR_EN (0X00000001U)
  2106. /*
  2107. Register VHA_CR_SLC_STATUS3
  2108. */
  2109. #define VHA_CR_SLC_STATUS3 (0x70A8U)
  2110. #define VHA_CR_SLC_STATUS3_MASKFULL (IMG_UINT64_C(0x0FFFFFFFFFFFFFFF))
  2111. #define VHA_CR_SLC_STATUS3_MAX_CRITICAL_QOS_READ_LATENCY_SHIFT (50U)
  2112. #define VHA_CR_SLC_STATUS3_MAX_CRITICAL_QOS_READ_LATENCY_CLRMSK (IMG_UINT64_C(0XF003FFFFFFFFFFFF))
  2113. #define VHA_CR_SLC_STATUS3_MAX_LOW_QOS_READ_LATENCY_SHIFT (40U)
  2114. #define VHA_CR_SLC_STATUS3_MAX_LOW_QOS_READ_LATENCY_CLRMSK (IMG_UINT64_C(0XFFFC00FFFFFFFFFF))
  2115. #define VHA_CR_SLC_STATUS3_AVG_CRITICAL_QOS_READ_LATENCY_SHIFT (30U)
  2116. #define VHA_CR_SLC_STATUS3_AVG_CRITICAL_QOS_READ_LATENCY_CLRMSK (IMG_UINT64_C(0XFFFFFF003FFFFFFF))
  2117. #define VHA_CR_SLC_STATUS3_AVG_LOW_QOS_READ_LATENCY_SHIFT (20U)
  2118. #define VHA_CR_SLC_STATUS3_AVG_LOW_QOS_READ_LATENCY_CLRMSK (IMG_UINT64_C(0XFFFFFFFFC00FFFFF))
  2119. #define VHA_CR_SLC_STATUS3_MIN_CRITICAL_QOS_READ_LATENCY_SHIFT (10U)
  2120. #define VHA_CR_SLC_STATUS3_MIN_CRITICAL_QOS_READ_LATENCY_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF003FF))
  2121. #define VHA_CR_SLC_STATUS3_MIN_LOW_QOS_READ_LATENCY_SHIFT (0U)
  2122. #define VHA_CR_SLC_STATUS3_MIN_LOW_QOS_READ_LATENCY_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFC00))
  2123. /*
  2124. Register VHA_CR_SLC_FAULT_STOP_STATUS
  2125. */
  2126. #define VHA_CR_SLC_FAULT_STOP_STATUS (0x70B0U)
  2127. #define VHA_CR_SLC_FAULT_STOP_STATUS_MASKFULL (IMG_UINT64_C(0x000000000001FFFF))
  2128. #define VHA_CR_SLC_FAULT_STOP_STATUS_BIF_SHIFT (0U)
  2129. #define VHA_CR_SLC_FAULT_STOP_STATUS_BIF_CLRMSK (0XFFFE0000U)
  2130. /*
  2131. Register VHA_CR_SLC_STATUS_DEBUG
  2132. */
  2133. #define VHA_CR_SLC_STATUS_DEBUG (0x70B8U)
  2134. #define VHA_CR_SLC_STATUS_DEBUG_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  2135. #define VHA_CR_SLC_STATUS_DEBUG_ERR_COH_REQ_SHIFT (16U)
  2136. #define VHA_CR_SLC_STATUS_DEBUG_ERR_COH_REQ_CLRMSK (0X0000FFFFU)
  2137. #define VHA_CR_SLC_STATUS_DEBUG_ERR_ADDR_ALIAS_SHIFT (0U)
  2138. #define VHA_CR_SLC_STATUS_DEBUG_ERR_ADDR_ALIAS_CLRMSK (0XFFFF0000U)
  2139. /*
  2140. Register VHA_CR_PERF_SLC
  2141. */
  2142. #define VHA_CR_PERF_SLC (0x70C0U)
  2143. #define VHA_CR_PERF_SLC_MASKFULL (IMG_UINT64_C(0x000000000FEFFEFF))
  2144. #define VHA_CR_PERF_SLC_EWO_REQ_RD_WORD_COUNTER_RESET_SHIFT (27U)
  2145. #define VHA_CR_PERF_SLC_EWO_REQ_RD_WORD_COUNTER_RESET_CLRMSK (IMG_UINT64_C(0XFFFFFFFFF7FFFFFF))
  2146. #define VHA_CR_PERF_SLC_EWO_REQ_RD_WORD_COUNTER_RESET_EN (IMG_UINT64_C(0X0000000008000000))
  2147. #define VHA_CR_PERF_SLC_EWO_REQ_RD_COUNTER_RESET_SHIFT (26U)
  2148. #define VHA_CR_PERF_SLC_EWO_REQ_RD_COUNTER_RESET_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFBFFFFFF))
  2149. #define VHA_CR_PERF_SLC_EWO_REQ_RD_COUNTER_RESET_EN (IMG_UINT64_C(0X0000000004000000))
  2150. #define VHA_CR_PERF_SLC_MMU_REQ_RD_WORD_COUNTER_RESET_SHIFT (25U)
  2151. #define VHA_CR_PERF_SLC_MMU_REQ_RD_WORD_COUNTER_RESET_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFDFFFFFF))
  2152. #define VHA_CR_PERF_SLC_MMU_REQ_RD_WORD_COUNTER_RESET_EN (IMG_UINT64_C(0X0000000002000000))
  2153. #define VHA_CR_PERF_SLC_MMU_REQ_RD_COUNTER_RESET_SHIFT (24U)
  2154. #define VHA_CR_PERF_SLC_MMU_REQ_RD_COUNTER_RESET_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFEFFFFFF))
  2155. #define VHA_CR_PERF_SLC_MMU_REQ_RD_COUNTER_RESET_EN (IMG_UINT64_C(0X0000000001000000))
  2156. #define VHA_CR_PERF_SLC_OPK_REQ_WR_WORD_COUNTER_RESET_SHIFT (23U)
  2157. #define VHA_CR_PERF_SLC_OPK_REQ_WR_WORD_COUNTER_RESET_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF7FFFFF))
  2158. #define VHA_CR_PERF_SLC_OPK_REQ_WR_WORD_COUNTER_RESET_EN (IMG_UINT64_C(0X0000000000800000))
  2159. #define VHA_CR_PERF_SLC_ABUF_REQ_RD_WORD_COUNTER_RESET_SHIFT (22U)
  2160. #define VHA_CR_PERF_SLC_ABUF_REQ_RD_WORD_COUNTER_RESET_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFBFFFFF))
  2161. #define VHA_CR_PERF_SLC_ABUF_REQ_RD_WORD_COUNTER_RESET_EN (IMG_UINT64_C(0X0000000000400000))
  2162. #define VHA_CR_PERF_SLC_CBUF_REQ_RD_WORD_COUNTER_RESET_SHIFT (21U)
  2163. #define VHA_CR_PERF_SLC_CBUF_REQ_RD_WORD_COUNTER_RESET_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFDFFFFF))
  2164. #define VHA_CR_PERF_SLC_CBUF_REQ_RD_WORD_COUNTER_RESET_EN (IMG_UINT64_C(0X0000000000200000))
  2165. #define VHA_CR_PERF_SLC_MMM_REQ_WR_WORD_COUNTER_RESET_SHIFT (19U)
  2166. #define VHA_CR_PERF_SLC_MMM_REQ_WR_WORD_COUNTER_RESET_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF7FFFF))
  2167. #define VHA_CR_PERF_SLC_MMM_REQ_WR_WORD_COUNTER_RESET_EN (IMG_UINT64_C(0X0000000000080000))
  2168. #define VHA_CR_PERF_SLC_MMM_REQ_RD_WORD_COUNTER_RESET_SHIFT (18U)
  2169. #define VHA_CR_PERF_SLC_MMM_REQ_RD_WORD_COUNTER_RESET_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFBFFFF))
  2170. #define VHA_CR_PERF_SLC_MMM_REQ_RD_WORD_COUNTER_RESET_EN (IMG_UINT64_C(0X0000000000040000))
  2171. #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_WORD_COUNTER_RESET_SHIFT (17U)
  2172. #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_WORD_COUNTER_RESET_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFDFFFF))
  2173. #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_WORD_COUNTER_RESET_EN (IMG_UINT64_C(0X0000000000020000))
  2174. #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_WORD_COUNTER_RESET_SHIFT (16U)
  2175. #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_WORD_COUNTER_RESET_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFEFFFF))
  2176. #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_WORD_COUNTER_RESET_EN (IMG_UINT64_C(0X0000000000010000))
  2177. #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_WORD_COUNTER_RESET_SHIFT (15U)
  2178. #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_WORD_COUNTER_RESET_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF7FFF))
  2179. #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_WORD_COUNTER_RESET_EN (IMG_UINT64_C(0X0000000000008000))
  2180. #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_WORD_COUNTER_RESET_SHIFT (14U)
  2181. #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_WORD_COUNTER_RESET_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFBFFF))
  2182. #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_WORD_COUNTER_RESET_EN (IMG_UINT64_C(0X0000000000004000))
  2183. #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_WORD_COUNTER_RESET_SHIFT (13U)
  2184. #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_WORD_COUNTER_RESET_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFDFFF))
  2185. #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_WORD_COUNTER_RESET_EN (IMG_UINT64_C(0X0000000000002000))
  2186. #define VHA_CR_PERF_SLC_CMD_REQ_RD_WORD_COUNTER_RESET_SHIFT (12U)
  2187. #define VHA_CR_PERF_SLC_CMD_REQ_RD_WORD_COUNTER_RESET_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFEFFF))
  2188. #define VHA_CR_PERF_SLC_CMD_REQ_RD_WORD_COUNTER_RESET_EN (IMG_UINT64_C(0X0000000000001000))
  2189. #define VHA_CR_PERF_SLC_OPK_REQ_WR_COUNTER_RESET_SHIFT (11U)
  2190. #define VHA_CR_PERF_SLC_OPK_REQ_WR_COUNTER_RESET_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF7FF))
  2191. #define VHA_CR_PERF_SLC_OPK_REQ_WR_COUNTER_RESET_EN (IMG_UINT64_C(0X0000000000000800))
  2192. #define VHA_CR_PERF_SLC_ABUF_REQ_RD_COUNTER_RESET_SHIFT (10U)
  2193. #define VHA_CR_PERF_SLC_ABUF_REQ_RD_COUNTER_RESET_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFBFF))
  2194. #define VHA_CR_PERF_SLC_ABUF_REQ_RD_COUNTER_RESET_EN (IMG_UINT64_C(0X0000000000000400))
  2195. #define VHA_CR_PERF_SLC_CBUF_REQ_RD_COUNTER_RESET_SHIFT (9U)
  2196. #define VHA_CR_PERF_SLC_CBUF_REQ_RD_COUNTER_RESET_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFDFF))
  2197. #define VHA_CR_PERF_SLC_CBUF_REQ_RD_COUNTER_RESET_EN (IMG_UINT64_C(0X0000000000000200))
  2198. #define VHA_CR_PERF_SLC_MMM_REQ_WR_COUNTER_RESET_SHIFT (7U)
  2199. #define VHA_CR_PERF_SLC_MMM_REQ_WR_COUNTER_RESET_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFF7F))
  2200. #define VHA_CR_PERF_SLC_MMM_REQ_WR_COUNTER_RESET_EN (IMG_UINT64_C(0X0000000000000080))
  2201. #define VHA_CR_PERF_SLC_MMM_REQ_RD_COUNTER_RESET_SHIFT (6U)
  2202. #define VHA_CR_PERF_SLC_MMM_REQ_RD_COUNTER_RESET_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFBF))
  2203. #define VHA_CR_PERF_SLC_MMM_REQ_RD_COUNTER_RESET_EN (IMG_UINT64_C(0X0000000000000040))
  2204. #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_COUNTER_RESET_SHIFT (5U)
  2205. #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_COUNTER_RESET_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFDF))
  2206. #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_COUNTER_RESET_EN (IMG_UINT64_C(0X0000000000000020))
  2207. #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_COUNTER_RESET_SHIFT (4U)
  2208. #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_COUNTER_RESET_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFEF))
  2209. #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_COUNTER_RESET_EN (IMG_UINT64_C(0X0000000000000010))
  2210. #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_COUNTER_RESET_SHIFT (3U)
  2211. #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_COUNTER_RESET_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF7))
  2212. #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_COUNTER_RESET_EN (IMG_UINT64_C(0X0000000000000008))
  2213. #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_COUNTER_RESET_SHIFT (2U)
  2214. #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_COUNTER_RESET_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFB))
  2215. #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_COUNTER_RESET_EN (IMG_UINT64_C(0X0000000000000004))
  2216. #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_COUNTER_RESET_SHIFT (1U)
  2217. #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_COUNTER_RESET_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFD))
  2218. #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_COUNTER_RESET_EN (IMG_UINT64_C(0X0000000000000002))
  2219. #define VHA_CR_PERF_SLC_CMD_REQ_RD_COUNTER_RESET_SHIFT (0U)
  2220. #define VHA_CR_PERF_SLC_CMD_REQ_RD_COUNTER_RESET_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  2221. #define VHA_CR_PERF_SLC_CMD_REQ_RD_COUNTER_RESET_EN (IMG_UINT64_C(0X0000000000000001))
  2222. /*
  2223. Register VHA_CR_PERF_SLC_REQ_COUNT
  2224. */
  2225. #define VHA_CR_PERF_SLC_REQ_COUNT (0x70C8U)
  2226. #define VHA_CR_PERF_SLC_REQ_COUNT_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  2227. #define VHA_CR_PERF_SLC_REQ_COUNT_ENABLE_SHIFT (0U)
  2228. #define VHA_CR_PERF_SLC_REQ_COUNT_ENABLE_CLRMSK (0XFFFFFFFEU)
  2229. #define VHA_CR_PERF_SLC_REQ_COUNT_ENABLE_EN (0X00000001U)
  2230. /*
  2231. Register VHA_CR_PERF_SLC_CMD_REQ_RD
  2232. */
  2233. #define VHA_CR_PERF_SLC_CMD_REQ_RD (0x70D0U)
  2234. #define VHA_CR_PERF_SLC_CMD_REQ_RD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  2235. #define VHA_CR_PERF_SLC_CMD_REQ_RD_COUNTER_SHIFT (0U)
  2236. #define VHA_CR_PERF_SLC_CMD_REQ_RD_COUNTER_CLRMSK (00000000U)
  2237. /*
  2238. Register VHA_CR_PERF_SLC_CMD_BCK_REQ_WR
  2239. */
  2240. #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR (0x70D8U)
  2241. #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  2242. #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_COUNTER_SHIFT (0U)
  2243. #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_COUNTER_CLRMSK (00000000U)
  2244. /*
  2245. Register VHA_CR_PERF_SLC_CMD_CRC_REQ_WR
  2246. */
  2247. #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR (0x70E0U)
  2248. #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  2249. #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_COUNTER_SHIFT (0U)
  2250. #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_COUNTER_CLRMSK (00000000U)
  2251. /*
  2252. Register VHA_CR_PERF_SLC_CMD_DBG_REQ_WR
  2253. */
  2254. #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR (0x70E8U)
  2255. #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  2256. #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_COUNTER_SHIFT (0U)
  2257. #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_COUNTER_CLRMSK (00000000U)
  2258. /*
  2259. Register VHA_CR_PERF_SLC_CMD_REQ_FENCE
  2260. */
  2261. #define VHA_CR_PERF_SLC_CMD_REQ_FENCE (0x70F0U)
  2262. #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  2263. #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_COUNTER_SHIFT (0U)
  2264. #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_COUNTER_CLRMSK (00000000U)
  2265. /*
  2266. Register VHA_CR_PERF_SLC_IBUF_REQ0_RD
  2267. */
  2268. #define VHA_CR_PERF_SLC_IBUF_REQ0_RD (0x70F8U)
  2269. #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  2270. #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_COUNTER_SHIFT (0U)
  2271. #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_COUNTER_CLRMSK (00000000U)
  2272. /*
  2273. Register VHA_CR_PERF_SLC_MMM_REQ_RD
  2274. */
  2275. #define VHA_CR_PERF_SLC_MMM_REQ_RD (0x7100U)
  2276. #define VHA_CR_PERF_SLC_MMM_REQ_RD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  2277. #define VHA_CR_PERF_SLC_MMM_REQ_RD_COUNTER_SHIFT (0U)
  2278. #define VHA_CR_PERF_SLC_MMM_REQ_RD_COUNTER_CLRMSK (00000000U)
  2279. /*
  2280. Register VHA_CR_PERF_SLC_MMM_REQ_WR
  2281. */
  2282. #define VHA_CR_PERF_SLC_MMM_REQ_WR (0x7108U)
  2283. #define VHA_CR_PERF_SLC_MMM_REQ_WR_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  2284. #define VHA_CR_PERF_SLC_MMM_REQ_WR_COUNTER_SHIFT (0U)
  2285. #define VHA_CR_PERF_SLC_MMM_REQ_WR_COUNTER_CLRMSK (00000000U)
  2286. /*
  2287. Register VHA_CR_PERF_SLC_CBUF_REQ_RD
  2288. */
  2289. #define VHA_CR_PERF_SLC_CBUF_REQ_RD (0x7110U)
  2290. #define VHA_CR_PERF_SLC_CBUF_REQ_RD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  2291. #define VHA_CR_PERF_SLC_CBUF_REQ_RD_COUNTER_SHIFT (0U)
  2292. #define VHA_CR_PERF_SLC_CBUF_REQ_RD_COUNTER_CLRMSK (00000000U)
  2293. /*
  2294. Register VHA_CR_PERF_SLC_ABUF_REQ_RD
  2295. */
  2296. #define VHA_CR_PERF_SLC_ABUF_REQ_RD (0x7118U)
  2297. #define VHA_CR_PERF_SLC_ABUF_REQ_RD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  2298. #define VHA_CR_PERF_SLC_ABUF_REQ_RD_COUNTER_SHIFT (0U)
  2299. #define VHA_CR_PERF_SLC_ABUF_REQ_RD_COUNTER_CLRMSK (00000000U)
  2300. /*
  2301. Register VHA_CR_PERF_SLC_OPK_REQ_WR
  2302. */
  2303. #define VHA_CR_PERF_SLC_OPK_REQ_WR (0x7120U)
  2304. #define VHA_CR_PERF_SLC_OPK_REQ_WR_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  2305. #define VHA_CR_PERF_SLC_OPK_REQ_WR_COUNTER_SHIFT (0U)
  2306. #define VHA_CR_PERF_SLC_OPK_REQ_WR_COUNTER_CLRMSK (00000000U)
  2307. /*
  2308. Register VHA_CR_PERF_SLC_CMD_REQ_RD_WORD
  2309. */
  2310. #define VHA_CR_PERF_SLC_CMD_REQ_RD_WORD (0x7128U)
  2311. #define VHA_CR_PERF_SLC_CMD_REQ_RD_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  2312. #define VHA_CR_PERF_SLC_CMD_REQ_RD_WORD_COUNTER_SHIFT (0U)
  2313. #define VHA_CR_PERF_SLC_CMD_REQ_RD_WORD_COUNTER_CLRMSK (00000000U)
  2314. /*
  2315. Register VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_WORD
  2316. */
  2317. #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_WORD (0x7130U)
  2318. #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  2319. #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_WORD_COUNTER_SHIFT (0U)
  2320. #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_WORD_COUNTER_CLRMSK (00000000U)
  2321. /*
  2322. Register VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_WORD
  2323. */
  2324. #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_WORD (0x7138U)
  2325. #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  2326. #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_WORD_COUNTER_SHIFT (0U)
  2327. #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_WORD_COUNTER_CLRMSK (00000000U)
  2328. /*
  2329. Register VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_WORD
  2330. */
  2331. #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_WORD (0x7140U)
  2332. #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  2333. #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_WORD_COUNTER_SHIFT (0U)
  2334. #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_WORD_COUNTER_CLRMSK (00000000U)
  2335. /*
  2336. Register VHA_CR_PERF_SLC_CMD_REQ_FENCE_WORD
  2337. */
  2338. #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_WORD (0x7148U)
  2339. #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  2340. #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_WORD_COUNTER_SHIFT (0U)
  2341. #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_WORD_COUNTER_CLRMSK (00000000U)
  2342. /*
  2343. Register VHA_CR_PERF_SLC_IBUF_REQ0_RD_WORD
  2344. */
  2345. #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_WORD (0x7150U)
  2346. #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  2347. #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_WORD_COUNTER_SHIFT (0U)
  2348. #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_WORD_COUNTER_CLRMSK (00000000U)
  2349. /*
  2350. Register VHA_CR_PERF_SLC_MMM_REQ_RD_WORD
  2351. */
  2352. #define VHA_CR_PERF_SLC_MMM_REQ_RD_WORD (0x7158U)
  2353. #define VHA_CR_PERF_SLC_MMM_REQ_RD_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  2354. #define VHA_CR_PERF_SLC_MMM_REQ_RD_WORD_COUNTER_SHIFT (0U)
  2355. #define VHA_CR_PERF_SLC_MMM_REQ_RD_WORD_COUNTER_CLRMSK (00000000U)
  2356. /*
  2357. Register VHA_CR_PERF_SLC_MMM_REQ_WR_WORD
  2358. */
  2359. #define VHA_CR_PERF_SLC_MMM_REQ_WR_WORD (0x7160U)
  2360. #define VHA_CR_PERF_SLC_MMM_REQ_WR_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  2361. #define VHA_CR_PERF_SLC_MMM_REQ_WR_WORD_COUNTER_SHIFT (0U)
  2362. #define VHA_CR_PERF_SLC_MMM_REQ_WR_WORD_COUNTER_CLRMSK (00000000U)
  2363. /*
  2364. Register VHA_CR_PERF_SLC_CBUF_REQ_RD_WORD
  2365. */
  2366. #define VHA_CR_PERF_SLC_CBUF_REQ_RD_WORD (0x7168U)
  2367. #define VHA_CR_PERF_SLC_CBUF_REQ_RD_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  2368. #define VHA_CR_PERF_SLC_CBUF_REQ_RD_WORD_COUNTER_SHIFT (0U)
  2369. #define VHA_CR_PERF_SLC_CBUF_REQ_RD_WORD_COUNTER_CLRMSK (00000000U)
  2370. /*
  2371. Register VHA_CR_PERF_SLC_ABUF_REQ_RD_WORD
  2372. */
  2373. #define VHA_CR_PERF_SLC_ABUF_REQ_RD_WORD (0x7170U)
  2374. #define VHA_CR_PERF_SLC_ABUF_REQ_RD_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  2375. #define VHA_CR_PERF_SLC_ABUF_REQ_RD_WORD_COUNTER_SHIFT (0U)
  2376. #define VHA_CR_PERF_SLC_ABUF_REQ_RD_WORD_COUNTER_CLRMSK (00000000U)
  2377. /*
  2378. Register VHA_CR_PERF_SLC_OPK_REQ_WR_WORD
  2379. */
  2380. #define VHA_CR_PERF_SLC_OPK_REQ_WR_WORD (0x7178U)
  2381. #define VHA_CR_PERF_SLC_OPK_REQ_WR_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  2382. #define VHA_CR_PERF_SLC_OPK_REQ_WR_WORD_COUNTER_SHIFT (0U)
  2383. #define VHA_CR_PERF_SLC_OPK_REQ_WR_WORD_COUNTER_CLRMSK (00000000U)
  2384. /*
  2385. Register VHA_CR_PERF_SLC_MMU_REQ_RD
  2386. */
  2387. #define VHA_CR_PERF_SLC_MMU_REQ_RD (0x7180U)
  2388. #define VHA_CR_PERF_SLC_MMU_REQ_RD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  2389. #define VHA_CR_PERF_SLC_MMU_REQ_RD_COUNTER_SHIFT (0U)
  2390. #define VHA_CR_PERF_SLC_MMU_REQ_RD_COUNTER_CLRMSK (00000000U)
  2391. /*
  2392. Register VHA_CR_PERF_SLC_MMU_REQ_RD_WORD
  2393. */
  2394. #define VHA_CR_PERF_SLC_MMU_REQ_RD_WORD (0x7188U)
  2395. #define VHA_CR_PERF_SLC_MMU_REQ_RD_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  2396. #define VHA_CR_PERF_SLC_MMU_REQ_RD_WORD_COUNTER_SHIFT (0U)
  2397. #define VHA_CR_PERF_SLC_MMU_REQ_RD_WORD_COUNTER_CLRMSK (00000000U)
  2398. /*
  2399. Register VHA_CR_PERF_SLC_EWO_REQ_RD
  2400. */
  2401. #define VHA_CR_PERF_SLC_EWO_REQ_RD (0x7190U)
  2402. #define VHA_CR_PERF_SLC_EWO_REQ_RD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  2403. #define VHA_CR_PERF_SLC_EWO_REQ_RD_COUNTER_SHIFT (0U)
  2404. #define VHA_CR_PERF_SLC_EWO_REQ_RD_COUNTER_CLRMSK (00000000U)
  2405. /*
  2406. Register VHA_CR_PERF_SLC_EWO_REQ_RD_WORD
  2407. */
  2408. #define VHA_CR_PERF_SLC_EWO_REQ_RD_WORD (0x7198U)
  2409. #define VHA_CR_PERF_SLC_EWO_REQ_RD_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  2410. #define VHA_CR_PERF_SLC_EWO_REQ_RD_WORD_COUNTER_SHIFT (0U)
  2411. #define VHA_CR_PERF_SLC_EWO_REQ_RD_WORD_COUNTER_CLRMSK (00000000U)
  2412. /*
  2413. Register VHA_CR_MMU_PAGE_SIZE_RANGE_ONE
  2414. */
  2415. #define VHA_CR_MMU_PAGE_SIZE_RANGE_ONE (0x7468U)
  2416. #define VHA_CR_MMU_PAGE_SIZE_RANGE_ONE_MASKFULL (IMG_UINT64_C(0x000001FFFFFFFFFF))
  2417. #define VHA_CR_MMU_PAGE_SIZE_RANGE_ONE_PAGE_SIZE_SHIFT (38U)
  2418. #define VHA_CR_MMU_PAGE_SIZE_RANGE_ONE_PAGE_SIZE_CLRMSK (IMG_UINT64_C(0XFFFFFE3FFFFFFFFF))
  2419. #define VHA_CR_MMU_PAGE_SIZE_RANGE_ONE_END_ADDR_SHIFT (19U)
  2420. #define VHA_CR_MMU_PAGE_SIZE_RANGE_ONE_END_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFFC00007FFFF))
  2421. #define VHA_CR_MMU_PAGE_SIZE_RANGE_ONE_END_ADDR_ALIGNSHIFT (21U)
  2422. #define VHA_CR_MMU_PAGE_SIZE_RANGE_ONE_END_ADDR_ALIGNSIZE (2097152U)
  2423. #define VHA_CR_MMU_PAGE_SIZE_RANGE_ONE_BASE_ADDR_SHIFT (0U)
  2424. #define VHA_CR_MMU_PAGE_SIZE_RANGE_ONE_BASE_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF80000))
  2425. #define VHA_CR_MMU_PAGE_SIZE_RANGE_ONE_BASE_ADDR_ALIGNSHIFT (21U)
  2426. #define VHA_CR_MMU_PAGE_SIZE_RANGE_ONE_BASE_ADDR_ALIGNSIZE (2097152U)
  2427. /*
  2428. Register VHA_CR_MMU_PAGE_SIZE_RANGE_TWO
  2429. */
  2430. #define VHA_CR_MMU_PAGE_SIZE_RANGE_TWO (0x7470U)
  2431. #define VHA_CR_MMU_PAGE_SIZE_RANGE_TWO_MASKFULL (IMG_UINT64_C(0x000001FFFFFFFFFF))
  2432. #define VHA_CR_MMU_PAGE_SIZE_RANGE_TWO_PAGE_SIZE_SHIFT (38U)
  2433. #define VHA_CR_MMU_PAGE_SIZE_RANGE_TWO_PAGE_SIZE_CLRMSK (IMG_UINT64_C(0XFFFFFE3FFFFFFFFF))
  2434. #define VHA_CR_MMU_PAGE_SIZE_RANGE_TWO_END_ADDR_SHIFT (19U)
  2435. #define VHA_CR_MMU_PAGE_SIZE_RANGE_TWO_END_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFFC00007FFFF))
  2436. #define VHA_CR_MMU_PAGE_SIZE_RANGE_TWO_END_ADDR_ALIGNSHIFT (21U)
  2437. #define VHA_CR_MMU_PAGE_SIZE_RANGE_TWO_END_ADDR_ALIGNSIZE (2097152U)
  2438. #define VHA_CR_MMU_PAGE_SIZE_RANGE_TWO_BASE_ADDR_SHIFT (0U)
  2439. #define VHA_CR_MMU_PAGE_SIZE_RANGE_TWO_BASE_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF80000))
  2440. #define VHA_CR_MMU_PAGE_SIZE_RANGE_TWO_BASE_ADDR_ALIGNSHIFT (21U)
  2441. #define VHA_CR_MMU_PAGE_SIZE_RANGE_TWO_BASE_ADDR_ALIGNSIZE (2097152U)
  2442. /*
  2443. Register VHA_CR_MMU_PAGE_SIZE_RANGE_THREE
  2444. */
  2445. #define VHA_CR_MMU_PAGE_SIZE_RANGE_THREE (0x7478U)
  2446. #define VHA_CR_MMU_PAGE_SIZE_RANGE_THREE_MASKFULL (IMG_UINT64_C(0x000001FFFFFFFFFF))
  2447. #define VHA_CR_MMU_PAGE_SIZE_RANGE_THREE_PAGE_SIZE_SHIFT (38U)
  2448. #define VHA_CR_MMU_PAGE_SIZE_RANGE_THREE_PAGE_SIZE_CLRMSK (IMG_UINT64_C(0XFFFFFE3FFFFFFFFF))
  2449. #define VHA_CR_MMU_PAGE_SIZE_RANGE_THREE_END_ADDR_SHIFT (19U)
  2450. #define VHA_CR_MMU_PAGE_SIZE_RANGE_THREE_END_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFFC00007FFFF))
  2451. #define VHA_CR_MMU_PAGE_SIZE_RANGE_THREE_END_ADDR_ALIGNSHIFT (21U)
  2452. #define VHA_CR_MMU_PAGE_SIZE_RANGE_THREE_END_ADDR_ALIGNSIZE (2097152U)
  2453. #define VHA_CR_MMU_PAGE_SIZE_RANGE_THREE_BASE_ADDR_SHIFT (0U)
  2454. #define VHA_CR_MMU_PAGE_SIZE_RANGE_THREE_BASE_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF80000))
  2455. #define VHA_CR_MMU_PAGE_SIZE_RANGE_THREE_BASE_ADDR_ALIGNSHIFT (21U)
  2456. #define VHA_CR_MMU_PAGE_SIZE_RANGE_THREE_BASE_ADDR_ALIGNSIZE (2097152U)
  2457. /*
  2458. Register VHA_CR_MMU_PAGE_SIZE_RANGE_FOUR
  2459. */
  2460. #define VHA_CR_MMU_PAGE_SIZE_RANGE_FOUR (0x7480U)
  2461. #define VHA_CR_MMU_PAGE_SIZE_RANGE_FOUR_MASKFULL (IMG_UINT64_C(0x000001FFFFFFFFFF))
  2462. #define VHA_CR_MMU_PAGE_SIZE_RANGE_FOUR_PAGE_SIZE_SHIFT (38U)
  2463. #define VHA_CR_MMU_PAGE_SIZE_RANGE_FOUR_PAGE_SIZE_CLRMSK (IMG_UINT64_C(0XFFFFFE3FFFFFFFFF))
  2464. #define VHA_CR_MMU_PAGE_SIZE_RANGE_FOUR_END_ADDR_SHIFT (19U)
  2465. #define VHA_CR_MMU_PAGE_SIZE_RANGE_FOUR_END_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFFC00007FFFF))
  2466. #define VHA_CR_MMU_PAGE_SIZE_RANGE_FOUR_END_ADDR_ALIGNSHIFT (21U)
  2467. #define VHA_CR_MMU_PAGE_SIZE_RANGE_FOUR_END_ADDR_ALIGNSIZE (2097152U)
  2468. #define VHA_CR_MMU_PAGE_SIZE_RANGE_FOUR_BASE_ADDR_SHIFT (0U)
  2469. #define VHA_CR_MMU_PAGE_SIZE_RANGE_FOUR_BASE_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF80000))
  2470. #define VHA_CR_MMU_PAGE_SIZE_RANGE_FOUR_BASE_ADDR_ALIGNSHIFT (21U)
  2471. #define VHA_CR_MMU_PAGE_SIZE_RANGE_FOUR_BASE_ADDR_ALIGNSIZE (2097152U)
  2472. #define VHA_CR_SLC_CTRL_ENUM_HASH_MODE_MASK (0x00000003U)
  2473. /*
  2474. Reserved value */
  2475. #define VHA_CR_SLC_CTRL_ENUM_HASH_MODE_RESERVED (0x00000000U)
  2476. /*
  2477. Addresses interleaved between Cache Bank using a combined Set & Bank hash of the upper address bits */
  2478. #define VHA_CR_SLC_CTRL_ENUM_HASH_MODE_PVR_V3_HASHING (0x00000001U)
  2479. /*
  2480. Addresses are interleaved between Cache Banks on a Cacheline boundary */
  2481. #define VHA_CR_SLC_CTRL_ENUM_HASH_MODE_LINEAR (0x00000002U)
  2482. /*
  2483. Addresses interleaved between Cache Banks using an XOR hash of the address bits below the 4KB page granularity */
  2484. #define VHA_CR_SLC_CTRL_ENUM_HASH_MODE_IN_PAGE_HASH (0x00000003U)
  2485. /*
  2486. Register VHA_CR_SLC_CTRL
  2487. */
  2488. #define VHA_CR_SLC_CTRL (0x7488U)
  2489. #define VHA_CR_SLC_CTRL_MASKFULL (IMG_UINT64_C(0x000000000001FFF3))
  2490. #define VHA_CR_SLC_CTRL_RESERVED_SHIFT (7U)
  2491. #define VHA_CR_SLC_CTRL_RESERVED_CLRMSK (0XFFFE007FU)
  2492. #define VHA_CR_SLC_CTRL_MAX_FENCES_SHIFT (4U)
  2493. #define VHA_CR_SLC_CTRL_MAX_FENCES_CLRMSK (0XFFFFFF8FU)
  2494. #define VHA_CR_SLC_CTRL_HASH_MODE_SHIFT (0U)
  2495. #define VHA_CR_SLC_CTRL_HASH_MODE_CLRMSK (0XFFFFFFFCU)
  2496. #define VHA_CR_SLC_CTRL_HASH_MODE_RESERVED (00000000U)
  2497. #define VHA_CR_SLC_CTRL_HASH_MODE_PVR_V3_HASHING (0X00000001U)
  2498. #define VHA_CR_SLC_CTRL_HASH_MODE_LINEAR (0X00000002U)
  2499. #define VHA_CR_SLC_CTRL_HASH_MODE_IN_PAGE_HASH (0X00000003U)
  2500. /*
  2501. Register VHA_CR_SLC_FAULT_STOP_CTRL
  2502. */
  2503. #define VHA_CR_SLC_FAULT_STOP_CTRL (0x7498U)
  2504. #define VHA_CR_SLC_FAULT_STOP_CTRL_MASKFULL (IMG_UINT64_C(0x000000000003FFFF))
  2505. #define VHA_CR_SLC_FAULT_STOP_CTRL_ALL_SHIFT (17U)
  2506. #define VHA_CR_SLC_FAULT_STOP_CTRL_ALL_CLRMSK (0XFFFDFFFFU)
  2507. #define VHA_CR_SLC_FAULT_STOP_CTRL_ALL_EN (0X00020000U)
  2508. #define VHA_CR_SLC_FAULT_STOP_CTRL_ENABLE_SHIFT (0U)
  2509. #define VHA_CR_SLC_FAULT_STOP_CTRL_ENABLE_CLRMSK (0XFFFE0000U)
  2510. /*
  2511. Register VHA_CR_MMU_OSID_CTXT_MAPPING0
  2512. */
  2513. #define VHA_CR_MMU_OSID_CTXT_MAPPING0 (0x7500U)
  2514. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_MASKFULL (IMG_UINT64_C(0x7777777777777777))
  2515. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_15_SHIFT (60U)
  2516. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_15_CLRMSK (IMG_UINT64_C(0X8FFFFFFFFFFFFFFF))
  2517. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_14_SHIFT (56U)
  2518. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_14_CLRMSK (IMG_UINT64_C(0XF8FFFFFFFFFFFFFF))
  2519. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_13_SHIFT (52U)
  2520. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_13_CLRMSK (IMG_UINT64_C(0XFF8FFFFFFFFFFFFF))
  2521. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_12_SHIFT (48U)
  2522. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_12_CLRMSK (IMG_UINT64_C(0XFFF8FFFFFFFFFFFF))
  2523. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_11_SHIFT (44U)
  2524. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_11_CLRMSK (IMG_UINT64_C(0XFFFF8FFFFFFFFFFF))
  2525. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_10_SHIFT (40U)
  2526. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_10_CLRMSK (IMG_UINT64_C(0XFFFFF8FFFFFFFFFF))
  2527. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_9_SHIFT (36U)
  2528. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_9_CLRMSK (IMG_UINT64_C(0XFFFFFF8FFFFFFFFF))
  2529. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_8_SHIFT (32U)
  2530. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_8_CLRMSK (IMG_UINT64_C(0XFFFFFFF8FFFFFFFF))
  2531. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_7_SHIFT (28U)
  2532. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_7_CLRMSK (IMG_UINT64_C(0XFFFFFFFF8FFFFFFF))
  2533. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_6_SHIFT (24U)
  2534. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_6_CLRMSK (IMG_UINT64_C(0XFFFFFFFFF8FFFFFF))
  2535. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_5_SHIFT (20U)
  2536. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_5_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF8FFFFF))
  2537. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_4_SHIFT (16U)
  2538. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_4_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF8FFFF))
  2539. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_3_SHIFT (12U)
  2540. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_3_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF8FFF))
  2541. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_2_SHIFT (8U)
  2542. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_2_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF8FF))
  2543. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_1_SHIFT (4U)
  2544. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFF8F))
  2545. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_0_SHIFT (0U)
  2546. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_0_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF8))
  2547. /*
  2548. Register VHA_CR_MMU_OSID_CTXT_MAPPING1
  2549. */
  2550. #define VHA_CR_MMU_OSID_CTXT_MAPPING1 (0x7508U)
  2551. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_MASKFULL (IMG_UINT64_C(0x7777777777777777))
  2552. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_31_SHIFT (60U)
  2553. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_31_CLRMSK (IMG_UINT64_C(0X8FFFFFFFFFFFFFFF))
  2554. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_30_SHIFT (56U)
  2555. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_30_CLRMSK (IMG_UINT64_C(0XF8FFFFFFFFFFFFFF))
  2556. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_29_SHIFT (52U)
  2557. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_29_CLRMSK (IMG_UINT64_C(0XFF8FFFFFFFFFFFFF))
  2558. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_28_SHIFT (48U)
  2559. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_28_CLRMSK (IMG_UINT64_C(0XFFF8FFFFFFFFFFFF))
  2560. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_27_SHIFT (44U)
  2561. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_27_CLRMSK (IMG_UINT64_C(0XFFFF8FFFFFFFFFFF))
  2562. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_26_SHIFT (40U)
  2563. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_26_CLRMSK (IMG_UINT64_C(0XFFFFF8FFFFFFFFFF))
  2564. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_25_SHIFT (36U)
  2565. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_25_CLRMSK (IMG_UINT64_C(0XFFFFFF8FFFFFFFFF))
  2566. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_24_SHIFT (32U)
  2567. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_24_CLRMSK (IMG_UINT64_C(0XFFFFFFF8FFFFFFFF))
  2568. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_23_SHIFT (28U)
  2569. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_23_CLRMSK (IMG_UINT64_C(0XFFFFFFFF8FFFFFFF))
  2570. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_22_SHIFT (24U)
  2571. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_22_CLRMSK (IMG_UINT64_C(0XFFFFFFFFF8FFFFFF))
  2572. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_21_SHIFT (20U)
  2573. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_21_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF8FFFFF))
  2574. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_20_SHIFT (16U)
  2575. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_20_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF8FFFF))
  2576. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_19_SHIFT (12U)
  2577. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_19_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF8FFF))
  2578. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_18_SHIFT (8U)
  2579. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_18_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF8FF))
  2580. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_17_SHIFT (4U)
  2581. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_17_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFF8F))
  2582. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_16_SHIFT (0U)
  2583. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_16_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF8))
  2584. /*
  2585. Register VHA_CR_ACE_QOS_CTRL
  2586. */
  2587. #define VHA_CR_ACE_QOS_CTRL (0x7580U)
  2588. #define VHA_CR_ACE_QOS_CTRL_MASKFULL (IMG_UINT64_C(0x000000000000FFFF))
  2589. #define VHA_CR_ACE_QOS_CTRL_CRITICAL_SHIFT (12U)
  2590. #define VHA_CR_ACE_QOS_CTRL_CRITICAL_CLRMSK (0XFFFF0FFFU)
  2591. #define VHA_CR_ACE_QOS_CTRL_HIGH_SHIFT (8U)
  2592. #define VHA_CR_ACE_QOS_CTRL_HIGH_CLRMSK (0XFFFFF0FFU)
  2593. #define VHA_CR_ACE_QOS_CTRL_MEDIUM_SHIFT (4U)
  2594. #define VHA_CR_ACE_QOS_CTRL_MEDIUM_CLRMSK (0XFFFFFF0FU)
  2595. #define VHA_CR_ACE_QOS_CTRL_LOW_SHIFT (0U)
  2596. #define VHA_CR_ACE_QOS_CTRL_LOW_CLRMSK (0XFFFFFFF0U)
  2597. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_ENUM_PRIORITIES_MASK (0x00000003U)
  2598. /*
  2599. Low */
  2600. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_ENUM_PRIORITIES_LOW (0x00000000U)
  2601. /*
  2602. Medium */
  2603. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_ENUM_PRIORITIES_MEDIUM (0x00000001U)
  2604. /*
  2605. High */
  2606. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_ENUM_PRIORITIES_HIGH (0x00000002U)
  2607. /*
  2608. Critical */
  2609. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_ENUM_PRIORITIES_CRITICAL (0x00000003U)
  2610. /*
  2611. Register VHA_CR_ACE_PRIORITY_MAPPING_CTRL
  2612. */
  2613. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL (0x7588U)
  2614. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MASKFULL (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
  2615. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMU_SHIFT (62U)
  2616. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMU_CLRMSK (IMG_UINT64_C(0X3FFFFFFFFFFFFFFF))
  2617. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMU_LOW (IMG_UINT64_C(0000000000000000))
  2618. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMU_MEDIUM (IMG_UINT64_C(0x4000000000000000))
  2619. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMU_HIGH (IMG_UINT64_C(0x8000000000000000))
  2620. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMU_CRITICAL (IMG_UINT64_C(0xc000000000000000))
  2621. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_RESERVED_SHIFT (32U)
  2622. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_RESERVED_CLRMSK (IMG_UINT64_C(0XC0000000FFFFFFFF))
  2623. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TRS_B_SHIFT (30U)
  2624. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TRS_B_CLRMSK (IMG_UINT64_C(0XFFFFFFFF3FFFFFFF))
  2625. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TRS_B_LOW (IMG_UINT64_C(0000000000000000))
  2626. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TRS_B_MEDIUM (IMG_UINT64_C(0x0000000040000000))
  2627. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TRS_B_HIGH (IMG_UINT64_C(0x0000000080000000))
  2628. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TRS_B_CRITICAL (IMG_UINT64_C(0x00000000c0000000))
  2629. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TRS_A_SHIFT (28U)
  2630. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TRS_A_CLRMSK (IMG_UINT64_C(0XFFFFFFFFCFFFFFFF))
  2631. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TRS_A_LOW (IMG_UINT64_C(0000000000000000))
  2632. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TRS_A_MEDIUM (IMG_UINT64_C(0x0000000010000000))
  2633. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TRS_A_HIGH (IMG_UINT64_C(0x0000000020000000))
  2634. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TRS_A_CRITICAL (IMG_UINT64_C(0x0000000030000000))
  2635. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_POOL_SHIFT (26U)
  2636. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_POOL_CLRMSK (IMG_UINT64_C(0XFFFFFFFFF3FFFFFF))
  2637. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_POOL_LOW (IMG_UINT64_C(0000000000000000))
  2638. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_POOL_MEDIUM (IMG_UINT64_C(0x0000000004000000))
  2639. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_POOL_HIGH (IMG_UINT64_C(0x0000000008000000))
  2640. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_POOL_CRITICAL (IMG_UINT64_C(0x000000000c000000))
  2641. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMM_WR_SHIFT (24U)
  2642. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMM_WR_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFCFFFFFF))
  2643. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMM_WR_LOW (IMG_UINT64_C(0000000000000000))
  2644. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMM_WR_MEDIUM (IMG_UINT64_C(0x0000000001000000))
  2645. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMM_WR_HIGH (IMG_UINT64_C(0x0000000002000000))
  2646. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMM_WR_CRITICAL (IMG_UINT64_C(0x0000000003000000))
  2647. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMM_RD_SHIFT (22U)
  2648. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMM_RD_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF3FFFFF))
  2649. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMM_RD_LOW (IMG_UINT64_C(0000000000000000))
  2650. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMM_RD_MEDIUM (IMG_UINT64_C(0x0000000000400000))
  2651. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMM_RD_HIGH (IMG_UINT64_C(0x0000000000800000))
  2652. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMM_RD_CRITICAL (IMG_UINT64_C(0x0000000000c00000))
  2653. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_EWO_PSF_SHIFT (20U)
  2654. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_EWO_PSF_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFCFFFFF))
  2655. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_EWO_PSF_LOW (IMG_UINT64_C(0000000000000000))
  2656. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_EWO_PSF_MEDIUM (IMG_UINT64_C(0x0000000000100000))
  2657. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_EWO_PSF_HIGH (IMG_UINT64_C(0x0000000000200000))
  2658. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_EWO_PSF_CRITICAL (IMG_UINT64_C(0x0000000000300000))
  2659. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_EWO_SHIFT (18U)
  2660. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_EWO_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF3FFFF))
  2661. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_EWO_LOW (IMG_UINT64_C(0000000000000000))
  2662. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_EWO_MEDIUM (IMG_UINT64_C(0x0000000000040000))
  2663. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_EWO_HIGH (IMG_UINT64_C(0x0000000000080000))
  2664. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_EWO_CRITICAL (IMG_UINT64_C(0x00000000000c0000))
  2665. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_OUTPACK_SHIFT (16U)
  2666. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_OUTPACK_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFCFFFF))
  2667. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_OUTPACK_LOW (IMG_UINT64_C(0000000000000000))
  2668. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_OUTPACK_MEDIUM (IMG_UINT64_C(0x0000000000010000))
  2669. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_OUTPACK_HIGH (IMG_UINT64_C(0x0000000000020000))
  2670. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_OUTPACK_CRITICAL (IMG_UINT64_C(0x0000000000030000))
  2671. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_ABUF_SHIFT (14U)
  2672. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_ABUF_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF3FFF))
  2673. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_ABUF_LOW (IMG_UINT64_C(0000000000000000))
  2674. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_ABUF_MEDIUM (IMG_UINT64_C(0x0000000000004000))
  2675. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_ABUF_HIGH (IMG_UINT64_C(0x0000000000008000))
  2676. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_ABUF_CRITICAL (IMG_UINT64_C(0x000000000000c000))
  2677. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CBUF_SHIFT (12U)
  2678. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CBUF_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFCFFF))
  2679. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CBUF_LOW (IMG_UINT64_C(0000000000000000))
  2680. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CBUF_MEDIUM (IMG_UINT64_C(0x0000000000001000))
  2681. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CBUF_HIGH (IMG_UINT64_C(0x0000000000002000))
  2682. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CBUF_CRITICAL (IMG_UINT64_C(0x0000000000003000))
  2683. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_IBUF_0_SHIFT (10U)
  2684. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_IBUF_0_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF3FF))
  2685. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_IBUF_0_LOW (IMG_UINT64_C(0000000000000000))
  2686. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_IBUF_0_MEDIUM (IMG_UINT64_C(0x0000000000000400))
  2687. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_IBUF_0_HIGH (IMG_UINT64_C(0x0000000000000800))
  2688. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_IBUF_0_CRITICAL (IMG_UINT64_C(0x0000000000000c00))
  2689. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_4_SHIFT (8U)
  2690. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_4_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFCFF))
  2691. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_4_LOW (IMG_UINT64_C(0000000000000000))
  2692. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_4_MEDIUM (IMG_UINT64_C(0x0000000000000100))
  2693. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_4_HIGH (IMG_UINT64_C(0x0000000000000200))
  2694. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_4_CRITICAL (IMG_UINT64_C(0x0000000000000300))
  2695. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_3_SHIFT (6U)
  2696. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_3_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFF3F))
  2697. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_3_LOW (IMG_UINT64_C(0000000000000000))
  2698. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_3_MEDIUM (IMG_UINT64_C(0x0000000000000040))
  2699. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_3_HIGH (IMG_UINT64_C(0x0000000000000080))
  2700. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_3_CRITICAL (IMG_UINT64_C(0x00000000000000c0))
  2701. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_2_SHIFT (4U)
  2702. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_2_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFCF))
  2703. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_2_LOW (IMG_UINT64_C(0000000000000000))
  2704. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_2_MEDIUM (IMG_UINT64_C(0x0000000000000010))
  2705. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_2_HIGH (IMG_UINT64_C(0x0000000000000020))
  2706. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_2_CRITICAL (IMG_UINT64_C(0x0000000000000030))
  2707. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_1_SHIFT (2U)
  2708. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF3))
  2709. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_1_LOW (IMG_UINT64_C(0000000000000000))
  2710. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_1_MEDIUM (IMG_UINT64_C(0x0000000000000004))
  2711. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_1_HIGH (IMG_UINT64_C(0x0000000000000008))
  2712. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_1_CRITICAL (IMG_UINT64_C(0x000000000000000c))
  2713. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_0_SHIFT (0U)
  2714. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_0_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFC))
  2715. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_0_LOW (IMG_UINT64_C(0000000000000000))
  2716. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_0_MEDIUM (IMG_UINT64_C(0x0000000000000001))
  2717. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_0_HIGH (IMG_UINT64_C(0x0000000000000002))
  2718. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_0_CRITICAL (IMG_UINT64_C(0x0000000000000003))
  2719. #define VHA_CR_ACE_CTRL_ENUM_WR_CACHEABLE_MASK (0x0000000FU)
  2720. /*
  2721. Device Non-bufferable */
  2722. #define VHA_CR_ACE_CTRL_ENUM_WR_CACHEABLE_DEVICE_NON_BUFFERABLE (0x00000000U)
  2723. /*
  2724. Device Bufferable */
  2725. #define VHA_CR_ACE_CTRL_ENUM_WR_CACHEABLE_DEVICE_BUFFERABLE (0x00000001U)
  2726. /*
  2727. Normal Non-cacheable Non-bufferable */
  2728. #define VHA_CR_ACE_CTRL_ENUM_WR_CACHEABLE_NORMAL_NC_NON_BUFFERABLE (0x00000002U)
  2729. /*
  2730. Normal Non-cacheable Bufferable */
  2731. #define VHA_CR_ACE_CTRL_ENUM_WR_CACHEABLE_NORMAL_NC_BUFFERABLE (0x00000003U)
  2732. /*
  2733. Write-through No-allocate */
  2734. #define VHA_CR_ACE_CTRL_ENUM_WR_CACHEABLE_WRITE_THROUGH_NO_ALLOCATE (0x00000006U)
  2735. /*
  2736. Write-through Write-allocate */
  2737. #define VHA_CR_ACE_CTRL_ENUM_WR_CACHEABLE_WRITE_THROUGH_WRITE_ALLOCATE (0x0000000eU)
  2738. /*
  2739. Write-back No-allocate */
  2740. #define VHA_CR_ACE_CTRL_ENUM_WR_CACHEABLE_WRITE_BACK_NO_ALLOCATE (0x00000007U)
  2741. /*
  2742. Write-back Write-allocate */
  2743. #define VHA_CR_ACE_CTRL_ENUM_WR_CACHEABLE_WRITE_BACK_WRITE_ALLOCATE (0x0000000fU)
  2744. #define VHA_CR_ACE_CTRL_ENUM_RD_CACHEABLE_MASK (0x0000000FU)
  2745. /*
  2746. Device Non-bufferable */
  2747. #define VHA_CR_ACE_CTRL_ENUM_RD_CACHEABLE_DEVICE_NON_BUFFERABLE (0x00000000U)
  2748. /*
  2749. Device Bufferable */
  2750. #define VHA_CR_ACE_CTRL_ENUM_RD_CACHEABLE_DEVICE_BUFFERABLE (0x00000001U)
  2751. /*
  2752. Normal Non-cacheable Non-bufferable */
  2753. #define VHA_CR_ACE_CTRL_ENUM_RD_CACHEABLE_NORMAL_NC_NON_BUFFERABLE (0x00000002U)
  2754. /*
  2755. Normal Non-cacheable Bufferable */
  2756. #define VHA_CR_ACE_CTRL_ENUM_RD_CACHEABLE_NORMAL_NC_BUFFERABLE (0x00000003U)
  2757. /*
  2758. Write-through No-allocate */
  2759. #define VHA_CR_ACE_CTRL_ENUM_RD_CACHEABLE_WRITE_THROUGH_NO_ALLOCATE (0x0000000aU)
  2760. /*
  2761. Write-through Read-allocate */
  2762. #define VHA_CR_ACE_CTRL_ENUM_RD_CACHEABLE_WRITE_THROUGH_READ_ALLOCATE (0x0000000eU)
  2763. /*
  2764. Write-back No-allocate */
  2765. #define VHA_CR_ACE_CTRL_ENUM_RD_CACHEABLE_WRITE_BACK_NO_ALLOCATE (0x0000000bU)
  2766. /*
  2767. Write-back Read-allocate */
  2768. #define VHA_CR_ACE_CTRL_ENUM_RD_CACHEABLE_WRITE_BACK_READ_ALLOCATE (0x0000000fU)
  2769. /*
  2770. Non-Shareable */
  2771. #define VHA_CR_ACE_CTRL_ENUM_NCOH_DOMAIN_NON_SHAREABLE (0x00000000U)
  2772. /*
  2773. System */
  2774. #define VHA_CR_ACE_CTRL_ENUM_NCOH_DOMAIN_SYSTEM (0x00000001U)
  2775. /*
  2776. Inner-Shareable */
  2777. #define VHA_CR_ACE_CTRL_ENUM_COH_DOMAIN_INNER_SHAREABLE (0x00000000U)
  2778. /*
  2779. Outer-Shareable */
  2780. #define VHA_CR_ACE_CTRL_ENUM_COH_DOMAIN_OUTER_SHAREABLE (0x00000001U)
  2781. /*
  2782. Register VHA_CR_ACE_CTRL
  2783. */
  2784. #define VHA_CR_ACE_CTRL (0x7590U)
  2785. #define VHA_CR_ACE_CTRL_MASKFULL (IMG_UINT64_C(0x00000000007FCFFF))
  2786. #define VHA_CR_ACE_CTRL_CLB_AXQOS_SHIFT (19U)
  2787. #define VHA_CR_ACE_CTRL_CLB_AXQOS_CLRMSK (0XFF87FFFFU)
  2788. #define VHA_CR_ACE_CTRL_PM_MMU_AXCACHE_SHIFT (15U)
  2789. #define VHA_CR_ACE_CTRL_PM_MMU_AXCACHE_CLRMSK (0XFFF87FFFU)
  2790. #define VHA_CR_ACE_CTRL_ENABLE_NONSECURE_PROT_MATCH_SHIFT (14U)
  2791. #define VHA_CR_ACE_CTRL_ENABLE_NONSECURE_PROT_MATCH_CLRMSK (0XFFFFBFFFU)
  2792. #define VHA_CR_ACE_CTRL_ENABLE_NONSECURE_PROT_MATCH_EN (0X00004000U)
  2793. #define VHA_CR_ACE_CTRL_MMU_AWCACHE_SHIFT (8U)
  2794. #define VHA_CR_ACE_CTRL_MMU_AWCACHE_CLRMSK (0XFFFFF0FFU)
  2795. #define VHA_CR_ACE_CTRL_MMU_AWCACHE_DEVICE_NON_BUFFERABLE (00000000U)
  2796. #define VHA_CR_ACE_CTRL_MMU_AWCACHE_DEVICE_BUFFERABLE (0X00000100U)
  2797. #define VHA_CR_ACE_CTRL_MMU_AWCACHE_NORMAL_NC_NON_BUFFERABLE (0X00000200U)
  2798. #define VHA_CR_ACE_CTRL_MMU_AWCACHE_NORMAL_NC_BUFFERABLE (0X00000300U)
  2799. #define VHA_CR_ACE_CTRL_MMU_AWCACHE_WRITE_THROUGH_NO_ALLOCATE (0X00000600U)
  2800. #define VHA_CR_ACE_CTRL_MMU_AWCACHE_WRITE_THROUGH_WRITE_ALLOCATE (0X00000E00U)
  2801. #define VHA_CR_ACE_CTRL_MMU_AWCACHE_WRITE_BACK_NO_ALLOCATE (0X00000700U)
  2802. #define VHA_CR_ACE_CTRL_MMU_AWCACHE_WRITE_BACK_WRITE_ALLOCATE (0X00000F00U)
  2803. #define VHA_CR_ACE_CTRL_MMU_ARCACHE_SHIFT (4U)
  2804. #define VHA_CR_ACE_CTRL_MMU_ARCACHE_CLRMSK (0XFFFFFF0FU)
  2805. #define VHA_CR_ACE_CTRL_MMU_ARCACHE_DEVICE_NON_BUFFERABLE (00000000U)
  2806. #define VHA_CR_ACE_CTRL_MMU_ARCACHE_DEVICE_BUFFERABLE (0X00000010U)
  2807. #define VHA_CR_ACE_CTRL_MMU_ARCACHE_NORMAL_NC_NON_BUFFERABLE (0X00000020U)
  2808. #define VHA_CR_ACE_CTRL_MMU_ARCACHE_NORMAL_NC_BUFFERABLE (0X00000030U)
  2809. #define VHA_CR_ACE_CTRL_MMU_ARCACHE_WRITE_THROUGH_NO_ALLOCATE (0X000000A0U)
  2810. #define VHA_CR_ACE_CTRL_MMU_ARCACHE_WRITE_THROUGH_READ_ALLOCATE (0X000000E0U)
  2811. #define VHA_CR_ACE_CTRL_MMU_ARCACHE_WRITE_BACK_NO_ALLOCATE (0X000000B0U)
  2812. #define VHA_CR_ACE_CTRL_MMU_ARCACHE_WRITE_BACK_READ_ALLOCATE (0X000000F0U)
  2813. #define VHA_CR_ACE_CTRL_MMU_DOMAIN_SHIFT (2U)
  2814. #define VHA_CR_ACE_CTRL_MMU_DOMAIN_CLRMSK (0XFFFFFFF3U)
  2815. #define VHA_CR_ACE_CTRL_COH_DOMAIN_SHIFT (1U)
  2816. #define VHA_CR_ACE_CTRL_COH_DOMAIN_CLRMSK (0XFFFFFFFDU)
  2817. #define VHA_CR_ACE_CTRL_COH_DOMAIN_INNER_SHAREABLE (00000000U)
  2818. #define VHA_CR_ACE_CTRL_COH_DOMAIN_OUTER_SHAREABLE (0X00000002U)
  2819. #define VHA_CR_ACE_CTRL_NON_COH_DOMAIN_SHIFT (0U)
  2820. #define VHA_CR_ACE_CTRL_NON_COH_DOMAIN_CLRMSK (0XFFFFFFFEU)
  2821. #define VHA_CR_ACE_CTRL_NON_COH_DOMAIN_NON_SHAREABLE (00000000U)
  2822. #define VHA_CR_ACE_CTRL_NON_COH_DOMAIN_SYSTEM (0X00000001U)
  2823. /*
  2824. Register VHA_CR_ACE_STATUS
  2825. */
  2826. #define VHA_CR_ACE_STATUS (0x7598U)
  2827. #define VHA_CR_ACE_STATUS_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  2828. #define VHA_CR_ACE_STATUS_WR_BUS3_ERROR_SHIFT (28U)
  2829. #define VHA_CR_ACE_STATUS_WR_BUS3_ERROR_CLRMSK (0X0FFFFFFFU)
  2830. #define VHA_CR_ACE_STATUS_RD_BUS3_ERROR_SHIFT (24U)
  2831. #define VHA_CR_ACE_STATUS_RD_BUS3_ERROR_CLRMSK (0XF0FFFFFFU)
  2832. #define VHA_CR_ACE_STATUS_WR_BUS2_ERROR_SHIFT (20U)
  2833. #define VHA_CR_ACE_STATUS_WR_BUS2_ERROR_CLRMSK (0XFF0FFFFFU)
  2834. #define VHA_CR_ACE_STATUS_RD_BUS2_ERROR_SHIFT (16U)
  2835. #define VHA_CR_ACE_STATUS_RD_BUS2_ERROR_CLRMSK (0XFFF0FFFFU)
  2836. #define VHA_CR_ACE_STATUS_WR_BUS1_ERROR_SHIFT (12U)
  2837. #define VHA_CR_ACE_STATUS_WR_BUS1_ERROR_CLRMSK (0XFFFF0FFFU)
  2838. #define VHA_CR_ACE_STATUS_RD_BUS1_ERROR_SHIFT (8U)
  2839. #define VHA_CR_ACE_STATUS_RD_BUS1_ERROR_CLRMSK (0XFFFFF0FFU)
  2840. #define VHA_CR_ACE_STATUS_WR_BUS0_ERROR_SHIFT (4U)
  2841. #define VHA_CR_ACE_STATUS_WR_BUS0_ERROR_CLRMSK (0XFFFFFF0FU)
  2842. #define VHA_CR_ACE_STATUS_RD_BUS0_ERROR_SHIFT (0U)
  2843. #define VHA_CR_ACE_STATUS_RD_BUS0_ERROR_CLRMSK (0XFFFFFFF0U)
  2844. /*
  2845. Register VHA_CR_PWR_MAN_HYSTERESIS
  2846. */
  2847. #define VHA_CR_PWR_MAN_HYSTERESIS (0x7608U)
  2848. #define VHA_CR_PWR_MAN_HYSTERESIS_MASKFULL (IMG_UINT64_C(0x000000000000001F))
  2849. #define VHA_CR_PWR_MAN_HYSTERESIS_VALUE_SHIFT (0U)
  2850. #define VHA_CR_PWR_MAN_HYSTERESIS_VALUE_CLRMSK (0XFFFFFFE0U)
  2851. /*
  2852. Register VHA_CR_OS0_MMU_CTRL_INVAL
  2853. */
  2854. #define VHA_CR_OS0_MMU_CTRL_INVAL (0x76A8U)
  2855. #define VHA_CR_OS0_MMU_CTRL_INVAL_MASKFULL (IMG_UINT64_C(0x0000000000000FFF))
  2856. #define VHA_CR_OS0_MMU_CTRL_INVAL_ALL_CONTEXTS_SHIFT (11U)
  2857. #define VHA_CR_OS0_MMU_CTRL_INVAL_ALL_CONTEXTS_CLRMSK (0XFFFFF7FFU)
  2858. #define VHA_CR_OS0_MMU_CTRL_INVAL_ALL_CONTEXTS_EN (0X00000800U)
  2859. #define VHA_CR_OS0_MMU_CTRL_INVAL_CONTEXT_SHIFT (3U)
  2860. #define VHA_CR_OS0_MMU_CTRL_INVAL_CONTEXT_CLRMSK (0XFFFFF807U)
  2861. #define VHA_CR_OS0_MMU_CTRL_INVAL_PC_SHIFT (2U)
  2862. #define VHA_CR_OS0_MMU_CTRL_INVAL_PC_CLRMSK (0XFFFFFFFBU)
  2863. #define VHA_CR_OS0_MMU_CTRL_INVAL_PC_EN (0X00000004U)
  2864. #define VHA_CR_OS0_MMU_CTRL_INVAL_PD_SHIFT (1U)
  2865. #define VHA_CR_OS0_MMU_CTRL_INVAL_PD_CLRMSK (0XFFFFFFFDU)
  2866. #define VHA_CR_OS0_MMU_CTRL_INVAL_PD_EN (0X00000002U)
  2867. #define VHA_CR_OS0_MMU_CTRL_INVAL_PT_SHIFT (0U)
  2868. #define VHA_CR_OS0_MMU_CTRL_INVAL_PT_CLRMSK (0XFFFFFFFEU)
  2869. #define VHA_CR_OS0_MMU_CTRL_INVAL_PT_EN (0X00000001U)
  2870. /*
  2871. Register VHA_CR_OS0_MMU_CTRL_INVAL_STATUS
  2872. */
  2873. #define VHA_CR_OS0_MMU_CTRL_INVAL_STATUS (0x76B0U)
  2874. #define VHA_CR_OS0_MMU_CTRL_INVAL_STATUS_MASKFULL (IMG_UINT64_C(0x0000000080000001))
  2875. #define VHA_CR_OS0_MMU_CTRL_INVAL_STATUS_PARITY_SHIFT (31U)
  2876. #define VHA_CR_OS0_MMU_CTRL_INVAL_STATUS_PARITY_CLRMSK (0X7FFFFFFFU)
  2877. #define VHA_CR_OS0_MMU_CTRL_INVAL_STATUS_PARITY_EN (0X80000000U)
  2878. #define VHA_CR_OS0_MMU_CTRL_INVAL_STATUS_PENDING_SHIFT (0U)
  2879. #define VHA_CR_OS0_MMU_CTRL_INVAL_STATUS_PENDING_CLRMSK (0XFFFFFFFEU)
  2880. #define VHA_CR_OS0_MMU_CTRL_INVAL_STATUS_PENDING_EN (0X00000001U)
  2881. /*
  2882. Register VHA_CR_OS0_MMU_CBASE_MAPPING_CONTEXT
  2883. */
  2884. #define VHA_CR_OS0_MMU_CBASE_MAPPING_CONTEXT (0x76B8U)
  2885. #define VHA_CR_OS0_MMU_CBASE_MAPPING_CONTEXT_MASKFULL (IMG_UINT64_C(0x00000000000000FF))
  2886. #define VHA_CR_OS0_MMU_CBASE_MAPPING_CONTEXT_ID_SHIFT (0U)
  2887. #define VHA_CR_OS0_MMU_CBASE_MAPPING_CONTEXT_ID_CLRMSK (0XFFFFFF00U)
  2888. /*
  2889. Register VHA_CR_OS0_MMU_CBASE_MAPPING
  2890. */
  2891. #define VHA_CR_OS0_MMU_CBASE_MAPPING (0x76C0U)
  2892. #define VHA_CR_OS0_MMU_CBASE_MAPPING_MASKFULL (IMG_UINT64_C(0x000000001FFFFFFF))
  2893. #define VHA_CR_OS0_MMU_CBASE_MAPPING_INVALID_SHIFT (28U)
  2894. #define VHA_CR_OS0_MMU_CBASE_MAPPING_INVALID_CLRMSK (0XEFFFFFFFU)
  2895. #define VHA_CR_OS0_MMU_CBASE_MAPPING_INVALID_EN (0X10000000U)
  2896. #define VHA_CR_OS0_MMU_CBASE_MAPPING_BASE_ADDR_SHIFT (0U)
  2897. #define VHA_CR_OS0_MMU_CBASE_MAPPING_BASE_ADDR_CLRMSK (0XF0000000U)
  2898. #define VHA_CR_OS0_MMU_CBASE_MAPPING_BASE_ADDR_ALIGNSHIFT (12U)
  2899. #define VHA_CR_OS0_MMU_CBASE_MAPPING_BASE_ADDR_ALIGNSIZE (4096U)
  2900. /*
  2901. Register VHA_CR_OS0_MMU_CTRL_LEGACY
  2902. */
  2903. #define VHA_CR_OS0_MMU_CTRL_LEGACY (0x76E8U)
  2904. #define VHA_CR_OS0_MMU_CTRL_LEGACY_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  2905. #define VHA_CR_OS0_MMU_CTRL_LEGACY_RESERVED_SHIFT (0U)
  2906. #define VHA_CR_OS0_MMU_CTRL_LEGACY_RESERVED_CLRMSK (0XFFFFFFFEU)
  2907. #define VHA_CR_OS0_MMU_CTRL_LEGACY_RESERVED_EN (0X00000001U)
  2908. #define VHA_CR_ACE_PROT_CTRL_ENUM_PROT_MASK (0x00000007U)
  2909. /*
  2910. Unprivileged secure data access*/
  2911. #define VHA_CR_ACE_PROT_CTRL_ENUM_PROT_UNPRIVILEGED_SECURE_DATA (0x00000000U)
  2912. /*
  2913. Privileged secure data access*/
  2914. #define VHA_CR_ACE_PROT_CTRL_ENUM_PROT_PRIVILEGED_SECURE_DATA (0x00000001U)
  2915. /*
  2916. Unprivileged non-secure data access*/
  2917. #define VHA_CR_ACE_PROT_CTRL_ENUM_PROT_UNPRIVILEGED_NONSECURE_DATA (0x00000002U)
  2918. /*
  2919. Privileged non-secure data access*/
  2920. #define VHA_CR_ACE_PROT_CTRL_ENUM_PROT_PRIVILEGED_NONSECURE_DATA (0x00000003U)
  2921. /*
  2922. Unprivileged secure instruction access*/
  2923. #define VHA_CR_ACE_PROT_CTRL_ENUM_PROT_UNPRIVILEGED_SECURE_INSTRUCTION (0x00000004U)
  2924. /*
  2925. Privileged secure instruction access*/
  2926. #define VHA_CR_ACE_PROT_CTRL_ENUM_PROT_PRIVILEGED_SECURE_INSTRUCTION (0x00000005U)
  2927. /*
  2928. Unprivileged non-secure instruction access*/
  2929. #define VHA_CR_ACE_PROT_CTRL_ENUM_PROT_UNPRIVILEGED_NONSECURE_INSTRUCTION (0x00000006U)
  2930. /*
  2931. Privileged non-secure instruction access*/
  2932. #define VHA_CR_ACE_PROT_CTRL_ENUM_PROT_PRIVILEGED_NONSECURE_INSTRUCTION (0x00000007U)
  2933. /*
  2934. Register VHA_CR_ACE_PROT_CTRL
  2935. */
  2936. #define VHA_CR_ACE_PROT_CTRL (0x76F8U)
  2937. #define VHA_CR_ACE_PROT_CTRL_MASKFULL (IMG_UINT64_C(0x0707070707070707))
  2938. #define VHA_CR_ACE_PROT_CTRL_OSID7_SHIFT (56U)
  2939. #define VHA_CR_ACE_PROT_CTRL_OSID7_CLRMSK (IMG_UINT64_C(0XF8FFFFFFFFFFFFFF))
  2940. #define VHA_CR_ACE_PROT_CTRL_OSID7_UNPRIVILEGED_SECURE_DATA (IMG_UINT64_C(0000000000000000))
  2941. #define VHA_CR_ACE_PROT_CTRL_OSID7_PRIVILEGED_SECURE_DATA (IMG_UINT64_C(0x0100000000000000))
  2942. #define VHA_CR_ACE_PROT_CTRL_OSID7_UNPRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0200000000000000))
  2943. #define VHA_CR_ACE_PROT_CTRL_OSID7_PRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0300000000000000))
  2944. #define VHA_CR_ACE_PROT_CTRL_OSID7_UNPRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0400000000000000))
  2945. #define VHA_CR_ACE_PROT_CTRL_OSID7_PRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0500000000000000))
  2946. #define VHA_CR_ACE_PROT_CTRL_OSID7_UNPRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0600000000000000))
  2947. #define VHA_CR_ACE_PROT_CTRL_OSID7_PRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0700000000000000))
  2948. #define VHA_CR_ACE_PROT_CTRL_OSID6_SHIFT (48U)
  2949. #define VHA_CR_ACE_PROT_CTRL_OSID6_CLRMSK (IMG_UINT64_C(0XFFF8FFFFFFFFFFFF))
  2950. #define VHA_CR_ACE_PROT_CTRL_OSID6_UNPRIVILEGED_SECURE_DATA (IMG_UINT64_C(0000000000000000))
  2951. #define VHA_CR_ACE_PROT_CTRL_OSID6_PRIVILEGED_SECURE_DATA (IMG_UINT64_C(0x0001000000000000))
  2952. #define VHA_CR_ACE_PROT_CTRL_OSID6_UNPRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0002000000000000))
  2953. #define VHA_CR_ACE_PROT_CTRL_OSID6_PRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0003000000000000))
  2954. #define VHA_CR_ACE_PROT_CTRL_OSID6_UNPRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0004000000000000))
  2955. #define VHA_CR_ACE_PROT_CTRL_OSID6_PRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0005000000000000))
  2956. #define VHA_CR_ACE_PROT_CTRL_OSID6_UNPRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0006000000000000))
  2957. #define VHA_CR_ACE_PROT_CTRL_OSID6_PRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0007000000000000))
  2958. #define VHA_CR_ACE_PROT_CTRL_OSID5_SHIFT (40U)
  2959. #define VHA_CR_ACE_PROT_CTRL_OSID5_CLRMSK (IMG_UINT64_C(0XFFFFF8FFFFFFFFFF))
  2960. #define VHA_CR_ACE_PROT_CTRL_OSID5_UNPRIVILEGED_SECURE_DATA (IMG_UINT64_C(0000000000000000))
  2961. #define VHA_CR_ACE_PROT_CTRL_OSID5_PRIVILEGED_SECURE_DATA (IMG_UINT64_C(0x0000010000000000))
  2962. #define VHA_CR_ACE_PROT_CTRL_OSID5_UNPRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0000020000000000))
  2963. #define VHA_CR_ACE_PROT_CTRL_OSID5_PRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0000030000000000))
  2964. #define VHA_CR_ACE_PROT_CTRL_OSID5_UNPRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0000040000000000))
  2965. #define VHA_CR_ACE_PROT_CTRL_OSID5_PRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0000050000000000))
  2966. #define VHA_CR_ACE_PROT_CTRL_OSID5_UNPRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0000060000000000))
  2967. #define VHA_CR_ACE_PROT_CTRL_OSID5_PRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0000070000000000))
  2968. #define VHA_CR_ACE_PROT_CTRL_OSID4_SHIFT (32U)
  2969. #define VHA_CR_ACE_PROT_CTRL_OSID4_CLRMSK (IMG_UINT64_C(0XFFFFFFF8FFFFFFFF))
  2970. #define VHA_CR_ACE_PROT_CTRL_OSID4_UNPRIVILEGED_SECURE_DATA (IMG_UINT64_C(0000000000000000))
  2971. #define VHA_CR_ACE_PROT_CTRL_OSID4_PRIVILEGED_SECURE_DATA (IMG_UINT64_C(0x0000000100000000))
  2972. #define VHA_CR_ACE_PROT_CTRL_OSID4_UNPRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0000000200000000))
  2973. #define VHA_CR_ACE_PROT_CTRL_OSID4_PRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0000000300000000))
  2974. #define VHA_CR_ACE_PROT_CTRL_OSID4_UNPRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0000000400000000))
  2975. #define VHA_CR_ACE_PROT_CTRL_OSID4_PRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0000000500000000))
  2976. #define VHA_CR_ACE_PROT_CTRL_OSID4_UNPRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0000000600000000))
  2977. #define VHA_CR_ACE_PROT_CTRL_OSID4_PRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0000000700000000))
  2978. #define VHA_CR_ACE_PROT_CTRL_OSID3_SHIFT (24U)
  2979. #define VHA_CR_ACE_PROT_CTRL_OSID3_CLRMSK (IMG_UINT64_C(0XFFFFFFFFF8FFFFFF))
  2980. #define VHA_CR_ACE_PROT_CTRL_OSID3_UNPRIVILEGED_SECURE_DATA (IMG_UINT64_C(0000000000000000))
  2981. #define VHA_CR_ACE_PROT_CTRL_OSID3_PRIVILEGED_SECURE_DATA (IMG_UINT64_C(0x0000000001000000))
  2982. #define VHA_CR_ACE_PROT_CTRL_OSID3_UNPRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0000000002000000))
  2983. #define VHA_CR_ACE_PROT_CTRL_OSID3_PRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0000000003000000))
  2984. #define VHA_CR_ACE_PROT_CTRL_OSID3_UNPRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0000000004000000))
  2985. #define VHA_CR_ACE_PROT_CTRL_OSID3_PRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0000000005000000))
  2986. #define VHA_CR_ACE_PROT_CTRL_OSID3_UNPRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0000000006000000))
  2987. #define VHA_CR_ACE_PROT_CTRL_OSID3_PRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0000000007000000))
  2988. #define VHA_CR_ACE_PROT_CTRL_OSID2_SHIFT (16U)
  2989. #define VHA_CR_ACE_PROT_CTRL_OSID2_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF8FFFF))
  2990. #define VHA_CR_ACE_PROT_CTRL_OSID2_UNPRIVILEGED_SECURE_DATA (IMG_UINT64_C(0000000000000000))
  2991. #define VHA_CR_ACE_PROT_CTRL_OSID2_PRIVILEGED_SECURE_DATA (IMG_UINT64_C(0x0000000000010000))
  2992. #define VHA_CR_ACE_PROT_CTRL_OSID2_UNPRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0000000000020000))
  2993. #define VHA_CR_ACE_PROT_CTRL_OSID2_PRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0000000000030000))
  2994. #define VHA_CR_ACE_PROT_CTRL_OSID2_UNPRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0000000000040000))
  2995. #define VHA_CR_ACE_PROT_CTRL_OSID2_PRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0000000000050000))
  2996. #define VHA_CR_ACE_PROT_CTRL_OSID2_UNPRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0000000000060000))
  2997. #define VHA_CR_ACE_PROT_CTRL_OSID2_PRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0000000000070000))
  2998. #define VHA_CR_ACE_PROT_CTRL_OSID1_SHIFT (8U)
  2999. #define VHA_CR_ACE_PROT_CTRL_OSID1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF8FF))
  3000. #define VHA_CR_ACE_PROT_CTRL_OSID1_UNPRIVILEGED_SECURE_DATA (IMG_UINT64_C(0000000000000000))
  3001. #define VHA_CR_ACE_PROT_CTRL_OSID1_PRIVILEGED_SECURE_DATA (IMG_UINT64_C(0x0000000000000100))
  3002. #define VHA_CR_ACE_PROT_CTRL_OSID1_UNPRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0000000000000200))
  3003. #define VHA_CR_ACE_PROT_CTRL_OSID1_PRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0000000000000300))
  3004. #define VHA_CR_ACE_PROT_CTRL_OSID1_UNPRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0000000000000400))
  3005. #define VHA_CR_ACE_PROT_CTRL_OSID1_PRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0000000000000500))
  3006. #define VHA_CR_ACE_PROT_CTRL_OSID1_UNPRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0000000000000600))
  3007. #define VHA_CR_ACE_PROT_CTRL_OSID1_PRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0000000000000700))
  3008. #define VHA_CR_ACE_PROT_CTRL_OSID0_SHIFT (0U)
  3009. #define VHA_CR_ACE_PROT_CTRL_OSID0_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF8))
  3010. #define VHA_CR_ACE_PROT_CTRL_OSID0_UNPRIVILEGED_SECURE_DATA (IMG_UINT64_C(0000000000000000))
  3011. #define VHA_CR_ACE_PROT_CTRL_OSID0_PRIVILEGED_SECURE_DATA (IMG_UINT64_C(0x0000000000000001))
  3012. #define VHA_CR_ACE_PROT_CTRL_OSID0_UNPRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0000000000000002))
  3013. #define VHA_CR_ACE_PROT_CTRL_OSID0_PRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0000000000000003))
  3014. #define VHA_CR_ACE_PROT_CTRL_OSID0_UNPRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0000000000000004))
  3015. #define VHA_CR_ACE_PROT_CTRL_OSID0_PRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0000000000000005))
  3016. #define VHA_CR_ACE_PROT_CTRL_OSID0_UNPRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0000000000000006))
  3017. #define VHA_CR_ACE_PROT_CTRL_OSID0_PRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0000000000000007))
  3018. /*
  3019. Register VHA_CR_OS0_MMU_CTRL
  3020. */
  3021. #define VHA_CR_OS0_MMU_CTRL (0x7708U)
  3022. #define VHA_CR_OS0_MMU_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  3023. #define VHA_CR_OS0_MMU_CTRL_BYPASS_SHIFT (0U)
  3024. #define VHA_CR_OS0_MMU_CTRL_BYPASS_CLRMSK (0XFFFFFFFEU)
  3025. #define VHA_CR_OS0_MMU_CTRL_BYPASS_EN (0X00000001U)
  3026. /*
  3027. Register VHA_CR_OS1_MMU_CTRL
  3028. */
  3029. #define VHA_CR_OS1_MMU_CTRL (0x7710U)
  3030. #define VHA_CR_OS1_MMU_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  3031. #define VHA_CR_OS1_MMU_CTRL_BYPASS_SHIFT (0U)
  3032. #define VHA_CR_OS1_MMU_CTRL_BYPASS_CLRMSK (0XFFFFFFFEU)
  3033. #define VHA_CR_OS1_MMU_CTRL_BYPASS_EN (0X00000001U)
  3034. /*
  3035. Register VHA_CR_OS2_MMU_CTRL
  3036. */
  3037. #define VHA_CR_OS2_MMU_CTRL (0x7718U)
  3038. #define VHA_CR_OS2_MMU_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  3039. #define VHA_CR_OS2_MMU_CTRL_BYPASS_SHIFT (0U)
  3040. #define VHA_CR_OS2_MMU_CTRL_BYPASS_CLRMSK (0XFFFFFFFEU)
  3041. #define VHA_CR_OS2_MMU_CTRL_BYPASS_EN (0X00000001U)
  3042. /*
  3043. Register VHA_CR_CORE0_MMU_FAULT_STATUS1
  3044. */
  3045. #define VHA_CR_CORE0_MMU_FAULT_STATUS1 (0x7B00U)
  3046. #define VHA_CR_CORE0_MMU_FAULT_STATUS1_MASKFULL (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
  3047. #define VHA_CR_CORE0_MMU_FAULT_STATUS1_LEVEL_SHIFT (62U)
  3048. #define VHA_CR_CORE0_MMU_FAULT_STATUS1_LEVEL_CLRMSK (IMG_UINT64_C(0X3FFFFFFFFFFFFFFF))
  3049. #define VHA_CR_CORE0_MMU_FAULT_STATUS1_REQ_ID_SHIFT (56U)
  3050. #define VHA_CR_CORE0_MMU_FAULT_STATUS1_REQ_ID_CLRMSK (IMG_UINT64_C(0XC0FFFFFFFFFFFFFF))
  3051. #define VHA_CR_CORE0_MMU_FAULT_STATUS1_CONTEXT_SHIFT (48U)
  3052. #define VHA_CR_CORE0_MMU_FAULT_STATUS1_CONTEXT_CLRMSK (IMG_UINT64_C(0XFF00FFFFFFFFFFFF))
  3053. #define VHA_CR_CORE0_MMU_FAULT_STATUS1_ADDRESS_SHIFT (4U)
  3054. #define VHA_CR_CORE0_MMU_FAULT_STATUS1_ADDRESS_CLRMSK (IMG_UINT64_C(0XFFFF00000000000F))
  3055. #define VHA_CR_CORE0_MMU_FAULT_STATUS1_RNW_SHIFT (3U)
  3056. #define VHA_CR_CORE0_MMU_FAULT_STATUS1_RNW_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF7))
  3057. #define VHA_CR_CORE0_MMU_FAULT_STATUS1_RNW_EN (IMG_UINT64_C(0X0000000000000008))
  3058. #define VHA_CR_CORE0_MMU_FAULT_STATUS1_TYPE_SHIFT (1U)
  3059. #define VHA_CR_CORE0_MMU_FAULT_STATUS1_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF9))
  3060. #define VHA_CR_CORE0_MMU_FAULT_STATUS1_FAULT_SHIFT (0U)
  3061. #define VHA_CR_CORE0_MMU_FAULT_STATUS1_FAULT_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  3062. #define VHA_CR_CORE0_MMU_FAULT_STATUS1_FAULT_EN (IMG_UINT64_C(0X0000000000000001))
  3063. /*
  3064. Register VHA_CR_CORE0_MMU_FAULT_STATUS2
  3065. */
  3066. #define VHA_CR_CORE0_MMU_FAULT_STATUS2 (0x7B08U)
  3067. #define VHA_CR_CORE0_MMU_FAULT_STATUS2_MASKFULL (IMG_UINT64_C(0x000000003FFF07FF))
  3068. #define VHA_CR_CORE0_MMU_FAULT_STATUS2_WRITEBACK_SHIFT (29U)
  3069. #define VHA_CR_CORE0_MMU_FAULT_STATUS2_WRITEBACK_CLRMSK (0XDFFFFFFFU)
  3070. #define VHA_CR_CORE0_MMU_FAULT_STATUS2_WRITEBACK_EN (0X20000000U)
  3071. #define VHA_CR_CORE0_MMU_FAULT_STATUS2_CLEANUNIQUE_SHIFT (28U)
  3072. #define VHA_CR_CORE0_MMU_FAULT_STATUS2_CLEANUNIQUE_CLRMSK (0XEFFFFFFFU)
  3073. #define VHA_CR_CORE0_MMU_FAULT_STATUS2_CLEANUNIQUE_EN (0X10000000U)
  3074. #define VHA_CR_CORE0_MMU_FAULT_STATUS2_BANK_SHIFT (24U)
  3075. #define VHA_CR_CORE0_MMU_FAULT_STATUS2_BANK_CLRMSK (0XF0FFFFFFU)
  3076. #define VHA_CR_CORE0_MMU_FAULT_STATUS2_TLB_ENTRY_SHIFT (16U)
  3077. #define VHA_CR_CORE0_MMU_FAULT_STATUS2_TLB_ENTRY_CLRMSK (0XFF00FFFFU)
  3078. #define VHA_CR_CORE0_MMU_FAULT_STATUS2_FBM_FAULT_SHIFT (10U)
  3079. #define VHA_CR_CORE0_MMU_FAULT_STATUS2_FBM_FAULT_CLRMSK (0XFFFFFBFFU)
  3080. #define VHA_CR_CORE0_MMU_FAULT_STATUS2_FBM_FAULT_EN (0X00000400U)
  3081. #define VHA_CR_CORE0_MMU_FAULT_STATUS2_BIF_ID_SHIFT (0U)
  3082. #define VHA_CR_CORE0_MMU_FAULT_STATUS2_BIF_ID_CLRMSK (0XFFFFFC00U)
  3083. /*
  3084. Register VHA_CR_CORE1_MMU_FAULT_STATUS1
  3085. */
  3086. #define VHA_CR_CORE1_MMU_FAULT_STATUS1 (0x7B10U)
  3087. #define VHA_CR_CORE1_MMU_FAULT_STATUS1_MASKFULL (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
  3088. #define VHA_CR_CORE1_MMU_FAULT_STATUS1_LEVEL_SHIFT (62U)
  3089. #define VHA_CR_CORE1_MMU_FAULT_STATUS1_LEVEL_CLRMSK (IMG_UINT64_C(0X3FFFFFFFFFFFFFFF))
  3090. #define VHA_CR_CORE1_MMU_FAULT_STATUS1_REQ_ID_SHIFT (56U)
  3091. #define VHA_CR_CORE1_MMU_FAULT_STATUS1_REQ_ID_CLRMSK (IMG_UINT64_C(0XC0FFFFFFFFFFFFFF))
  3092. #define VHA_CR_CORE1_MMU_FAULT_STATUS1_CONTEXT_SHIFT (48U)
  3093. #define VHA_CR_CORE1_MMU_FAULT_STATUS1_CONTEXT_CLRMSK (IMG_UINT64_C(0XFF00FFFFFFFFFFFF))
  3094. #define VHA_CR_CORE1_MMU_FAULT_STATUS1_ADDRESS_SHIFT (4U)
  3095. #define VHA_CR_CORE1_MMU_FAULT_STATUS1_ADDRESS_CLRMSK (IMG_UINT64_C(0XFFFF00000000000F))
  3096. #define VHA_CR_CORE1_MMU_FAULT_STATUS1_RNW_SHIFT (3U)
  3097. #define VHA_CR_CORE1_MMU_FAULT_STATUS1_RNW_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF7))
  3098. #define VHA_CR_CORE1_MMU_FAULT_STATUS1_RNW_EN (IMG_UINT64_C(0X0000000000000008))
  3099. #define VHA_CR_CORE1_MMU_FAULT_STATUS1_TYPE_SHIFT (1U)
  3100. #define VHA_CR_CORE1_MMU_FAULT_STATUS1_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF9))
  3101. #define VHA_CR_CORE1_MMU_FAULT_STATUS1_FAULT_SHIFT (0U)
  3102. #define VHA_CR_CORE1_MMU_FAULT_STATUS1_FAULT_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  3103. #define VHA_CR_CORE1_MMU_FAULT_STATUS1_FAULT_EN (IMG_UINT64_C(0X0000000000000001))
  3104. /*
  3105. Register VHA_CR_CORE1_MMU_FAULT_STATUS2
  3106. */
  3107. #define VHA_CR_CORE1_MMU_FAULT_STATUS2 (0x7B18U)
  3108. #define VHA_CR_CORE1_MMU_FAULT_STATUS2_MASKFULL (IMG_UINT64_C(0x000000003FFF07FF))
  3109. #define VHA_CR_CORE1_MMU_FAULT_STATUS2_WRITEBACK_SHIFT (29U)
  3110. #define VHA_CR_CORE1_MMU_FAULT_STATUS2_WRITEBACK_CLRMSK (0XDFFFFFFFU)
  3111. #define VHA_CR_CORE1_MMU_FAULT_STATUS2_WRITEBACK_EN (0X20000000U)
  3112. #define VHA_CR_CORE1_MMU_FAULT_STATUS2_CLEANUNIQUE_SHIFT (28U)
  3113. #define VHA_CR_CORE1_MMU_FAULT_STATUS2_CLEANUNIQUE_CLRMSK (0XEFFFFFFFU)
  3114. #define VHA_CR_CORE1_MMU_FAULT_STATUS2_CLEANUNIQUE_EN (0X10000000U)
  3115. #define VHA_CR_CORE1_MMU_FAULT_STATUS2_BANK_SHIFT (24U)
  3116. #define VHA_CR_CORE1_MMU_FAULT_STATUS2_BANK_CLRMSK (0XF0FFFFFFU)
  3117. #define VHA_CR_CORE1_MMU_FAULT_STATUS2_TLB_ENTRY_SHIFT (16U)
  3118. #define VHA_CR_CORE1_MMU_FAULT_STATUS2_TLB_ENTRY_CLRMSK (0XFF00FFFFU)
  3119. #define VHA_CR_CORE1_MMU_FAULT_STATUS2_FBM_FAULT_SHIFT (10U)
  3120. #define VHA_CR_CORE1_MMU_FAULT_STATUS2_FBM_FAULT_CLRMSK (0XFFFFFBFFU)
  3121. #define VHA_CR_CORE1_MMU_FAULT_STATUS2_FBM_FAULT_EN (0X00000400U)
  3122. #define VHA_CR_CORE1_MMU_FAULT_STATUS2_BIF_ID_SHIFT (0U)
  3123. #define VHA_CR_CORE1_MMU_FAULT_STATUS2_BIF_ID_CLRMSK (0XFFFFFC00U)
  3124. /*
  3125. Register VHA_CR_CORE2_MMU_FAULT_STATUS1
  3126. */
  3127. #define VHA_CR_CORE2_MMU_FAULT_STATUS1 (0x7B20U)
  3128. #define VHA_CR_CORE2_MMU_FAULT_STATUS1_MASKFULL (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
  3129. #define VHA_CR_CORE2_MMU_FAULT_STATUS1_LEVEL_SHIFT (62U)
  3130. #define VHA_CR_CORE2_MMU_FAULT_STATUS1_LEVEL_CLRMSK (IMG_UINT64_C(0X3FFFFFFFFFFFFFFF))
  3131. #define VHA_CR_CORE2_MMU_FAULT_STATUS1_REQ_ID_SHIFT (56U)
  3132. #define VHA_CR_CORE2_MMU_FAULT_STATUS1_REQ_ID_CLRMSK (IMG_UINT64_C(0XC0FFFFFFFFFFFFFF))
  3133. #define VHA_CR_CORE2_MMU_FAULT_STATUS1_CONTEXT_SHIFT (48U)
  3134. #define VHA_CR_CORE2_MMU_FAULT_STATUS1_CONTEXT_CLRMSK (IMG_UINT64_C(0XFF00FFFFFFFFFFFF))
  3135. #define VHA_CR_CORE2_MMU_FAULT_STATUS1_ADDRESS_SHIFT (4U)
  3136. #define VHA_CR_CORE2_MMU_FAULT_STATUS1_ADDRESS_CLRMSK (IMG_UINT64_C(0XFFFF00000000000F))
  3137. #define VHA_CR_CORE2_MMU_FAULT_STATUS1_RNW_SHIFT (3U)
  3138. #define VHA_CR_CORE2_MMU_FAULT_STATUS1_RNW_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF7))
  3139. #define VHA_CR_CORE2_MMU_FAULT_STATUS1_RNW_EN (IMG_UINT64_C(0X0000000000000008))
  3140. #define VHA_CR_CORE2_MMU_FAULT_STATUS1_TYPE_SHIFT (1U)
  3141. #define VHA_CR_CORE2_MMU_FAULT_STATUS1_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF9))
  3142. #define VHA_CR_CORE2_MMU_FAULT_STATUS1_FAULT_SHIFT (0U)
  3143. #define VHA_CR_CORE2_MMU_FAULT_STATUS1_FAULT_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  3144. #define VHA_CR_CORE2_MMU_FAULT_STATUS1_FAULT_EN (IMG_UINT64_C(0X0000000000000001))
  3145. /*
  3146. Register VHA_CR_CORE2_MMU_FAULT_STATUS2
  3147. */
  3148. #define VHA_CR_CORE2_MMU_FAULT_STATUS2 (0x7B28U)
  3149. #define VHA_CR_CORE2_MMU_FAULT_STATUS2_MASKFULL (IMG_UINT64_C(0x000000003FFF07FF))
  3150. #define VHA_CR_CORE2_MMU_FAULT_STATUS2_WRITEBACK_SHIFT (29U)
  3151. #define VHA_CR_CORE2_MMU_FAULT_STATUS2_WRITEBACK_CLRMSK (0XDFFFFFFFU)
  3152. #define VHA_CR_CORE2_MMU_FAULT_STATUS2_WRITEBACK_EN (0X20000000U)
  3153. #define VHA_CR_CORE2_MMU_FAULT_STATUS2_CLEANUNIQUE_SHIFT (28U)
  3154. #define VHA_CR_CORE2_MMU_FAULT_STATUS2_CLEANUNIQUE_CLRMSK (0XEFFFFFFFU)
  3155. #define VHA_CR_CORE2_MMU_FAULT_STATUS2_CLEANUNIQUE_EN (0X10000000U)
  3156. #define VHA_CR_CORE2_MMU_FAULT_STATUS2_BANK_SHIFT (24U)
  3157. #define VHA_CR_CORE2_MMU_FAULT_STATUS2_BANK_CLRMSK (0XF0FFFFFFU)
  3158. #define VHA_CR_CORE2_MMU_FAULT_STATUS2_TLB_ENTRY_SHIFT (16U)
  3159. #define VHA_CR_CORE2_MMU_FAULT_STATUS2_TLB_ENTRY_CLRMSK (0XFF00FFFFU)
  3160. #define VHA_CR_CORE2_MMU_FAULT_STATUS2_FBM_FAULT_SHIFT (10U)
  3161. #define VHA_CR_CORE2_MMU_FAULT_STATUS2_FBM_FAULT_CLRMSK (0XFFFFFBFFU)
  3162. #define VHA_CR_CORE2_MMU_FAULT_STATUS2_FBM_FAULT_EN (0X00000400U)
  3163. #define VHA_CR_CORE2_MMU_FAULT_STATUS2_BIF_ID_SHIFT (0U)
  3164. #define VHA_CR_CORE2_MMU_FAULT_STATUS2_BIF_ID_CLRMSK (0XFFFFFC00U)
  3165. /*
  3166. Register VHA_CR_CORE3_MMU_FAULT_STATUS1
  3167. */
  3168. #define VHA_CR_CORE3_MMU_FAULT_STATUS1 (0x7B30U)
  3169. #define VHA_CR_CORE3_MMU_FAULT_STATUS1_MASKFULL (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
  3170. #define VHA_CR_CORE3_MMU_FAULT_STATUS1_LEVEL_SHIFT (62U)
  3171. #define VHA_CR_CORE3_MMU_FAULT_STATUS1_LEVEL_CLRMSK (IMG_UINT64_C(0X3FFFFFFFFFFFFFFF))
  3172. #define VHA_CR_CORE3_MMU_FAULT_STATUS1_REQ_ID_SHIFT (56U)
  3173. #define VHA_CR_CORE3_MMU_FAULT_STATUS1_REQ_ID_CLRMSK (IMG_UINT64_C(0XC0FFFFFFFFFFFFFF))
  3174. #define VHA_CR_CORE3_MMU_FAULT_STATUS1_CONTEXT_SHIFT (48U)
  3175. #define VHA_CR_CORE3_MMU_FAULT_STATUS1_CONTEXT_CLRMSK (IMG_UINT64_C(0XFF00FFFFFFFFFFFF))
  3176. #define VHA_CR_CORE3_MMU_FAULT_STATUS1_ADDRESS_SHIFT (4U)
  3177. #define VHA_CR_CORE3_MMU_FAULT_STATUS1_ADDRESS_CLRMSK (IMG_UINT64_C(0XFFFF00000000000F))
  3178. #define VHA_CR_CORE3_MMU_FAULT_STATUS1_RNW_SHIFT (3U)
  3179. #define VHA_CR_CORE3_MMU_FAULT_STATUS1_RNW_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF7))
  3180. #define VHA_CR_CORE3_MMU_FAULT_STATUS1_RNW_EN (IMG_UINT64_C(0X0000000000000008))
  3181. #define VHA_CR_CORE3_MMU_FAULT_STATUS1_TYPE_SHIFT (1U)
  3182. #define VHA_CR_CORE3_MMU_FAULT_STATUS1_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF9))
  3183. #define VHA_CR_CORE3_MMU_FAULT_STATUS1_FAULT_SHIFT (0U)
  3184. #define VHA_CR_CORE3_MMU_FAULT_STATUS1_FAULT_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  3185. #define VHA_CR_CORE3_MMU_FAULT_STATUS1_FAULT_EN (IMG_UINT64_C(0X0000000000000001))
  3186. /*
  3187. Register VHA_CR_CORE3_MMU_FAULT_STATUS2
  3188. */
  3189. #define VHA_CR_CORE3_MMU_FAULT_STATUS2 (0x7B38U)
  3190. #define VHA_CR_CORE3_MMU_FAULT_STATUS2_MASKFULL (IMG_UINT64_C(0x000000003FFF07FF))
  3191. #define VHA_CR_CORE3_MMU_FAULT_STATUS2_WRITEBACK_SHIFT (29U)
  3192. #define VHA_CR_CORE3_MMU_FAULT_STATUS2_WRITEBACK_CLRMSK (0XDFFFFFFFU)
  3193. #define VHA_CR_CORE3_MMU_FAULT_STATUS2_WRITEBACK_EN (0X20000000U)
  3194. #define VHA_CR_CORE3_MMU_FAULT_STATUS2_CLEANUNIQUE_SHIFT (28U)
  3195. #define VHA_CR_CORE3_MMU_FAULT_STATUS2_CLEANUNIQUE_CLRMSK (0XEFFFFFFFU)
  3196. #define VHA_CR_CORE3_MMU_FAULT_STATUS2_CLEANUNIQUE_EN (0X10000000U)
  3197. #define VHA_CR_CORE3_MMU_FAULT_STATUS2_BANK_SHIFT (24U)
  3198. #define VHA_CR_CORE3_MMU_FAULT_STATUS2_BANK_CLRMSK (0XF0FFFFFFU)
  3199. #define VHA_CR_CORE3_MMU_FAULT_STATUS2_TLB_ENTRY_SHIFT (16U)
  3200. #define VHA_CR_CORE3_MMU_FAULT_STATUS2_TLB_ENTRY_CLRMSK (0XFF00FFFFU)
  3201. #define VHA_CR_CORE3_MMU_FAULT_STATUS2_FBM_FAULT_SHIFT (10U)
  3202. #define VHA_CR_CORE3_MMU_FAULT_STATUS2_FBM_FAULT_CLRMSK (0XFFFFFBFFU)
  3203. #define VHA_CR_CORE3_MMU_FAULT_STATUS2_FBM_FAULT_EN (0X00000400U)
  3204. #define VHA_CR_CORE3_MMU_FAULT_STATUS2_BIF_ID_SHIFT (0U)
  3205. #define VHA_CR_CORE3_MMU_FAULT_STATUS2_BIF_ID_CLRMSK (0XFFFFFC00U)
  3206. /*
  3207. Register VHA_CR_CORE4_MMU_FAULT_STATUS1
  3208. */
  3209. #define VHA_CR_CORE4_MMU_FAULT_STATUS1 (0x7B40U)
  3210. #define VHA_CR_CORE4_MMU_FAULT_STATUS1_MASKFULL (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
  3211. #define VHA_CR_CORE4_MMU_FAULT_STATUS1_LEVEL_SHIFT (62U)
  3212. #define VHA_CR_CORE4_MMU_FAULT_STATUS1_LEVEL_CLRMSK (IMG_UINT64_C(0X3FFFFFFFFFFFFFFF))
  3213. #define VHA_CR_CORE4_MMU_FAULT_STATUS1_REQ_ID_SHIFT (56U)
  3214. #define VHA_CR_CORE4_MMU_FAULT_STATUS1_REQ_ID_CLRMSK (IMG_UINT64_C(0XC0FFFFFFFFFFFFFF))
  3215. #define VHA_CR_CORE4_MMU_FAULT_STATUS1_CONTEXT_SHIFT (48U)
  3216. #define VHA_CR_CORE4_MMU_FAULT_STATUS1_CONTEXT_CLRMSK (IMG_UINT64_C(0XFF00FFFFFFFFFFFF))
  3217. #define VHA_CR_CORE4_MMU_FAULT_STATUS1_ADDRESS_SHIFT (4U)
  3218. #define VHA_CR_CORE4_MMU_FAULT_STATUS1_ADDRESS_CLRMSK (IMG_UINT64_C(0XFFFF00000000000F))
  3219. #define VHA_CR_CORE4_MMU_FAULT_STATUS1_RNW_SHIFT (3U)
  3220. #define VHA_CR_CORE4_MMU_FAULT_STATUS1_RNW_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF7))
  3221. #define VHA_CR_CORE4_MMU_FAULT_STATUS1_RNW_EN (IMG_UINT64_C(0X0000000000000008))
  3222. #define VHA_CR_CORE4_MMU_FAULT_STATUS1_TYPE_SHIFT (1U)
  3223. #define VHA_CR_CORE4_MMU_FAULT_STATUS1_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF9))
  3224. #define VHA_CR_CORE4_MMU_FAULT_STATUS1_FAULT_SHIFT (0U)
  3225. #define VHA_CR_CORE4_MMU_FAULT_STATUS1_FAULT_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  3226. #define VHA_CR_CORE4_MMU_FAULT_STATUS1_FAULT_EN (IMG_UINT64_C(0X0000000000000001))
  3227. /*
  3228. Register VHA_CR_CORE4_MMU_FAULT_STATUS2
  3229. */
  3230. #define VHA_CR_CORE4_MMU_FAULT_STATUS2 (0x7B48U)
  3231. #define VHA_CR_CORE4_MMU_FAULT_STATUS2_MASKFULL (IMG_UINT64_C(0x000000003FFF07FF))
  3232. #define VHA_CR_CORE4_MMU_FAULT_STATUS2_WRITEBACK_SHIFT (29U)
  3233. #define VHA_CR_CORE4_MMU_FAULT_STATUS2_WRITEBACK_CLRMSK (0XDFFFFFFFU)
  3234. #define VHA_CR_CORE4_MMU_FAULT_STATUS2_WRITEBACK_EN (0X20000000U)
  3235. #define VHA_CR_CORE4_MMU_FAULT_STATUS2_CLEANUNIQUE_SHIFT (28U)
  3236. #define VHA_CR_CORE4_MMU_FAULT_STATUS2_CLEANUNIQUE_CLRMSK (0XEFFFFFFFU)
  3237. #define VHA_CR_CORE4_MMU_FAULT_STATUS2_CLEANUNIQUE_EN (0X10000000U)
  3238. #define VHA_CR_CORE4_MMU_FAULT_STATUS2_BANK_SHIFT (24U)
  3239. #define VHA_CR_CORE4_MMU_FAULT_STATUS2_BANK_CLRMSK (0XF0FFFFFFU)
  3240. #define VHA_CR_CORE4_MMU_FAULT_STATUS2_TLB_ENTRY_SHIFT (16U)
  3241. #define VHA_CR_CORE4_MMU_FAULT_STATUS2_TLB_ENTRY_CLRMSK (0XFF00FFFFU)
  3242. #define VHA_CR_CORE4_MMU_FAULT_STATUS2_FBM_FAULT_SHIFT (10U)
  3243. #define VHA_CR_CORE4_MMU_FAULT_STATUS2_FBM_FAULT_CLRMSK (0XFFFFFBFFU)
  3244. #define VHA_CR_CORE4_MMU_FAULT_STATUS2_FBM_FAULT_EN (0X00000400U)
  3245. #define VHA_CR_CORE4_MMU_FAULT_STATUS2_BIF_ID_SHIFT (0U)
  3246. #define VHA_CR_CORE4_MMU_FAULT_STATUS2_BIF_ID_CLRMSK (0XFFFFFC00U)
  3247. /*
  3248. Register VHA_CR_CORE5_MMU_FAULT_STATUS1
  3249. */
  3250. #define VHA_CR_CORE5_MMU_FAULT_STATUS1 (0x7B50U)
  3251. #define VHA_CR_CORE5_MMU_FAULT_STATUS1_MASKFULL (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
  3252. #define VHA_CR_CORE5_MMU_FAULT_STATUS1_LEVEL_SHIFT (62U)
  3253. #define VHA_CR_CORE5_MMU_FAULT_STATUS1_LEVEL_CLRMSK (IMG_UINT64_C(0X3FFFFFFFFFFFFFFF))
  3254. #define VHA_CR_CORE5_MMU_FAULT_STATUS1_REQ_ID_SHIFT (56U)
  3255. #define VHA_CR_CORE5_MMU_FAULT_STATUS1_REQ_ID_CLRMSK (IMG_UINT64_C(0XC0FFFFFFFFFFFFFF))
  3256. #define VHA_CR_CORE5_MMU_FAULT_STATUS1_CONTEXT_SHIFT (48U)
  3257. #define VHA_CR_CORE5_MMU_FAULT_STATUS1_CONTEXT_CLRMSK (IMG_UINT64_C(0XFF00FFFFFFFFFFFF))
  3258. #define VHA_CR_CORE5_MMU_FAULT_STATUS1_ADDRESS_SHIFT (4U)
  3259. #define VHA_CR_CORE5_MMU_FAULT_STATUS1_ADDRESS_CLRMSK (IMG_UINT64_C(0XFFFF00000000000F))
  3260. #define VHA_CR_CORE5_MMU_FAULT_STATUS1_RNW_SHIFT (3U)
  3261. #define VHA_CR_CORE5_MMU_FAULT_STATUS1_RNW_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF7))
  3262. #define VHA_CR_CORE5_MMU_FAULT_STATUS1_RNW_EN (IMG_UINT64_C(0X0000000000000008))
  3263. #define VHA_CR_CORE5_MMU_FAULT_STATUS1_TYPE_SHIFT (1U)
  3264. #define VHA_CR_CORE5_MMU_FAULT_STATUS1_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF9))
  3265. #define VHA_CR_CORE5_MMU_FAULT_STATUS1_FAULT_SHIFT (0U)
  3266. #define VHA_CR_CORE5_MMU_FAULT_STATUS1_FAULT_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  3267. #define VHA_CR_CORE5_MMU_FAULT_STATUS1_FAULT_EN (IMG_UINT64_C(0X0000000000000001))
  3268. /*
  3269. Register VHA_CR_CORE5_MMU_FAULT_STATUS2
  3270. */
  3271. #define VHA_CR_CORE5_MMU_FAULT_STATUS2 (0x7B58U)
  3272. #define VHA_CR_CORE5_MMU_FAULT_STATUS2_MASKFULL (IMG_UINT64_C(0x000000003FFF07FF))
  3273. #define VHA_CR_CORE5_MMU_FAULT_STATUS2_WRITEBACK_SHIFT (29U)
  3274. #define VHA_CR_CORE5_MMU_FAULT_STATUS2_WRITEBACK_CLRMSK (0XDFFFFFFFU)
  3275. #define VHA_CR_CORE5_MMU_FAULT_STATUS2_WRITEBACK_EN (0X20000000U)
  3276. #define VHA_CR_CORE5_MMU_FAULT_STATUS2_CLEANUNIQUE_SHIFT (28U)
  3277. #define VHA_CR_CORE5_MMU_FAULT_STATUS2_CLEANUNIQUE_CLRMSK (0XEFFFFFFFU)
  3278. #define VHA_CR_CORE5_MMU_FAULT_STATUS2_CLEANUNIQUE_EN (0X10000000U)
  3279. #define VHA_CR_CORE5_MMU_FAULT_STATUS2_BANK_SHIFT (24U)
  3280. #define VHA_CR_CORE5_MMU_FAULT_STATUS2_BANK_CLRMSK (0XF0FFFFFFU)
  3281. #define VHA_CR_CORE5_MMU_FAULT_STATUS2_TLB_ENTRY_SHIFT (16U)
  3282. #define VHA_CR_CORE5_MMU_FAULT_STATUS2_TLB_ENTRY_CLRMSK (0XFF00FFFFU)
  3283. #define VHA_CR_CORE5_MMU_FAULT_STATUS2_FBM_FAULT_SHIFT (10U)
  3284. #define VHA_CR_CORE5_MMU_FAULT_STATUS2_FBM_FAULT_CLRMSK (0XFFFFFBFFU)
  3285. #define VHA_CR_CORE5_MMU_FAULT_STATUS2_FBM_FAULT_EN (0X00000400U)
  3286. #define VHA_CR_CORE5_MMU_FAULT_STATUS2_BIF_ID_SHIFT (0U)
  3287. #define VHA_CR_CORE5_MMU_FAULT_STATUS2_BIF_ID_CLRMSK (0XFFFFFC00U)
  3288. /*
  3289. Register VHA_CR_CORE6_MMU_FAULT_STATUS1
  3290. */
  3291. #define VHA_CR_CORE6_MMU_FAULT_STATUS1 (0x7B60U)
  3292. #define VHA_CR_CORE6_MMU_FAULT_STATUS1_MASKFULL (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
  3293. #define VHA_CR_CORE6_MMU_FAULT_STATUS1_LEVEL_SHIFT (62U)
  3294. #define VHA_CR_CORE6_MMU_FAULT_STATUS1_LEVEL_CLRMSK (IMG_UINT64_C(0X3FFFFFFFFFFFFFFF))
  3295. #define VHA_CR_CORE6_MMU_FAULT_STATUS1_REQ_ID_SHIFT (56U)
  3296. #define VHA_CR_CORE6_MMU_FAULT_STATUS1_REQ_ID_CLRMSK (IMG_UINT64_C(0XC0FFFFFFFFFFFFFF))
  3297. #define VHA_CR_CORE6_MMU_FAULT_STATUS1_CONTEXT_SHIFT (48U)
  3298. #define VHA_CR_CORE6_MMU_FAULT_STATUS1_CONTEXT_CLRMSK (IMG_UINT64_C(0XFF00FFFFFFFFFFFF))
  3299. #define VHA_CR_CORE6_MMU_FAULT_STATUS1_ADDRESS_SHIFT (4U)
  3300. #define VHA_CR_CORE6_MMU_FAULT_STATUS1_ADDRESS_CLRMSK (IMG_UINT64_C(0XFFFF00000000000F))
  3301. #define VHA_CR_CORE6_MMU_FAULT_STATUS1_RNW_SHIFT (3U)
  3302. #define VHA_CR_CORE6_MMU_FAULT_STATUS1_RNW_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF7))
  3303. #define VHA_CR_CORE6_MMU_FAULT_STATUS1_RNW_EN (IMG_UINT64_C(0X0000000000000008))
  3304. #define VHA_CR_CORE6_MMU_FAULT_STATUS1_TYPE_SHIFT (1U)
  3305. #define VHA_CR_CORE6_MMU_FAULT_STATUS1_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF9))
  3306. #define VHA_CR_CORE6_MMU_FAULT_STATUS1_FAULT_SHIFT (0U)
  3307. #define VHA_CR_CORE6_MMU_FAULT_STATUS1_FAULT_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  3308. #define VHA_CR_CORE6_MMU_FAULT_STATUS1_FAULT_EN (IMG_UINT64_C(0X0000000000000001))
  3309. /*
  3310. Register VHA_CR_CORE6_MMU_FAULT_STATUS2
  3311. */
  3312. #define VHA_CR_CORE6_MMU_FAULT_STATUS2 (0x7B68U)
  3313. #define VHA_CR_CORE6_MMU_FAULT_STATUS2_MASKFULL (IMG_UINT64_C(0x000000003FFF07FF))
  3314. #define VHA_CR_CORE6_MMU_FAULT_STATUS2_WRITEBACK_SHIFT (29U)
  3315. #define VHA_CR_CORE6_MMU_FAULT_STATUS2_WRITEBACK_CLRMSK (0XDFFFFFFFU)
  3316. #define VHA_CR_CORE6_MMU_FAULT_STATUS2_WRITEBACK_EN (0X20000000U)
  3317. #define VHA_CR_CORE6_MMU_FAULT_STATUS2_CLEANUNIQUE_SHIFT (28U)
  3318. #define VHA_CR_CORE6_MMU_FAULT_STATUS2_CLEANUNIQUE_CLRMSK (0XEFFFFFFFU)
  3319. #define VHA_CR_CORE6_MMU_FAULT_STATUS2_CLEANUNIQUE_EN (0X10000000U)
  3320. #define VHA_CR_CORE6_MMU_FAULT_STATUS2_BANK_SHIFT (24U)
  3321. #define VHA_CR_CORE6_MMU_FAULT_STATUS2_BANK_CLRMSK (0XF0FFFFFFU)
  3322. #define VHA_CR_CORE6_MMU_FAULT_STATUS2_TLB_ENTRY_SHIFT (16U)
  3323. #define VHA_CR_CORE6_MMU_FAULT_STATUS2_TLB_ENTRY_CLRMSK (0XFF00FFFFU)
  3324. #define VHA_CR_CORE6_MMU_FAULT_STATUS2_FBM_FAULT_SHIFT (10U)
  3325. #define VHA_CR_CORE6_MMU_FAULT_STATUS2_FBM_FAULT_CLRMSK (0XFFFFFBFFU)
  3326. #define VHA_CR_CORE6_MMU_FAULT_STATUS2_FBM_FAULT_EN (0X00000400U)
  3327. #define VHA_CR_CORE6_MMU_FAULT_STATUS2_BIF_ID_SHIFT (0U)
  3328. #define VHA_CR_CORE6_MMU_FAULT_STATUS2_BIF_ID_CLRMSK (0XFFFFFC00U)
  3329. /*
  3330. Register VHA_CR_CORE7_MMU_FAULT_STATUS1
  3331. */
  3332. #define VHA_CR_CORE7_MMU_FAULT_STATUS1 (0x7B70U)
  3333. #define VHA_CR_CORE7_MMU_FAULT_STATUS1_MASKFULL (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
  3334. #define VHA_CR_CORE7_MMU_FAULT_STATUS1_LEVEL_SHIFT (62U)
  3335. #define VHA_CR_CORE7_MMU_FAULT_STATUS1_LEVEL_CLRMSK (IMG_UINT64_C(0X3FFFFFFFFFFFFFFF))
  3336. #define VHA_CR_CORE7_MMU_FAULT_STATUS1_REQ_ID_SHIFT (56U)
  3337. #define VHA_CR_CORE7_MMU_FAULT_STATUS1_REQ_ID_CLRMSK (IMG_UINT64_C(0XC0FFFFFFFFFFFFFF))
  3338. #define VHA_CR_CORE7_MMU_FAULT_STATUS1_CONTEXT_SHIFT (48U)
  3339. #define VHA_CR_CORE7_MMU_FAULT_STATUS1_CONTEXT_CLRMSK (IMG_UINT64_C(0XFF00FFFFFFFFFFFF))
  3340. #define VHA_CR_CORE7_MMU_FAULT_STATUS1_ADDRESS_SHIFT (4U)
  3341. #define VHA_CR_CORE7_MMU_FAULT_STATUS1_ADDRESS_CLRMSK (IMG_UINT64_C(0XFFFF00000000000F))
  3342. #define VHA_CR_CORE7_MMU_FAULT_STATUS1_RNW_SHIFT (3U)
  3343. #define VHA_CR_CORE7_MMU_FAULT_STATUS1_RNW_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF7))
  3344. #define VHA_CR_CORE7_MMU_FAULT_STATUS1_RNW_EN (IMG_UINT64_C(0X0000000000000008))
  3345. #define VHA_CR_CORE7_MMU_FAULT_STATUS1_TYPE_SHIFT (1U)
  3346. #define VHA_CR_CORE7_MMU_FAULT_STATUS1_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF9))
  3347. #define VHA_CR_CORE7_MMU_FAULT_STATUS1_FAULT_SHIFT (0U)
  3348. #define VHA_CR_CORE7_MMU_FAULT_STATUS1_FAULT_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  3349. #define VHA_CR_CORE7_MMU_FAULT_STATUS1_FAULT_EN (IMG_UINT64_C(0X0000000000000001))
  3350. /*
  3351. Register VHA_CR_CORE7_MMU_FAULT_STATUS2
  3352. */
  3353. #define VHA_CR_CORE7_MMU_FAULT_STATUS2 (0x7B78U)
  3354. #define VHA_CR_CORE7_MMU_FAULT_STATUS2_MASKFULL (IMG_UINT64_C(0x000000003FFF07FF))
  3355. #define VHA_CR_CORE7_MMU_FAULT_STATUS2_WRITEBACK_SHIFT (29U)
  3356. #define VHA_CR_CORE7_MMU_FAULT_STATUS2_WRITEBACK_CLRMSK (0XDFFFFFFFU)
  3357. #define VHA_CR_CORE7_MMU_FAULT_STATUS2_WRITEBACK_EN (0X20000000U)
  3358. #define VHA_CR_CORE7_MMU_FAULT_STATUS2_CLEANUNIQUE_SHIFT (28U)
  3359. #define VHA_CR_CORE7_MMU_FAULT_STATUS2_CLEANUNIQUE_CLRMSK (0XEFFFFFFFU)
  3360. #define VHA_CR_CORE7_MMU_FAULT_STATUS2_CLEANUNIQUE_EN (0X10000000U)
  3361. #define VHA_CR_CORE7_MMU_FAULT_STATUS2_BANK_SHIFT (24U)
  3362. #define VHA_CR_CORE7_MMU_FAULT_STATUS2_BANK_CLRMSK (0XF0FFFFFFU)
  3363. #define VHA_CR_CORE7_MMU_FAULT_STATUS2_TLB_ENTRY_SHIFT (16U)
  3364. #define VHA_CR_CORE7_MMU_FAULT_STATUS2_TLB_ENTRY_CLRMSK (0XFF00FFFFU)
  3365. #define VHA_CR_CORE7_MMU_FAULT_STATUS2_FBM_FAULT_SHIFT (10U)
  3366. #define VHA_CR_CORE7_MMU_FAULT_STATUS2_FBM_FAULT_CLRMSK (0XFFFFFBFFU)
  3367. #define VHA_CR_CORE7_MMU_FAULT_STATUS2_FBM_FAULT_EN (0X00000400U)
  3368. #define VHA_CR_CORE7_MMU_FAULT_STATUS2_BIF_ID_SHIFT (0U)
  3369. #define VHA_CR_CORE7_MMU_FAULT_STATUS2_BIF_ID_CLRMSK (0XFFFFFC00U)
  3370. /*
  3371. Register VHA_CR_WM_WL_CONTROL
  3372. */
  3373. #define VHA_CR_WM_WL_CONTROL (0x10000U)
  3374. #define VHA_CR_WM_WL_CONTROL_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  3375. #define VHA_CR_WM_WL_CONTROL_WL_START_SHIFT (0U)
  3376. #define VHA_CR_WM_WL_CONTROL_WL_START_CLRMSK (0XFFFFFFFEU)
  3377. #define VHA_CR_WM_WL_CONTROL_WL_START_EN (0X00000001U)
  3378. #define VHA_CR_WM_STATUS_STATE_MASK (0x00000007U)
  3379. /*
  3380. The WM is ready to be programmed */
  3381. #define VHA_CR_WM_STATUS_STATE_IDLE (0x00000000U)
  3382. /*
  3383. The WM is initiating the execution of a Workload*/
  3384. #define VHA_CR_WM_STATUS_STATE_PENDING (0x00000001U)
  3385. /*
  3386. A Workload is being run */
  3387. #define VHA_CR_WM_STATUS_STATE_RUN (0x00000002U)
  3388. /*
  3389. The Workload had an error and execution is halted. A WM reset is required */
  3390. #define VHA_CR_WM_STATUS_STATE_HALTED (0x00000003U)
  3391. /*
  3392. The Workload Manager's Response FIFO is full. Workloads cannot be kicked in the WM unless a RESPONSE_FIFO_READ is issued*/
  3393. #define VHA_CR_WM_STATUS_STATE_RESPONSE_FIFO_FULL (0x00000004U)
  3394. /*
  3395. Register VHA_CR_WM_STATUS
  3396. */
  3397. #define VHA_CR_WM_STATUS (0x10008U)
  3398. #define VHA_CR_WM_STATUS_MASKFULL (IMG_UINT64_C(0x0000000001000007))
  3399. #define VHA_CR_WM_STATUS_PARITY_SHIFT (24U)
  3400. #define VHA_CR_WM_STATUS_PARITY_CLRMSK (0XFEFFFFFFU)
  3401. #define VHA_CR_WM_STATUS_PARITY_EN (0X01000000U)
  3402. #define VHA_CR_WM_STATUS_CURRENT_STATE_SHIFT (0U)
  3403. #define VHA_CR_WM_STATUS_CURRENT_STATE_CLRMSK (0XFFFFFFF8U)
  3404. #define VHA_CR_WM_STATUS_CURRENT_STATE_IDLE (00000000U)
  3405. #define VHA_CR_WM_STATUS_CURRENT_STATE_PENDING (0X00000001U)
  3406. #define VHA_CR_WM_STATUS_CURRENT_STATE_RUN (0X00000002U)
  3407. #define VHA_CR_WM_STATUS_CURRENT_STATE_HALTED (0X00000003U)
  3408. #define VHA_CR_WM_STATUS_CURRENT_STATE_RESPONSE_FIFO_FULL (0X00000004U)
  3409. #define VHA_CR_WM_EVENT_TYPE_WM_WL_WDT_SHIFT (4U)
  3410. #define VHA_CR_WM_EVENT_TYPE_WM_WL_WDT_CLRMSK (0XFFFFFFEFU)
  3411. #define VHA_CR_WM_EVENT_TYPE_WM_WL_WDT_EN (0X00000010U)
  3412. #define VHA_CR_WM_EVENT_TYPE_WM_WL_IDLE_WDT_SHIFT (3U)
  3413. #define VHA_CR_WM_EVENT_TYPE_WM_WL_IDLE_WDT_CLRMSK (0XFFFFFFF7U)
  3414. #define VHA_CR_WM_EVENT_TYPE_WM_WL_IDLE_WDT_EN (0X00000008U)
  3415. #define VHA_CR_WM_EVENT_TYPE_WM_SOCIF_WDT_SHIFT (2U)
  3416. #define VHA_CR_WM_EVENT_TYPE_WM_SOCIF_WDT_CLRMSK (0XFFFFFFFBU)
  3417. #define VHA_CR_WM_EVENT_TYPE_WM_SOCIF_WDT_EN (0X00000004U)
  3418. #define VHA_CR_WM_EVENT_TYPE_LOGIC_FAULT_SHIFT (1U)
  3419. #define VHA_CR_WM_EVENT_TYPE_LOGIC_FAULT_CLRMSK (0XFFFFFFFDU)
  3420. #define VHA_CR_WM_EVENT_TYPE_LOGIC_FAULT_EN (0X00000002U)
  3421. #define VHA_CR_WM_EVENT_TYPE_RESPONSE_FIFO_READY_SHIFT (0U)
  3422. #define VHA_CR_WM_EVENT_TYPE_RESPONSE_FIFO_READY_CLRMSK (0XFFFFFFFEU)
  3423. #define VHA_CR_WM_EVENT_TYPE_RESPONSE_FIFO_READY_EN (0X00000001U)
  3424. #define VHA_CR_WM_EVENT_STATUS_TYPE_PARITY_SHIFT (31U)
  3425. #define VHA_CR_WM_EVENT_STATUS_TYPE_PARITY_CLRMSK (0X7FFFFFFFU)
  3426. #define VHA_CR_WM_EVENT_STATUS_TYPE_PARITY_EN (0X80000000U)
  3427. #define VHA_CR_WM_EVENT_STATUS_TYPE_WM_WL_WDT_SHIFT (4U)
  3428. #define VHA_CR_WM_EVENT_STATUS_TYPE_WM_WL_WDT_CLRMSK (0XFFFFFFEFU)
  3429. #define VHA_CR_WM_EVENT_STATUS_TYPE_WM_WL_WDT_EN (0X00000010U)
  3430. #define VHA_CR_WM_EVENT_STATUS_TYPE_WM_WL_IDLE_WDT_SHIFT (3U)
  3431. #define VHA_CR_WM_EVENT_STATUS_TYPE_WM_WL_IDLE_WDT_CLRMSK (0XFFFFFFF7U)
  3432. #define VHA_CR_WM_EVENT_STATUS_TYPE_WM_WL_IDLE_WDT_EN (0X00000008U)
  3433. #define VHA_CR_WM_EVENT_STATUS_TYPE_WM_SOCIF_WDT_SHIFT (2U)
  3434. #define VHA_CR_WM_EVENT_STATUS_TYPE_WM_SOCIF_WDT_CLRMSK (0XFFFFFFFBU)
  3435. #define VHA_CR_WM_EVENT_STATUS_TYPE_WM_SOCIF_WDT_EN (0X00000004U)
  3436. #define VHA_CR_WM_EVENT_STATUS_TYPE_LOGIC_FAULT_SHIFT (1U)
  3437. #define VHA_CR_WM_EVENT_STATUS_TYPE_LOGIC_FAULT_CLRMSK (0XFFFFFFFDU)
  3438. #define VHA_CR_WM_EVENT_STATUS_TYPE_LOGIC_FAULT_EN (0X00000002U)
  3439. #define VHA_CR_WM_EVENT_STATUS_TYPE_RESPONSE_FIFO_READY_SHIFT (0U)
  3440. #define VHA_CR_WM_EVENT_STATUS_TYPE_RESPONSE_FIFO_READY_CLRMSK (0XFFFFFFFEU)
  3441. #define VHA_CR_WM_EVENT_STATUS_TYPE_RESPONSE_FIFO_READY_EN (0X00000001U)
  3442. /*
  3443. Register VHA_CR_WM_EVENT_ENABLE
  3444. */
  3445. #define VHA_CR_WM_EVENT_ENABLE (0x10010U)
  3446. #define VHA_CR_WM_EVENT_ENABLE_MASKFULL (IMG_UINT64_C(0x000000000000001F))
  3447. #define VHA_CR_WM_EVENT_ENABLE_WM_WL_WDT_SHIFT (4U)
  3448. #define VHA_CR_WM_EVENT_ENABLE_WM_WL_WDT_CLRMSK (0XFFFFFFEFU)
  3449. #define VHA_CR_WM_EVENT_ENABLE_WM_WL_WDT_EN (0X00000010U)
  3450. #define VHA_CR_WM_EVENT_ENABLE_WM_WL_IDLE_WDT_SHIFT (3U)
  3451. #define VHA_CR_WM_EVENT_ENABLE_WM_WL_IDLE_WDT_CLRMSK (0XFFFFFFF7U)
  3452. #define VHA_CR_WM_EVENT_ENABLE_WM_WL_IDLE_WDT_EN (0X00000008U)
  3453. #define VHA_CR_WM_EVENT_ENABLE_WM_SOCIF_WDT_SHIFT (2U)
  3454. #define VHA_CR_WM_EVENT_ENABLE_WM_SOCIF_WDT_CLRMSK (0XFFFFFFFBU)
  3455. #define VHA_CR_WM_EVENT_ENABLE_WM_SOCIF_WDT_EN (0X00000004U)
  3456. #define VHA_CR_WM_EVENT_ENABLE_LOGIC_FAULT_SHIFT (1U)
  3457. #define VHA_CR_WM_EVENT_ENABLE_LOGIC_FAULT_CLRMSK (0XFFFFFFFDU)
  3458. #define VHA_CR_WM_EVENT_ENABLE_LOGIC_FAULT_EN (0X00000002U)
  3459. #define VHA_CR_WM_EVENT_ENABLE_RESPONSE_FIFO_READY_SHIFT (0U)
  3460. #define VHA_CR_WM_EVENT_ENABLE_RESPONSE_FIFO_READY_CLRMSK (0XFFFFFFFEU)
  3461. #define VHA_CR_WM_EVENT_ENABLE_RESPONSE_FIFO_READY_EN (0X00000001U)
  3462. /*
  3463. Register VHA_CR_WM_EVENT_STATUS
  3464. */
  3465. #define VHA_CR_WM_EVENT_STATUS (0x10018U)
  3466. #define VHA_CR_WM_EVENT_STATUS_MASKFULL (IMG_UINT64_C(0x000000008000001F))
  3467. #define VHA_CR_WM_EVENT_STATUS_PARITY_SHIFT (31U)
  3468. #define VHA_CR_WM_EVENT_STATUS_PARITY_CLRMSK (0X7FFFFFFFU)
  3469. #define VHA_CR_WM_EVENT_STATUS_PARITY_EN (0X80000000U)
  3470. #define VHA_CR_WM_EVENT_STATUS_WM_WL_WDT_SHIFT (4U)
  3471. #define VHA_CR_WM_EVENT_STATUS_WM_WL_WDT_CLRMSK (0XFFFFFFEFU)
  3472. #define VHA_CR_WM_EVENT_STATUS_WM_WL_WDT_EN (0X00000010U)
  3473. #define VHA_CR_WM_EVENT_STATUS_WM_WL_IDLE_WDT_SHIFT (3U)
  3474. #define VHA_CR_WM_EVENT_STATUS_WM_WL_IDLE_WDT_CLRMSK (0XFFFFFFF7U)
  3475. #define VHA_CR_WM_EVENT_STATUS_WM_WL_IDLE_WDT_EN (0X00000008U)
  3476. #define VHA_CR_WM_EVENT_STATUS_WM_SOCIF_WDT_SHIFT (2U)
  3477. #define VHA_CR_WM_EVENT_STATUS_WM_SOCIF_WDT_CLRMSK (0XFFFFFFFBU)
  3478. #define VHA_CR_WM_EVENT_STATUS_WM_SOCIF_WDT_EN (0X00000004U)
  3479. #define VHA_CR_WM_EVENT_STATUS_LOGIC_FAULT_SHIFT (1U)
  3480. #define VHA_CR_WM_EVENT_STATUS_LOGIC_FAULT_CLRMSK (0XFFFFFFFDU)
  3481. #define VHA_CR_WM_EVENT_STATUS_LOGIC_FAULT_EN (0X00000002U)
  3482. #define VHA_CR_WM_EVENT_STATUS_RESPONSE_FIFO_READY_SHIFT (0U)
  3483. #define VHA_CR_WM_EVENT_STATUS_RESPONSE_FIFO_READY_CLRMSK (0XFFFFFFFEU)
  3484. #define VHA_CR_WM_EVENT_STATUS_RESPONSE_FIFO_READY_EN (0X00000001U)
  3485. /*
  3486. Register VHA_CR_WM_EVENT_STATUS_DISABLE
  3487. */
  3488. #define VHA_CR_WM_EVENT_STATUS_DISABLE (0x10028U)
  3489. #define VHA_CR_WM_EVENT_STATUS_DISABLE_MASKFULL (IMG_UINT64_C(0x000000000000001F))
  3490. #define VHA_CR_WM_EVENT_STATUS_DISABLE_WM_WL_WDT_SHIFT (4U)
  3491. #define VHA_CR_WM_EVENT_STATUS_DISABLE_WM_WL_WDT_CLRMSK (0XFFFFFFEFU)
  3492. #define VHA_CR_WM_EVENT_STATUS_DISABLE_WM_WL_WDT_EN (0X00000010U)
  3493. #define VHA_CR_WM_EVENT_STATUS_DISABLE_WM_WL_IDLE_WDT_SHIFT (3U)
  3494. #define VHA_CR_WM_EVENT_STATUS_DISABLE_WM_WL_IDLE_WDT_CLRMSK (0XFFFFFFF7U)
  3495. #define VHA_CR_WM_EVENT_STATUS_DISABLE_WM_WL_IDLE_WDT_EN (0X00000008U)
  3496. #define VHA_CR_WM_EVENT_STATUS_DISABLE_WM_SOCIF_WDT_SHIFT (2U)
  3497. #define VHA_CR_WM_EVENT_STATUS_DISABLE_WM_SOCIF_WDT_CLRMSK (0XFFFFFFFBU)
  3498. #define VHA_CR_WM_EVENT_STATUS_DISABLE_WM_SOCIF_WDT_EN (0X00000004U)
  3499. #define VHA_CR_WM_EVENT_STATUS_DISABLE_LOGIC_FAULT_SHIFT (1U)
  3500. #define VHA_CR_WM_EVENT_STATUS_DISABLE_LOGIC_FAULT_CLRMSK (0XFFFFFFFDU)
  3501. #define VHA_CR_WM_EVENT_STATUS_DISABLE_LOGIC_FAULT_EN (0X00000002U)
  3502. #define VHA_CR_WM_EVENT_STATUS_DISABLE_RESPONSE_FIFO_READY_SHIFT (0U)
  3503. #define VHA_CR_WM_EVENT_STATUS_DISABLE_RESPONSE_FIFO_READY_CLRMSK (0XFFFFFFFEU)
  3504. #define VHA_CR_WM_EVENT_STATUS_DISABLE_RESPONSE_FIFO_READY_EN (0X00000001U)
  3505. /*
  3506. Register VHA_CR_WM_EVENT_CLEAR
  3507. */
  3508. #define VHA_CR_WM_EVENT_CLEAR (0x10020U)
  3509. #define VHA_CR_WM_EVENT_CLEAR_MASKFULL (IMG_UINT64_C(0x000000000000001F))
  3510. #define VHA_CR_WM_EVENT_CLEAR_WM_WL_WDT_SHIFT (4U)
  3511. #define VHA_CR_WM_EVENT_CLEAR_WM_WL_WDT_CLRMSK (0XFFFFFFEFU)
  3512. #define VHA_CR_WM_EVENT_CLEAR_WM_WL_WDT_EN (0X00000010U)
  3513. #define VHA_CR_WM_EVENT_CLEAR_WM_WL_IDLE_WDT_SHIFT (3U)
  3514. #define VHA_CR_WM_EVENT_CLEAR_WM_WL_IDLE_WDT_CLRMSK (0XFFFFFFF7U)
  3515. #define VHA_CR_WM_EVENT_CLEAR_WM_WL_IDLE_WDT_EN (0X00000008U)
  3516. #define VHA_CR_WM_EVENT_CLEAR_WM_SOCIF_WDT_SHIFT (2U)
  3517. #define VHA_CR_WM_EVENT_CLEAR_WM_SOCIF_WDT_CLRMSK (0XFFFFFFFBU)
  3518. #define VHA_CR_WM_EVENT_CLEAR_WM_SOCIF_WDT_EN (0X00000004U)
  3519. #define VHA_CR_WM_EVENT_CLEAR_LOGIC_FAULT_SHIFT (1U)
  3520. #define VHA_CR_WM_EVENT_CLEAR_LOGIC_FAULT_CLRMSK (0XFFFFFFFDU)
  3521. #define VHA_CR_WM_EVENT_CLEAR_LOGIC_FAULT_EN (0X00000002U)
  3522. #define VHA_CR_WM_EVENT_CLEAR_RESPONSE_FIFO_READY_SHIFT (0U)
  3523. #define VHA_CR_WM_EVENT_CLEAR_RESPONSE_FIFO_READY_CLRMSK (0XFFFFFFFEU)
  3524. #define VHA_CR_WM_EVENT_CLEAR_RESPONSE_FIFO_READY_EN (0X00000001U)
  3525. /*
  3526. Register VHA_CR_WM_EVENT_INJECT
  3527. */
  3528. #define VHA_CR_WM_EVENT_INJECT (0x10030U)
  3529. #define VHA_CR_WM_EVENT_INJECT_MASKFULL (IMG_UINT64_C(0x000000000000001F))
  3530. #define VHA_CR_WM_EVENT_INJECT_WM_WL_WDT_SHIFT (4U)
  3531. #define VHA_CR_WM_EVENT_INJECT_WM_WL_WDT_CLRMSK (0XFFFFFFEFU)
  3532. #define VHA_CR_WM_EVENT_INJECT_WM_WL_WDT_EN (0X00000010U)
  3533. #define VHA_CR_WM_EVENT_INJECT_WM_WL_IDLE_WDT_SHIFT (3U)
  3534. #define VHA_CR_WM_EVENT_INJECT_WM_WL_IDLE_WDT_CLRMSK (0XFFFFFFF7U)
  3535. #define VHA_CR_WM_EVENT_INJECT_WM_WL_IDLE_WDT_EN (0X00000008U)
  3536. #define VHA_CR_WM_EVENT_INJECT_WM_SOCIF_WDT_SHIFT (2U)
  3537. #define VHA_CR_WM_EVENT_INJECT_WM_SOCIF_WDT_CLRMSK (0XFFFFFFFBU)
  3538. #define VHA_CR_WM_EVENT_INJECT_WM_SOCIF_WDT_EN (0X00000004U)
  3539. #define VHA_CR_WM_EVENT_INJECT_LOGIC_FAULT_SHIFT (1U)
  3540. #define VHA_CR_WM_EVENT_INJECT_LOGIC_FAULT_CLRMSK (0XFFFFFFFDU)
  3541. #define VHA_CR_WM_EVENT_INJECT_LOGIC_FAULT_EN (0X00000002U)
  3542. #define VHA_CR_WM_EVENT_INJECT_RESPONSE_FIFO_READY_SHIFT (0U)
  3543. #define VHA_CR_WM_EVENT_INJECT_RESPONSE_FIFO_READY_CLRMSK (0XFFFFFFFEU)
  3544. #define VHA_CR_WM_EVENT_INJECT_RESPONSE_FIFO_READY_EN (0X00000001U)
  3545. /*
  3546. Register VHA_CR_WM_WL_ID
  3547. */
  3548. #define VHA_CR_WM_WL_ID (0x10040U)
  3549. #define VHA_CR_WM_WL_ID_MASKFULL (IMG_UINT64_C(0x000000000000FFFF))
  3550. #define VHA_CR_WM_WL_ID_WL_ID_SHIFT (0U)
  3551. #define VHA_CR_WM_WL_ID_WL_ID_CLRMSK (0XFFFF0000U)
  3552. /*
  3553. Register VHA_CR_WM_DEBUG_CONTROL
  3554. */
  3555. #define VHA_CR_WM_DEBUG_CONTROL (0x10048U)
  3556. #define VHA_CR_WM_DEBUG_CONTROL_MASKFULL (IMG_UINT64_C(0x0000000000000003))
  3557. #define VHA_CR_WM_DEBUG_CONTROL_BW_ENABLE_SHIFT (1U)
  3558. #define VHA_CR_WM_DEBUG_CONTROL_BW_ENABLE_CLRMSK (0XFFFFFFFDU)
  3559. #define VHA_CR_WM_DEBUG_CONTROL_BW_ENABLE_EN (0X00000002U)
  3560. #define VHA_CR_WM_DEBUG_CONTROL_PERF_ENABLE_SHIFT (0U)
  3561. #define VHA_CR_WM_DEBUG_CONTROL_PERF_ENABLE_CLRMSK (0XFFFFFFFEU)
  3562. #define VHA_CR_WM_DEBUG_CONTROL_PERF_ENABLE_EN (0X00000001U)
  3563. /*
  3564. WM_WL_WDT is Disabled */
  3565. #define VHA_CR_WM_WL_WDT_CTRL_WL_WDT_CTRL_NONE (0x00000000U)
  3566. /*
  3567. WM_WL_WDT is Cleared when WM kicks a Workload */
  3568. #define VHA_CR_WM_WL_WDT_CTRL_WL_WDT_CTRL_KICK_WL (0x00000001U)
  3569. /*
  3570. Register VHA_CR_WM_WL_WDT_CTRL
  3571. */
  3572. #define VHA_CR_WM_WL_WDT_CTRL (0x10100U)
  3573. #define VHA_CR_WM_WL_WDT_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  3574. #define VHA_CR_WM_WL_WDT_CTRL_MODE_SHIFT (0U)
  3575. #define VHA_CR_WM_WL_WDT_CTRL_MODE_CLRMSK (0XFFFFFFFEU)
  3576. #define VHA_CR_WM_WL_WDT_CTRL_MODE_NONE (00000000U)
  3577. #define VHA_CR_WM_WL_WDT_CTRL_MODE_KICK_WL (0X00000001U)
  3578. /*
  3579. Register VHA_CR_WM_WL_WDT_COMPAREMATCH
  3580. */
  3581. #define VHA_CR_WM_WL_WDT_COMPAREMATCH (0x10108U)
  3582. #define VHA_CR_WM_WL_WDT_COMPAREMATCH_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  3583. #define VHA_CR_WM_WL_WDT_COMPAREMATCH_VALUE_SHIFT (0U)
  3584. #define VHA_CR_WM_WL_WDT_COMPAREMATCH_VALUE_CLRMSK (00000000U)
  3585. /*
  3586. Register VHA_CR_WM_WL_WDT_TIMER
  3587. */
  3588. #define VHA_CR_WM_WL_WDT_TIMER (0x10110U)
  3589. #define VHA_CR_WM_WL_WDT_TIMER_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  3590. #define VHA_CR_WM_WL_WDT_TIMER_VALUE_SHIFT (0U)
  3591. #define VHA_CR_WM_WL_WDT_TIMER_VALUE_CLRMSK (00000000U)
  3592. /*
  3593. WL_IDLE_WDT is Disabled */
  3594. #define VHA_CR_WM_WL_IDLE_WDT_CTRL_WL_IDLE_WDT_CTRL_NONE (0x00000000U)
  3595. /*
  3596. WL_IDLE_WDT is Enabled */
  3597. #define VHA_CR_WM_WL_IDLE_WDT_CTRL_WL_IDLE_WDT_CTRL_ENABLED (0x00000001U)
  3598. /*
  3599. Register VHA_CR_WM_WL_IDLE_WDT_CTRL
  3600. */
  3601. #define VHA_CR_WM_WL_IDLE_WDT_CTRL (0x10118U)
  3602. #define VHA_CR_WM_WL_IDLE_WDT_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  3603. #define VHA_CR_WM_WL_IDLE_WDT_CTRL_MODE_SHIFT (0U)
  3604. #define VHA_CR_WM_WL_IDLE_WDT_CTRL_MODE_CLRMSK (0XFFFFFFFEU)
  3605. #define VHA_CR_WM_WL_IDLE_WDT_CTRL_MODE_NONE (00000000U)
  3606. #define VHA_CR_WM_WL_IDLE_WDT_CTRL_MODE_ENABLED (0X00000001U)
  3607. /*
  3608. Register VHA_CR_WM_WL_IDLE_WDT_COMPAREMATCH
  3609. */
  3610. #define VHA_CR_WM_WL_IDLE_WDT_COMPAREMATCH (0x10120U)
  3611. #define VHA_CR_WM_WL_IDLE_WDT_COMPAREMATCH_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  3612. #define VHA_CR_WM_WL_IDLE_WDT_COMPAREMATCH_VALUE_SHIFT (0U)
  3613. #define VHA_CR_WM_WL_IDLE_WDT_COMPAREMATCH_VALUE_CLRMSK (00000000U)
  3614. /*
  3615. Register VHA_CR_WM_WL_IDLE_WDT_TIMER
  3616. */
  3617. #define VHA_CR_WM_WL_IDLE_WDT_TIMER (0x10128U)
  3618. #define VHA_CR_WM_WL_IDLE_WDT_TIMER_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  3619. #define VHA_CR_WM_WL_IDLE_WDT_TIMER_VALUE_SHIFT (0U)
  3620. #define VHA_CR_WM_WL_IDLE_WDT_TIMER_VALUE_CLRMSK (00000000U)
  3621. /*
  3622. WM_SOCIF_WDT is Disabled */
  3623. #define VHA_CR_WM_SOCIF_WDT_CTRL_WM_SOCIF_WDT_CTRL_NONE (0x00000000U)
  3624. /*
  3625. WM_SOFIC_WDT is Enabled */
  3626. #define VHA_CR_WM_SOCIF_WDT_CTRL_WM_SOCIF_WDT_CTRL_ENABLED (0x00000001U)
  3627. /*
  3628. Register VHA_CR_WM_SOCIF_WDT_CTRL
  3629. */
  3630. #define VHA_CR_WM_SOCIF_WDT_CTRL (0x10130U)
  3631. #define VHA_CR_WM_SOCIF_WDT_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  3632. #define VHA_CR_WM_SOCIF_WDT_CTRL_MODE_SHIFT (0U)
  3633. #define VHA_CR_WM_SOCIF_WDT_CTRL_MODE_CLRMSK (0XFFFFFFFEU)
  3634. #define VHA_CR_WM_SOCIF_WDT_CTRL_MODE_NONE (00000000U)
  3635. #define VHA_CR_WM_SOCIF_WDT_CTRL_MODE_ENABLED (0X00000001U)
  3636. /*
  3637. Register VHA_CR_WM_SOCIF_WDT_COMPAREMATCH
  3638. */
  3639. #define VHA_CR_WM_SOCIF_WDT_COMPAREMATCH (0x10138U)
  3640. #define VHA_CR_WM_SOCIF_WDT_COMPAREMATCH_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  3641. #define VHA_CR_WM_SOCIF_WDT_COMPAREMATCH_VALUE_SHIFT (0U)
  3642. #define VHA_CR_WM_SOCIF_WDT_COMPAREMATCH_VALUE_CLRMSK (00000000U)
  3643. /*
  3644. Register VHA_CR_WM_SOCIF_WDT_TIMER
  3645. */
  3646. #define VHA_CR_WM_SOCIF_WDT_TIMER (0x10140U)
  3647. #define VHA_CR_WM_SOCIF_WDT_TIMER_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  3648. #define VHA_CR_WM_SOCIF_WDT_TIMER_VALUE_SHIFT (0U)
  3649. #define VHA_CR_WM_SOCIF_WDT_TIMER_VALUE_CLRMSK (00000000U)
  3650. /*
  3651. Register VHA_CR_WM_RESPONSE_FIFO_READ
  3652. */
  3653. #define VHA_CR_WM_RESPONSE_FIFO_READ (0x101F8U)
  3654. #define VHA_CR_WM_RESPONSE_FIFO_READ_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  3655. #define VHA_CR_WM_RESPONSE_FIFO_READ_FIFO_READ_SHIFT (0U)
  3656. #define VHA_CR_WM_RESPONSE_FIFO_READ_FIFO_READ_CLRMSK (0XFFFFFFFEU)
  3657. #define VHA_CR_WM_RESPONSE_FIFO_READ_FIFO_READ_EN (0X00000001U)
  3658. /*
  3659. Register VHA_CR_WM_RESPONSE_FIFO_WL_ID
  3660. */
  3661. #define VHA_CR_WM_RESPONSE_FIFO_WL_ID (0x10200U)
  3662. #define VHA_CR_WM_RESPONSE_FIFO_WL_ID_MASKFULL (IMG_UINT64_C(0x000000000000FFFF))
  3663. #define VHA_CR_WM_RESPONSE_FIFO_WL_ID_WL_ID_SHIFT (0U)
  3664. #define VHA_CR_WM_RESPONSE_FIFO_WL_ID_WL_ID_CLRMSK (0XFFFF0000U)
  3665. #define VHA_CR_WM_RESPONSE_FIFO_WL_STATUS_WL_ERROR_CODE_MASK (0x0000000FU)
  3666. /*
  3667. Workload was not kicked because an interrupt was raised from a core before start, FAILED_CORE_IDX indicates the core associated with the error.*/
  3668. #define VHA_CR_WM_RESPONSE_FIFO_WL_STATUS_WL_ERROR_CODE_CORE_IRQ_BEFORE_KICK (0x00000000U)
  3669. /*
  3670. Error while read-back CORE_MASK for multi-cast kick*/
  3671. #define VHA_CR_WM_RESPONSE_FIFO_WL_STATUS_WL_ERROR_CODE_INDIRECT_MASK_SET_ERROR (0x00000001U)
  3672. /*
  3673. Error while read-back CORE_MASK for single-core checks, FAILED_CORE_IDX indicates the core associated with the error.*/
  3674. #define VHA_CR_WM_RESPONSE_FIFO_WL_STATUS_WL_ERROR_CODE_KICK_CORE_ACCESS_ERROR (0x00000002U)
  3675. /*
  3676. Error while checking VHA_CR_OS0_CNN_CONTROL.START, FAILED_CORE_IDX indicates the core associated with the error.*/
  3677. #define VHA_CR_WM_RESPONSE_FIFO_WL_STATUS_WL_ERROR_CODE_CNN_CONTROL_START_HIGH (0x00000003U)
  3678. /*
  3679. Error while checking VHA_CR_OS0_CNN_STATUS, FAILED_CORE_IDX indicates the core associated with the error.*/
  3680. #define VHA_CR_WM_RESPONSE_FIFO_WL_STATUS_WL_ERROR_CODE_CNN_STATUS_ERROR (0x00000004U)
  3681. /*
  3682. Error while read-back CORE_MASK for single-core checks, FAILED_CORE_IDX indicates the core associated with the error.*/
  3683. #define VHA_CR_WM_RESPONSE_FIFO_WL_STATUS_WL_ERROR_CODE_INT_CORE_ACCESS_ERROR (0x00000005U)
  3684. /*
  3685. Error while checking VHA_CR_CORE_EVENT_WM_STATUS before clear, FAILED_CORE_IDX indicates the core associated with the error.*/
  3686. #define VHA_CR_WM_RESPONSE_FIFO_WL_STATUS_WL_ERROR_CODE_CORE_EVENT_ERROR (0x00000006U)
  3687. /*
  3688. Error while checking VHA_CR_CORE_EVENT_WM_STATUS after clear, FAILED_CORE_IDX indicates the core associated with the error.*/
  3689. #define VHA_CR_WM_RESPONSE_FIFO_WL_STATUS_WL_ERROR_CODE_CORE_EVENT_NOT_CLEARED (0x00000007U)
  3690. /*
  3691. Error while checking IRQ signal after clear, FAILED_CORE_IDX indicates the core associated with the error.*/
  3692. #define VHA_CR_WM_RESPONSE_FIFO_WL_STATUS_WL_ERROR_CODE_CORE_EVENT_IRQ_HIGH (0x00000008U)
  3693. /*
  3694. Detected an error in the interconnect parity or on lockstep cores, FAILED_CORE_IDX indicates the core associated with the error.*/
  3695. #define VHA_CR_WM_RESPONSE_FIFO_WL_STATUS_WL_ERROR_CODE_INTERCONNECT_ERROR (0x00000009U)
  3696. /*
  3697. Register VHA_CR_WM_RESPONSE_FIFO_WL_STATUS
  3698. */
  3699. #define VHA_CR_WM_RESPONSE_FIFO_WL_STATUS (0x10208U)
  3700. #define VHA_CR_WM_RESPONSE_FIFO_WL_STATUS_MASKFULL (IMG_UINT64_C(0x00000000800007F3))
  3701. #define VHA_CR_WM_RESPONSE_FIFO_WL_STATUS_PARITY_SHIFT (31U)
  3702. #define VHA_CR_WM_RESPONSE_FIFO_WL_STATUS_PARITY_CLRMSK (0X7FFFFFFFU)
  3703. #define VHA_CR_WM_RESPONSE_FIFO_WL_STATUS_PARITY_EN (0X80000000U)
  3704. #define VHA_CR_WM_RESPONSE_FIFO_WL_STATUS_FAILED_CORE_IDX_SHIFT (8U)
  3705. #define VHA_CR_WM_RESPONSE_FIFO_WL_STATUS_FAILED_CORE_IDX_CLRMSK (0XFFFFF8FFU)
  3706. #define VHA_CR_WM_RESPONSE_FIFO_WL_STATUS_ERROR_CODE_SHIFT (4U)
  3707. #define VHA_CR_WM_RESPONSE_FIFO_WL_STATUS_ERROR_CODE_CLRMSK (0XFFFFFF0FU)
  3708. #define VHA_CR_WM_RESPONSE_FIFO_WL_STATUS_ERROR_CODE_CORE_IRQ_BEFORE_KICK (00000000U)
  3709. #define VHA_CR_WM_RESPONSE_FIFO_WL_STATUS_ERROR_CODE_INDIRECT_MASK_SET_ERROR (0X00000010U)
  3710. #define VHA_CR_WM_RESPONSE_FIFO_WL_STATUS_ERROR_CODE_KICK_CORE_ACCESS_ERROR (0X00000020U)
  3711. #define VHA_CR_WM_RESPONSE_FIFO_WL_STATUS_ERROR_CODE_CNN_CONTROL_START_HIGH (0X00000030U)
  3712. #define VHA_CR_WM_RESPONSE_FIFO_WL_STATUS_ERROR_CODE_CNN_STATUS_ERROR (0X00000040U)
  3713. #define VHA_CR_WM_RESPONSE_FIFO_WL_STATUS_ERROR_CODE_INT_CORE_ACCESS_ERROR (0X00000050U)
  3714. #define VHA_CR_WM_RESPONSE_FIFO_WL_STATUS_ERROR_CODE_CORE_EVENT_ERROR (0X00000060U)
  3715. #define VHA_CR_WM_RESPONSE_FIFO_WL_STATUS_ERROR_CODE_CORE_EVENT_NOT_CLEARED (0X00000070U)
  3716. #define VHA_CR_WM_RESPONSE_FIFO_WL_STATUS_ERROR_CODE_CORE_EVENT_IRQ_HIGH (0X00000080U)
  3717. #define VHA_CR_WM_RESPONSE_FIFO_WL_STATUS_ERROR_CODE_INTERCONNECT_ERROR (0X00000090U)
  3718. #define VHA_CR_WM_RESPONSE_FIFO_WL_STATUS_WL_FAILURE_SHIFT (1U)
  3719. #define VHA_CR_WM_RESPONSE_FIFO_WL_STATUS_WL_FAILURE_CLRMSK (0XFFFFFFFDU)
  3720. #define VHA_CR_WM_RESPONSE_FIFO_WL_STATUS_WL_FAILURE_EN (0X00000002U)
  3721. #define VHA_CR_WM_RESPONSE_FIFO_WL_STATUS_SUCCESS_SHIFT (0U)
  3722. #define VHA_CR_WM_RESPONSE_FIFO_WL_STATUS_SUCCESS_CLRMSK (0XFFFFFFFEU)
  3723. #define VHA_CR_WM_RESPONSE_FIFO_WL_STATUS_SUCCESS_EN (0X00000001U)
  3724. /*
  3725. Register VHA_CR_WM_RESPONSE_FIFO_WL_PERF
  3726. */
  3727. #define VHA_CR_WM_RESPONSE_FIFO_WL_PERF (0x10210U)
  3728. #define VHA_CR_WM_RESPONSE_FIFO_WL_PERF_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  3729. #define VHA_CR_WM_RESPONSE_FIFO_WL_PERF_CYCLES_SHIFT (0U)
  3730. #define VHA_CR_WM_RESPONSE_FIFO_WL_PERF_CYCLES_CLRMSK (00000000U)
  3731. /*
  3732. Register VHA_CR_WM_RESPONSE_FIFO_WL_BW_LOCM_RD
  3733. */
  3734. #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_LOCM_RD (0x10218U)
  3735. #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_LOCM_RD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  3736. #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_LOCM_RD_BW_SHIFT (0U)
  3737. #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_LOCM_RD_BW_CLRMSK (00000000U)
  3738. /*
  3739. Register VHA_CR_WM_RESPONSE_FIFO_WL_BW_LOCM_WR
  3740. */
  3741. #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_LOCM_WR (0x10220U)
  3742. #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_LOCM_WR_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  3743. #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_LOCM_WR_BW_SHIFT (0U)
  3744. #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_LOCM_WR_BW_CLRMSK (00000000U)
  3745. /*
  3746. Register VHA_CR_WM_RESPONSE_FIFO_WL_BW_LOCM_MWR
  3747. */
  3748. #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_LOCM_MWR (0x10228U)
  3749. #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_LOCM_MWR_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  3750. #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_LOCM_MWR_BW_SHIFT (0U)
  3751. #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_LOCM_MWR_BW_CLRMSK (00000000U)
  3752. /*
  3753. Register VHA_CR_WM_RESPONSE_FIFO_WL_BW_SOCM_RD
  3754. */
  3755. #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_SOCM_RD (0x10230U)
  3756. #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_SOCM_RD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  3757. #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_SOCM_RD_BW_SHIFT (0U)
  3758. #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_SOCM_RD_BW_CLRMSK (00000000U)
  3759. /*
  3760. Register VHA_CR_WM_RESPONSE_FIFO_WL_BW_SOCM_WR
  3761. */
  3762. #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_SOCM_WR (0x10238U)
  3763. #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_SOCM_WR_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  3764. #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_SOCM_WR_BW_SHIFT (0U)
  3765. #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_SOCM_WR_BW_CLRMSK (00000000U)
  3766. /*
  3767. Register VHA_CR_WM_RESPONSE_FIFO_WL_BW_SOCM_MWR
  3768. */
  3769. #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_SOCM_MWR (0x10240U)
  3770. #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_SOCM_MWR_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  3771. #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_SOCM_MWR_BW_SHIFT (0U)
  3772. #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_SOCM_MWR_BW_CLRMSK (00000000U)
  3773. /*
  3774. Register VHA_CR_WM_RESPONSE_FIFO_WL_BW_DDR_RD
  3775. */
  3776. #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_DDR_RD (0x10248U)
  3777. #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_DDR_RD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  3778. #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_DDR_RD_BW_SHIFT (0U)
  3779. #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_DDR_RD_BW_CLRMSK (00000000U)
  3780. /*
  3781. Register VHA_CR_WM_RESPONSE_FIFO_WL_BW_DDR_WR
  3782. */
  3783. #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_DDR_WR (0x10250U)
  3784. #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_DDR_WR_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  3785. #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_DDR_WR_BW_SHIFT (0U)
  3786. #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_DDR_WR_BW_CLRMSK (00000000U)
  3787. /*
  3788. Register VHA_CR_WM_RESPONSE_FIFO_WL_BW_DDR_MWR
  3789. */
  3790. #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_DDR_MWR (0x10258U)
  3791. #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_DDR_MWR_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  3792. #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_DDR_MWR_BW_SHIFT (0U)
  3793. #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_DDR_MWR_BW_CLRMSK (00000000U)
  3794. /*
  3795. Register VHA_CR_WM_RESPONSE_FIFO_WL_BW_LOCM_RD_WORD
  3796. */
  3797. #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_LOCM_RD_WORD (0x10260U)
  3798. #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_LOCM_RD_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  3799. #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_LOCM_RD_WORD_BW_SHIFT (0U)
  3800. #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_LOCM_RD_WORD_BW_CLRMSK (00000000U)
  3801. /*
  3802. Register VHA_CR_WM_RESPONSE_FIFO_WL_BW_LOCM_WR_WORD
  3803. */
  3804. #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_LOCM_WR_WORD (0x10268U)
  3805. #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_LOCM_WR_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  3806. #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_LOCM_WR_WORD_BW_SHIFT (0U)
  3807. #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_LOCM_WR_WORD_BW_CLRMSK (00000000U)
  3808. /*
  3809. Register VHA_CR_WM_RESPONSE_FIFO_WL_BW_SOCM_RD_WORD
  3810. */
  3811. #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_SOCM_RD_WORD (0x10270U)
  3812. #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_SOCM_RD_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  3813. #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_SOCM_RD_WORD_BW_SHIFT (0U)
  3814. #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_SOCM_RD_WORD_BW_CLRMSK (00000000U)
  3815. /*
  3816. Register VHA_CR_WM_RESPONSE_FIFO_WL_BW_SOCM_WR_WORD
  3817. */
  3818. #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_SOCM_WR_WORD (0x10278U)
  3819. #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_SOCM_WR_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  3820. #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_SOCM_WR_WORD_BW_SHIFT (0U)
  3821. #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_SOCM_WR_WORD_BW_CLRMSK (00000000U)
  3822. /*
  3823. Register VHA_CR_WM_RESPONSE_FIFO_WL_BW_DDR_RD_WORD
  3824. */
  3825. #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_DDR_RD_WORD (0x10280U)
  3826. #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_DDR_RD_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  3827. #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_DDR_RD_WORD_BW_SHIFT (0U)
  3828. #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_DDR_RD_WORD_BW_CLRMSK (00000000U)
  3829. /*
  3830. Register VHA_CR_WM_RESPONSE_FIFO_WL_BW_DDR_WR_WORD
  3831. */
  3832. #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_DDR_WR_WORD (0x10288U)
  3833. #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_DDR_WR_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  3834. #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_DDR_WR_WORD_BW_SHIFT (0U)
  3835. #define VHA_CR_WM_RESPONSE_FIFO_WL_BW_DDR_WR_WORD_BW_CLRMSK (00000000U)
  3836. #define VHA_CR_MH_CONTROL_MAX_BURST_LENGTH_MASK (0x00000003U)
  3837. /*
  3838. Register VHA_CR_CORE_MASK
  3839. */
  3840. #define VHA_CR_CORE_MASK (0x20000U)
  3841. #define VHA_CR_CORE_MASK_MASKFULL (IMG_UINT64_C(0x00000000000000FF))
  3842. #define VHA_CR_CORE_MASK_CORE_MASK_SHIFT (0U)
  3843. #define VHA_CR_CORE_MASK_CORE_MASK_CLRMSK (0XFFFFFF00U)
  3844. #define VHA_CR_CLK_CTRL0_MODE_MASK (0x00000003U)
  3845. /*
  3846. The domain clock is forced off */
  3847. #define VHA_CR_CLK_CTRL0_MODE_OFF (0x00000000U)
  3848. /*
  3849. The domain clock is forced on */
  3850. #define VHA_CR_CLK_CTRL0_MODE_ON (0x00000001U)
  3851. /*
  3852. Automatic clock gating is active, the domain clock is only on whilst data is being processed */
  3853. #define VHA_CR_CLK_CTRL0_MODE_AUTO (0x00000002U)
  3854. /*
  3855. Register VHA_CR_CLK_CTRL0
  3856. */
  3857. #define VHA_CR_CLK_CTRL0 (0x20100U)
  3858. #define VHA_CR_CLK_CTRL0_MASKFULL (IMG_UINT64_C(0xF3FFFFFF3F00FF33))
  3859. #define VHA_CR_CLK_CTRL0_CNN_CORE_XBAR_SHIFT (62U)
  3860. #define VHA_CR_CLK_CTRL0_CNN_CORE_XBAR_CLRMSK (IMG_UINT64_C(0X3FFFFFFFFFFFFFFF))
  3861. #define VHA_CR_CLK_CTRL0_CNN_CORE_XBAR_OFF (IMG_UINT64_C(0000000000000000))
  3862. #define VHA_CR_CLK_CTRL0_CNN_CORE_XBAR_ON (IMG_UINT64_C(0x4000000000000000))
  3863. #define VHA_CR_CLK_CTRL0_CNN_CORE_XBAR_AUTO (IMG_UINT64_C(0x8000000000000000))
  3864. #define VHA_CR_CLK_CTRL0_CNN_MMM_SHIFT (60U)
  3865. #define VHA_CR_CLK_CTRL0_CNN_MMM_CLRMSK (IMG_UINT64_C(0XCFFFFFFFFFFFFFFF))
  3866. #define VHA_CR_CLK_CTRL0_CNN_MMM_OFF (IMG_UINT64_C(0000000000000000))
  3867. #define VHA_CR_CLK_CTRL0_CNN_MMM_ON (IMG_UINT64_C(0x1000000000000000))
  3868. #define VHA_CR_CLK_CTRL0_CNN_MMM_AUTO (IMG_UINT64_C(0x2000000000000000))
  3869. #define VHA_CR_CLK_CTRL0_CNN_EWO_SHIFT (56U)
  3870. #define VHA_CR_CLK_CTRL0_CNN_EWO_CLRMSK (IMG_UINT64_C(0XFCFFFFFFFFFFFFFF))
  3871. #define VHA_CR_CLK_CTRL0_CNN_EWO_OFF (IMG_UINT64_C(0000000000000000))
  3872. #define VHA_CR_CLK_CTRL0_CNN_EWO_ON (IMG_UINT64_C(0x0100000000000000))
  3873. #define VHA_CR_CLK_CTRL0_CNN_EWO_AUTO (IMG_UINT64_C(0x0200000000000000))
  3874. #define VHA_CR_CLK_CTRL0_CNN_PACK_SHIFT (54U)
  3875. #define VHA_CR_CLK_CTRL0_CNN_PACK_CLRMSK (IMG_UINT64_C(0XFF3FFFFFFFFFFFFF))
  3876. #define VHA_CR_CLK_CTRL0_CNN_PACK_OFF (IMG_UINT64_C(0000000000000000))
  3877. #define VHA_CR_CLK_CTRL0_CNN_PACK_ON (IMG_UINT64_C(0x0040000000000000))
  3878. #define VHA_CR_CLK_CTRL0_CNN_PACK_AUTO (IMG_UINT64_C(0x0080000000000000))
  3879. #define VHA_CR_CLK_CTRL0_CNN_OIN_SHIFT (52U)
  3880. #define VHA_CR_CLK_CTRL0_CNN_OIN_CLRMSK (IMG_UINT64_C(0XFFCFFFFFFFFFFFFF))
  3881. #define VHA_CR_CLK_CTRL0_CNN_OIN_OFF (IMG_UINT64_C(0000000000000000))
  3882. #define VHA_CR_CLK_CTRL0_CNN_OIN_ON (IMG_UINT64_C(0x0010000000000000))
  3883. #define VHA_CR_CLK_CTRL0_CNN_OIN_AUTO (IMG_UINT64_C(0x0020000000000000))
  3884. #define VHA_CR_CLK_CTRL0_CNN_POOL_SHIFT (50U)
  3885. #define VHA_CR_CLK_CTRL0_CNN_POOL_CLRMSK (IMG_UINT64_C(0XFFF3FFFFFFFFFFFF))
  3886. #define VHA_CR_CLK_CTRL0_CNN_POOL_OFF (IMG_UINT64_C(0000000000000000))
  3887. #define VHA_CR_CLK_CTRL0_CNN_POOL_ON (IMG_UINT64_C(0x0004000000000000))
  3888. #define VHA_CR_CLK_CTRL0_CNN_POOL_AUTO (IMG_UINT64_C(0x0008000000000000))
  3889. #define VHA_CR_CLK_CTRL0_CNN_SB_SHIFT (48U)
  3890. #define VHA_CR_CLK_CTRL0_CNN_SB_CLRMSK (IMG_UINT64_C(0XFFFCFFFFFFFFFFFF))
  3891. #define VHA_CR_CLK_CTRL0_CNN_SB_OFF (IMG_UINT64_C(0000000000000000))
  3892. #define VHA_CR_CLK_CTRL0_CNN_SB_ON (IMG_UINT64_C(0x0001000000000000))
  3893. #define VHA_CR_CLK_CTRL0_CNN_SB_AUTO (IMG_UINT64_C(0x0002000000000000))
  3894. #define VHA_CR_CLK_CTRL0_CNN_XBAR_SHIFT (46U)
  3895. #define VHA_CR_CLK_CTRL0_CNN_XBAR_CLRMSK (IMG_UINT64_C(0XFFFF3FFFFFFFFFFF))
  3896. #define VHA_CR_CLK_CTRL0_CNN_XBAR_OFF (IMG_UINT64_C(0000000000000000))
  3897. #define VHA_CR_CLK_CTRL0_CNN_XBAR_ON (IMG_UINT64_C(0x0000400000000000))
  3898. #define VHA_CR_CLK_CTRL0_CNN_XBAR_AUTO (IMG_UINT64_C(0x0000800000000000))
  3899. #define VHA_CR_CLK_CTRL0_CNN_NORM_SHIFT (44U)
  3900. #define VHA_CR_CLK_CTRL0_CNN_NORM_CLRMSK (IMG_UINT64_C(0XFFFFCFFFFFFFFFFF))
  3901. #define VHA_CR_CLK_CTRL0_CNN_NORM_OFF (IMG_UINT64_C(0000000000000000))
  3902. #define VHA_CR_CLK_CTRL0_CNN_NORM_ON (IMG_UINT64_C(0x0000100000000000))
  3903. #define VHA_CR_CLK_CTRL0_CNN_NORM_AUTO (IMG_UINT64_C(0x0000200000000000))
  3904. #define VHA_CR_CLK_CTRL0_CNN_ACT_SHIFT (42U)
  3905. #define VHA_CR_CLK_CTRL0_CNN_ACT_CLRMSK (IMG_UINT64_C(0XFFFFF3FFFFFFFFFF))
  3906. #define VHA_CR_CLK_CTRL0_CNN_ACT_OFF (IMG_UINT64_C(0000000000000000))
  3907. #define VHA_CR_CLK_CTRL0_CNN_ACT_ON (IMG_UINT64_C(0x0000040000000000))
  3908. #define VHA_CR_CLK_CTRL0_CNN_ACT_AUTO (IMG_UINT64_C(0x0000080000000000))
  3909. #define VHA_CR_CLK_CTRL0_CNN_ACCUM_SHIFT (40U)
  3910. #define VHA_CR_CLK_CTRL0_CNN_ACCUM_CLRMSK (IMG_UINT64_C(0XFFFFFCFFFFFFFFFF))
  3911. #define VHA_CR_CLK_CTRL0_CNN_ACCUM_OFF (IMG_UINT64_C(0000000000000000))
  3912. #define VHA_CR_CLK_CTRL0_CNN_ACCUM_ON (IMG_UINT64_C(0x0000010000000000))
  3913. #define VHA_CR_CLK_CTRL0_CNN_ACCUM_AUTO (IMG_UINT64_C(0x0000020000000000))
  3914. #define VHA_CR_CLK_CTRL0_CNN_CNV_SHIFT (38U)
  3915. #define VHA_CR_CLK_CTRL0_CNN_CNV_CLRMSK (IMG_UINT64_C(0XFFFFFF3FFFFFFFFF))
  3916. #define VHA_CR_CLK_CTRL0_CNN_CNV_OFF (IMG_UINT64_C(0000000000000000))
  3917. #define VHA_CR_CLK_CTRL0_CNN_CNV_ON (IMG_UINT64_C(0x0000004000000000))
  3918. #define VHA_CR_CLK_CTRL0_CNN_CNV_AUTO (IMG_UINT64_C(0x0000008000000000))
  3919. #define VHA_CR_CLK_CTRL0_CNN_CBUF_SHIFT (36U)
  3920. #define VHA_CR_CLK_CTRL0_CNN_CBUF_CLRMSK (IMG_UINT64_C(0XFFFFFFCFFFFFFFFF))
  3921. #define VHA_CR_CLK_CTRL0_CNN_CBUF_OFF (IMG_UINT64_C(0000000000000000))
  3922. #define VHA_CR_CLK_CTRL0_CNN_CBUF_ON (IMG_UINT64_C(0x0000001000000000))
  3923. #define VHA_CR_CLK_CTRL0_CNN_CBUF_AUTO (IMG_UINT64_C(0x0000002000000000))
  3924. #define VHA_CR_CLK_CTRL0_CNN_IBUF_SHIFT (34U)
  3925. #define VHA_CR_CLK_CTRL0_CNN_IBUF_CLRMSK (IMG_UINT64_C(0XFFFFFFF3FFFFFFFF))
  3926. #define VHA_CR_CLK_CTRL0_CNN_IBUF_OFF (IMG_UINT64_C(0000000000000000))
  3927. #define VHA_CR_CLK_CTRL0_CNN_IBUF_ON (IMG_UINT64_C(0x0000000400000000))
  3928. #define VHA_CR_CLK_CTRL0_CNN_IBUF_AUTO (IMG_UINT64_C(0x0000000800000000))
  3929. #define VHA_CR_CLK_CTRL0_CNN_CMD_SHIFT (32U)
  3930. #define VHA_CR_CLK_CTRL0_CNN_CMD_CLRMSK (IMG_UINT64_C(0XFFFFFFFCFFFFFFFF))
  3931. #define VHA_CR_CLK_CTRL0_CNN_CMD_OFF (IMG_UINT64_C(0000000000000000))
  3932. #define VHA_CR_CLK_CTRL0_CNN_CMD_ON (IMG_UINT64_C(0x0000000100000000))
  3933. #define VHA_CR_CLK_CTRL0_CNN_CMD_AUTO (IMG_UINT64_C(0x0000000200000000))
  3934. #define VHA_CR_CLK_CTRL0_CNN_SHIFT (28U)
  3935. #define VHA_CR_CLK_CTRL0_CNN_CLRMSK (IMG_UINT64_C(0XFFFFFFFFCFFFFFFF))
  3936. #define VHA_CR_CLK_CTRL0_CNN_OFF (IMG_UINT64_C(0000000000000000))
  3937. #define VHA_CR_CLK_CTRL0_CNN_ON (IMG_UINT64_C(0x0000000010000000))
  3938. #define VHA_CR_CLK_CTRL0_CNN_AUTO (IMG_UINT64_C(0x0000000020000000))
  3939. #define VHA_CR_CLK_CTRL0_CNN_TRS_A_SHIFT (26U)
  3940. #define VHA_CR_CLK_CTRL0_CNN_TRS_A_CLRMSK (IMG_UINT64_C(0XFFFFFFFFF3FFFFFF))
  3941. #define VHA_CR_CLK_CTRL0_CNN_TRS_A_OFF (IMG_UINT64_C(0000000000000000))
  3942. #define VHA_CR_CLK_CTRL0_CNN_TRS_A_ON (IMG_UINT64_C(0x0000000004000000))
  3943. #define VHA_CR_CLK_CTRL0_CNN_TRS_A_AUTO (IMG_UINT64_C(0x0000000008000000))
  3944. #define VHA_CR_CLK_CTRL0_CNN_TRS_B_SHIFT (24U)
  3945. #define VHA_CR_CLK_CTRL0_CNN_TRS_B_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFCFFFFFF))
  3946. #define VHA_CR_CLK_CTRL0_CNN_TRS_B_OFF (IMG_UINT64_C(0000000000000000))
  3947. #define VHA_CR_CLK_CTRL0_CNN_TRS_B_ON (IMG_UINT64_C(0x0000000001000000))
  3948. #define VHA_CR_CLK_CTRL0_CNN_TRS_B_AUTO (IMG_UINT64_C(0x0000000002000000))
  3949. #define VHA_CR_CLK_CTRL0_MEMBUS_RESET_SHIFT (14U)
  3950. #define VHA_CR_CLK_CTRL0_MEMBUS_RESET_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF3FFF))
  3951. #define VHA_CR_CLK_CTRL0_MEMBUS_RESET_OFF (IMG_UINT64_C(0000000000000000))
  3952. #define VHA_CR_CLK_CTRL0_MEMBUS_RESET_ON (IMG_UINT64_C(0x0000000000004000))
  3953. #define VHA_CR_CLK_CTRL0_MEMBUS_RESET_AUTO (IMG_UINT64_C(0x0000000000008000))
  3954. #define VHA_CR_CLK_CTRL0_BWM_SHIFT (12U)
  3955. #define VHA_CR_CLK_CTRL0_BWM_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFCFFF))
  3956. #define VHA_CR_CLK_CTRL0_BWM_OFF (IMG_UINT64_C(0000000000000000))
  3957. #define VHA_CR_CLK_CTRL0_BWM_ON (IMG_UINT64_C(0x0000000000001000))
  3958. #define VHA_CR_CLK_CTRL0_BWM_AUTO (IMG_UINT64_C(0x0000000000002000))
  3959. #define VHA_CR_CLK_CTRL0_LOCM_SHIFT (10U)
  3960. #define VHA_CR_CLK_CTRL0_LOCM_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF3FF))
  3961. #define VHA_CR_CLK_CTRL0_LOCM_OFF (IMG_UINT64_C(0000000000000000))
  3962. #define VHA_CR_CLK_CTRL0_LOCM_ON (IMG_UINT64_C(0x0000000000000400))
  3963. #define VHA_CR_CLK_CTRL0_LOCM_AUTO (IMG_UINT64_C(0x0000000000000800))
  3964. #define VHA_CR_CLK_CTRL0_NOC_SHIFT (8U)
  3965. #define VHA_CR_CLK_CTRL0_NOC_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFCFF))
  3966. #define VHA_CR_CLK_CTRL0_NOC_OFF (IMG_UINT64_C(0000000000000000))
  3967. #define VHA_CR_CLK_CTRL0_NOC_ON (IMG_UINT64_C(0x0000000000000100))
  3968. #define VHA_CR_CLK_CTRL0_NOC_AUTO (IMG_UINT64_C(0x0000000000000200))
  3969. #define VHA_CR_CLK_CTRL0_ARB_SHIFT (4U)
  3970. #define VHA_CR_CLK_CTRL0_ARB_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFCF))
  3971. #define VHA_CR_CLK_CTRL0_ARB_OFF (IMG_UINT64_C(0000000000000000))
  3972. #define VHA_CR_CLK_CTRL0_ARB_ON (IMG_UINT64_C(0x0000000000000010))
  3973. #define VHA_CR_CLK_CTRL0_ARB_AUTO (IMG_UINT64_C(0x0000000000000020))
  3974. #define VHA_CR_CLK_CTRL0_BIF_SHIFT (0U)
  3975. #define VHA_CR_CLK_CTRL0_BIF_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFC))
  3976. #define VHA_CR_CLK_CTRL0_BIF_OFF (IMG_UINT64_C(0000000000000000))
  3977. #define VHA_CR_CLK_CTRL0_BIF_ON (IMG_UINT64_C(0x0000000000000001))
  3978. #define VHA_CR_CLK_CTRL0_BIF_AUTO (IMG_UINT64_C(0x0000000000000002))
  3979. /*
  3980. Clock is gated and the module is inactive */
  3981. #define VHA_CR_CLK_STATUS0_MODE_GATED (0x00000000U)
  3982. /*
  3983. Clock is running */
  3984. #define VHA_CR_CLK_STATUS0_MODE_RUNNING (0x00000001U)
  3985. /*
  3986. Register VHA_CR_CLK_STATUS0
  3987. */
  3988. #define VHA_CR_CLK_STATUS0 (0x20108U)
  3989. #define VHA_CR_CLK_STATUS0_MASKFULL (IMG_UINT64_C(0x00000037FFDC1F04))
  3990. #define VHA_CR_CLK_STATUS0_CNN_CORE_XBAR_SHIFT (37U)
  3991. #define VHA_CR_CLK_STATUS0_CNN_CORE_XBAR_CLRMSK (IMG_UINT64_C(0XFFFFFFDFFFFFFFFF))
  3992. #define VHA_CR_CLK_STATUS0_CNN_CORE_XBAR_GATED (IMG_UINT64_C(0000000000000000))
  3993. #define VHA_CR_CLK_STATUS0_CNN_CORE_XBAR_RUNNING (IMG_UINT64_C(0x0000002000000000))
  3994. #define VHA_CR_CLK_STATUS0_CNN_MMM_SHIFT (36U)
  3995. #define VHA_CR_CLK_STATUS0_CNN_MMM_CLRMSK (IMG_UINT64_C(0XFFFFFFEFFFFFFFFF))
  3996. #define VHA_CR_CLK_STATUS0_CNN_MMM_GATED (IMG_UINT64_C(0000000000000000))
  3997. #define VHA_CR_CLK_STATUS0_CNN_MMM_RUNNING (IMG_UINT64_C(0x0000001000000000))
  3998. #define VHA_CR_CLK_STATUS0_CNN_EWO_SHIFT (34U)
  3999. #define VHA_CR_CLK_STATUS0_CNN_EWO_CLRMSK (IMG_UINT64_C(0XFFFFFFFBFFFFFFFF))
  4000. #define VHA_CR_CLK_STATUS0_CNN_EWO_GATED (IMG_UINT64_C(0000000000000000))
  4001. #define VHA_CR_CLK_STATUS0_CNN_EWO_RUNNING (IMG_UINT64_C(0x0000000400000000))
  4002. #define VHA_CR_CLK_STATUS0_CNN_PACK_SHIFT (33U)
  4003. #define VHA_CR_CLK_STATUS0_CNN_PACK_CLRMSK (IMG_UINT64_C(0XFFFFFFFDFFFFFFFF))
  4004. #define VHA_CR_CLK_STATUS0_CNN_PACK_GATED (IMG_UINT64_C(0000000000000000))
  4005. #define VHA_CR_CLK_STATUS0_CNN_PACK_RUNNING (IMG_UINT64_C(0x0000000200000000))
  4006. #define VHA_CR_CLK_STATUS0_CNN_OIN_SHIFT (32U)
  4007. #define VHA_CR_CLK_STATUS0_CNN_OIN_CLRMSK (IMG_UINT64_C(0XFFFFFFFEFFFFFFFF))
  4008. #define VHA_CR_CLK_STATUS0_CNN_OIN_GATED (IMG_UINT64_C(0000000000000000))
  4009. #define VHA_CR_CLK_STATUS0_CNN_OIN_RUNNING (IMG_UINT64_C(0x0000000100000000))
  4010. #define VHA_CR_CLK_STATUS0_CNN_POOL_SHIFT (31U)
  4011. #define VHA_CR_CLK_STATUS0_CNN_POOL_CLRMSK (IMG_UINT64_C(0XFFFFFFFF7FFFFFFF))
  4012. #define VHA_CR_CLK_STATUS0_CNN_POOL_GATED (IMG_UINT64_C(0000000000000000))
  4013. #define VHA_CR_CLK_STATUS0_CNN_POOL_RUNNING (IMG_UINT64_C(0x0000000080000000))
  4014. #define VHA_CR_CLK_STATUS0_CNN_SB_SHIFT (30U)
  4015. #define VHA_CR_CLK_STATUS0_CNN_SB_CLRMSK (IMG_UINT64_C(0XFFFFFFFFBFFFFFFF))
  4016. #define VHA_CR_CLK_STATUS0_CNN_SB_GATED (IMG_UINT64_C(0000000000000000))
  4017. #define VHA_CR_CLK_STATUS0_CNN_SB_RUNNING (IMG_UINT64_C(0x0000000040000000))
  4018. #define VHA_CR_CLK_STATUS0_CNN_XBAR_SHIFT (29U)
  4019. #define VHA_CR_CLK_STATUS0_CNN_XBAR_CLRMSK (IMG_UINT64_C(0XFFFFFFFFDFFFFFFF))
  4020. #define VHA_CR_CLK_STATUS0_CNN_XBAR_GATED (IMG_UINT64_C(0000000000000000))
  4021. #define VHA_CR_CLK_STATUS0_CNN_XBAR_RUNNING (IMG_UINT64_C(0x0000000020000000))
  4022. #define VHA_CR_CLK_STATUS0_CNN_NORM_SHIFT (28U)
  4023. #define VHA_CR_CLK_STATUS0_CNN_NORM_CLRMSK (IMG_UINT64_C(0XFFFFFFFFEFFFFFFF))
  4024. #define VHA_CR_CLK_STATUS0_CNN_NORM_GATED (IMG_UINT64_C(0000000000000000))
  4025. #define VHA_CR_CLK_STATUS0_CNN_NORM_RUNNING (IMG_UINT64_C(0x0000000010000000))
  4026. #define VHA_CR_CLK_STATUS0_CNN_ACT_SHIFT (27U)
  4027. #define VHA_CR_CLK_STATUS0_CNN_ACT_CLRMSK (IMG_UINT64_C(0XFFFFFFFFF7FFFFFF))
  4028. #define VHA_CR_CLK_STATUS0_CNN_ACT_GATED (IMG_UINT64_C(0000000000000000))
  4029. #define VHA_CR_CLK_STATUS0_CNN_ACT_RUNNING (IMG_UINT64_C(0x0000000008000000))
  4030. #define VHA_CR_CLK_STATUS0_CNN_ACCUM_SHIFT (26U)
  4031. #define VHA_CR_CLK_STATUS0_CNN_ACCUM_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFBFFFFFF))
  4032. #define VHA_CR_CLK_STATUS0_CNN_ACCUM_GATED (IMG_UINT64_C(0000000000000000))
  4033. #define VHA_CR_CLK_STATUS0_CNN_ACCUM_RUNNING (IMG_UINT64_C(0x0000000004000000))
  4034. #define VHA_CR_CLK_STATUS0_CNN_CNV_SHIFT (25U)
  4035. #define VHA_CR_CLK_STATUS0_CNN_CNV_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFDFFFFFF))
  4036. #define VHA_CR_CLK_STATUS0_CNN_CNV_GATED (IMG_UINT64_C(0000000000000000))
  4037. #define VHA_CR_CLK_STATUS0_CNN_CNV_RUNNING (IMG_UINT64_C(0x0000000002000000))
  4038. #define VHA_CR_CLK_STATUS0_CNN_CBUF_SHIFT (24U)
  4039. #define VHA_CR_CLK_STATUS0_CNN_CBUF_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFEFFFFFF))
  4040. #define VHA_CR_CLK_STATUS0_CNN_CBUF_GATED (IMG_UINT64_C(0000000000000000))
  4041. #define VHA_CR_CLK_STATUS0_CNN_CBUF_RUNNING (IMG_UINT64_C(0x0000000001000000))
  4042. #define VHA_CR_CLK_STATUS0_CNN_IBUF_SHIFT (23U)
  4043. #define VHA_CR_CLK_STATUS0_CNN_IBUF_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF7FFFFF))
  4044. #define VHA_CR_CLK_STATUS0_CNN_IBUF_GATED (IMG_UINT64_C(0000000000000000))
  4045. #define VHA_CR_CLK_STATUS0_CNN_IBUF_RUNNING (IMG_UINT64_C(0x0000000000800000))
  4046. #define VHA_CR_CLK_STATUS0_CNN_CMD_SHIFT (22U)
  4047. #define VHA_CR_CLK_STATUS0_CNN_CMD_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFBFFFFF))
  4048. #define VHA_CR_CLK_STATUS0_CNN_CMD_GATED (IMG_UINT64_C(0000000000000000))
  4049. #define VHA_CR_CLK_STATUS0_CNN_CMD_RUNNING (IMG_UINT64_C(0x0000000000400000))
  4050. #define VHA_CR_CLK_STATUS0_CNN_SHIFT (20U)
  4051. #define VHA_CR_CLK_STATUS0_CNN_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFEFFFFF))
  4052. #define VHA_CR_CLK_STATUS0_CNN_GATED (IMG_UINT64_C(0000000000000000))
  4053. #define VHA_CR_CLK_STATUS0_CNN_RUNNING (IMG_UINT64_C(0x0000000000100000))
  4054. #define VHA_CR_CLK_STATUS0_CNN_TRS_A_SHIFT (19U)
  4055. #define VHA_CR_CLK_STATUS0_CNN_TRS_A_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF7FFFF))
  4056. #define VHA_CR_CLK_STATUS0_CNN_TRS_A_GATED (IMG_UINT64_C(0000000000000000))
  4057. #define VHA_CR_CLK_STATUS0_CNN_TRS_A_RUNNING (IMG_UINT64_C(0x0000000000080000))
  4058. #define VHA_CR_CLK_STATUS0_CNN_TRS_B_SHIFT (18U)
  4059. #define VHA_CR_CLK_STATUS0_CNN_TRS_B_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFBFFFF))
  4060. #define VHA_CR_CLK_STATUS0_CNN_TRS_B_GATED (IMG_UINT64_C(0000000000000000))
  4061. #define VHA_CR_CLK_STATUS0_CNN_TRS_B_RUNNING (IMG_UINT64_C(0x0000000000040000))
  4062. #define VHA_CR_CLK_STATUS0_MEMBUS_RESET_SHIFT (12U)
  4063. #define VHA_CR_CLK_STATUS0_MEMBUS_RESET_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFEFFF))
  4064. #define VHA_CR_CLK_STATUS0_MEMBUS_RESET_GATED (IMG_UINT64_C(0000000000000000))
  4065. #define VHA_CR_CLK_STATUS0_MEMBUS_RESET_RUNNING (IMG_UINT64_C(0x0000000000001000))
  4066. #define VHA_CR_CLK_STATUS0_BWM_SHIFT (11U)
  4067. #define VHA_CR_CLK_STATUS0_BWM_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF7FF))
  4068. #define VHA_CR_CLK_STATUS0_BWM_GATED (IMG_UINT64_C(0000000000000000))
  4069. #define VHA_CR_CLK_STATUS0_BWM_RUNNING (IMG_UINT64_C(0x0000000000000800))
  4070. #define VHA_CR_CLK_STATUS0_LOCM_SHIFT (10U)
  4071. #define VHA_CR_CLK_STATUS0_LOCM_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFBFF))
  4072. #define VHA_CR_CLK_STATUS0_LOCM_GATED (IMG_UINT64_C(0000000000000000))
  4073. #define VHA_CR_CLK_STATUS0_LOCM_RUNNING (IMG_UINT64_C(0x0000000000000400))
  4074. #define VHA_CR_CLK_STATUS0_NOC_SHIFT (9U)
  4075. #define VHA_CR_CLK_STATUS0_NOC_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFDFF))
  4076. #define VHA_CR_CLK_STATUS0_NOC_GATED (IMG_UINT64_C(0000000000000000))
  4077. #define VHA_CR_CLK_STATUS0_NOC_RUNNING (IMG_UINT64_C(0x0000000000000200))
  4078. #define VHA_CR_CLK_STATUS0_ARB_SHIFT (8U)
  4079. #define VHA_CR_CLK_STATUS0_ARB_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFEFF))
  4080. #define VHA_CR_CLK_STATUS0_ARB_GATED (IMG_UINT64_C(0000000000000000))
  4081. #define VHA_CR_CLK_STATUS0_ARB_RUNNING (IMG_UINT64_C(0x0000000000000100))
  4082. #define VHA_CR_CLK_STATUS0_BIF_SHIFT (2U)
  4083. #define VHA_CR_CLK_STATUS0_BIF_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFB))
  4084. #define VHA_CR_CLK_STATUS0_BIF_GATED (IMG_UINT64_C(0000000000000000))
  4085. #define VHA_CR_CLK_STATUS0_BIF_RUNNING (IMG_UINT64_C(0x0000000000000004))
  4086. /*
  4087. Register VHA_CR_CORE_SOFT_RESET
  4088. */
  4089. #define VHA_CR_CORE_SOFT_RESET (0x20110U)
  4090. #define VHA_CR_CORE_SOFT_RESET_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  4091. #define VHA_CR_CORE_SOFT_RESET_CORE_RESET_SHIFT (0U)
  4092. #define VHA_CR_CORE_SOFT_RESET_CORE_RESET_CLRMSK (0XFFFFFFFEU)
  4093. #define VHA_CR_CORE_SOFT_RESET_CORE_RESET_EN (0X00000001U)
  4094. /*
  4095. Register VHA_CR_MEMBUS_RESET_CTRL
  4096. */
  4097. #define VHA_CR_MEMBUS_RESET_CTRL (0x20118U)
  4098. #define VHA_CR_MEMBUS_RESET_CTRL_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  4099. #define VHA_CR_MEMBUS_RESET_CTRL_SOFT_RESET_CYCLES_SHIFT (0U)
  4100. #define VHA_CR_MEMBUS_RESET_CTRL_SOFT_RESET_CYCLES_CLRMSK (00000000U)
  4101. #define VHA_CR_CORE_EVENT_TYPE_LOGIC_ERROR_SHIFT (30U)
  4102. #define VHA_CR_CORE_EVENT_TYPE_LOGIC_ERROR_CLRMSK (0XBFFFFFFFU)
  4103. #define VHA_CR_CORE_EVENT_TYPE_LOGIC_ERROR_EN (0X40000000U)
  4104. #define VHA_CR_CORE_EVENT_TYPE_RAM_CORRECTION_SHIFT (29U)
  4105. #define VHA_CR_CORE_EVENT_TYPE_RAM_CORRECTION_CLRMSK (0XDFFFFFFFU)
  4106. #define VHA_CR_CORE_EVENT_TYPE_RAM_CORRECTION_EN (0X20000000U)
  4107. #define VHA_CR_CORE_EVENT_TYPE_RAM_DETECTION_SHIFT (28U)
  4108. #define VHA_CR_CORE_EVENT_TYPE_RAM_DETECTION_CLRMSK (0XEFFFFFFFU)
  4109. #define VHA_CR_CORE_EVENT_TYPE_RAM_DETECTION_EN (0X10000000U)
  4110. #define VHA_CR_CORE_EVENT_TYPE_LOCM_SCRUB_DONE_SHIFT (16U)
  4111. #define VHA_CR_CORE_EVENT_TYPE_LOCM_SCRUB_DONE_CLRMSK (0XFFFEFFFFU)
  4112. #define VHA_CR_CORE_EVENT_TYPE_LOCM_SCRUB_DONE_EN (0X00010000U)
  4113. #define VHA_CR_CORE_EVENT_TYPE_DMR_COMPLETE_SHIFT (11U)
  4114. #define VHA_CR_CORE_EVENT_TYPE_DMR_COMPLETE_CLRMSK (0XFFFFF7FFU)
  4115. #define VHA_CR_CORE_EVENT_TYPE_DMR_COMPLETE_EN (0X00000800U)
  4116. #define VHA_CR_CORE_EVENT_TYPE_CORE_SYNC_ERROR_SHIFT (10U)
  4117. #define VHA_CR_CORE_EVENT_TYPE_CORE_SYNC_ERROR_CLRMSK (0XFFFFFBFFU)
  4118. #define VHA_CR_CORE_EVENT_TYPE_CORE_SYNC_ERROR_EN (0X00000400U)
  4119. #define VHA_CR_CORE_EVENT_TYPE_CORE_WDT_SHIFT (9U)
  4120. #define VHA_CR_CORE_EVENT_TYPE_CORE_WDT_CLRMSK (0XFFFFFDFFU)
  4121. #define VHA_CR_CORE_EVENT_TYPE_CORE_WDT_EN (0X00000200U)
  4122. #define VHA_CR_CORE_EVENT_TYPE_CORE_MEM_WDT_SHIFT (8U)
  4123. #define VHA_CR_CORE_EVENT_TYPE_CORE_MEM_WDT_CLRMSK (0XFFFFFEFFU)
  4124. #define VHA_CR_CORE_EVENT_TYPE_CORE_MEM_WDT_EN (0X00000100U)
  4125. #define VHA_CR_CORE_EVENT_TYPE_RAM_INIT_DONE_SHIFT (3U)
  4126. #define VHA_CR_CORE_EVENT_TYPE_RAM_INIT_DONE_CLRMSK (0XFFFFFFF7U)
  4127. #define VHA_CR_CORE_EVENT_TYPE_RAM_INIT_DONE_EN (0X00000008U)
  4128. #define VHA_CR_CORE_EVENT_TYPE_MEMBUS_RESET_DONE_SHIFT (2U)
  4129. #define VHA_CR_CORE_EVENT_TYPE_MEMBUS_RESET_DONE_CLRMSK (0XFFFFFFFBU)
  4130. #define VHA_CR_CORE_EVENT_TYPE_MEMBUS_RESET_DONE_EN (0X00000004U)
  4131. #define VHA_CR_CORE_EVENT_TYPE_CNN_ERROR_SHIFT (1U)
  4132. #define VHA_CR_CORE_EVENT_TYPE_CNN_ERROR_CLRMSK (0XFFFFFFFDU)
  4133. #define VHA_CR_CORE_EVENT_TYPE_CNN_ERROR_EN (0X00000002U)
  4134. #define VHA_CR_CORE_EVENT_TYPE_CNN_COMPLETE_SHIFT (0U)
  4135. #define VHA_CR_CORE_EVENT_TYPE_CNN_COMPLETE_CLRMSK (0XFFFFFFFEU)
  4136. #define VHA_CR_CORE_EVENT_TYPE_CNN_COMPLETE_EN (0X00000001U)
  4137. #define VHA_CR_CORE_EVENT_STATUS_TYPE_PARITY_SHIFT (31U)
  4138. #define VHA_CR_CORE_EVENT_STATUS_TYPE_PARITY_CLRMSK (0X7FFFFFFFU)
  4139. #define VHA_CR_CORE_EVENT_STATUS_TYPE_PARITY_EN (0X80000000U)
  4140. #define VHA_CR_CORE_EVENT_STATUS_TYPE_LOGIC_ERROR_SHIFT (30U)
  4141. #define VHA_CR_CORE_EVENT_STATUS_TYPE_LOGIC_ERROR_CLRMSK (0XBFFFFFFFU)
  4142. #define VHA_CR_CORE_EVENT_STATUS_TYPE_LOGIC_ERROR_EN (0X40000000U)
  4143. #define VHA_CR_CORE_EVENT_STATUS_TYPE_RAM_CORRECTION_SHIFT (29U)
  4144. #define VHA_CR_CORE_EVENT_STATUS_TYPE_RAM_CORRECTION_CLRMSK (0XDFFFFFFFU)
  4145. #define VHA_CR_CORE_EVENT_STATUS_TYPE_RAM_CORRECTION_EN (0X20000000U)
  4146. #define VHA_CR_CORE_EVENT_STATUS_TYPE_RAM_DETECTION_SHIFT (28U)
  4147. #define VHA_CR_CORE_EVENT_STATUS_TYPE_RAM_DETECTION_CLRMSK (0XEFFFFFFFU)
  4148. #define VHA_CR_CORE_EVENT_STATUS_TYPE_RAM_DETECTION_EN (0X10000000U)
  4149. #define VHA_CR_CORE_EVENT_STATUS_TYPE_LOCM_SCRUB_DONE_SHIFT (16U)
  4150. #define VHA_CR_CORE_EVENT_STATUS_TYPE_LOCM_SCRUB_DONE_CLRMSK (0XFFFEFFFFU)
  4151. #define VHA_CR_CORE_EVENT_STATUS_TYPE_LOCM_SCRUB_DONE_EN (0X00010000U)
  4152. #define VHA_CR_CORE_EVENT_STATUS_TYPE_DMR_COMPLETE_SHIFT (11U)
  4153. #define VHA_CR_CORE_EVENT_STATUS_TYPE_DMR_COMPLETE_CLRMSK (0XFFFFF7FFU)
  4154. #define VHA_CR_CORE_EVENT_STATUS_TYPE_DMR_COMPLETE_EN (0X00000800U)
  4155. #define VHA_CR_CORE_EVENT_STATUS_TYPE_CORE_SYNC_ERROR_SHIFT (10U)
  4156. #define VHA_CR_CORE_EVENT_STATUS_TYPE_CORE_SYNC_ERROR_CLRMSK (0XFFFFFBFFU)
  4157. #define VHA_CR_CORE_EVENT_STATUS_TYPE_CORE_SYNC_ERROR_EN (0X00000400U)
  4158. #define VHA_CR_CORE_EVENT_STATUS_TYPE_CORE_WDT_SHIFT (9U)
  4159. #define VHA_CR_CORE_EVENT_STATUS_TYPE_CORE_WDT_CLRMSK (0XFFFFFDFFU)
  4160. #define VHA_CR_CORE_EVENT_STATUS_TYPE_CORE_WDT_EN (0X00000200U)
  4161. #define VHA_CR_CORE_EVENT_STATUS_TYPE_CORE_MEM_WDT_SHIFT (8U)
  4162. #define VHA_CR_CORE_EVENT_STATUS_TYPE_CORE_MEM_WDT_CLRMSK (0XFFFFFEFFU)
  4163. #define VHA_CR_CORE_EVENT_STATUS_TYPE_CORE_MEM_WDT_EN (0X00000100U)
  4164. #define VHA_CR_CORE_EVENT_STATUS_TYPE_RAM_INIT_DONE_SHIFT (3U)
  4165. #define VHA_CR_CORE_EVENT_STATUS_TYPE_RAM_INIT_DONE_CLRMSK (0XFFFFFFF7U)
  4166. #define VHA_CR_CORE_EVENT_STATUS_TYPE_RAM_INIT_DONE_EN (0X00000008U)
  4167. #define VHA_CR_CORE_EVENT_STATUS_TYPE_MEMBUS_RESET_DONE_SHIFT (2U)
  4168. #define VHA_CR_CORE_EVENT_STATUS_TYPE_MEMBUS_RESET_DONE_CLRMSK (0XFFFFFFFBU)
  4169. #define VHA_CR_CORE_EVENT_STATUS_TYPE_MEMBUS_RESET_DONE_EN (0X00000004U)
  4170. #define VHA_CR_CORE_EVENT_STATUS_TYPE_CNN_ERROR_SHIFT (1U)
  4171. #define VHA_CR_CORE_EVENT_STATUS_TYPE_CNN_ERROR_CLRMSK (0XFFFFFFFDU)
  4172. #define VHA_CR_CORE_EVENT_STATUS_TYPE_CNN_ERROR_EN (0X00000002U)
  4173. #define VHA_CR_CORE_EVENT_STATUS_TYPE_CNN_COMPLETE_SHIFT (0U)
  4174. #define VHA_CR_CORE_EVENT_STATUS_TYPE_CNN_COMPLETE_CLRMSK (0XFFFFFFFEU)
  4175. #define VHA_CR_CORE_EVENT_STATUS_TYPE_CNN_COMPLETE_EN (0X00000001U)
  4176. /*
  4177. Register VHA_CR_CORE_EVENT_HOST_ENABLE
  4178. */
  4179. #define VHA_CR_CORE_EVENT_HOST_ENABLE (0x20120U)
  4180. #define VHA_CR_CORE_EVENT_HOST_ENABLE_MASKFULL (IMG_UINT64_C(0x0000000070010F0F))
  4181. #define VHA_CR_CORE_EVENT_HOST_ENABLE_LOGIC_ERROR_SHIFT (30U)
  4182. #define VHA_CR_CORE_EVENT_HOST_ENABLE_LOGIC_ERROR_CLRMSK (0XBFFFFFFFU)
  4183. #define VHA_CR_CORE_EVENT_HOST_ENABLE_LOGIC_ERROR_EN (0X40000000U)
  4184. #define VHA_CR_CORE_EVENT_HOST_ENABLE_RAM_CORRECTION_SHIFT (29U)
  4185. #define VHA_CR_CORE_EVENT_HOST_ENABLE_RAM_CORRECTION_CLRMSK (0XDFFFFFFFU)
  4186. #define VHA_CR_CORE_EVENT_HOST_ENABLE_RAM_CORRECTION_EN (0X20000000U)
  4187. #define VHA_CR_CORE_EVENT_HOST_ENABLE_RAM_DETECTION_SHIFT (28U)
  4188. #define VHA_CR_CORE_EVENT_HOST_ENABLE_RAM_DETECTION_CLRMSK (0XEFFFFFFFU)
  4189. #define VHA_CR_CORE_EVENT_HOST_ENABLE_RAM_DETECTION_EN (0X10000000U)
  4190. #define VHA_CR_CORE_EVENT_HOST_ENABLE_LOCM_SCRUB_DONE_SHIFT (16U)
  4191. #define VHA_CR_CORE_EVENT_HOST_ENABLE_LOCM_SCRUB_DONE_CLRMSK (0XFFFEFFFFU)
  4192. #define VHA_CR_CORE_EVENT_HOST_ENABLE_LOCM_SCRUB_DONE_EN (0X00010000U)
  4193. #define VHA_CR_CORE_EVENT_HOST_ENABLE_DMR_COMPLETE_SHIFT (11U)
  4194. #define VHA_CR_CORE_EVENT_HOST_ENABLE_DMR_COMPLETE_CLRMSK (0XFFFFF7FFU)
  4195. #define VHA_CR_CORE_EVENT_HOST_ENABLE_DMR_COMPLETE_EN (0X00000800U)
  4196. #define VHA_CR_CORE_EVENT_HOST_ENABLE_CORE_SYNC_ERROR_SHIFT (10U)
  4197. #define VHA_CR_CORE_EVENT_HOST_ENABLE_CORE_SYNC_ERROR_CLRMSK (0XFFFFFBFFU)
  4198. #define VHA_CR_CORE_EVENT_HOST_ENABLE_CORE_SYNC_ERROR_EN (0X00000400U)
  4199. #define VHA_CR_CORE_EVENT_HOST_ENABLE_CORE_WDT_SHIFT (9U)
  4200. #define VHA_CR_CORE_EVENT_HOST_ENABLE_CORE_WDT_CLRMSK (0XFFFFFDFFU)
  4201. #define VHA_CR_CORE_EVENT_HOST_ENABLE_CORE_WDT_EN (0X00000200U)
  4202. #define VHA_CR_CORE_EVENT_HOST_ENABLE_CORE_MEM_WDT_SHIFT (8U)
  4203. #define VHA_CR_CORE_EVENT_HOST_ENABLE_CORE_MEM_WDT_CLRMSK (0XFFFFFEFFU)
  4204. #define VHA_CR_CORE_EVENT_HOST_ENABLE_CORE_MEM_WDT_EN (0X00000100U)
  4205. #define VHA_CR_CORE_EVENT_HOST_ENABLE_RAM_INIT_DONE_SHIFT (3U)
  4206. #define VHA_CR_CORE_EVENT_HOST_ENABLE_RAM_INIT_DONE_CLRMSK (0XFFFFFFF7U)
  4207. #define VHA_CR_CORE_EVENT_HOST_ENABLE_RAM_INIT_DONE_EN (0X00000008U)
  4208. #define VHA_CR_CORE_EVENT_HOST_ENABLE_MEMBUS_RESET_DONE_SHIFT (2U)
  4209. #define VHA_CR_CORE_EVENT_HOST_ENABLE_MEMBUS_RESET_DONE_CLRMSK (0XFFFFFFFBU)
  4210. #define VHA_CR_CORE_EVENT_HOST_ENABLE_MEMBUS_RESET_DONE_EN (0X00000004U)
  4211. #define VHA_CR_CORE_EVENT_HOST_ENABLE_CNN_ERROR_SHIFT (1U)
  4212. #define VHA_CR_CORE_EVENT_HOST_ENABLE_CNN_ERROR_CLRMSK (0XFFFFFFFDU)
  4213. #define VHA_CR_CORE_EVENT_HOST_ENABLE_CNN_ERROR_EN (0X00000002U)
  4214. #define VHA_CR_CORE_EVENT_HOST_ENABLE_CNN_COMPLETE_SHIFT (0U)
  4215. #define VHA_CR_CORE_EVENT_HOST_ENABLE_CNN_COMPLETE_CLRMSK (0XFFFFFFFEU)
  4216. #define VHA_CR_CORE_EVENT_HOST_ENABLE_CNN_COMPLETE_EN (0X00000001U)
  4217. /*
  4218. Register VHA_CR_CORE_EVENT_HOST_STATUS
  4219. */
  4220. #define VHA_CR_CORE_EVENT_HOST_STATUS (0x20128U)
  4221. #define VHA_CR_CORE_EVENT_HOST_STATUS_MASKFULL (IMG_UINT64_C(0x00000000F0010F0F))
  4222. #define VHA_CR_CORE_EVENT_HOST_STATUS_PARITY_SHIFT (31U)
  4223. #define VHA_CR_CORE_EVENT_HOST_STATUS_PARITY_CLRMSK (0X7FFFFFFFU)
  4224. #define VHA_CR_CORE_EVENT_HOST_STATUS_PARITY_EN (0X80000000U)
  4225. #define VHA_CR_CORE_EVENT_HOST_STATUS_LOGIC_ERROR_SHIFT (30U)
  4226. #define VHA_CR_CORE_EVENT_HOST_STATUS_LOGIC_ERROR_CLRMSK (0XBFFFFFFFU)
  4227. #define VHA_CR_CORE_EVENT_HOST_STATUS_LOGIC_ERROR_EN (0X40000000U)
  4228. #define VHA_CR_CORE_EVENT_HOST_STATUS_RAM_CORRECTION_SHIFT (29U)
  4229. #define VHA_CR_CORE_EVENT_HOST_STATUS_RAM_CORRECTION_CLRMSK (0XDFFFFFFFU)
  4230. #define VHA_CR_CORE_EVENT_HOST_STATUS_RAM_CORRECTION_EN (0X20000000U)
  4231. #define VHA_CR_CORE_EVENT_HOST_STATUS_RAM_DETECTION_SHIFT (28U)
  4232. #define VHA_CR_CORE_EVENT_HOST_STATUS_RAM_DETECTION_CLRMSK (0XEFFFFFFFU)
  4233. #define VHA_CR_CORE_EVENT_HOST_STATUS_RAM_DETECTION_EN (0X10000000U)
  4234. #define VHA_CR_CORE_EVENT_HOST_STATUS_LOCM_SCRUB_DONE_SHIFT (16U)
  4235. #define VHA_CR_CORE_EVENT_HOST_STATUS_LOCM_SCRUB_DONE_CLRMSK (0XFFFEFFFFU)
  4236. #define VHA_CR_CORE_EVENT_HOST_STATUS_LOCM_SCRUB_DONE_EN (0X00010000U)
  4237. #define VHA_CR_CORE_EVENT_HOST_STATUS_DMR_COMPLETE_SHIFT (11U)
  4238. #define VHA_CR_CORE_EVENT_HOST_STATUS_DMR_COMPLETE_CLRMSK (0XFFFFF7FFU)
  4239. #define VHA_CR_CORE_EVENT_HOST_STATUS_DMR_COMPLETE_EN (0X00000800U)
  4240. #define VHA_CR_CORE_EVENT_HOST_STATUS_CORE_SYNC_ERROR_SHIFT (10U)
  4241. #define VHA_CR_CORE_EVENT_HOST_STATUS_CORE_SYNC_ERROR_CLRMSK (0XFFFFFBFFU)
  4242. #define VHA_CR_CORE_EVENT_HOST_STATUS_CORE_SYNC_ERROR_EN (0X00000400U)
  4243. #define VHA_CR_CORE_EVENT_HOST_STATUS_CORE_WDT_SHIFT (9U)
  4244. #define VHA_CR_CORE_EVENT_HOST_STATUS_CORE_WDT_CLRMSK (0XFFFFFDFFU)
  4245. #define VHA_CR_CORE_EVENT_HOST_STATUS_CORE_WDT_EN (0X00000200U)
  4246. #define VHA_CR_CORE_EVENT_HOST_STATUS_CORE_MEM_WDT_SHIFT (8U)
  4247. #define VHA_CR_CORE_EVENT_HOST_STATUS_CORE_MEM_WDT_CLRMSK (0XFFFFFEFFU)
  4248. #define VHA_CR_CORE_EVENT_HOST_STATUS_CORE_MEM_WDT_EN (0X00000100U)
  4249. #define VHA_CR_CORE_EVENT_HOST_STATUS_RAM_INIT_DONE_SHIFT (3U)
  4250. #define VHA_CR_CORE_EVENT_HOST_STATUS_RAM_INIT_DONE_CLRMSK (0XFFFFFFF7U)
  4251. #define VHA_CR_CORE_EVENT_HOST_STATUS_RAM_INIT_DONE_EN (0X00000008U)
  4252. #define VHA_CR_CORE_EVENT_HOST_STATUS_MEMBUS_RESET_DONE_SHIFT (2U)
  4253. #define VHA_CR_CORE_EVENT_HOST_STATUS_MEMBUS_RESET_DONE_CLRMSK (0XFFFFFFFBU)
  4254. #define VHA_CR_CORE_EVENT_HOST_STATUS_MEMBUS_RESET_DONE_EN (0X00000004U)
  4255. #define VHA_CR_CORE_EVENT_HOST_STATUS_CNN_ERROR_SHIFT (1U)
  4256. #define VHA_CR_CORE_EVENT_HOST_STATUS_CNN_ERROR_CLRMSK (0XFFFFFFFDU)
  4257. #define VHA_CR_CORE_EVENT_HOST_STATUS_CNN_ERROR_EN (0X00000002U)
  4258. #define VHA_CR_CORE_EVENT_HOST_STATUS_CNN_COMPLETE_SHIFT (0U)
  4259. #define VHA_CR_CORE_EVENT_HOST_STATUS_CNN_COMPLETE_CLRMSK (0XFFFFFFFEU)
  4260. #define VHA_CR_CORE_EVENT_HOST_STATUS_CNN_COMPLETE_EN (0X00000001U)
  4261. /*
  4262. Register VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE
  4263. */
  4264. #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE (0x20178U)
  4265. #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_MASKFULL (IMG_UINT64_C(0x0000000070010F0F))
  4266. #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_LOGIC_ERROR_SHIFT (30U)
  4267. #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_LOGIC_ERROR_CLRMSK (0XBFFFFFFFU)
  4268. #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_LOGIC_ERROR_EN (0X40000000U)
  4269. #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_RAM_CORRECTION_SHIFT (29U)
  4270. #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_RAM_CORRECTION_CLRMSK (0XDFFFFFFFU)
  4271. #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_RAM_CORRECTION_EN (0X20000000U)
  4272. #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_RAM_DETECTION_SHIFT (28U)
  4273. #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_RAM_DETECTION_CLRMSK (0XEFFFFFFFU)
  4274. #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_RAM_DETECTION_EN (0X10000000U)
  4275. #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_LOCM_SCRUB_DONE_SHIFT (16U)
  4276. #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_LOCM_SCRUB_DONE_CLRMSK (0XFFFEFFFFU)
  4277. #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_LOCM_SCRUB_DONE_EN (0X00010000U)
  4278. #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_DMR_COMPLETE_SHIFT (11U)
  4279. #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_DMR_COMPLETE_CLRMSK (0XFFFFF7FFU)
  4280. #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_DMR_COMPLETE_EN (0X00000800U)
  4281. #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_CORE_SYNC_ERROR_SHIFT (10U)
  4282. #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_CORE_SYNC_ERROR_CLRMSK (0XFFFFFBFFU)
  4283. #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_CORE_SYNC_ERROR_EN (0X00000400U)
  4284. #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_CORE_WDT_SHIFT (9U)
  4285. #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_CORE_WDT_CLRMSK (0XFFFFFDFFU)
  4286. #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_CORE_WDT_EN (0X00000200U)
  4287. #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_CORE_MEM_WDT_SHIFT (8U)
  4288. #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_CORE_MEM_WDT_CLRMSK (0XFFFFFEFFU)
  4289. #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_CORE_MEM_WDT_EN (0X00000100U)
  4290. #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_RAM_INIT_DONE_SHIFT (3U)
  4291. #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_RAM_INIT_DONE_CLRMSK (0XFFFFFFF7U)
  4292. #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_RAM_INIT_DONE_EN (0X00000008U)
  4293. #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_MEMBUS_RESET_DONE_SHIFT (2U)
  4294. #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_MEMBUS_RESET_DONE_CLRMSK (0XFFFFFFFBU)
  4295. #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_MEMBUS_RESET_DONE_EN (0X00000004U)
  4296. #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_CNN_ERROR_SHIFT (1U)
  4297. #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_CNN_ERROR_CLRMSK (0XFFFFFFFDU)
  4298. #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_CNN_ERROR_EN (0X00000002U)
  4299. #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_CNN_COMPLETE_SHIFT (0U)
  4300. #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_CNN_COMPLETE_CLRMSK (0XFFFFFFFEU)
  4301. #define VHA_CR_CORE_EVENT_HOST_STATUS_DISABLE_CNN_COMPLETE_EN (0X00000001U)
  4302. /*
  4303. Register VHA_CR_CORE_EVENT_HOST_CLEAR
  4304. */
  4305. #define VHA_CR_CORE_EVENT_HOST_CLEAR (0x20130U)
  4306. #define VHA_CR_CORE_EVENT_HOST_CLEAR_MASKFULL (IMG_UINT64_C(0x0000000070010F0F))
  4307. #define VHA_CR_CORE_EVENT_HOST_CLEAR_LOGIC_ERROR_SHIFT (30U)
  4308. #define VHA_CR_CORE_EVENT_HOST_CLEAR_LOGIC_ERROR_CLRMSK (0XBFFFFFFFU)
  4309. #define VHA_CR_CORE_EVENT_HOST_CLEAR_LOGIC_ERROR_EN (0X40000000U)
  4310. #define VHA_CR_CORE_EVENT_HOST_CLEAR_RAM_CORRECTION_SHIFT (29U)
  4311. #define VHA_CR_CORE_EVENT_HOST_CLEAR_RAM_CORRECTION_CLRMSK (0XDFFFFFFFU)
  4312. #define VHA_CR_CORE_EVENT_HOST_CLEAR_RAM_CORRECTION_EN (0X20000000U)
  4313. #define VHA_CR_CORE_EVENT_HOST_CLEAR_RAM_DETECTION_SHIFT (28U)
  4314. #define VHA_CR_CORE_EVENT_HOST_CLEAR_RAM_DETECTION_CLRMSK (0XEFFFFFFFU)
  4315. #define VHA_CR_CORE_EVENT_HOST_CLEAR_RAM_DETECTION_EN (0X10000000U)
  4316. #define VHA_CR_CORE_EVENT_HOST_CLEAR_LOCM_SCRUB_DONE_SHIFT (16U)
  4317. #define VHA_CR_CORE_EVENT_HOST_CLEAR_LOCM_SCRUB_DONE_CLRMSK (0XFFFEFFFFU)
  4318. #define VHA_CR_CORE_EVENT_HOST_CLEAR_LOCM_SCRUB_DONE_EN (0X00010000U)
  4319. #define VHA_CR_CORE_EVENT_HOST_CLEAR_DMR_COMPLETE_SHIFT (11U)
  4320. #define VHA_CR_CORE_EVENT_HOST_CLEAR_DMR_COMPLETE_CLRMSK (0XFFFFF7FFU)
  4321. #define VHA_CR_CORE_EVENT_HOST_CLEAR_DMR_COMPLETE_EN (0X00000800U)
  4322. #define VHA_CR_CORE_EVENT_HOST_CLEAR_CORE_SYNC_ERROR_SHIFT (10U)
  4323. #define VHA_CR_CORE_EVENT_HOST_CLEAR_CORE_SYNC_ERROR_CLRMSK (0XFFFFFBFFU)
  4324. #define VHA_CR_CORE_EVENT_HOST_CLEAR_CORE_SYNC_ERROR_EN (0X00000400U)
  4325. #define VHA_CR_CORE_EVENT_HOST_CLEAR_CORE_WDT_SHIFT (9U)
  4326. #define VHA_CR_CORE_EVENT_HOST_CLEAR_CORE_WDT_CLRMSK (0XFFFFFDFFU)
  4327. #define VHA_CR_CORE_EVENT_HOST_CLEAR_CORE_WDT_EN (0X00000200U)
  4328. #define VHA_CR_CORE_EVENT_HOST_CLEAR_CORE_MEM_WDT_SHIFT (8U)
  4329. #define VHA_CR_CORE_EVENT_HOST_CLEAR_CORE_MEM_WDT_CLRMSK (0XFFFFFEFFU)
  4330. #define VHA_CR_CORE_EVENT_HOST_CLEAR_CORE_MEM_WDT_EN (0X00000100U)
  4331. #define VHA_CR_CORE_EVENT_HOST_CLEAR_RAM_INIT_DONE_SHIFT (3U)
  4332. #define VHA_CR_CORE_EVENT_HOST_CLEAR_RAM_INIT_DONE_CLRMSK (0XFFFFFFF7U)
  4333. #define VHA_CR_CORE_EVENT_HOST_CLEAR_RAM_INIT_DONE_EN (0X00000008U)
  4334. #define VHA_CR_CORE_EVENT_HOST_CLEAR_MEMBUS_RESET_DONE_SHIFT (2U)
  4335. #define VHA_CR_CORE_EVENT_HOST_CLEAR_MEMBUS_RESET_DONE_CLRMSK (0XFFFFFFFBU)
  4336. #define VHA_CR_CORE_EVENT_HOST_CLEAR_MEMBUS_RESET_DONE_EN (0X00000004U)
  4337. #define VHA_CR_CORE_EVENT_HOST_CLEAR_CNN_ERROR_SHIFT (1U)
  4338. #define VHA_CR_CORE_EVENT_HOST_CLEAR_CNN_ERROR_CLRMSK (0XFFFFFFFDU)
  4339. #define VHA_CR_CORE_EVENT_HOST_CLEAR_CNN_ERROR_EN (0X00000002U)
  4340. #define VHA_CR_CORE_EVENT_HOST_CLEAR_CNN_COMPLETE_SHIFT (0U)
  4341. #define VHA_CR_CORE_EVENT_HOST_CLEAR_CNN_COMPLETE_CLRMSK (0XFFFFFFFEU)
  4342. #define VHA_CR_CORE_EVENT_HOST_CLEAR_CNN_COMPLETE_EN (0X00000001U)
  4343. /*
  4344. Register VHA_CR_CORE_EVENT_WM_ENABLE
  4345. */
  4346. #define VHA_CR_CORE_EVENT_WM_ENABLE (0x20140U)
  4347. #define VHA_CR_CORE_EVENT_WM_ENABLE_MASKFULL (IMG_UINT64_C(0x0000000070010F0F))
  4348. #define VHA_CR_CORE_EVENT_WM_ENABLE_LOGIC_ERROR_SHIFT (30U)
  4349. #define VHA_CR_CORE_EVENT_WM_ENABLE_LOGIC_ERROR_CLRMSK (0XBFFFFFFFU)
  4350. #define VHA_CR_CORE_EVENT_WM_ENABLE_LOGIC_ERROR_EN (0X40000000U)
  4351. #define VHA_CR_CORE_EVENT_WM_ENABLE_RAM_CORRECTION_SHIFT (29U)
  4352. #define VHA_CR_CORE_EVENT_WM_ENABLE_RAM_CORRECTION_CLRMSK (0XDFFFFFFFU)
  4353. #define VHA_CR_CORE_EVENT_WM_ENABLE_RAM_CORRECTION_EN (0X20000000U)
  4354. #define VHA_CR_CORE_EVENT_WM_ENABLE_RAM_DETECTION_SHIFT (28U)
  4355. #define VHA_CR_CORE_EVENT_WM_ENABLE_RAM_DETECTION_CLRMSK (0XEFFFFFFFU)
  4356. #define VHA_CR_CORE_EVENT_WM_ENABLE_RAM_DETECTION_EN (0X10000000U)
  4357. #define VHA_CR_CORE_EVENT_WM_ENABLE_LOCM_SCRUB_DONE_SHIFT (16U)
  4358. #define VHA_CR_CORE_EVENT_WM_ENABLE_LOCM_SCRUB_DONE_CLRMSK (0XFFFEFFFFU)
  4359. #define VHA_CR_CORE_EVENT_WM_ENABLE_LOCM_SCRUB_DONE_EN (0X00010000U)
  4360. #define VHA_CR_CORE_EVENT_WM_ENABLE_DMR_COMPLETE_SHIFT (11U)
  4361. #define VHA_CR_CORE_EVENT_WM_ENABLE_DMR_COMPLETE_CLRMSK (0XFFFFF7FFU)
  4362. #define VHA_CR_CORE_EVENT_WM_ENABLE_DMR_COMPLETE_EN (0X00000800U)
  4363. #define VHA_CR_CORE_EVENT_WM_ENABLE_CORE_SYNC_ERROR_SHIFT (10U)
  4364. #define VHA_CR_CORE_EVENT_WM_ENABLE_CORE_SYNC_ERROR_CLRMSK (0XFFFFFBFFU)
  4365. #define VHA_CR_CORE_EVENT_WM_ENABLE_CORE_SYNC_ERROR_EN (0X00000400U)
  4366. #define VHA_CR_CORE_EVENT_WM_ENABLE_CORE_WDT_SHIFT (9U)
  4367. #define VHA_CR_CORE_EVENT_WM_ENABLE_CORE_WDT_CLRMSK (0XFFFFFDFFU)
  4368. #define VHA_CR_CORE_EVENT_WM_ENABLE_CORE_WDT_EN (0X00000200U)
  4369. #define VHA_CR_CORE_EVENT_WM_ENABLE_CORE_MEM_WDT_SHIFT (8U)
  4370. #define VHA_CR_CORE_EVENT_WM_ENABLE_CORE_MEM_WDT_CLRMSK (0XFFFFFEFFU)
  4371. #define VHA_CR_CORE_EVENT_WM_ENABLE_CORE_MEM_WDT_EN (0X00000100U)
  4372. #define VHA_CR_CORE_EVENT_WM_ENABLE_RAM_INIT_DONE_SHIFT (3U)
  4373. #define VHA_CR_CORE_EVENT_WM_ENABLE_RAM_INIT_DONE_CLRMSK (0XFFFFFFF7U)
  4374. #define VHA_CR_CORE_EVENT_WM_ENABLE_RAM_INIT_DONE_EN (0X00000008U)
  4375. #define VHA_CR_CORE_EVENT_WM_ENABLE_MEMBUS_RESET_DONE_SHIFT (2U)
  4376. #define VHA_CR_CORE_EVENT_WM_ENABLE_MEMBUS_RESET_DONE_CLRMSK (0XFFFFFFFBU)
  4377. #define VHA_CR_CORE_EVENT_WM_ENABLE_MEMBUS_RESET_DONE_EN (0X00000004U)
  4378. #define VHA_CR_CORE_EVENT_WM_ENABLE_CNN_ERROR_SHIFT (1U)
  4379. #define VHA_CR_CORE_EVENT_WM_ENABLE_CNN_ERROR_CLRMSK (0XFFFFFFFDU)
  4380. #define VHA_CR_CORE_EVENT_WM_ENABLE_CNN_ERROR_EN (0X00000002U)
  4381. #define VHA_CR_CORE_EVENT_WM_ENABLE_CNN_COMPLETE_SHIFT (0U)
  4382. #define VHA_CR_CORE_EVENT_WM_ENABLE_CNN_COMPLETE_CLRMSK (0XFFFFFFFEU)
  4383. #define VHA_CR_CORE_EVENT_WM_ENABLE_CNN_COMPLETE_EN (0X00000001U)
  4384. /*
  4385. Register VHA_CR_CORE_EVENT_WM_STATUS
  4386. */
  4387. #define VHA_CR_CORE_EVENT_WM_STATUS (0x20148U)
  4388. #define VHA_CR_CORE_EVENT_WM_STATUS_MASKFULL (IMG_UINT64_C(0x00000000F0010F0F))
  4389. #define VHA_CR_CORE_EVENT_WM_STATUS_PARITY_SHIFT (31U)
  4390. #define VHA_CR_CORE_EVENT_WM_STATUS_PARITY_CLRMSK (0X7FFFFFFFU)
  4391. #define VHA_CR_CORE_EVENT_WM_STATUS_PARITY_EN (0X80000000U)
  4392. #define VHA_CR_CORE_EVENT_WM_STATUS_LOGIC_ERROR_SHIFT (30U)
  4393. #define VHA_CR_CORE_EVENT_WM_STATUS_LOGIC_ERROR_CLRMSK (0XBFFFFFFFU)
  4394. #define VHA_CR_CORE_EVENT_WM_STATUS_LOGIC_ERROR_EN (0X40000000U)
  4395. #define VHA_CR_CORE_EVENT_WM_STATUS_RAM_CORRECTION_SHIFT (29U)
  4396. #define VHA_CR_CORE_EVENT_WM_STATUS_RAM_CORRECTION_CLRMSK (0XDFFFFFFFU)
  4397. #define VHA_CR_CORE_EVENT_WM_STATUS_RAM_CORRECTION_EN (0X20000000U)
  4398. #define VHA_CR_CORE_EVENT_WM_STATUS_RAM_DETECTION_SHIFT (28U)
  4399. #define VHA_CR_CORE_EVENT_WM_STATUS_RAM_DETECTION_CLRMSK (0XEFFFFFFFU)
  4400. #define VHA_CR_CORE_EVENT_WM_STATUS_RAM_DETECTION_EN (0X10000000U)
  4401. #define VHA_CR_CORE_EVENT_WM_STATUS_LOCM_SCRUB_DONE_SHIFT (16U)
  4402. #define VHA_CR_CORE_EVENT_WM_STATUS_LOCM_SCRUB_DONE_CLRMSK (0XFFFEFFFFU)
  4403. #define VHA_CR_CORE_EVENT_WM_STATUS_LOCM_SCRUB_DONE_EN (0X00010000U)
  4404. #define VHA_CR_CORE_EVENT_WM_STATUS_DMR_COMPLETE_SHIFT (11U)
  4405. #define VHA_CR_CORE_EVENT_WM_STATUS_DMR_COMPLETE_CLRMSK (0XFFFFF7FFU)
  4406. #define VHA_CR_CORE_EVENT_WM_STATUS_DMR_COMPLETE_EN (0X00000800U)
  4407. #define VHA_CR_CORE_EVENT_WM_STATUS_CORE_SYNC_ERROR_SHIFT (10U)
  4408. #define VHA_CR_CORE_EVENT_WM_STATUS_CORE_SYNC_ERROR_CLRMSK (0XFFFFFBFFU)
  4409. #define VHA_CR_CORE_EVENT_WM_STATUS_CORE_SYNC_ERROR_EN (0X00000400U)
  4410. #define VHA_CR_CORE_EVENT_WM_STATUS_CORE_WDT_SHIFT (9U)
  4411. #define VHA_CR_CORE_EVENT_WM_STATUS_CORE_WDT_CLRMSK (0XFFFFFDFFU)
  4412. #define VHA_CR_CORE_EVENT_WM_STATUS_CORE_WDT_EN (0X00000200U)
  4413. #define VHA_CR_CORE_EVENT_WM_STATUS_CORE_MEM_WDT_SHIFT (8U)
  4414. #define VHA_CR_CORE_EVENT_WM_STATUS_CORE_MEM_WDT_CLRMSK (0XFFFFFEFFU)
  4415. #define VHA_CR_CORE_EVENT_WM_STATUS_CORE_MEM_WDT_EN (0X00000100U)
  4416. #define VHA_CR_CORE_EVENT_WM_STATUS_RAM_INIT_DONE_SHIFT (3U)
  4417. #define VHA_CR_CORE_EVENT_WM_STATUS_RAM_INIT_DONE_CLRMSK (0XFFFFFFF7U)
  4418. #define VHA_CR_CORE_EVENT_WM_STATUS_RAM_INIT_DONE_EN (0X00000008U)
  4419. #define VHA_CR_CORE_EVENT_WM_STATUS_MEMBUS_RESET_DONE_SHIFT (2U)
  4420. #define VHA_CR_CORE_EVENT_WM_STATUS_MEMBUS_RESET_DONE_CLRMSK (0XFFFFFFFBU)
  4421. #define VHA_CR_CORE_EVENT_WM_STATUS_MEMBUS_RESET_DONE_EN (0X00000004U)
  4422. #define VHA_CR_CORE_EVENT_WM_STATUS_CNN_ERROR_SHIFT (1U)
  4423. #define VHA_CR_CORE_EVENT_WM_STATUS_CNN_ERROR_CLRMSK (0XFFFFFFFDU)
  4424. #define VHA_CR_CORE_EVENT_WM_STATUS_CNN_ERROR_EN (0X00000002U)
  4425. #define VHA_CR_CORE_EVENT_WM_STATUS_CNN_COMPLETE_SHIFT (0U)
  4426. #define VHA_CR_CORE_EVENT_WM_STATUS_CNN_COMPLETE_CLRMSK (0XFFFFFFFEU)
  4427. #define VHA_CR_CORE_EVENT_WM_STATUS_CNN_COMPLETE_EN (0X00000001U)
  4428. /*
  4429. Register VHA_CR_CORE_EVENT_WM_STATUS_DISABLE
  4430. */
  4431. #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE (0x20180U)
  4432. #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_MASKFULL (IMG_UINT64_C(0x0000000070010F0F))
  4433. #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_LOGIC_ERROR_SHIFT (30U)
  4434. #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_LOGIC_ERROR_CLRMSK (0XBFFFFFFFU)
  4435. #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_LOGIC_ERROR_EN (0X40000000U)
  4436. #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_RAM_CORRECTION_SHIFT (29U)
  4437. #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_RAM_CORRECTION_CLRMSK (0XDFFFFFFFU)
  4438. #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_RAM_CORRECTION_EN (0X20000000U)
  4439. #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_RAM_DETECTION_SHIFT (28U)
  4440. #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_RAM_DETECTION_CLRMSK (0XEFFFFFFFU)
  4441. #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_RAM_DETECTION_EN (0X10000000U)
  4442. #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_LOCM_SCRUB_DONE_SHIFT (16U)
  4443. #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_LOCM_SCRUB_DONE_CLRMSK (0XFFFEFFFFU)
  4444. #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_LOCM_SCRUB_DONE_EN (0X00010000U)
  4445. #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_DMR_COMPLETE_SHIFT (11U)
  4446. #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_DMR_COMPLETE_CLRMSK (0XFFFFF7FFU)
  4447. #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_DMR_COMPLETE_EN (0X00000800U)
  4448. #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_CORE_SYNC_ERROR_SHIFT (10U)
  4449. #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_CORE_SYNC_ERROR_CLRMSK (0XFFFFFBFFU)
  4450. #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_CORE_SYNC_ERROR_EN (0X00000400U)
  4451. #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_CORE_WDT_SHIFT (9U)
  4452. #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_CORE_WDT_CLRMSK (0XFFFFFDFFU)
  4453. #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_CORE_WDT_EN (0X00000200U)
  4454. #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_CORE_MEM_WDT_SHIFT (8U)
  4455. #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_CORE_MEM_WDT_CLRMSK (0XFFFFFEFFU)
  4456. #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_CORE_MEM_WDT_EN (0X00000100U)
  4457. #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_RAM_INIT_DONE_SHIFT (3U)
  4458. #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_RAM_INIT_DONE_CLRMSK (0XFFFFFFF7U)
  4459. #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_RAM_INIT_DONE_EN (0X00000008U)
  4460. #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_MEMBUS_RESET_DONE_SHIFT (2U)
  4461. #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_MEMBUS_RESET_DONE_CLRMSK (0XFFFFFFFBU)
  4462. #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_MEMBUS_RESET_DONE_EN (0X00000004U)
  4463. #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_CNN_ERROR_SHIFT (1U)
  4464. #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_CNN_ERROR_CLRMSK (0XFFFFFFFDU)
  4465. #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_CNN_ERROR_EN (0X00000002U)
  4466. #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_CNN_COMPLETE_SHIFT (0U)
  4467. #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_CNN_COMPLETE_CLRMSK (0XFFFFFFFEU)
  4468. #define VHA_CR_CORE_EVENT_WM_STATUS_DISABLE_CNN_COMPLETE_EN (0X00000001U)
  4469. /*
  4470. Register VHA_CR_CORE_EVENT_WM_CLEAR
  4471. */
  4472. #define VHA_CR_CORE_EVENT_WM_CLEAR (0x20150U)
  4473. #define VHA_CR_CORE_EVENT_WM_CLEAR_MASKFULL (IMG_UINT64_C(0x0000000070010F0F))
  4474. #define VHA_CR_CORE_EVENT_WM_CLEAR_LOGIC_ERROR_SHIFT (30U)
  4475. #define VHA_CR_CORE_EVENT_WM_CLEAR_LOGIC_ERROR_CLRMSK (0XBFFFFFFFU)
  4476. #define VHA_CR_CORE_EVENT_WM_CLEAR_LOGIC_ERROR_EN (0X40000000U)
  4477. #define VHA_CR_CORE_EVENT_WM_CLEAR_RAM_CORRECTION_SHIFT (29U)
  4478. #define VHA_CR_CORE_EVENT_WM_CLEAR_RAM_CORRECTION_CLRMSK (0XDFFFFFFFU)
  4479. #define VHA_CR_CORE_EVENT_WM_CLEAR_RAM_CORRECTION_EN (0X20000000U)
  4480. #define VHA_CR_CORE_EVENT_WM_CLEAR_RAM_DETECTION_SHIFT (28U)
  4481. #define VHA_CR_CORE_EVENT_WM_CLEAR_RAM_DETECTION_CLRMSK (0XEFFFFFFFU)
  4482. #define VHA_CR_CORE_EVENT_WM_CLEAR_RAM_DETECTION_EN (0X10000000U)
  4483. #define VHA_CR_CORE_EVENT_WM_CLEAR_LOCM_SCRUB_DONE_SHIFT (16U)
  4484. #define VHA_CR_CORE_EVENT_WM_CLEAR_LOCM_SCRUB_DONE_CLRMSK (0XFFFEFFFFU)
  4485. #define VHA_CR_CORE_EVENT_WM_CLEAR_LOCM_SCRUB_DONE_EN (0X00010000U)
  4486. #define VHA_CR_CORE_EVENT_WM_CLEAR_DMR_COMPLETE_SHIFT (11U)
  4487. #define VHA_CR_CORE_EVENT_WM_CLEAR_DMR_COMPLETE_CLRMSK (0XFFFFF7FFU)
  4488. #define VHA_CR_CORE_EVENT_WM_CLEAR_DMR_COMPLETE_EN (0X00000800U)
  4489. #define VHA_CR_CORE_EVENT_WM_CLEAR_CORE_SYNC_ERROR_SHIFT (10U)
  4490. #define VHA_CR_CORE_EVENT_WM_CLEAR_CORE_SYNC_ERROR_CLRMSK (0XFFFFFBFFU)
  4491. #define VHA_CR_CORE_EVENT_WM_CLEAR_CORE_SYNC_ERROR_EN (0X00000400U)
  4492. #define VHA_CR_CORE_EVENT_WM_CLEAR_CORE_WDT_SHIFT (9U)
  4493. #define VHA_CR_CORE_EVENT_WM_CLEAR_CORE_WDT_CLRMSK (0XFFFFFDFFU)
  4494. #define VHA_CR_CORE_EVENT_WM_CLEAR_CORE_WDT_EN (0X00000200U)
  4495. #define VHA_CR_CORE_EVENT_WM_CLEAR_CORE_MEM_WDT_SHIFT (8U)
  4496. #define VHA_CR_CORE_EVENT_WM_CLEAR_CORE_MEM_WDT_CLRMSK (0XFFFFFEFFU)
  4497. #define VHA_CR_CORE_EVENT_WM_CLEAR_CORE_MEM_WDT_EN (0X00000100U)
  4498. #define VHA_CR_CORE_EVENT_WM_CLEAR_RAM_INIT_DONE_SHIFT (3U)
  4499. #define VHA_CR_CORE_EVENT_WM_CLEAR_RAM_INIT_DONE_CLRMSK (0XFFFFFFF7U)
  4500. #define VHA_CR_CORE_EVENT_WM_CLEAR_RAM_INIT_DONE_EN (0X00000008U)
  4501. #define VHA_CR_CORE_EVENT_WM_CLEAR_MEMBUS_RESET_DONE_SHIFT (2U)
  4502. #define VHA_CR_CORE_EVENT_WM_CLEAR_MEMBUS_RESET_DONE_CLRMSK (0XFFFFFFFBU)
  4503. #define VHA_CR_CORE_EVENT_WM_CLEAR_MEMBUS_RESET_DONE_EN (0X00000004U)
  4504. #define VHA_CR_CORE_EVENT_WM_CLEAR_CNN_ERROR_SHIFT (1U)
  4505. #define VHA_CR_CORE_EVENT_WM_CLEAR_CNN_ERROR_CLRMSK (0XFFFFFFFDU)
  4506. #define VHA_CR_CORE_EVENT_WM_CLEAR_CNN_ERROR_EN (0X00000002U)
  4507. #define VHA_CR_CORE_EVENT_WM_CLEAR_CNN_COMPLETE_SHIFT (0U)
  4508. #define VHA_CR_CORE_EVENT_WM_CLEAR_CNN_COMPLETE_CLRMSK (0XFFFFFFFEU)
  4509. #define VHA_CR_CORE_EVENT_WM_CLEAR_CNN_COMPLETE_EN (0X00000001U)
  4510. /*
  4511. Register VHA_CR_CORE_EVENT_HOST_THRESHOLD
  4512. */
  4513. #define VHA_CR_CORE_EVENT_HOST_THRESHOLD (0x20158U)
  4514. #define VHA_CR_CORE_EVENT_HOST_THRESHOLD_MASKFULL (IMG_UINT64_C(0x000000000000FFFF))
  4515. #define VHA_CR_CORE_EVENT_HOST_THRESHOLD_RAM_CORRECTION_SHIFT (0U)
  4516. #define VHA_CR_CORE_EVENT_HOST_THRESHOLD_RAM_CORRECTION_CLRMSK (0XFFFF0000U)
  4517. /*
  4518. Register VHA_CR_CORE_EVENT_HOST_THRESHOLD_VAL
  4519. */
  4520. #define VHA_CR_CORE_EVENT_HOST_THRESHOLD_VAL (0x20160U)
  4521. #define VHA_CR_CORE_EVENT_HOST_THRESHOLD_VAL_MASKFULL (IMG_UINT64_C(0x000000000000FFFF))
  4522. #define VHA_CR_CORE_EVENT_HOST_THRESHOLD_VAL_RAM_CORRECTION_SHIFT (0U)
  4523. #define VHA_CR_CORE_EVENT_HOST_THRESHOLD_VAL_RAM_CORRECTION_CLRMSK (0XFFFF0000U)
  4524. /*
  4525. Register VHA_CR_CORE_EVENT_WM_THRESHOLD
  4526. */
  4527. #define VHA_CR_CORE_EVENT_WM_THRESHOLD (0x20168U)
  4528. #define VHA_CR_CORE_EVENT_WM_THRESHOLD_MASKFULL (IMG_UINT64_C(0x000000000000FFFF))
  4529. #define VHA_CR_CORE_EVENT_WM_THRESHOLD_RAM_CORRECTION_SHIFT (0U)
  4530. #define VHA_CR_CORE_EVENT_WM_THRESHOLD_RAM_CORRECTION_CLRMSK (0XFFFF0000U)
  4531. /*
  4532. Register VHA_CR_CORE_EVENT_WM_THRESHOLD_VAL
  4533. */
  4534. #define VHA_CR_CORE_EVENT_WM_THRESHOLD_VAL (0x20170U)
  4535. #define VHA_CR_CORE_EVENT_WM_THRESHOLD_VAL_MASKFULL (IMG_UINT64_C(0x000000000000FFFF))
  4536. #define VHA_CR_CORE_EVENT_WM_THRESHOLD_VAL_RAM_CORRECTION_SHIFT (0U)
  4537. #define VHA_CR_CORE_EVENT_WM_THRESHOLD_VAL_RAM_CORRECTION_CLRMSK (0XFFFF0000U)
  4538. /*
  4539. Register VHA_CR_CORE_EVENT_INJECT
  4540. */
  4541. #define VHA_CR_CORE_EVENT_INJECT (0x20188U)
  4542. #define VHA_CR_CORE_EVENT_INJECT_MASKFULL (IMG_UINT64_C(0x0000000070010F0F))
  4543. #define VHA_CR_CORE_EVENT_INJECT_LOGIC_ERROR_SHIFT (30U)
  4544. #define VHA_CR_CORE_EVENT_INJECT_LOGIC_ERROR_CLRMSK (0XBFFFFFFFU)
  4545. #define VHA_CR_CORE_EVENT_INJECT_LOGIC_ERROR_EN (0X40000000U)
  4546. #define VHA_CR_CORE_EVENT_INJECT_RAM_CORRECTION_SHIFT (29U)
  4547. #define VHA_CR_CORE_EVENT_INJECT_RAM_CORRECTION_CLRMSK (0XDFFFFFFFU)
  4548. #define VHA_CR_CORE_EVENT_INJECT_RAM_CORRECTION_EN (0X20000000U)
  4549. #define VHA_CR_CORE_EVENT_INJECT_RAM_DETECTION_SHIFT (28U)
  4550. #define VHA_CR_CORE_EVENT_INJECT_RAM_DETECTION_CLRMSK (0XEFFFFFFFU)
  4551. #define VHA_CR_CORE_EVENT_INJECT_RAM_DETECTION_EN (0X10000000U)
  4552. #define VHA_CR_CORE_EVENT_INJECT_LOCM_SCRUB_DONE_SHIFT (16U)
  4553. #define VHA_CR_CORE_EVENT_INJECT_LOCM_SCRUB_DONE_CLRMSK (0XFFFEFFFFU)
  4554. #define VHA_CR_CORE_EVENT_INJECT_LOCM_SCRUB_DONE_EN (0X00010000U)
  4555. #define VHA_CR_CORE_EVENT_INJECT_DMR_COMPLETE_SHIFT (11U)
  4556. #define VHA_CR_CORE_EVENT_INJECT_DMR_COMPLETE_CLRMSK (0XFFFFF7FFU)
  4557. #define VHA_CR_CORE_EVENT_INJECT_DMR_COMPLETE_EN (0X00000800U)
  4558. #define VHA_CR_CORE_EVENT_INJECT_CORE_SYNC_ERROR_SHIFT (10U)
  4559. #define VHA_CR_CORE_EVENT_INJECT_CORE_SYNC_ERROR_CLRMSK (0XFFFFFBFFU)
  4560. #define VHA_CR_CORE_EVENT_INJECT_CORE_SYNC_ERROR_EN (0X00000400U)
  4561. #define VHA_CR_CORE_EVENT_INJECT_CORE_WDT_SHIFT (9U)
  4562. #define VHA_CR_CORE_EVENT_INJECT_CORE_WDT_CLRMSK (0XFFFFFDFFU)
  4563. #define VHA_CR_CORE_EVENT_INJECT_CORE_WDT_EN (0X00000200U)
  4564. #define VHA_CR_CORE_EVENT_INJECT_CORE_MEM_WDT_SHIFT (8U)
  4565. #define VHA_CR_CORE_EVENT_INJECT_CORE_MEM_WDT_CLRMSK (0XFFFFFEFFU)
  4566. #define VHA_CR_CORE_EVENT_INJECT_CORE_MEM_WDT_EN (0X00000100U)
  4567. #define VHA_CR_CORE_EVENT_INJECT_RAM_INIT_DONE_SHIFT (3U)
  4568. #define VHA_CR_CORE_EVENT_INJECT_RAM_INIT_DONE_CLRMSK (0XFFFFFFF7U)
  4569. #define VHA_CR_CORE_EVENT_INJECT_RAM_INIT_DONE_EN (0X00000008U)
  4570. #define VHA_CR_CORE_EVENT_INJECT_MEMBUS_RESET_DONE_SHIFT (2U)
  4571. #define VHA_CR_CORE_EVENT_INJECT_MEMBUS_RESET_DONE_CLRMSK (0XFFFFFFFBU)
  4572. #define VHA_CR_CORE_EVENT_INJECT_MEMBUS_RESET_DONE_EN (0X00000004U)
  4573. #define VHA_CR_CORE_EVENT_INJECT_CNN_ERROR_SHIFT (1U)
  4574. #define VHA_CR_CORE_EVENT_INJECT_CNN_ERROR_CLRMSK (0XFFFFFFFDU)
  4575. #define VHA_CR_CORE_EVENT_INJECT_CNN_ERROR_EN (0X00000002U)
  4576. #define VHA_CR_CORE_EVENT_INJECT_CNN_COMPLETE_SHIFT (0U)
  4577. #define VHA_CR_CORE_EVENT_INJECT_CNN_COMPLETE_CLRMSK (0XFFFFFFFEU)
  4578. #define VHA_CR_CORE_EVENT_INJECT_CNN_COMPLETE_EN (0X00000001U)
  4579. /*
  4580. Register VHA_CR_CORE_VHA_FLOP_ERR_INJ_CTRL
  4581. */
  4582. #define VHA_CR_CORE_VHA_FLOP_ERR_INJ_CTRL (0x20280U)
  4583. #define VHA_CR_CORE_VHA_FLOP_ERR_INJ_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  4584. #define VHA_CR_CORE_VHA_FLOP_ERR_INJ_CTRL_ERR_INJ_CTRL_SHIFT (0U)
  4585. #define VHA_CR_CORE_VHA_FLOP_ERR_INJ_CTRL_ERR_INJ_CTRL_CLRMSK (0XFFFFFFFEU)
  4586. #define VHA_CR_CORE_VHA_FLOP_ERR_INJ_CTRL_ERR_INJ_CTRL_EN (0X00000001U)
  4587. /*
  4588. Register VHA_CR_CORE_VHA_FLOP_ERR_INJ_STATUS
  4589. */
  4590. #define VHA_CR_CORE_VHA_FLOP_ERR_INJ_STATUS (0x20288U)
  4591. #define VHA_CR_CORE_VHA_FLOP_ERR_INJ_STATUS_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  4592. #define VHA_CR_CORE_VHA_FLOP_ERR_INJ_STATUS_ERR_INJ_STATUS_SHIFT (0U)
  4593. #define VHA_CR_CORE_VHA_FLOP_ERR_INJ_STATUS_ERR_INJ_STATUS_CLRMSK (0XFFFFFFFEU)
  4594. #define VHA_CR_CORE_VHA_FLOP_ERR_INJ_STATUS_ERR_INJ_STATUS_EN (0X00000001U)
  4595. /*
  4596. Register VHA_CR_CNN_MEM_WDT_TIMER
  4597. */
  4598. #define VHA_CR_CNN_MEM_WDT_TIMER (0x20030U)
  4599. #define VHA_CR_CNN_MEM_WDT_TIMER_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  4600. #define VHA_CR_CNN_MEM_WDT_TIMER_VALUE_SHIFT (0U)
  4601. #define VHA_CR_CNN_MEM_WDT_TIMER_VALUE_CLRMSK (00000000U)
  4602. /*
  4603. Register VHA_CR_CNN_WDT_TIMER
  4604. */
  4605. #define VHA_CR_CNN_WDT_TIMER (0x20038U)
  4606. #define VHA_CR_CNN_WDT_TIMER_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  4607. #define VHA_CR_CNN_WDT_TIMER_VALUE_SHIFT (0U)
  4608. #define VHA_CR_CNN_WDT_TIMER_VALUE_CLRMSK (00000000U)
  4609. /*
  4610. Register VHA_CR_RTM_CTRL
  4611. */
  4612. #define VHA_CR_RTM_CTRL (0x20040U)
  4613. #define VHA_CR_RTM_CTRL_MASKFULL (IMG_UINT64_C(0x00000000C0FFFFF8))
  4614. #define VHA_CR_RTM_CTRL_RTM_ENABLE_SHIFT (31U)
  4615. #define VHA_CR_RTM_CTRL_RTM_ENABLE_CLRMSK (0X7FFFFFFFU)
  4616. #define VHA_CR_RTM_CTRL_RTM_ENABLE_EN (0X80000000U)
  4617. #define VHA_CR_RTM_CTRL_RTM_CHECK_SHIFT (30U)
  4618. #define VHA_CR_RTM_CTRL_RTM_CHECK_CLRMSK (0XBFFFFFFFU)
  4619. #define VHA_CR_RTM_CTRL_RTM_CHECK_EN (0X40000000U)
  4620. #define VHA_CR_RTM_CTRL_RTM_SELECTOR_SHIFT (3U)
  4621. #define VHA_CR_RTM_CTRL_RTM_SELECTOR_CLRMSK (0XFF000007U)
  4622. /*
  4623. Register VHA_CR_RTM_DATA
  4624. */
  4625. #define VHA_CR_RTM_DATA (0x20048U)
  4626. #define VHA_CR_RTM_DATA_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  4627. #define VHA_CR_RTM_DATA_RTM_DATA_SHIFT (0U)
  4628. #define VHA_CR_RTM_DATA_RTM_DATA_CLRMSK (00000000U)
  4629. /*
  4630. Register VHA_CR_BIF_OUTSTANDING_READ
  4631. */
  4632. #define VHA_CR_BIF_OUTSTANDING_READ (0x20078U)
  4633. #define VHA_CR_BIF_OUTSTANDING_READ_MASKFULL (IMG_UINT64_C(0x000000000000FFFF))
  4634. #define VHA_CR_BIF_OUTSTANDING_READ_COUNTER_SHIFT (0U)
  4635. #define VHA_CR_BIF_OUTSTANDING_READ_COUNTER_CLRMSK (0XFFFF0000U)
  4636. /*
  4637. Register VHA_CR_BIF_PAGE_FAULT_STALL
  4638. */
  4639. #define VHA_CR_BIF_PAGE_FAULT_STALL (0x20080U)
  4640. #define VHA_CR_BIF_PAGE_FAULT_STALL_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  4641. #define VHA_CR_BIF_PAGE_FAULT_STALL_STATUS_SHIFT (0U)
  4642. #define VHA_CR_BIF_PAGE_FAULT_STALL_STATUS_CLRMSK (0XFFFFFFFEU)
  4643. #define VHA_CR_BIF_PAGE_FAULT_STALL_STATUS_EN (0X00000001U)
  4644. /*
  4645. Register VHA_CR_BIF_RTN_FIFO_WORD_COUNT
  4646. */
  4647. #define VHA_CR_BIF_RTN_FIFO_WORD_COUNT (0x20088U)
  4648. #define VHA_CR_BIF_RTN_FIFO_WORD_COUNT_MASKFULL (IMG_UINT64_C(0x00000000000001FF))
  4649. #define VHA_CR_BIF_RTN_FIFO_WORD_COUNT_COUNTER_SHIFT (0U)
  4650. #define VHA_CR_BIF_RTN_FIFO_WORD_COUNT_COUNTER_CLRMSK (0XFFFFFE00U)
  4651. /*
  4652. Register VHA_CR_CNN_CMD_MH_CONTROL
  4653. */
  4654. #define VHA_CR_CNN_CMD_MH_CONTROL (0x201A0U)
  4655. #define VHA_CR_CNN_CMD_MH_CONTROL_MASKFULL (IMG_UINT64_C(0x0000000000000034))
  4656. #define VHA_CR_CNN_CMD_MH_CONTROL_MAX_BURST_LENGTH_SHIFT (4U)
  4657. #define VHA_CR_CNN_CMD_MH_CONTROL_MAX_BURST_LENGTH_CLRMSK (0XFFFFFFCFU)
  4658. #define VHA_CR_CNN_CMD_MH_CONTROL_SLC_CACHE_POLICY_SHIFT (2U)
  4659. #define VHA_CR_CNN_CMD_MH_CONTROL_SLC_CACHE_POLICY_CLRMSK (0XFFFFFFFBU)
  4660. #define VHA_CR_CNN_CMD_MH_CONTROL_SLC_CACHE_POLICY_EN (0X00000004U)
  4661. /*
  4662. Register VHA_CR_CNN_IBUF_MH_CONTROL
  4663. */
  4664. #define VHA_CR_CNN_IBUF_MH_CONTROL (0x201A8U)
  4665. #define VHA_CR_CNN_IBUF_MH_CONTROL_MASKFULL (IMG_UINT64_C(0x0000000000000018))
  4666. #define VHA_CR_CNN_IBUF_MH_CONTROL_MAX_BURST_LENGTH_SHIFT (3U)
  4667. #define VHA_CR_CNN_IBUF_MH_CONTROL_MAX_BURST_LENGTH_CLRMSK (0XFFFFFFE7U)
  4668. /*
  4669. Register VHA_CR_CNN_CBUF_MH_CONTROL
  4670. */
  4671. #define VHA_CR_CNN_CBUF_MH_CONTROL (0x201B0U)
  4672. #define VHA_CR_CNN_CBUF_MH_CONTROL_MASKFULL (IMG_UINT64_C(0x0000000000000018))
  4673. #define VHA_CR_CNN_CBUF_MH_CONTROL_MAX_BURST_LENGTH_SHIFT (3U)
  4674. #define VHA_CR_CNN_CBUF_MH_CONTROL_MAX_BURST_LENGTH_CLRMSK (0XFFFFFFE7U)
  4675. /*
  4676. Register VHA_CR_CNN_ABUF_MH_CONTROL
  4677. */
  4678. #define VHA_CR_CNN_ABUF_MH_CONTROL (0x201B8U)
  4679. #define VHA_CR_CNN_ABUF_MH_CONTROL_MASKFULL (IMG_UINT64_C(0x0000000000000018))
  4680. #define VHA_CR_CNN_ABUF_MH_CONTROL_MAX_BURST_LENGTH_SHIFT (3U)
  4681. #define VHA_CR_CNN_ABUF_MH_CONTROL_MAX_BURST_LENGTH_CLRMSK (0XFFFFFFE7U)
  4682. /*
  4683. Register VHA_CR_CNN_OUTPACK_MH_CONTROL
  4684. */
  4685. #define VHA_CR_CNN_OUTPACK_MH_CONTROL (0x201C0U)
  4686. #define VHA_CR_CNN_OUTPACK_MH_CONTROL_MASKFULL (IMG_UINT64_C(0x0000000000000018))
  4687. #define VHA_CR_CNN_OUTPACK_MH_CONTROL_MAX_BURST_LENGTH_SHIFT (3U)
  4688. #define VHA_CR_CNN_OUTPACK_MH_CONTROL_MAX_BURST_LENGTH_CLRMSK (0XFFFFFFE7U)
  4689. /*
  4690. Register VHA_CR_CNN_ELEMENTOPS_MH_CONTROL
  4691. */
  4692. #define VHA_CR_CNN_ELEMENTOPS_MH_CONTROL (0x201C8U)
  4693. #define VHA_CR_CNN_ELEMENTOPS_MH_CONTROL_MASKFULL (IMG_UINT64_C(0x0000000000000018))
  4694. #define VHA_CR_CNN_ELEMENTOPS_MH_CONTROL_MAX_BURST_LENGTH_SHIFT (3U)
  4695. #define VHA_CR_CNN_ELEMENTOPS_MH_CONTROL_MAX_BURST_LENGTH_CLRMSK (0XFFFFFFE7U)
  4696. /*
  4697. Register VHA_CR_CNN_MMM_MH_CONTROL
  4698. */
  4699. #define VHA_CR_CNN_MMM_MH_CONTROL (0x201D0U)
  4700. #define VHA_CR_CNN_MMM_MH_CONTROL_MASKFULL (IMG_UINT64_C(0x0000000000000018))
  4701. #define VHA_CR_CNN_MMM_MH_CONTROL_MAX_BURST_LENGTH_SHIFT (3U)
  4702. #define VHA_CR_CNN_MMM_MH_CONTROL_MAX_BURST_LENGTH_CLRMSK (0XFFFFFFE7U)
  4703. /*
  4704. Register VHA_CR_CNN_TRS_A_MH_CONTROL
  4705. */
  4706. #define VHA_CR_CNN_TRS_A_MH_CONTROL (0x201D8U)
  4707. #define VHA_CR_CNN_TRS_A_MH_CONTROL_MASKFULL (IMG_UINT64_C(0x0000000000000018))
  4708. #define VHA_CR_CNN_TRS_A_MH_CONTROL_MAX_BURST_LENGTH_SHIFT (3U)
  4709. #define VHA_CR_CNN_TRS_A_MH_CONTROL_MAX_BURST_LENGTH_CLRMSK (0XFFFFFFE7U)
  4710. /*
  4711. Register VHA_CR_CNN_TRS_B_MH_CONTROL
  4712. */
  4713. #define VHA_CR_CNN_TRS_B_MH_CONTROL (0x201E0U)
  4714. #define VHA_CR_CNN_TRS_B_MH_CONTROL_MASKFULL (IMG_UINT64_C(0x0000000000000018))
  4715. #define VHA_CR_CNN_TRS_B_MH_CONTROL_MAX_BURST_LENGTH_SHIFT (3U)
  4716. #define VHA_CR_CNN_TRS_B_MH_CONTROL_MAX_BURST_LENGTH_CLRMSK (0XFFFFFFE7U)
  4717. /*
  4718. Register VHA_CR_CNN_DWPE_MH_CONTROL
  4719. */
  4720. #define VHA_CR_CNN_DWPE_MH_CONTROL (0x201E8U)
  4721. #define VHA_CR_CNN_DWPE_MH_CONTROL_MASKFULL (IMG_UINT64_C(0x0000000000000018))
  4722. #define VHA_CR_CNN_DWPE_MH_CONTROL_MAX_BURST_LENGTH_SHIFT (3U)
  4723. #define VHA_CR_CNN_DWPE_MH_CONTROL_MAX_BURST_LENGTH_CLRMSK (0XFFFFFFE7U)
  4724. /*
  4725. Register VHA_CR_FUSA_CONTROL
  4726. */
  4727. #define VHA_CR_FUSA_CONTROL (0x201F0U)
  4728. #define VHA_CR_FUSA_CONTROL_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  4729. #define VHA_CR_FUSA_CONTROL_ECC_INIT_KICK_SHIFT (0U)
  4730. #define VHA_CR_FUSA_CONTROL_ECC_INIT_KICK_CLRMSK (0XFFFFFFFEU)
  4731. #define VHA_CR_FUSA_CONTROL_ECC_INIT_KICK_EN (0X00000001U)
  4732. /*
  4733. Register VHA_CR_CNN_MEM_WDT_COMPAREMATCH
  4734. */
  4735. #define VHA_CR_CNN_MEM_WDT_COMPAREMATCH (0x201F8U)
  4736. #define VHA_CR_CNN_MEM_WDT_COMPAREMATCH_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  4737. #define VHA_CR_CNN_MEM_WDT_COMPAREMATCH_REG_SHIFT (0U)
  4738. #define VHA_CR_CNN_MEM_WDT_COMPAREMATCH_REG_CLRMSK (00000000U)
  4739. #define VHA_CR_CNN_MEM_WDT_CTRL_CNN_MEM_WDT_CTRL_MASK (0x00000003U)
  4740. /*
  4741. WDT is Disabled */
  4742. #define VHA_CR_CNN_MEM_WDT_CTRL_CNN_MEM_WDT_CTRL_NONE (0x00000000U)
  4743. /*
  4744. WDT is Cleared when CMD Parser starts a pass or CMD parser is kicked*/
  4745. #define VHA_CR_CNN_MEM_WDT_CTRL_CNN_MEM_WDT_CTRL_KICK_PASS (0x00000001U)
  4746. /*
  4747. WDT is Cleared when CMD Parser is kicked */
  4748. #define VHA_CR_CNN_MEM_WDT_CTRL_CNN_MEM_WDT_CTRL_KICK (0x00000002U)
  4749. /*
  4750. Register VHA_CR_CNN_MEM_WDT_CTRL
  4751. */
  4752. #define VHA_CR_CNN_MEM_WDT_CTRL (0x20200U)
  4753. #define VHA_CR_CNN_MEM_WDT_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000000003))
  4754. #define VHA_CR_CNN_MEM_WDT_CTRL_MODE_SHIFT (0U)
  4755. #define VHA_CR_CNN_MEM_WDT_CTRL_MODE_CLRMSK (0XFFFFFFFCU)
  4756. #define VHA_CR_CNN_MEM_WDT_CTRL_MODE_NONE (00000000U)
  4757. #define VHA_CR_CNN_MEM_WDT_CTRL_MODE_KICK_PASS (0X00000001U)
  4758. #define VHA_CR_CNN_MEM_WDT_CTRL_MODE_KICK (0X00000002U)
  4759. #define VHA_CR_CNN_WDT_CTRL_CNN_WDT_CTRL_MASK (0x00000003U)
  4760. /*
  4761. WDT is Cleared when CMD Parser starts a pass or CMD parser is kicked*/
  4762. #define VHA_CR_CNN_WDT_CTRL_CNN_WDT_CTRL_KICK_PASS (0x00000001U)
  4763. /*
  4764. WDT is Cleared when CMD Parser starts a layer group or CMD parser is kicked*/
  4765. #define VHA_CR_CNN_WDT_CTRL_CNN_WDT_CTRL_KICK_LAYER (0x00000002U)
  4766. /*
  4767. Register VHA_CR_CNN_WDT_CTRL
  4768. */
  4769. #define VHA_CR_CNN_WDT_CTRL (0x20208U)
  4770. #define VHA_CR_CNN_WDT_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000000003))
  4771. #define VHA_CR_CNN_WDT_CTRL_MODE_SHIFT (0U)
  4772. #define VHA_CR_CNN_WDT_CTRL_MODE_CLRMSK (0XFFFFFFFCU)
  4773. #define VHA_CR_CNN_WDT_CTRL_MODE_KICK_PASS (0X00000001U)
  4774. #define VHA_CR_CNN_WDT_CTRL_MODE_KICK_LAYER (0X00000002U)
  4775. /*
  4776. Register VHA_CR_CNN_WDT_COMPAREMATCH
  4777. */
  4778. #define VHA_CR_CNN_WDT_COMPAREMATCH (0x20210U)
  4779. #define VHA_CR_CNN_WDT_COMPAREMATCH_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  4780. #define VHA_CR_CNN_WDT_COMPAREMATCH_REG_SHIFT (0U)
  4781. #define VHA_CR_CNN_WDT_COMPAREMATCH_REG_CLRMSK (00000000U)
  4782. /*
  4783. Register VHA_CR_VHA_CNN_CMD_SECURITY_CONTROL
  4784. */
  4785. #define VHA_CR_VHA_CNN_CMD_SECURITY_CONTROL (0x20230U)
  4786. #define VHA_CR_VHA_CNN_CMD_SECURITY_CONTROL_MASKFULL (IMG_UINT64_C(0x0000000000000004))
  4787. #define VHA_CR_VHA_CNN_CMD_SECURITY_CONTROL_FORCE_DISABLE_CRC_SHIFT (2U)
  4788. #define VHA_CR_VHA_CNN_CMD_SECURITY_CONTROL_FORCE_DISABLE_CRC_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFB))
  4789. #define VHA_CR_VHA_CNN_CMD_SECURITY_CONTROL_FORCE_DISABLE_CRC_EN (IMG_UINT64_C(0X0000000000000004))
  4790. /*
  4791. Register VHA_CR_CNN_ARB_STALL_RATIO
  4792. */
  4793. #define VHA_CR_CNN_ARB_STALL_RATIO (0x20240U)
  4794. #define VHA_CR_CNN_ARB_STALL_RATIO_MASKFULL (IMG_UINT64_C(0x0000000FFFFFFFFF))
  4795. #define VHA_CR_CNN_ARB_STALL_RATIO_OUTPUT_SHIFT (32U)
  4796. #define VHA_CR_CNN_ARB_STALL_RATIO_OUTPUT_CLRMSK (IMG_UINT64_C(0XFFFFFFF0FFFFFFFF))
  4797. #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_8_SHIFT (28U)
  4798. #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_8_CLRMSK (IMG_UINT64_C(0XFFFFFFFF0FFFFFFF))
  4799. #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_7_SHIFT (24U)
  4800. #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_7_CLRMSK (IMG_UINT64_C(0XFFFFFFFFF0FFFFFF))
  4801. #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_6_SHIFT (20U)
  4802. #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_6_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF0FFFFF))
  4803. #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_5_SHIFT (16U)
  4804. #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_5_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF0FFFF))
  4805. #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_4_SHIFT (12U)
  4806. #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_4_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF0FFF))
  4807. #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_3_SHIFT (8U)
  4808. #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_3_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF0FF))
  4809. #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_2_SHIFT (4U)
  4810. #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_2_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFF0F))
  4811. #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_1_SHIFT (0U)
  4812. #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF0))
  4813. /*
  4814. Register VHA_CR_CNN_DATAPATH_STALL_RATIO_0
  4815. */
  4816. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0 (0x20248U)
  4817. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_MASKFULL (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
  4818. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_CORE_XBAR_ACT_SHIFT (60U)
  4819. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_CORE_XBAR_ACT_CLRMSK (IMG_UINT64_C(0X0FFFFFFFFFFFFFFF))
  4820. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_ACT_CORE_XBAR_SHIFT (56U)
  4821. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_ACT_CORE_XBAR_CLRMSK (IMG_UINT64_C(0XF0FFFFFFFFFFFFFF))
  4822. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_EWO_CORE_XBAR_SHIFT (52U)
  4823. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_EWO_CORE_XBAR_CLRMSK (IMG_UINT64_C(0XFF0FFFFFFFFFFFFF))
  4824. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_TENSORB_CORE_XBAR_SHIFT (48U)
  4825. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_TENSORB_CORE_XBAR_CLRMSK (IMG_UINT64_C(0XFFF0FFFFFFFFFFFF))
  4826. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_CORE_XBAR_EWO_SHIFT (44U)
  4827. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_CORE_XBAR_EWO_CLRMSK (IMG_UINT64_C(0XFFFF0FFFFFFFFFFF))
  4828. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_CORE_XBAR_TENSORB_SHIFT (40U)
  4829. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_CORE_XBAR_TENSORB_CLRMSK (IMG_UINT64_C(0XFFFFF0FFFFFFFFFF))
  4830. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_CORE_XBAR_NORM_SHIFT (36U)
  4831. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_CORE_XBAR_NORM_CLRMSK (IMG_UINT64_C(0XFFFFFF0FFFFFFFFF))
  4832. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_NORM_POOL_SHIFT (32U)
  4833. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_NORM_POOL_CLRMSK (IMG_UINT64_C(0XFFFFFFF0FFFFFFFF))
  4834. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_CNV_ABUF_SHIFT (28U)
  4835. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_CNV_ABUF_CLRMSK (IMG_UINT64_C(0XFFFFFFFF0FFFFFFF))
  4836. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_IBUF_CNV_SHIFT (24U)
  4837. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_IBUF_CNV_CLRMSK (IMG_UINT64_C(0XFFFFFFFFF0FFFFFF))
  4838. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_ABUF_CORE_XBAR_SHIFT (20U)
  4839. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_ABUF_CORE_XBAR_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF0FFFFF))
  4840. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_CORE_XBAR_IBUF_SHIFT (16U)
  4841. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_CORE_XBAR_IBUF_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF0FFFF))
  4842. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_IBUF_CORE_XBAR_SHIFT (12U)
  4843. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_IBUF_CORE_XBAR_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF0FFF))
  4844. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_CBUF_CNV_SHIFT (8U)
  4845. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_CBUF_CNV_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF0FF))
  4846. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_ABUF_OUTPACK_SHIFT (4U)
  4847. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_ABUF_OUTPACK_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFF0F))
  4848. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_CBUF_ABUF_SHIFT (0U)
  4849. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_CBUF_ABUF_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF0))
  4850. /*
  4851. Register VHA_CR_CNN_DATAPATH_STALL_RATIO_1
  4852. */
  4853. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_1 (0x20250U)
  4854. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_1_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  4855. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_1_NORM_POOL_BYPASS_SHIFT (36U)
  4856. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_1_NORM_POOL_BYPASS_CLRMSK (IMG_UINT64_C(0XFFFFFF0FFFFFFFFF))
  4857. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_1_TRS_B_XBAR_SHIFT (32U)
  4858. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_1_TRS_B_XBAR_CLRMSK (IMG_UINT64_C(0XFFFFFFF0FFFFFFFF))
  4859. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_1_XBAR_TRS_B_SHIFT (28U)
  4860. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_1_XBAR_TRS_B_CLRMSK (IMG_UINT64_C(0XFFFFFFFF0FFFFFFF))
  4861. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_1_TRS_A_XBAR_SHIFT (24U)
  4862. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_1_TRS_A_XBAR_CLRMSK (IMG_UINT64_C(0XFFFFFFFFF0FFFFFF))
  4863. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_1_XBAR_TRS_A_SHIFT (20U)
  4864. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_1_XBAR_TRS_A_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF0FFFFF))
  4865. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_1_OIN_OPK_SHIFT (16U)
  4866. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_1_OIN_OPK_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF0FFFF))
  4867. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_1_CORE_XBAR_OIN_SHIFT (12U)
  4868. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_1_CORE_XBAR_OIN_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF0FFF))
  4869. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_1_POOL_CORE_XBAR_SHIFT (8U)
  4870. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_1_POOL_CORE_XBAR_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF0FF))
  4871. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_1_POOL_SB_SHIFT (4U)
  4872. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_1_POOL_SB_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFF0F))
  4873. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_1_OIN_SB_SHIFT (0U)
  4874. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_1_OIN_SB_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF0))
  4875. /*
  4876. Register VHA_CR_NN_SYS2_MEMBUS_CORE_STALL_RATIO
  4877. */
  4878. #define VHA_CR_NN_SYS2_MEMBUS_CORE_STALL_RATIO (0x20258U)
  4879. #define VHA_CR_NN_SYS2_MEMBUS_CORE_STALL_RATIO_MASKFULL (IMG_UINT64_C(0x0000000000FFFFFF))
  4880. #define VHA_CR_NN_SYS2_MEMBUS_CORE_STALL_RATIO_CORE_NOC_MEMBUS_RESET_RTN_SHIFT (20U)
  4881. #define VHA_CR_NN_SYS2_MEMBUS_CORE_STALL_RATIO_CORE_NOC_MEMBUS_RESET_RTN_CLRMSK (0XFF0FFFFFU)
  4882. #define VHA_CR_NN_SYS2_MEMBUS_CORE_STALL_RATIO_CORE_NOC_MEMBUS_RESET_SHIFT (16U)
  4883. #define VHA_CR_NN_SYS2_MEMBUS_CORE_STALL_RATIO_CORE_NOC_MEMBUS_RESET_CLRMSK (0XFFF0FFFFU)
  4884. #define VHA_CR_NN_SYS2_MEMBUS_CORE_STALL_RATIO_CORE_NOC_LOCM_RTN_SHIFT (12U)
  4885. #define VHA_CR_NN_SYS2_MEMBUS_CORE_STALL_RATIO_CORE_NOC_LOCM_RTN_CLRMSK (0XFFFF0FFFU)
  4886. #define VHA_CR_NN_SYS2_MEMBUS_CORE_STALL_RATIO_CORE_NOC_LOCM_SHIFT (8U)
  4887. #define VHA_CR_NN_SYS2_MEMBUS_CORE_STALL_RATIO_CORE_NOC_LOCM_CLRMSK (0XFFFFF0FFU)
  4888. #define VHA_CR_NN_SYS2_MEMBUS_CORE_STALL_RATIO_BIF_CORE_NOC_RTN_SHIFT (4U)
  4889. #define VHA_CR_NN_SYS2_MEMBUS_CORE_STALL_RATIO_BIF_CORE_NOC_RTN_CLRMSK (0XFFFFFF0FU)
  4890. #define VHA_CR_NN_SYS2_MEMBUS_CORE_STALL_RATIO_BIF_CORE_NOC_SHIFT (0U)
  4891. #define VHA_CR_NN_SYS2_MEMBUS_CORE_STALL_RATIO_BIF_CORE_NOC_CLRMSK (0XFFFFFFF0U)
  4892. /*
  4893. Register VHA_CR_CNN_ARB_CTRL
  4894. */
  4895. #define VHA_CR_CNN_ARB_CTRL (0x20260U)
  4896. #define VHA_CR_CNN_ARB_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000000307))
  4897. #define VHA_CR_CNN_ARB_CTRL_ENABLE_PASS_PRIORITY_SHIFT (9U)
  4898. #define VHA_CR_CNN_ARB_CTRL_ENABLE_PASS_PRIORITY_CLRMSK (0XFFFFFDFFU)
  4899. #define VHA_CR_CNN_ARB_CTRL_ENABLE_PASS_PRIORITY_EN (0X00000200U)
  4900. #define VHA_CR_CNN_ARB_CTRL_MMM_PRIORITY_SEL_SHIFT (8U)
  4901. #define VHA_CR_CNN_ARB_CTRL_MMM_PRIORITY_SEL_CLRMSK (0XFFFFFEFFU)
  4902. #define VHA_CR_CNN_ARB_CTRL_MMM_PRIORITY_SEL_EN (0X00000100U)
  4903. #define VHA_CR_CNN_ARB_CTRL_MAX_PAGE_COUNT_MIN1_SHIFT (0U)
  4904. #define VHA_CR_CNN_ARB_CTRL_MAX_PAGE_COUNT_MIN1_CLRMSK (0XFFFFFFF8U)
  4905. /*
  4906. Register VHA_CR_REQ_CTXT_OVERRIDE
  4907. */
  4908. #define VHA_CR_REQ_CTXT_OVERRIDE (0x203A8U)
  4909. #define VHA_CR_REQ_CTXT_OVERRIDE_MASKFULL (IMG_UINT64_C(0x0000000000000007))
  4910. #define VHA_CR_REQ_CTXT_OVERRIDE_OVERRIDE_OS2_SHIFT (2U)
  4911. #define VHA_CR_REQ_CTXT_OVERRIDE_OVERRIDE_OS2_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFB))
  4912. #define VHA_CR_REQ_CTXT_OVERRIDE_OVERRIDE_OS2_EN (IMG_UINT64_C(0X0000000000000004))
  4913. #define VHA_CR_REQ_CTXT_OVERRIDE_OVERRIDE_OS1_SHIFT (1U)
  4914. #define VHA_CR_REQ_CTXT_OVERRIDE_OVERRIDE_OS1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFD))
  4915. #define VHA_CR_REQ_CTXT_OVERRIDE_OVERRIDE_OS1_EN (IMG_UINT64_C(0X0000000000000002))
  4916. #define VHA_CR_REQ_CTXT_OVERRIDE_OVERRIDE_OS0_SHIFT (0U)
  4917. #define VHA_CR_REQ_CTXT_OVERRIDE_OVERRIDE_OS0_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  4918. #define VHA_CR_REQ_CTXT_OVERRIDE_OVERRIDE_OS0_EN (IMG_UINT64_C(0X0000000000000001))
  4919. /*
  4920. Register VHA_CR_CNN_CMD_PRIORITY_LIMITS
  4921. */
  4922. #define VHA_CR_CNN_CMD_PRIORITY_LIMITS (0x203B0U)
  4923. #define VHA_CR_CNN_CMD_PRIORITY_LIMITS_MASKFULL (IMG_UINT64_C(0x000000000000019B))
  4924. #define VHA_CR_CNN_CMD_PRIORITY_LIMITS_OS2_LIMIT_SHIFT (7U)
  4925. #define VHA_CR_CNN_CMD_PRIORITY_LIMITS_OS2_LIMIT_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFE7F))
  4926. #define VHA_CR_CNN_CMD_PRIORITY_LIMITS_OS1_LIMIT_SHIFT (3U)
  4927. #define VHA_CR_CNN_CMD_PRIORITY_LIMITS_OS1_LIMIT_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFE7))
  4928. #define VHA_CR_CNN_CMD_PRIORITY_LIMITS_OS0_LIMIT_SHIFT (0U)
  4929. #define VHA_CR_CNN_CMD_PRIORITY_LIMITS_OS0_LIMIT_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFC))
  4930. /*
  4931. Register VHA_CR_LOCM_SCRUB_CTRL
  4932. */
  4933. #define VHA_CR_LOCM_SCRUB_CTRL (0x203B8U)
  4934. #define VHA_CR_LOCM_SCRUB_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000000011))
  4935. #define VHA_CR_LOCM_SCRUB_CTRL_MODE_SHIFT (4U)
  4936. #define VHA_CR_LOCM_SCRUB_CTRL_MODE_CLRMSK (0XFFFFFFEFU)
  4937. #define VHA_CR_LOCM_SCRUB_CTRL_MODE_EN (0X00000010U)
  4938. #define VHA_CR_LOCM_SCRUB_CTRL_KICK_SHIFT (0U)
  4939. #define VHA_CR_LOCM_SCRUB_CTRL_KICK_CLRMSK (0XFFFFFFFEU)
  4940. #define VHA_CR_LOCM_SCRUB_CTRL_KICK_EN (0X00000001U)
  4941. #define VHA_CR_CNN_MASK_CTRL_MASK (0x00000003U)
  4942. /*
  4943. No Masks Applied */
  4944. #define VHA_CR_CNN_MASK_CTRL_DEBUG_INTERNAL (0x00000000U)
  4945. /*
  4946. Mask port with mask_level < 1 */
  4947. #define VHA_CR_CNN_MASK_CTRL_DEBUG_SILICON (0x00000001U)
  4948. /*
  4949. Mask port with mask_level < 2 */
  4950. #define VHA_CR_CNN_MASK_CTRL_SAFETY (0x00000002U)
  4951. /*
  4952. Mask port with mask_level < 3 */
  4953. #define VHA_CR_CNN_MASK_CTRL_RESERVED (0x00000003U)
  4954. #define VHA_CR_CNN_DEBUG_CTRL_MASK (0x00000003U)
  4955. /*
  4956. Debug is switched off */
  4957. #define VHA_CR_CNN_DEBUG_CTRL_DISABLE (0x00000000U)
  4958. /*
  4959. Debug is output at the end of each stream */
  4960. #define VHA_CR_CNN_DEBUG_CTRL_STREAM (0x00000001U)
  4961. /*
  4962. Debug is output at the end of each layer */
  4963. #define VHA_CR_CNN_DEBUG_CTRL_LAYER (0x00000002U)
  4964. /*
  4965. Debug is output at the end of each pass */
  4966. #define VHA_CR_CNN_DEBUG_CTRL_PASS (0x00000003U)
  4967. #define VHA_CR_CNN_DEBUG_CTRL_BAND_MASK (0x00000003U)
  4968. /*
  4969. Debug is switched off */
  4970. #define VHA_CR_CNN_DEBUG_CTRL_BAND_DISABLE (0x00000000U)
  4971. /*
  4972. Debug is Switched off */
  4973. #define VHA_CR_CNN_DEBUG_CTRL_BAND_RESERVED (0x00000001U)
  4974. /*
  4975. Debug is output at the end of each layer */
  4976. #define VHA_CR_CNN_DEBUG_CTRL_BAND_LAYER (0x00000002U)
  4977. /*
  4978. Debug is output at the end of each pass */
  4979. #define VHA_CR_CNN_DEBUG_CTRL_BAND_PASS (0x00000003U)
  4980. #define VHA_CR_CNN_PRELOAD_CTRL_MASK (0x00000007U)
  4981. /*
  4982. Preloads are switched off */
  4983. #define VHA_CR_CNN_PRELOAD_CTRL_DISABLE (0x00000000U)
  4984. /*
  4985. Preloads are triggered 64 requests after the previous 32k boundary */
  4986. #define VHA_CR_CNN_PRELOAD_CTRL_N_64 (0x00000001U)
  4987. /*
  4988. Preloads are triggered 128 requests after the previous 32k boundary */
  4989. #define VHA_CR_CNN_PRELOAD_CTRL_N_128 (0x00000002U)
  4990. /*
  4991. Preloads are triggered 192 requests after the previous 32k boundary */
  4992. #define VHA_CR_CNN_PRELOAD_CTRL_N_192 (0x00000003U)
  4993. /*
  4994. Preloads are triggered 256 requests after the previous 32k boundary */
  4995. #define VHA_CR_CNN_PRELOAD_CTRL_N_256 (0x00000004U)
  4996. /*
  4997. Preloads are triggered 320 requests after the previous 32k boundary */
  4998. #define VHA_CR_CNN_PRELOAD_CTRL_N_320 (0x00000005U)
  4999. /*
  5000. Preloads are triggered 384 requests after the previous 32k boundary */
  5001. #define VHA_CR_CNN_PRELOAD_CTRL_N_384 (0x00000006U)
  5002. /*
  5003. Preloads are triggered 448 requests after the previous 32k boundary */
  5004. #define VHA_CR_CNN_PRELOAD_CTRL_N_448 (0x00000007U)
  5005. /*
  5006. Memory buffer will be used for MODEL only (CBUF, CMD , DEBUG, PERF) */
  5007. #define VHA_CR_ALT_ADDR_BUF_TYPE_MODEL_ONLY (0x00000000U)
  5008. /*
  5009. Memory buffer will be used for IO Only( OUTPACK , IBUF , ABUF, EWO ) or Both MODEL and IO */
  5010. #define VHA_CR_ALT_ADDR_BUF_TYPE_IO_OR_SHARED (0x00000001U)
  5011. /*
  5012. Register VHA_CR_OS0_CNN_CONTROL
  5013. */
  5014. #define VHA_CR_OS0_CNN_CONTROL (0x30000U)
  5015. #define VHA_CR_OS0_CNN_CONTROL_MASKFULL (IMG_UINT64_C(0x00000000013F7F7E))
  5016. #define VHA_CR_OS0_CNN_CONTROL_START_SHIFT (24U)
  5017. #define VHA_CR_OS0_CNN_CONTROL_START_CLRMSK (0XFEFFFFFFU)
  5018. #define VHA_CR_OS0_CNN_CONTROL_START_EN (0X01000000U)
  5019. #define VHA_CR_OS0_CNN_CONTROL_ENABLE_SKIP_LAYERS_SHIFT (21U)
  5020. #define VHA_CR_OS0_CNN_CONTROL_ENABLE_SKIP_LAYERS_CLRMSK (0XFFDFFFFFU)
  5021. #define VHA_CR_OS0_CNN_CONTROL_ENABLE_SKIP_LAYERS_EN (0X00200000U)
  5022. #define VHA_CR_OS0_CNN_CONTROL_CTXT_PASID_SHIFT (16U)
  5023. #define VHA_CR_OS0_CNN_CONTROL_CTXT_PASID_CLRMSK (0XFFE0FFFFU)
  5024. #define VHA_CR_OS0_CNN_CONTROL_CTXT_PASID_IO_SHIFT (10U)
  5025. #define VHA_CR_OS0_CNN_CONTROL_CTXT_PASID_IO_CLRMSK (0XFFFF83FFU)
  5026. #define VHA_CR_OS0_CNN_CONTROL_PRIORITY_SHIFT (8U)
  5027. #define VHA_CR_OS0_CNN_CONTROL_PRIORITY_CLRMSK (0XFFFFFCFFU)
  5028. #define VHA_CR_OS0_CNN_CONTROL_CMD_SIZE_MIN1_SHIFT (1U)
  5029. #define VHA_CR_OS0_CNN_CONTROL_CMD_SIZE_MIN1_CLRMSK (0XFFFFFF81U)
  5030. #define VHA_CR_OS0_CNN_STATUS_STATE_MASK (0x00000003U)
  5031. /*
  5032. No requests are pending for this host*/
  5033. #define VHA_CR_OS0_CNN_STATUS_STATE_IDLE (0x00000000U)
  5034. /*
  5035. A command stream from this host is being processed*/
  5036. #define VHA_CR_OS0_CNN_STATUS_STATE_RUN (0x00000001U)
  5037. /*
  5038. The command stream from this host has been suspended due to higher priority request from another host*/
  5039. #define VHA_CR_OS0_CNN_STATUS_STATE_SUSPEND (0x00000002U)
  5040. /*
  5041. A command stream from this host is pending but not been started */
  5042. #define VHA_CR_OS0_CNN_STATUS_STATE_PENDING (0x00000003U)
  5043. /*
  5044. Register VHA_CR_OS0_CNN_STATUS
  5045. */
  5046. #define VHA_CR_OS0_CNN_STATUS (0x30008U)
  5047. #define VHA_CR_OS0_CNN_STATUS_MASKFULL (IMG_UINT64_C(0x00000000C1FFFFFF))
  5048. #define VHA_CR_OS0_CNN_STATUS_CURRENT_STATE_SHIFT (30U)
  5049. #define VHA_CR_OS0_CNN_STATUS_CURRENT_STATE_CLRMSK (0X3FFFFFFFU)
  5050. #define VHA_CR_OS0_CNN_STATUS_CURRENT_STATE_IDLE (00000000U)
  5051. #define VHA_CR_OS0_CNN_STATUS_CURRENT_STATE_RUN (0X40000000U)
  5052. #define VHA_CR_OS0_CNN_STATUS_CURRENT_STATE_SUSPEND (0X80000000U)
  5053. #define VHA_CR_OS0_CNN_STATUS_CURRENT_STATE_PENDING (0XC0000000U)
  5054. #define VHA_CR_OS0_CNN_STATUS_PARITY_SHIFT (24U)
  5055. #define VHA_CR_OS0_CNN_STATUS_PARITY_CLRMSK (0XFEFFFFFFU)
  5056. #define VHA_CR_OS0_CNN_STATUS_PARITY_EN (0X01000000U)
  5057. #define VHA_CR_OS0_CNN_STATUS_LAYER_COUNT_SHIFT (8U)
  5058. #define VHA_CR_OS0_CNN_STATUS_LAYER_COUNT_CLRMSK (0XFF0000FFU)
  5059. #define VHA_CR_OS0_CNN_STATUS_STREAM_COUNT_SHIFT (0U)
  5060. #define VHA_CR_OS0_CNN_STATUS_STREAM_COUNT_CLRMSK (0XFFFFFF00U)
  5061. /*
  5062. Register VHA_CR_OS0_CNN_STATUS2
  5063. */
  5064. #define VHA_CR_OS0_CNN_STATUS2 (0x30010U)
  5065. #define VHA_CR_OS0_CNN_STATUS2_MASKFULL (IMG_UINT64_C(0x000000000000FFFF))
  5066. #define VHA_CR_OS0_CNN_STATUS2_PASS_COUNT_SHIFT (0U)
  5067. #define VHA_CR_OS0_CNN_STATUS2_PASS_COUNT_CLRMSK (0XFFFF0000U)
  5068. /*
  5069. Register VHA_CR_OS0_CNN_CMD_BASE_ADDRESS
  5070. */
  5071. #define VHA_CR_OS0_CNN_CMD_BASE_ADDRESS (0x30018U)
  5072. #define VHA_CR_OS0_CNN_CMD_BASE_ADDRESS_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFF80))
  5073. #define VHA_CR_OS0_CNN_CMD_BASE_ADDRESS_BASE_ADDR_SHIFT (7U)
  5074. #define VHA_CR_OS0_CNN_CMD_BASE_ADDRESS_BASE_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF000000007F))
  5075. /*
  5076. Register VHA_CR_OS0_CNN_ALT_ADDRESS_USED
  5077. */
  5078. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED (0x30020U)
  5079. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  5080. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR15_BUF_TYPE_SHIFT (31U)
  5081. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR15_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFF7FFFFFFF))
  5082. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR15_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  5083. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR15_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000080000000))
  5084. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR14_BUF_TYPE_SHIFT (30U)
  5085. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR14_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFBFFFFFFF))
  5086. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR14_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  5087. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR14_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000040000000))
  5088. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR13_BUF_TYPE_SHIFT (29U)
  5089. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR13_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFDFFFFFFF))
  5090. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR13_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  5091. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR13_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000020000000))
  5092. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR12_BUF_TYPE_SHIFT (28U)
  5093. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR12_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFEFFFFFFF))
  5094. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR12_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  5095. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR12_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000010000000))
  5096. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR11_BUF_TYPE_SHIFT (27U)
  5097. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR11_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFF7FFFFFF))
  5098. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR11_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  5099. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR11_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000008000000))
  5100. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR10_BUF_TYPE_SHIFT (26U)
  5101. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR10_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFBFFFFFF))
  5102. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR10_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  5103. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR10_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000004000000))
  5104. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR9_BUF_TYPE_SHIFT (25U)
  5105. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR9_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFDFFFFFF))
  5106. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR9_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  5107. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR9_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000002000000))
  5108. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR8_BUF_TYPE_SHIFT (24U)
  5109. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR8_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFEFFFFFF))
  5110. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR8_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  5111. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR8_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000001000000))
  5112. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR7_BUF_TYPE_SHIFT (23U)
  5113. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR7_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF7FFFFF))
  5114. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR7_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  5115. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR7_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000000800000))
  5116. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR6_BUF_TYPE_SHIFT (22U)
  5117. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR6_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFBFFFFF))
  5118. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR6_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  5119. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR6_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000000400000))
  5120. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR5_BUF_TYPE_SHIFT (21U)
  5121. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR5_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFDFFFFF))
  5122. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR5_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  5123. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR5_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000000200000))
  5124. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR4_BUF_TYPE_SHIFT (20U)
  5125. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR4_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFEFFFFF))
  5126. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR4_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  5127. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR4_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000000100000))
  5128. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR3_BUF_TYPE_SHIFT (19U)
  5129. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR3_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF7FFFF))
  5130. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR3_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  5131. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR3_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000000080000))
  5132. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR2_BUF_TYPE_SHIFT (18U)
  5133. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR2_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFBFFFF))
  5134. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR2_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  5135. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR2_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000000040000))
  5136. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR1_BUF_TYPE_SHIFT (17U)
  5137. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR1_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFDFFFF))
  5138. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR1_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  5139. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR1_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000000020000))
  5140. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR0_BUF_TYPE_SHIFT (16U)
  5141. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR0_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFEFFFF))
  5142. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR0_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  5143. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR0_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000000010000))
  5144. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR15_USED_SHIFT (15U)
  5145. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR15_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF7FFF))
  5146. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR15_USED_EN (IMG_UINT64_C(0X0000000000008000))
  5147. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR14_USED_SHIFT (14U)
  5148. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR14_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFBFFF))
  5149. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR14_USED_EN (IMG_UINT64_C(0X0000000000004000))
  5150. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR13_USED_SHIFT (13U)
  5151. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR13_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFDFFF))
  5152. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR13_USED_EN (IMG_UINT64_C(0X0000000000002000))
  5153. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR12_USED_SHIFT (12U)
  5154. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR12_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFEFFF))
  5155. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR12_USED_EN (IMG_UINT64_C(0X0000000000001000))
  5156. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR11_USED_SHIFT (11U)
  5157. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR11_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF7FF))
  5158. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR11_USED_EN (IMG_UINT64_C(0X0000000000000800))
  5159. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR10_USED_SHIFT (10U)
  5160. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR10_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFBFF))
  5161. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR10_USED_EN (IMG_UINT64_C(0X0000000000000400))
  5162. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR9_USED_SHIFT (9U)
  5163. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR9_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFDFF))
  5164. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR9_USED_EN (IMG_UINT64_C(0X0000000000000200))
  5165. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR8_USED_SHIFT (8U)
  5166. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR8_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFEFF))
  5167. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR8_USED_EN (IMG_UINT64_C(0X0000000000000100))
  5168. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR7_USED_SHIFT (7U)
  5169. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR7_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFF7F))
  5170. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR7_USED_EN (IMG_UINT64_C(0X0000000000000080))
  5171. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR6_USED_SHIFT (6U)
  5172. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR6_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFBF))
  5173. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR6_USED_EN (IMG_UINT64_C(0X0000000000000040))
  5174. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR5_USED_SHIFT (5U)
  5175. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR5_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFDF))
  5176. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR5_USED_EN (IMG_UINT64_C(0X0000000000000020))
  5177. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR4_USED_SHIFT (4U)
  5178. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR4_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFEF))
  5179. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR4_USED_EN (IMG_UINT64_C(0X0000000000000010))
  5180. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR3_USED_SHIFT (3U)
  5181. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR3_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF7))
  5182. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR3_USED_EN (IMG_UINT64_C(0X0000000000000008))
  5183. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR2_USED_SHIFT (2U)
  5184. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR2_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFB))
  5185. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR2_USED_EN (IMG_UINT64_C(0X0000000000000004))
  5186. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR1_USED_SHIFT (1U)
  5187. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR1_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFD))
  5188. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR1_USED_EN (IMG_UINT64_C(0X0000000000000002))
  5189. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR0_USED_SHIFT (0U)
  5190. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR0_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  5191. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR0_USED_EN (IMG_UINT64_C(0X0000000000000001))
  5192. /*
  5193. Register VHA_CR_OS0_CNN_ALT_ADDRESS0
  5194. */
  5195. #define VHA_CR_OS0_CNN_ALT_ADDRESS0 (0x30028U)
  5196. #define VHA_CR_OS0_CNN_ALT_ADDRESS0_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  5197. #define VHA_CR_OS0_CNN_ALT_ADDRESS0_ALT_ADDR_SHIFT (0U)
  5198. #define VHA_CR_OS0_CNN_ALT_ADDRESS0_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  5199. /*
  5200. Register VHA_CR_OS0_CNN_ALT_ADDRESS1
  5201. */
  5202. #define VHA_CR_OS0_CNN_ALT_ADDRESS1 (0x30030U)
  5203. #define VHA_CR_OS0_CNN_ALT_ADDRESS1_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  5204. #define VHA_CR_OS0_CNN_ALT_ADDRESS1_ALT_ADDR_SHIFT (0U)
  5205. #define VHA_CR_OS0_CNN_ALT_ADDRESS1_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  5206. /*
  5207. Register VHA_CR_OS0_CNN_ALT_ADDRESS2
  5208. */
  5209. #define VHA_CR_OS0_CNN_ALT_ADDRESS2 (0x30038U)
  5210. #define VHA_CR_OS0_CNN_ALT_ADDRESS2_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  5211. #define VHA_CR_OS0_CNN_ALT_ADDRESS2_ALT_ADDR_SHIFT (0U)
  5212. #define VHA_CR_OS0_CNN_ALT_ADDRESS2_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  5213. /*
  5214. Register VHA_CR_OS0_CNN_ALT_ADDRESS3
  5215. */
  5216. #define VHA_CR_OS0_CNN_ALT_ADDRESS3 (0x30040U)
  5217. #define VHA_CR_OS0_CNN_ALT_ADDRESS3_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  5218. #define VHA_CR_OS0_CNN_ALT_ADDRESS3_ALT_ADDR_SHIFT (0U)
  5219. #define VHA_CR_OS0_CNN_ALT_ADDRESS3_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  5220. /*
  5221. Register VHA_CR_OS0_CNN_ALT_ADDRESS4
  5222. */
  5223. #define VHA_CR_OS0_CNN_ALT_ADDRESS4 (0x30048U)
  5224. #define VHA_CR_OS0_CNN_ALT_ADDRESS4_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  5225. #define VHA_CR_OS0_CNN_ALT_ADDRESS4_ALT_ADDR_SHIFT (0U)
  5226. #define VHA_CR_OS0_CNN_ALT_ADDRESS4_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  5227. /*
  5228. Register VHA_CR_OS0_CNN_ALT_ADDRESS5
  5229. */
  5230. #define VHA_CR_OS0_CNN_ALT_ADDRESS5 (0x30050U)
  5231. #define VHA_CR_OS0_CNN_ALT_ADDRESS5_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  5232. #define VHA_CR_OS0_CNN_ALT_ADDRESS5_ALT_ADDR_SHIFT (0U)
  5233. #define VHA_CR_OS0_CNN_ALT_ADDRESS5_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  5234. /*
  5235. Register VHA_CR_OS0_CNN_ALT_ADDRESS6
  5236. */
  5237. #define VHA_CR_OS0_CNN_ALT_ADDRESS6 (0x30058U)
  5238. #define VHA_CR_OS0_CNN_ALT_ADDRESS6_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  5239. #define VHA_CR_OS0_CNN_ALT_ADDRESS6_ALT_ADDR_SHIFT (0U)
  5240. #define VHA_CR_OS0_CNN_ALT_ADDRESS6_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  5241. /*
  5242. Register VHA_CR_OS0_CNN_ALT_ADDRESS7
  5243. */
  5244. #define VHA_CR_OS0_CNN_ALT_ADDRESS7 (0x30060U)
  5245. #define VHA_CR_OS0_CNN_ALT_ADDRESS7_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  5246. #define VHA_CR_OS0_CNN_ALT_ADDRESS7_ALT_ADDR_SHIFT (0U)
  5247. #define VHA_CR_OS0_CNN_ALT_ADDRESS7_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  5248. /*
  5249. Register VHA_CR_OS0_CNN_WRITEBACK_CONTROL
  5250. */
  5251. #define VHA_CR_OS0_CNN_WRITEBACK_CONTROL (0x30068U)
  5252. #define VHA_CR_OS0_CNN_WRITEBACK_CONTROL_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  5253. #define VHA_CR_OS0_CNN_WRITEBACK_CONTROL_WRITE_BACK_VALUE_SHIFT (0U)
  5254. #define VHA_CR_OS0_CNN_WRITEBACK_CONTROL_WRITE_BACK_VALUE_CLRMSK (00000000U)
  5255. /*
  5256. Register VHA_CR_OS0_CNN_CRC_CONTROL
  5257. */
  5258. #define VHA_CR_OS0_CNN_CRC_CONTROL (0x30088U)
  5259. #define VHA_CR_OS0_CNN_CRC_CONTROL_MASKFULL (IMG_UINT64_C(0x0000000000000013))
  5260. #define VHA_CR_OS0_CNN_CRC_CONTROL_COMBINED_CNN_CRC_ENABLE_SHIFT (4U)
  5261. #define VHA_CR_OS0_CNN_CRC_CONTROL_COMBINED_CNN_CRC_ENABLE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFEF))
  5262. #define VHA_CR_OS0_CNN_CRC_CONTROL_COMBINED_CNN_CRC_ENABLE_EN (IMG_UINT64_C(0X0000000000000010))
  5263. #define VHA_CR_OS0_CNN_CRC_CONTROL_CNN_CRC_ENABLE_SHIFT (0U)
  5264. #define VHA_CR_OS0_CNN_CRC_CONTROL_CNN_CRC_ENABLE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFC))
  5265. #define VHA_CR_OS0_CNN_CRC_CONTROL_CNN_CRC_ENABLE_DISABLE (IMG_UINT64_C(0000000000000000))
  5266. #define VHA_CR_OS0_CNN_CRC_CONTROL_CNN_CRC_ENABLE_STREAM (IMG_UINT64_C(0x0000000000000001))
  5267. #define VHA_CR_OS0_CNN_CRC_CONTROL_CNN_CRC_ENABLE_LAYER (IMG_UINT64_C(0x0000000000000002))
  5268. #define VHA_CR_OS0_CNN_CRC_CONTROL_CNN_CRC_ENABLE_PASS (IMG_UINT64_C(0x0000000000000003))
  5269. /*
  5270. Register VHA_CR_OS0_CNN_CRC_ADDRESS
  5271. */
  5272. #define VHA_CR_OS0_CNN_CRC_ADDRESS (0x30090U)
  5273. #define VHA_CR_OS0_CNN_CRC_ADDRESS_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFF80))
  5274. #define VHA_CR_OS0_CNN_CRC_ADDRESS_CNN_CRC_ADDR_SHIFT (7U)
  5275. #define VHA_CR_OS0_CNN_CRC_ADDRESS_CNN_CRC_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF000000007F))
  5276. #define VHA_CR_OS0_CNN_CRC_ADDRESS_CNN_CRC_ADDR_ALIGNSHIFT (7U)
  5277. #define VHA_CR_OS0_CNN_CRC_ADDRESS_CNN_CRC_ADDR_ALIGNSIZE (128U)
  5278. /*
  5279. Register VHA_CR_OS0_CNN_DEBUG_ADDRESS
  5280. */
  5281. #define VHA_CR_OS0_CNN_DEBUG_ADDRESS (0x30098U)
  5282. #define VHA_CR_OS0_CNN_DEBUG_ADDRESS_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFF80))
  5283. #define VHA_CR_OS0_CNN_DEBUG_ADDRESS_CNN_DEBUG_ADDR_SHIFT (7U)
  5284. #define VHA_CR_OS0_CNN_DEBUG_ADDRESS_CNN_DEBUG_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF000000007F))
  5285. #define VHA_CR_OS0_CNN_DEBUG_ADDRESS_CNN_DEBUG_ADDR_ALIGNSHIFT (7U)
  5286. #define VHA_CR_OS0_CNN_DEBUG_ADDRESS_CNN_DEBUG_ADDR_ALIGNSIZE (128U)
  5287. /*
  5288. Register VHA_CR_OS0_CNN_DEBUG_SIZE_LEGACY
  5289. */
  5290. #define VHA_CR_OS0_CNN_DEBUG_SIZE_LEGACY (0x300A0U)
  5291. #define VHA_CR_OS0_CNN_DEBUG_SIZE_LEGACY_MASKFULL (IMG_UINT64_C(0x0000000000FFFFE0))
  5292. #define VHA_CR_OS0_CNN_DEBUG_SIZE_LEGACY_CNN_DEBUG_SIZE_SHIFT (5U)
  5293. #define VHA_CR_OS0_CNN_DEBUG_SIZE_LEGACY_CNN_DEBUG_SIZE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF00001F))
  5294. #define VHA_CR_OS0_CNN_DEBUG_SIZE_LEGACY_CNN_DEBUG_SIZE_ALIGNSHIFT (5U)
  5295. #define VHA_CR_OS0_CNN_DEBUG_SIZE_LEGACY_CNN_DEBUG_SIZE_ALIGNSIZE (32U)
  5296. /*
  5297. Register VHA_CR_OS0_CNN_DEBUG_CONTROL
  5298. */
  5299. #define VHA_CR_OS0_CNN_DEBUG_CONTROL (0x300A8U)
  5300. #define VHA_CR_OS0_CNN_DEBUG_CONTROL_MASKFULL (IMG_UINT64_C(0x000000000000000F))
  5301. #define VHA_CR_OS0_CNN_DEBUG_CONTROL_CNN_PERF_ENABLE_SHIFT (2U)
  5302. #define VHA_CR_OS0_CNN_DEBUG_CONTROL_CNN_PERF_ENABLE_CLRMSK (0XFFFFFFF3U)
  5303. #define VHA_CR_OS0_CNN_DEBUG_CONTROL_CNN_PERF_ENABLE_DISABLE (00000000U)
  5304. #define VHA_CR_OS0_CNN_DEBUG_CONTROL_CNN_PERF_ENABLE_STREAM (0X00000004U)
  5305. #define VHA_CR_OS0_CNN_DEBUG_CONTROL_CNN_PERF_ENABLE_LAYER (0X00000008U)
  5306. #define VHA_CR_OS0_CNN_DEBUG_CONTROL_CNN_PERF_ENABLE_PASS (0X0000000CU)
  5307. #define VHA_CR_OS0_CNN_DEBUG_CONTROL_CNN_BAND_ENABLE_SHIFT (0U)
  5308. #define VHA_CR_OS0_CNN_DEBUG_CONTROL_CNN_BAND_ENABLE_CLRMSK (0XFFFFFFFCU)
  5309. #define VHA_CR_OS0_CNN_DEBUG_CONTROL_CNN_BAND_ENABLE_DISABLE (00000000U)
  5310. #define VHA_CR_OS0_CNN_DEBUG_CONTROL_CNN_BAND_ENABLE_RESERVED (0X00000001U)
  5311. #define VHA_CR_OS0_CNN_DEBUG_CONTROL_CNN_BAND_ENABLE_LAYER (0X00000002U)
  5312. #define VHA_CR_OS0_CNN_DEBUG_CONTROL_CNN_BAND_ENABLE_PASS (0X00000003U)
  5313. /*
  5314. Register VHA_CR_OS0_CNN_DEBUG_STATUS
  5315. */
  5316. #define VHA_CR_OS0_CNN_DEBUG_STATUS (0x300B0U)
  5317. #define VHA_CR_OS0_CNN_DEBUG_STATUS_MASKFULL (IMG_UINT64_C(0x000000000007FFFF))
  5318. #define VHA_CR_OS0_CNN_DEBUG_STATUS_CNN_DEBUG_OFFSET_SHIFT (0U)
  5319. #define VHA_CR_OS0_CNN_DEBUG_STATUS_CNN_DEBUG_OFFSET_CLRMSK (0XFFF80000U)
  5320. /*
  5321. Register VHA_CR_OS0_CNN_PRELOAD_CONTROL
  5322. */
  5323. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL (0x300B8U)
  5324. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MASKFULL (IMG_UINT64_C(0x0000000001FF7777))
  5325. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_SHIFT (22U)
  5326. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFE3FFFFF))
  5327. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_DISABLE (IMG_UINT64_C(0000000000000000))
  5328. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_N_64 (IMG_UINT64_C(0x0000000000400000))
  5329. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_N_128 (IMG_UINT64_C(0x0000000000800000))
  5330. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_N_192 (IMG_UINT64_C(0x0000000000c00000))
  5331. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_N_256 (IMG_UINT64_C(0x0000000001000000))
  5332. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_N_320 (IMG_UINT64_C(0x0000000001400000))
  5333. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_N_384 (IMG_UINT64_C(0x0000000001800000))
  5334. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_N_448 (IMG_UINT64_C(0x0000000001c00000))
  5335. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_SHIFT (19U)
  5336. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFC7FFFF))
  5337. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_DISABLE (IMG_UINT64_C(0000000000000000))
  5338. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_N_64 (IMG_UINT64_C(0x0000000000080000))
  5339. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_N_128 (IMG_UINT64_C(0x0000000000100000))
  5340. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_N_192 (IMG_UINT64_C(0x0000000000180000))
  5341. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_N_256 (IMG_UINT64_C(0x0000000000200000))
  5342. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_N_320 (IMG_UINT64_C(0x0000000000280000))
  5343. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_N_384 (IMG_UINT64_C(0x0000000000300000))
  5344. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_N_448 (IMG_UINT64_C(0x0000000000380000))
  5345. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_SHIFT (16U)
  5346. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF8FFFF))
  5347. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_DISABLE (IMG_UINT64_C(0000000000000000))
  5348. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_N_64 (IMG_UINT64_C(0x0000000000010000))
  5349. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_N_128 (IMG_UINT64_C(0x0000000000020000))
  5350. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_N_192 (IMG_UINT64_C(0x0000000000030000))
  5351. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_N_256 (IMG_UINT64_C(0x0000000000040000))
  5352. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_N_320 (IMG_UINT64_C(0x0000000000050000))
  5353. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_N_384 (IMG_UINT64_C(0x0000000000060000))
  5354. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_N_448 (IMG_UINT64_C(0x0000000000070000))
  5355. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_EWO_N_REQS_SHIFT (12U)
  5356. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_EWO_N_REQS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF8FFF))
  5357. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_EWO_N_REQS_DISABLE (IMG_UINT64_C(0000000000000000))
  5358. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_EWO_N_REQS_N_64 (IMG_UINT64_C(0x0000000000001000))
  5359. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_EWO_N_REQS_N_128 (IMG_UINT64_C(0x0000000000002000))
  5360. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_EWO_N_REQS_N_192 (IMG_UINT64_C(0x0000000000003000))
  5361. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_EWO_N_REQS_N_256 (IMG_UINT64_C(0x0000000000004000))
  5362. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_EWO_N_REQS_N_320 (IMG_UINT64_C(0x0000000000005000))
  5363. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_EWO_N_REQS_N_384 (IMG_UINT64_C(0x0000000000006000))
  5364. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_EWO_N_REQS_N_448 (IMG_UINT64_C(0x0000000000007000))
  5365. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_ABUF_N_REQS_SHIFT (8U)
  5366. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_ABUF_N_REQS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF8FF))
  5367. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_ABUF_N_REQS_DISABLE (IMG_UINT64_C(0000000000000000))
  5368. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_ABUF_N_REQS_N_64 (IMG_UINT64_C(0x0000000000000100))
  5369. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_ABUF_N_REQS_N_128 (IMG_UINT64_C(0x0000000000000200))
  5370. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_ABUF_N_REQS_N_192 (IMG_UINT64_C(0x0000000000000300))
  5371. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_ABUF_N_REQS_N_256 (IMG_UINT64_C(0x0000000000000400))
  5372. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_ABUF_N_REQS_N_320 (IMG_UINT64_C(0x0000000000000500))
  5373. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_ABUF_N_REQS_N_384 (IMG_UINT64_C(0x0000000000000600))
  5374. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_ABUF_N_REQS_N_448 (IMG_UINT64_C(0x0000000000000700))
  5375. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_CBUF_N_REQS_SHIFT (4U)
  5376. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_CBUF_N_REQS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFF8F))
  5377. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_CBUF_N_REQS_DISABLE (IMG_UINT64_C(0000000000000000))
  5378. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_CBUF_N_REQS_N_64 (IMG_UINT64_C(0x0000000000000010))
  5379. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_CBUF_N_REQS_N_128 (IMG_UINT64_C(0x0000000000000020))
  5380. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_CBUF_N_REQS_N_192 (IMG_UINT64_C(0x0000000000000030))
  5381. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_CBUF_N_REQS_N_256 (IMG_UINT64_C(0x0000000000000040))
  5382. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_CBUF_N_REQS_N_320 (IMG_UINT64_C(0x0000000000000050))
  5383. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_CBUF_N_REQS_N_384 (IMG_UINT64_C(0x0000000000000060))
  5384. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_CBUF_N_REQS_N_448 (IMG_UINT64_C(0x0000000000000070))
  5385. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_IBUF_N_REQS_SHIFT (0U)
  5386. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_IBUF_N_REQS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF8))
  5387. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_IBUF_N_REQS_DISABLE (IMG_UINT64_C(0000000000000000))
  5388. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_IBUF_N_REQS_N_64 (IMG_UINT64_C(0x0000000000000001))
  5389. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_IBUF_N_REQS_N_128 (IMG_UINT64_C(0x0000000000000002))
  5390. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_IBUF_N_REQS_N_192 (IMG_UINT64_C(0x0000000000000003))
  5391. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_IBUF_N_REQS_N_256 (IMG_UINT64_C(0x0000000000000004))
  5392. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_IBUF_N_REQS_N_320 (IMG_UINT64_C(0x0000000000000005))
  5393. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_IBUF_N_REQS_N_384 (IMG_UINT64_C(0x0000000000000006))
  5394. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_IBUF_N_REQS_N_448 (IMG_UINT64_C(0x0000000000000007))
  5395. /*
  5396. Register VHA_CR_OS0_CNN_ALT_ADDRESS8
  5397. */
  5398. #define VHA_CR_OS0_CNN_ALT_ADDRESS8 (0x300C0U)
  5399. #define VHA_CR_OS0_CNN_ALT_ADDRESS8_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  5400. #define VHA_CR_OS0_CNN_ALT_ADDRESS8_ALT_ADDR_SHIFT (0U)
  5401. #define VHA_CR_OS0_CNN_ALT_ADDRESS8_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  5402. /*
  5403. Register VHA_CR_OS0_CNN_ALT_ADDRESS9
  5404. */
  5405. #define VHA_CR_OS0_CNN_ALT_ADDRESS9 (0x300C8U)
  5406. #define VHA_CR_OS0_CNN_ALT_ADDRESS9_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  5407. #define VHA_CR_OS0_CNN_ALT_ADDRESS9_ALT_ADDR_SHIFT (0U)
  5408. #define VHA_CR_OS0_CNN_ALT_ADDRESS9_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  5409. /*
  5410. Register VHA_CR_OS0_CNN_ALT_ADDRESS10
  5411. */
  5412. #define VHA_CR_OS0_CNN_ALT_ADDRESS10 (0x300D0U)
  5413. #define VHA_CR_OS0_CNN_ALT_ADDRESS10_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  5414. #define VHA_CR_OS0_CNN_ALT_ADDRESS10_ALT_ADDR_SHIFT (0U)
  5415. #define VHA_CR_OS0_CNN_ALT_ADDRESS10_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  5416. /*
  5417. Register VHA_CR_OS0_CNN_ALT_ADDRESS11
  5418. */
  5419. #define VHA_CR_OS0_CNN_ALT_ADDRESS11 (0x300D8U)
  5420. #define VHA_CR_OS0_CNN_ALT_ADDRESS11_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  5421. #define VHA_CR_OS0_CNN_ALT_ADDRESS11_ALT_ADDR_SHIFT (0U)
  5422. #define VHA_CR_OS0_CNN_ALT_ADDRESS11_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  5423. /*
  5424. Register VHA_CR_OS0_CNN_ALT_ADDRESS12
  5425. */
  5426. #define VHA_CR_OS0_CNN_ALT_ADDRESS12 (0x300E0U)
  5427. #define VHA_CR_OS0_CNN_ALT_ADDRESS12_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  5428. #define VHA_CR_OS0_CNN_ALT_ADDRESS12_ALT_ADDR_SHIFT (0U)
  5429. #define VHA_CR_OS0_CNN_ALT_ADDRESS12_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  5430. /*
  5431. Register VHA_CR_OS0_CNN_ALT_ADDRESS13
  5432. */
  5433. #define VHA_CR_OS0_CNN_ALT_ADDRESS13 (0x300E8U)
  5434. #define VHA_CR_OS0_CNN_ALT_ADDRESS13_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  5435. #define VHA_CR_OS0_CNN_ALT_ADDRESS13_ALT_ADDR_SHIFT (0U)
  5436. #define VHA_CR_OS0_CNN_ALT_ADDRESS13_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  5437. /*
  5438. Register VHA_CR_OS0_CNN_ALT_ADDRESS14
  5439. */
  5440. #define VHA_CR_OS0_CNN_ALT_ADDRESS14 (0x300F0U)
  5441. #define VHA_CR_OS0_CNN_ALT_ADDRESS14_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  5442. #define VHA_CR_OS0_CNN_ALT_ADDRESS14_ALT_ADDR_SHIFT (0U)
  5443. #define VHA_CR_OS0_CNN_ALT_ADDRESS14_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  5444. /*
  5445. Register VHA_CR_OS0_CNN_ALT_ADDRESS15
  5446. */
  5447. #define VHA_CR_OS0_CNN_ALT_ADDRESS15 (0x300F8U)
  5448. #define VHA_CR_OS0_CNN_ALT_ADDRESS15_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  5449. #define VHA_CR_OS0_CNN_ALT_ADDRESS15_ALT_ADDR_SHIFT (0U)
  5450. #define VHA_CR_OS0_CNN_ALT_ADDRESS15_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  5451. /*
  5452. Register VHA_CR_OS0_CNN_PERFORMANCE
  5453. */
  5454. #define VHA_CR_OS0_CNN_PERFORMANCE (0x30100U)
  5455. #define VHA_CR_OS0_CNN_PERFORMANCE_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  5456. #define VHA_CR_OS0_CNN_PERFORMANCE_VALUE_SHIFT (0U)
  5457. #define VHA_CR_OS0_CNN_PERFORMANCE_VALUE_CLRMSK (00000000U)
  5458. /*
  5459. Register VHA_CR_OS0_LOCM_BASE_ADDR
  5460. */
  5461. #define VHA_CR_OS0_LOCM_BASE_ADDR (0x30108U)
  5462. #define VHA_CR_OS0_LOCM_BASE_ADDR_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFE0))
  5463. #define VHA_CR_OS0_LOCM_BASE_ADDR_BASE_ADDR_SHIFT (5U)
  5464. #define VHA_CR_OS0_LOCM_BASE_ADDR_BASE_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF000000001F))
  5465. /*
  5466. Register VHA_CR_OS0_SAVE_RESTORE_BUFFER_BASE_ADDR
  5467. */
  5468. #define VHA_CR_OS0_SAVE_RESTORE_BUFFER_BASE_ADDR (0x30110U)
  5469. #define VHA_CR_OS0_SAVE_RESTORE_BUFFER_BASE_ADDR_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  5470. #define VHA_CR_OS0_SAVE_RESTORE_BUFFER_BASE_ADDR_BASE_ADDR_SHIFT (0U)
  5471. #define VHA_CR_OS0_SAVE_RESTORE_BUFFER_BASE_ADDR_BASE_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  5472. /*
  5473. Register VHA_CR_OS0_SAVE_RESTORE_CTRL
  5474. */
  5475. #define VHA_CR_OS0_SAVE_RESTORE_CTRL (0x30118U)
  5476. #define VHA_CR_OS0_SAVE_RESTORE_CTRL_MASKFULL (IMG_UINT64_C(0x000000000000000F))
  5477. #define VHA_CR_OS0_SAVE_RESTORE_CTRL_N_REQS_SHIFT (1U)
  5478. #define VHA_CR_OS0_SAVE_RESTORE_CTRL_N_REQS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF1))
  5479. #define VHA_CR_OS0_SAVE_RESTORE_CTRL_N_REQS_DISABLE (IMG_UINT64_C(0000000000000000))
  5480. #define VHA_CR_OS0_SAVE_RESTORE_CTRL_N_REQS_N_64 (IMG_UINT64_C(0x0000000000000002))
  5481. #define VHA_CR_OS0_SAVE_RESTORE_CTRL_N_REQS_N_128 (IMG_UINT64_C(0x0000000000000004))
  5482. #define VHA_CR_OS0_SAVE_RESTORE_CTRL_N_REQS_N_192 (IMG_UINT64_C(0x0000000000000006))
  5483. #define VHA_CR_OS0_SAVE_RESTORE_CTRL_N_REQS_N_256 (IMG_UINT64_C(0x0000000000000008))
  5484. #define VHA_CR_OS0_SAVE_RESTORE_CTRL_N_REQS_N_320 (IMG_UINT64_C(0x000000000000000a))
  5485. #define VHA_CR_OS0_SAVE_RESTORE_CTRL_N_REQS_N_384 (IMG_UINT64_C(0x000000000000000c))
  5486. #define VHA_CR_OS0_SAVE_RESTORE_CTRL_N_REQS_N_448 (IMG_UINT64_C(0x000000000000000e))
  5487. #define VHA_CR_OS0_SAVE_RESTORE_CTRL_WRITE_CACHE_POLICY_SHIFT (0U)
  5488. #define VHA_CR_OS0_SAVE_RESTORE_CTRL_WRITE_CACHE_POLICY_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  5489. #define VHA_CR_OS0_SAVE_RESTORE_CTRL_WRITE_CACHE_POLICY_EN (IMG_UINT64_C(0X0000000000000001))
  5490. /*
  5491. Register VHA_CR_OS0_CNN_CRC_MASK_CTRL
  5492. */
  5493. #define VHA_CR_OS0_CNN_CRC_MASK_CTRL (0x30120U)
  5494. #define VHA_CR_OS0_CNN_CRC_MASK_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000000003))
  5495. #define VHA_CR_OS0_CNN_CRC_MASK_CTRL_LEVEL_SHIFT (0U)
  5496. #define VHA_CR_OS0_CNN_CRC_MASK_CTRL_LEVEL_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFC))
  5497. #define VHA_CR_OS0_CNN_CRC_MASK_CTRL_LEVEL_DEBUG_INTERNAL (IMG_UINT64_C(0000000000000000))
  5498. #define VHA_CR_OS0_CNN_CRC_MASK_CTRL_LEVEL_DEBUG_SILICON (IMG_UINT64_C(0x0000000000000001))
  5499. #define VHA_CR_OS0_CNN_CRC_MASK_CTRL_LEVEL_SAFETY (IMG_UINT64_C(0x0000000000000002))
  5500. #define VHA_CR_OS0_CNN_CRC_MASK_CTRL_LEVEL_RESERVED (IMG_UINT64_C(0x0000000000000003))
  5501. /*
  5502. Register VHA_CR_OS0_CNN_VCORE_MAPPING
  5503. */
  5504. #define VHA_CR_OS0_CNN_VCORE_MAPPING (0x30128U)
  5505. #define VHA_CR_OS0_CNN_VCORE_MAPPING_MASKFULL (IMG_UINT64_C(0x0000000077777777))
  5506. #define VHA_CR_OS0_CNN_VCORE_MAPPING_VCORE7_SHIFT (28U)
  5507. #define VHA_CR_OS0_CNN_VCORE_MAPPING_VCORE7_CLRMSK (IMG_UINT64_C(0XFFFFFFFF8FFFFFFF))
  5508. #define VHA_CR_OS0_CNN_VCORE_MAPPING_VCORE6_SHIFT (24U)
  5509. #define VHA_CR_OS0_CNN_VCORE_MAPPING_VCORE6_CLRMSK (IMG_UINT64_C(0XFFFFFFFFF8FFFFFF))
  5510. #define VHA_CR_OS0_CNN_VCORE_MAPPING_VCORE5_SHIFT (20U)
  5511. #define VHA_CR_OS0_CNN_VCORE_MAPPING_VCORE5_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF8FFFFF))
  5512. #define VHA_CR_OS0_CNN_VCORE_MAPPING_VCORE4_SHIFT (16U)
  5513. #define VHA_CR_OS0_CNN_VCORE_MAPPING_VCORE4_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF8FFFF))
  5514. #define VHA_CR_OS0_CNN_VCORE_MAPPING_VCORE3_SHIFT (12U)
  5515. #define VHA_CR_OS0_CNN_VCORE_MAPPING_VCORE3_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF8FFF))
  5516. #define VHA_CR_OS0_CNN_VCORE_MAPPING_VCORE2_SHIFT (8U)
  5517. #define VHA_CR_OS0_CNN_VCORE_MAPPING_VCORE2_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF8FF))
  5518. #define VHA_CR_OS0_CNN_VCORE_MAPPING_VCORE1_SHIFT (4U)
  5519. #define VHA_CR_OS0_CNN_VCORE_MAPPING_VCORE1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFF8F))
  5520. #define VHA_CR_OS0_CNN_VCORE_MAPPING_VCORE0_SHIFT (0U)
  5521. #define VHA_CR_OS0_CNN_VCORE_MAPPING_VCORE0_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF8))
  5522. /*
  5523. Register VHA_CR_CORE0_LAST_NNA_SYNC_ID
  5524. */
  5525. #define VHA_CR_CORE0_LAST_NNA_SYNC_ID (0x30130U)
  5526. #define VHA_CR_CORE0_LAST_NNA_SYNC_ID_MASKFULL (IMG_UINT64_C(0x0000000070FFFFFF))
  5527. #define VHA_CR_CORE0_LAST_NNA_SYNC_ID_CORE0_LAST_NNA_SYNC_ID_PARITY_SHIFT (28U)
  5528. #define VHA_CR_CORE0_LAST_NNA_SYNC_ID_CORE0_LAST_NNA_SYNC_ID_PARITY_CLRMSK (IMG_UINT64_C(0XFFFFFFFF8FFFFFFF))
  5529. #define VHA_CR_CORE0_LAST_NNA_SYNC_ID_CORE0_LAST_NNA_SYNC_ID_SHIFT (0U)
  5530. #define VHA_CR_CORE0_LAST_NNA_SYNC_ID_CORE0_LAST_NNA_SYNC_ID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF000000))
  5531. /*
  5532. Register VHA_CR_CORE1_LAST_NNA_SYNC_ID
  5533. */
  5534. #define VHA_CR_CORE1_LAST_NNA_SYNC_ID (0x30138U)
  5535. #define VHA_CR_CORE1_LAST_NNA_SYNC_ID_MASKFULL (IMG_UINT64_C(0x0000000070FFFFFF))
  5536. #define VHA_CR_CORE1_LAST_NNA_SYNC_ID_CORE1_LAST_NNA_SYNC_ID_PARITY_SHIFT (28U)
  5537. #define VHA_CR_CORE1_LAST_NNA_SYNC_ID_CORE1_LAST_NNA_SYNC_ID_PARITY_CLRMSK (IMG_UINT64_C(0XFFFFFFFF8FFFFFFF))
  5538. #define VHA_CR_CORE1_LAST_NNA_SYNC_ID_CORE1_LAST_NNA_SYNC_ID_SHIFT (0U)
  5539. #define VHA_CR_CORE1_LAST_NNA_SYNC_ID_CORE1_LAST_NNA_SYNC_ID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF000000))
  5540. /*
  5541. Register VHA_CR_CORE2_LAST_NNA_SYNC_ID
  5542. */
  5543. #define VHA_CR_CORE2_LAST_NNA_SYNC_ID (0x30140U)
  5544. #define VHA_CR_CORE2_LAST_NNA_SYNC_ID_MASKFULL (IMG_UINT64_C(0x0000000070FFFFFF))
  5545. #define VHA_CR_CORE2_LAST_NNA_SYNC_ID_CORE2_LAST_NNA_SYNC_ID_PARITY_SHIFT (28U)
  5546. #define VHA_CR_CORE2_LAST_NNA_SYNC_ID_CORE2_LAST_NNA_SYNC_ID_PARITY_CLRMSK (IMG_UINT64_C(0XFFFFFFFF8FFFFFFF))
  5547. #define VHA_CR_CORE2_LAST_NNA_SYNC_ID_CORE2_LAST_NNA_SYNC_ID_SHIFT (0U)
  5548. #define VHA_CR_CORE2_LAST_NNA_SYNC_ID_CORE2_LAST_NNA_SYNC_ID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF000000))
  5549. /*
  5550. Register VHA_CR_CORE3_LAST_NNA_SYNC_ID
  5551. */
  5552. #define VHA_CR_CORE3_LAST_NNA_SYNC_ID (0x30148U)
  5553. #define VHA_CR_CORE3_LAST_NNA_SYNC_ID_MASKFULL (IMG_UINT64_C(0x0000000070FFFFFF))
  5554. #define VHA_CR_CORE3_LAST_NNA_SYNC_ID_CORE3_LAST_NNA_SYNC_ID_PARITY_SHIFT (28U)
  5555. #define VHA_CR_CORE3_LAST_NNA_SYNC_ID_CORE3_LAST_NNA_SYNC_ID_PARITY_CLRMSK (IMG_UINT64_C(0XFFFFFFFF8FFFFFFF))
  5556. #define VHA_CR_CORE3_LAST_NNA_SYNC_ID_CORE3_LAST_NNA_SYNC_ID_SHIFT (0U)
  5557. #define VHA_CR_CORE3_LAST_NNA_SYNC_ID_CORE3_LAST_NNA_SYNC_ID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF000000))
  5558. /*
  5559. Register VHA_CR_CORE4_LAST_NNA_SYNC_ID
  5560. */
  5561. #define VHA_CR_CORE4_LAST_NNA_SYNC_ID (0x30150U)
  5562. #define VHA_CR_CORE4_LAST_NNA_SYNC_ID_MASKFULL (IMG_UINT64_C(0x0000000070FFFFFF))
  5563. #define VHA_CR_CORE4_LAST_NNA_SYNC_ID_CORE4_LAST_NNA_SYNC_ID_PARITY_SHIFT (28U)
  5564. #define VHA_CR_CORE4_LAST_NNA_SYNC_ID_CORE4_LAST_NNA_SYNC_ID_PARITY_CLRMSK (IMG_UINT64_C(0XFFFFFFFF8FFFFFFF))
  5565. #define VHA_CR_CORE4_LAST_NNA_SYNC_ID_CORE4_LAST_NNA_SYNC_ID_SHIFT (0U)
  5566. #define VHA_CR_CORE4_LAST_NNA_SYNC_ID_CORE4_LAST_NNA_SYNC_ID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF000000))
  5567. /*
  5568. Register VHA_CR_CORE5_LAST_NNA_SYNC_ID
  5569. */
  5570. #define VHA_CR_CORE5_LAST_NNA_SYNC_ID (0x30158U)
  5571. #define VHA_CR_CORE5_LAST_NNA_SYNC_ID_MASKFULL (IMG_UINT64_C(0x0000000070FFFFFF))
  5572. #define VHA_CR_CORE5_LAST_NNA_SYNC_ID_CORE5_LAST_NNA_SYNC_ID_PARITY_SHIFT (28U)
  5573. #define VHA_CR_CORE5_LAST_NNA_SYNC_ID_CORE5_LAST_NNA_SYNC_ID_PARITY_CLRMSK (IMG_UINT64_C(0XFFFFFFFF8FFFFFFF))
  5574. #define VHA_CR_CORE5_LAST_NNA_SYNC_ID_CORE5_LAST_NNA_SYNC_ID_SHIFT (0U)
  5575. #define VHA_CR_CORE5_LAST_NNA_SYNC_ID_CORE5_LAST_NNA_SYNC_ID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF000000))
  5576. /*
  5577. Register VHA_CR_CORE6_LAST_NNA_SYNC_ID
  5578. */
  5579. #define VHA_CR_CORE6_LAST_NNA_SYNC_ID (0x30160U)
  5580. #define VHA_CR_CORE6_LAST_NNA_SYNC_ID_MASKFULL (IMG_UINT64_C(0x0000000070FFFFFF))
  5581. #define VHA_CR_CORE6_LAST_NNA_SYNC_ID_CORE6_LAST_NNA_SYNC_ID_PARITY_SHIFT (28U)
  5582. #define VHA_CR_CORE6_LAST_NNA_SYNC_ID_CORE6_LAST_NNA_SYNC_ID_PARITY_CLRMSK (IMG_UINT64_C(0XFFFFFFFF8FFFFFFF))
  5583. #define VHA_CR_CORE6_LAST_NNA_SYNC_ID_CORE6_LAST_NNA_SYNC_ID_SHIFT (0U)
  5584. #define VHA_CR_CORE6_LAST_NNA_SYNC_ID_CORE6_LAST_NNA_SYNC_ID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF000000))
  5585. /*
  5586. Register VHA_CR_CORE7_LAST_NNA_SYNC_ID
  5587. */
  5588. #define VHA_CR_CORE7_LAST_NNA_SYNC_ID (0x30168U)
  5589. #define VHA_CR_CORE7_LAST_NNA_SYNC_ID_MASKFULL (IMG_UINT64_C(0x0000000070FFFFFF))
  5590. #define VHA_CR_CORE7_LAST_NNA_SYNC_ID_CORE7_LAST_NNA_SYNC_ID_PARITY_SHIFT (28U)
  5591. #define VHA_CR_CORE7_LAST_NNA_SYNC_ID_CORE7_LAST_NNA_SYNC_ID_PARITY_CLRMSK (IMG_UINT64_C(0XFFFFFFFF8FFFFFFF))
  5592. #define VHA_CR_CORE7_LAST_NNA_SYNC_ID_CORE7_LAST_NNA_SYNC_ID_SHIFT (0U)
  5593. #define VHA_CR_CORE7_LAST_NNA_SYNC_ID_CORE7_LAST_NNA_SYNC_ID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF000000))
  5594. /*
  5595. Register VHA_CR_CORE0_LAST_MMM_SYNC_ID
  5596. */
  5597. #define VHA_CR_CORE0_LAST_MMM_SYNC_ID (0x30230U)
  5598. #define VHA_CR_CORE0_LAST_MMM_SYNC_ID_MASKFULL (IMG_UINT64_C(0x0000000070FFFFFF))
  5599. #define VHA_CR_CORE0_LAST_MMM_SYNC_ID_CORE0_LAST_MMM_SYNC_ID_PARITY_SHIFT (28U)
  5600. #define VHA_CR_CORE0_LAST_MMM_SYNC_ID_CORE0_LAST_MMM_SYNC_ID_PARITY_CLRMSK (IMG_UINT64_C(0XFFFFFFFF8FFFFFFF))
  5601. #define VHA_CR_CORE0_LAST_MMM_SYNC_ID_CORE0_LAST_MMM_SYNC_ID_SHIFT (0U)
  5602. #define VHA_CR_CORE0_LAST_MMM_SYNC_ID_CORE0_LAST_MMM_SYNC_ID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF000000))
  5603. /*
  5604. Register VHA_CR_CORE1_LAST_MMM_SYNC_ID
  5605. */
  5606. #define VHA_CR_CORE1_LAST_MMM_SYNC_ID (0x30238U)
  5607. #define VHA_CR_CORE1_LAST_MMM_SYNC_ID_MASKFULL (IMG_UINT64_C(0x0000000070FFFFFF))
  5608. #define VHA_CR_CORE1_LAST_MMM_SYNC_ID_CORE1_LAST_MMM_SYNC_ID_PARITY_SHIFT (28U)
  5609. #define VHA_CR_CORE1_LAST_MMM_SYNC_ID_CORE1_LAST_MMM_SYNC_ID_PARITY_CLRMSK (IMG_UINT64_C(0XFFFFFFFF8FFFFFFF))
  5610. #define VHA_CR_CORE1_LAST_MMM_SYNC_ID_CORE1_LAST_MMM_SYNC_ID_SHIFT (0U)
  5611. #define VHA_CR_CORE1_LAST_MMM_SYNC_ID_CORE1_LAST_MMM_SYNC_ID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF000000))
  5612. /*
  5613. Register VHA_CR_CORE2_LAST_MMM_SYNC_ID
  5614. */
  5615. #define VHA_CR_CORE2_LAST_MMM_SYNC_ID (0x30240U)
  5616. #define VHA_CR_CORE2_LAST_MMM_SYNC_ID_MASKFULL (IMG_UINT64_C(0x0000000070FFFFFF))
  5617. #define VHA_CR_CORE2_LAST_MMM_SYNC_ID_CORE2_LAST_MMM_SYNC_ID_PARITY_SHIFT (28U)
  5618. #define VHA_CR_CORE2_LAST_MMM_SYNC_ID_CORE2_LAST_MMM_SYNC_ID_PARITY_CLRMSK (IMG_UINT64_C(0XFFFFFFFF8FFFFFFF))
  5619. #define VHA_CR_CORE2_LAST_MMM_SYNC_ID_CORE2_LAST_MMM_SYNC_ID_SHIFT (0U)
  5620. #define VHA_CR_CORE2_LAST_MMM_SYNC_ID_CORE2_LAST_MMM_SYNC_ID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF000000))
  5621. /*
  5622. Register VHA_CR_CORE3_LAST_MMM_SYNC_ID
  5623. */
  5624. #define VHA_CR_CORE3_LAST_MMM_SYNC_ID (0x30248U)
  5625. #define VHA_CR_CORE3_LAST_MMM_SYNC_ID_MASKFULL (IMG_UINT64_C(0x0000000070FFFFFF))
  5626. #define VHA_CR_CORE3_LAST_MMM_SYNC_ID_CORE3_LAST_MMM_SYNC_ID_PARITY_SHIFT (28U)
  5627. #define VHA_CR_CORE3_LAST_MMM_SYNC_ID_CORE3_LAST_MMM_SYNC_ID_PARITY_CLRMSK (IMG_UINT64_C(0XFFFFFFFF8FFFFFFF))
  5628. #define VHA_CR_CORE3_LAST_MMM_SYNC_ID_CORE3_LAST_MMM_SYNC_ID_SHIFT (0U)
  5629. #define VHA_CR_CORE3_LAST_MMM_SYNC_ID_CORE3_LAST_MMM_SYNC_ID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF000000))
  5630. /*
  5631. Register VHA_CR_CORE4_LAST_MMM_SYNC_ID
  5632. */
  5633. #define VHA_CR_CORE4_LAST_MMM_SYNC_ID (0x30250U)
  5634. #define VHA_CR_CORE4_LAST_MMM_SYNC_ID_MASKFULL (IMG_UINT64_C(0x0000000070FFFFFF))
  5635. #define VHA_CR_CORE4_LAST_MMM_SYNC_ID_CORE4_LAST_MMM_SYNC_ID_PARITY_SHIFT (28U)
  5636. #define VHA_CR_CORE4_LAST_MMM_SYNC_ID_CORE4_LAST_MMM_SYNC_ID_PARITY_CLRMSK (IMG_UINT64_C(0XFFFFFFFF8FFFFFFF))
  5637. #define VHA_CR_CORE4_LAST_MMM_SYNC_ID_CORE4_LAST_MMM_SYNC_ID_SHIFT (0U)
  5638. #define VHA_CR_CORE4_LAST_MMM_SYNC_ID_CORE4_LAST_MMM_SYNC_ID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF000000))
  5639. /*
  5640. Register VHA_CR_CORE5_LAST_MMM_SYNC_ID
  5641. */
  5642. #define VHA_CR_CORE5_LAST_MMM_SYNC_ID (0x30258U)
  5643. #define VHA_CR_CORE5_LAST_MMM_SYNC_ID_MASKFULL (IMG_UINT64_C(0x0000000070FFFFFF))
  5644. #define VHA_CR_CORE5_LAST_MMM_SYNC_ID_CORE5_LAST_MMM_SYNC_ID_PARITY_SHIFT (28U)
  5645. #define VHA_CR_CORE5_LAST_MMM_SYNC_ID_CORE5_LAST_MMM_SYNC_ID_PARITY_CLRMSK (IMG_UINT64_C(0XFFFFFFFF8FFFFFFF))
  5646. #define VHA_CR_CORE5_LAST_MMM_SYNC_ID_CORE5_LAST_MMM_SYNC_ID_SHIFT (0U)
  5647. #define VHA_CR_CORE5_LAST_MMM_SYNC_ID_CORE5_LAST_MMM_SYNC_ID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF000000))
  5648. /*
  5649. Register VHA_CR_CORE6_LAST_MMM_SYNC_ID
  5650. */
  5651. #define VHA_CR_CORE6_LAST_MMM_SYNC_ID (0x30260U)
  5652. #define VHA_CR_CORE6_LAST_MMM_SYNC_ID_MASKFULL (IMG_UINT64_C(0x0000000070FFFFFF))
  5653. #define VHA_CR_CORE6_LAST_MMM_SYNC_ID_CORE6_LAST_MMM_SYNC_ID_PARITY_SHIFT (28U)
  5654. #define VHA_CR_CORE6_LAST_MMM_SYNC_ID_CORE6_LAST_MMM_SYNC_ID_PARITY_CLRMSK (IMG_UINT64_C(0XFFFFFFFF8FFFFFFF))
  5655. #define VHA_CR_CORE6_LAST_MMM_SYNC_ID_CORE6_LAST_MMM_SYNC_ID_SHIFT (0U)
  5656. #define VHA_CR_CORE6_LAST_MMM_SYNC_ID_CORE6_LAST_MMM_SYNC_ID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF000000))
  5657. /*
  5658. Register VHA_CR_CORE7_LAST_MMM_SYNC_ID
  5659. */
  5660. #define VHA_CR_CORE7_LAST_MMM_SYNC_ID (0x30268U)
  5661. #define VHA_CR_CORE7_LAST_MMM_SYNC_ID_MASKFULL (IMG_UINT64_C(0x0000000070FFFFFF))
  5662. #define VHA_CR_CORE7_LAST_MMM_SYNC_ID_CORE7_LAST_MMM_SYNC_ID_PARITY_SHIFT (28U)
  5663. #define VHA_CR_CORE7_LAST_MMM_SYNC_ID_CORE7_LAST_MMM_SYNC_ID_PARITY_CLRMSK (IMG_UINT64_C(0XFFFFFFFF8FFFFFFF))
  5664. #define VHA_CR_CORE7_LAST_MMM_SYNC_ID_CORE7_LAST_MMM_SYNC_ID_SHIFT (0U)
  5665. #define VHA_CR_CORE7_LAST_MMM_SYNC_ID_CORE7_LAST_MMM_SYNC_ID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF000000))
  5666. /*
  5667. Register VHA_CR_CNN_CORE_SYNC_WDT_CTRL
  5668. */
  5669. #define VHA_CR_CNN_CORE_SYNC_WDT_CTRL (0x30270U)
  5670. #define VHA_CR_CNN_CORE_SYNC_WDT_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000FFFF01))
  5671. #define VHA_CR_CNN_CORE_SYNC_WDT_CTRL_VALUE_SHIFT (8U)
  5672. #define VHA_CR_CNN_CORE_SYNC_WDT_CTRL_VALUE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF0000FF))
  5673. #define VHA_CR_CNN_CORE_SYNC_WDT_CTRL_ENABLE_SHIFT (0U)
  5674. #define VHA_CR_CNN_CORE_SYNC_WDT_CTRL_ENABLE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  5675. #define VHA_CR_CNN_CORE_SYNC_WDT_CTRL_ENABLE_EN (IMG_UINT64_C(0X0000000000000001))
  5676. /*
  5677. Register VHA_CR_CORE_BW_LOCM_RD
  5678. */
  5679. #define VHA_CR_CORE_BW_LOCM_RD (0x30278U)
  5680. #define VHA_CR_CORE_BW_LOCM_RD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  5681. #define VHA_CR_CORE_BW_LOCM_RD_BW_SHIFT (0U)
  5682. #define VHA_CR_CORE_BW_LOCM_RD_BW_CLRMSK (IMG_UINT64_C(0XFFFFFFFF00000000))
  5683. /*
  5684. Register VHA_CR_CORE_BW_LOCM_WR
  5685. */
  5686. #define VHA_CR_CORE_BW_LOCM_WR (0x30280U)
  5687. #define VHA_CR_CORE_BW_LOCM_WR_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  5688. #define VHA_CR_CORE_BW_LOCM_WR_BW_SHIFT (0U)
  5689. #define VHA_CR_CORE_BW_LOCM_WR_BW_CLRMSK (IMG_UINT64_C(0XFFFFFFFF00000000))
  5690. /*
  5691. Register VHA_CR_CORE_BW_LOCM_MWR
  5692. */
  5693. #define VHA_CR_CORE_BW_LOCM_MWR (0x30288U)
  5694. #define VHA_CR_CORE_BW_LOCM_MWR_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  5695. #define VHA_CR_CORE_BW_LOCM_MWR_BW_SHIFT (0U)
  5696. #define VHA_CR_CORE_BW_LOCM_MWR_BW_CLRMSK (IMG_UINT64_C(0XFFFFFFFF00000000))
  5697. /*
  5698. Register VHA_CR_CORE_BW_LOCM_RD_WORD
  5699. */
  5700. #define VHA_CR_CORE_BW_LOCM_RD_WORD (0x30290U)
  5701. #define VHA_CR_CORE_BW_LOCM_RD_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  5702. #define VHA_CR_CORE_BW_LOCM_RD_WORD_BW_SHIFT (0U)
  5703. #define VHA_CR_CORE_BW_LOCM_RD_WORD_BW_CLRMSK (IMG_UINT64_C(0XFFFFFFFF00000000))
  5704. /*
  5705. Register VHA_CR_CORE_BW_LOCM_WR_WORD
  5706. */
  5707. #define VHA_CR_CORE_BW_LOCM_WR_WORD (0x30298U)
  5708. #define VHA_CR_CORE_BW_LOCM_WR_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  5709. #define VHA_CR_CORE_BW_LOCM_WR_WORD_BW_SHIFT (0U)
  5710. #define VHA_CR_CORE_BW_LOCM_WR_WORD_BW_CLRMSK (IMG_UINT64_C(0XFFFFFFFF00000000))
  5711. /*
  5712. Register VHA_CR_CORE_BW_TLC_RD
  5713. */
  5714. #define VHA_CR_CORE_BW_TLC_RD (0x30300U)
  5715. #define VHA_CR_CORE_BW_TLC_RD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  5716. #define VHA_CR_CORE_BW_TLC_RD_BW_SHIFT (0U)
  5717. #define VHA_CR_CORE_BW_TLC_RD_BW_CLRMSK (IMG_UINT64_C(0XFFFFFFFF00000000))
  5718. /*
  5719. Register VHA_CR_CORE_BW_TLC_WR
  5720. */
  5721. #define VHA_CR_CORE_BW_TLC_WR (0x30308U)
  5722. #define VHA_CR_CORE_BW_TLC_WR_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  5723. #define VHA_CR_CORE_BW_TLC_WR_BW_SHIFT (0U)
  5724. #define VHA_CR_CORE_BW_TLC_WR_BW_CLRMSK (IMG_UINT64_C(0XFFFFFFFF00000000))
  5725. /*
  5726. Register VHA_CR_CORE_BW_TLC_MWR
  5727. */
  5728. #define VHA_CR_CORE_BW_TLC_MWR (0x30310U)
  5729. #define VHA_CR_CORE_BW_TLC_MWR_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  5730. #define VHA_CR_CORE_BW_TLC_MWR_BW_SHIFT (0U)
  5731. #define VHA_CR_CORE_BW_TLC_MWR_BW_CLRMSK (IMG_UINT64_C(0XFFFFFFFF00000000))
  5732. /*
  5733. Register VHA_CR_CORE_BW_TLC_RD_WORD
  5734. */
  5735. #define VHA_CR_CORE_BW_TLC_RD_WORD (0x30318U)
  5736. #define VHA_CR_CORE_BW_TLC_RD_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  5737. #define VHA_CR_CORE_BW_TLC_RD_WORD_BW_SHIFT (0U)
  5738. #define VHA_CR_CORE_BW_TLC_RD_WORD_BW_CLRMSK (IMG_UINT64_C(0XFFFFFFFF00000000))
  5739. /*
  5740. Register VHA_CR_CORE_BW_TLC_WR_WORD
  5741. */
  5742. #define VHA_CR_CORE_BW_TLC_WR_WORD (0x30320U)
  5743. #define VHA_CR_CORE_BW_TLC_WR_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  5744. #define VHA_CR_CORE_BW_TLC_WR_WORD_BW_SHIFT (0U)
  5745. #define VHA_CR_CORE_BW_TLC_WR_WORD_BW_CLRMSK (IMG_UINT64_C(0XFFFFFFFF00000000))
  5746. /*
  5747. Register VHA_CR_OS0_COMBINED_CNN_CRC_ADDRESS
  5748. */
  5749. #define VHA_CR_OS0_COMBINED_CNN_CRC_ADDRESS (0x30328U)
  5750. #define VHA_CR_OS0_COMBINED_CNN_CRC_ADDRESS_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFF80))
  5751. #define VHA_CR_OS0_COMBINED_CNN_CRC_ADDRESS_CNN_CRC_ADDR_SHIFT (7U)
  5752. #define VHA_CR_OS0_COMBINED_CNN_CRC_ADDRESS_CNN_CRC_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF000000007F))
  5753. #define VHA_CR_OS0_COMBINED_CNN_CRC_ADDRESS_CNN_CRC_ADDR_ALIGNSHIFT (7U)
  5754. #define VHA_CR_OS0_COMBINED_CNN_CRC_ADDRESS_CNN_CRC_ADDR_ALIGNSIZE (128U)
  5755. /*
  5756. Register VHA_CR_PERF_SLC_SNOOP_HITS
  5757. */
  5758. #define VHA_CR_PERF_SLC_SNOOP_HITS (0x7728U)
  5759. #define VHA_CR_PERF_SLC_SNOOP_HITS_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  5760. #define VHA_CR_PERF_SLC_SNOOP_HITS_COUNT_SHIFT (0U)
  5761. #define VHA_CR_PERF_SLC_SNOOP_HITS_COUNT_CLRMSK (00000000U)
  5762. /*
  5763. Register VHA_CR_PERF_SLC_SNOOP_MISSES
  5764. */
  5765. #define VHA_CR_PERF_SLC_SNOOP_MISSES (0x7730U)
  5766. #define VHA_CR_PERF_SLC_SNOOP_MISSES_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  5767. #define VHA_CR_PERF_SLC_SNOOP_MISSES_COUNT_SHIFT (0U)
  5768. #define VHA_CR_PERF_SLC_SNOOP_MISSES_COUNT_CLRMSK (00000000U)
  5769. /*
  5770. Register VHA_CR_SLC_CCM_CTRL
  5771. */
  5772. #define VHA_CR_SLC_CCM_CTRL (0x78F8U)
  5773. #define VHA_CR_SLC_CCM_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000FF00FF))
  5774. #define VHA_CR_SLC_CCM_CTRL_SPILL_AMOUNT_SHIFT (16U)
  5775. #define VHA_CR_SLC_CCM_CTRL_SPILL_AMOUNT_CLRMSK (0XFF00FFFFU)
  5776. #define VHA_CR_SLC_CCM_CTRL_SPILL_THRESHOLD_SHIFT (0U)
  5777. #define VHA_CR_SLC_CCM_CTRL_SPILL_THRESHOLD_CLRMSK (0XFFFFFF00U)
  5778. /*
  5779. Register VHA_CR_SLC_CCM_STATUS
  5780. */
  5781. #define VHA_CR_SLC_CCM_STATUS (0x7900U)
  5782. #define VHA_CR_SLC_CCM_STATUS_MASKFULL (IMG_UINT64_C(0x0FFFFFFFF10FF0FF))
  5783. #define VHA_CR_SLC_CCM_STATUS_SNOOP_COUNT3_SHIFT (52U)
  5784. #define VHA_CR_SLC_CCM_STATUS_SNOOP_COUNT3_CLRMSK (IMG_UINT64_C(0XF00FFFFFFFFFFFFF))
  5785. #define VHA_CR_SLC_CCM_STATUS_SNOOP_COUNT2_SHIFT (44U)
  5786. #define VHA_CR_SLC_CCM_STATUS_SNOOP_COUNT2_CLRMSK (IMG_UINT64_C(0XFFF00FFFFFFFFFFF))
  5787. #define VHA_CR_SLC_CCM_STATUS_SNOOP_COUNT1_SHIFT (36U)
  5788. #define VHA_CR_SLC_CCM_STATUS_SNOOP_COUNT1_CLRMSK (IMG_UINT64_C(0XFFFFF00FFFFFFFFF))
  5789. #define VHA_CR_SLC_CCM_STATUS_SNOOP_COUNT0_SHIFT (28U)
  5790. #define VHA_CR_SLC_CCM_STATUS_SNOOP_COUNT0_CLRMSK (IMG_UINT64_C(0XFFFFFFF00FFFFFFF))
  5791. #define VHA_CR_SLC_CCM_STATUS_SPILLING_SHIFT (24U)
  5792. #define VHA_CR_SLC_CCM_STATUS_SPILLING_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFEFFFFFF))
  5793. #define VHA_CR_SLC_CCM_STATUS_SPILLING_EN (IMG_UINT64_C(0X0000000001000000))
  5794. #define VHA_CR_SLC_CCM_STATUS_SPILL_ENTRIES_SHIFT (12U)
  5795. #define VHA_CR_SLC_CCM_STATUS_SPILL_ENTRIES_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF00FFF))
  5796. #define VHA_CR_SLC_CCM_STATUS_ACTIVE_ENTRIES_SHIFT (0U)
  5797. #define VHA_CR_SLC_CCM_STATUS_ACTIVE_ENTRIES_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFF00))
  5798. #endif /* _VHA_CR_MAGNA_H_ */
  5799. /*****************************************************************************
  5800. End of file (vha_cr_magna.h)
  5801. *****************************************************************************/