vha_cr_gyrus.h 277 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121212221232124212521262127212821292130213121322133213421352136213721382139214021412142214321442145214621472148214921502151215221532154215521562157215821592160216121622163216421652166216721682169217021712172217321742175217621772178217921802181218221832184218521862187218821892190219121922193219421952196219721982199220022012202220322042205220622072208220922102211221222132214221522162217221822192220222122222223222422252226222722282229223022312232223322342235223622372238223922402241224222432244224522462247224822492250225122522253225422552256225722582259226022612262226322642265226622672268226922702271227222732274227522762277227822792280228122822283228422852286228722882289229022912292229322942295229622972298229923002301230223032304230523062307230823092310231123122313231423152316231723182319232023212322232323242325232623272328232923302331233223332334233523362337233823392340234123422343234423452346234723482349235023512352235323542355235623572358235923602361236223632364236523662367236823692370237123722373237423752376237723782379238023812382238323842385238623872388238923902391239223932394239523962397239823992400240124022403240424052406240724082409241024112412241324142415241624172418241924202421242224232424242524262427242824292430243124322433243424352436243724382439244024412442244324442445244624472448244924502451245224532454245524562457245824592460246124622463246424652466246724682469247024712472247324742475247624772478247924802481248224832484248524862487248824892490249124922493249424952496249724982499250025012502250325042505250625072508250925102511251225132514251525162517251825192520252125222523252425252526252725282529253025312532253325342535253625372538253925402541254225432544254525462547254825492550255125522553255425552556255725582559256025612562256325642565256625672568256925702571257225732574257525762577257825792580258125822583258425852586258725882589259025912592259325942595259625972598259926002601260226032604260526062607260826092610261126122613261426152616261726182619262026212622262326242625262626272628262926302631263226332634263526362637263826392640264126422643264426452646264726482649265026512652265326542655265626572658265926602661266226632664266526662667266826692670267126722673267426752676267726782679268026812682268326842685268626872688268926902691269226932694269526962697269826992700270127022703270427052706270727082709271027112712271327142715271627172718271927202721272227232724272527262727272827292730273127322733273427352736273727382739274027412742274327442745274627472748274927502751275227532754275527562757275827592760276127622763276427652766276727682769277027712772277327742775277627772778277927802781278227832784278527862787278827892790279127922793279427952796279727982799280028012802280328042805280628072808280928102811281228132814281528162817281828192820282128222823282428252826282728282829283028312832283328342835283628372838283928402841284228432844284528462847284828492850285128522853285428552856285728582859286028612862286328642865286628672868286928702871287228732874287528762877287828792880288128822883288428852886288728882889289028912892289328942895289628972898289929002901290229032904290529062907290829092910291129122913291429152916291729182919292029212922292329242925292629272928292929302931293229332934293529362937293829392940294129422943294429452946294729482949295029512952295329542955295629572958295929602961296229632964296529662967296829692970297129722973297429752976297729782979298029812982298329842985298629872988298929902991299229932994299529962997299829993000300130023003300430053006300730083009301030113012301330143015301630173018301930203021302230233024302530263027302830293030303130323033303430353036303730383039304030413042304330443045304630473048304930503051305230533054305530563057305830593060306130623063306430653066306730683069307030713072307330743075307630773078307930803081308230833084308530863087308830893090309130923093309430953096309730983099310031013102310331043105310631073108310931103111311231133114311531163117311831193120312131223123312431253126312731283129313031313132313331343135313631373138313931403141314231433144314531463147314831493150315131523153315431553156315731583159316031613162316331643165316631673168316931703171317231733174317531763177317831793180318131823183318431853186318731883189319031913192319331943195319631973198319932003201320232033204320532063207320832093210321132123213321432153216321732183219322032213222322332243225322632273228322932303231323232333234323532363237323832393240324132423243324432453246324732483249325032513252325332543255325632573258325932603261326232633264326532663267326832693270327132723273327432753276327732783279328032813282328332843285328632873288328932903291329232933294329532963297329832993300330133023303330433053306330733083309331033113312331333143315331633173318331933203321332233233324332533263327332833293330333133323333333433353336333733383339334033413342334333443345334633473348334933503351335233533354335533563357335833593360336133623363336433653366336733683369337033713372337333743375337633773378337933803381338233833384338533863387338833893390339133923393339433953396339733983399340034013402340334043405340634073408340934103411341234133414341534163417341834193420342134223423342434253426342734283429343034313432343334343435343634373438343934403441344234433444344534463447344834493450345134523453345434553456345734583459346034613462346334643465346634673468346934703471347234733474347534763477347834793480348134823483348434853486348734883489349034913492349334943495349634973498349935003501350235033504350535063507350835093510351135123513351435153516351735183519352035213522352335243525352635273528352935303531353235333534353535363537353835393540354135423543354435453546354735483549355035513552355335543555355635573558355935603561356235633564356535663567356835693570357135723573357435753576357735783579358035813582358335843585358635873588358935903591359235933594359535963597359835993600360136023603360436053606360736083609361036113612361336143615361636173618361936203621362236233624362536263627362836293630363136323633363436353636363736383639364036413642364336443645364636473648364936503651365236533654365536563657365836593660366136623663366436653666366736683669367036713672367336743675367636773678367936803681368236833684368536863687368836893690369136923693369436953696369736983699370037013702370337043705370637073708370937103711371237133714371537163717371837193720372137223723372437253726372737283729373037313732373337343735373637373738373937403741374237433744374537463747374837493750375137523753375437553756375737583759376037613762376337643765376637673768376937703771377237733774377537763777377837793780378137823783378437853786378737883789379037913792379337943795379637973798379938003801380238033804380538063807380838093810381138123813381438153816381738183819382038213822382338243825382638273828382938303831383238333834383538363837383838393840384138423843384438453846384738483849385038513852385338543855385638573858385938603861386238633864386538663867386838693870387138723873387438753876387738783879388038813882388338843885388638873888388938903891389238933894389538963897389838993900390139023903390439053906390739083909391039113912391339143915391639173918391939203921392239233924392539263927392839293930393139323933393439353936393739383939394039413942394339443945394639473948394939503951395239533954395539563957395839593960396139623963396439653966396739683969397039713972397339743975397639773978397939803981398239833984398539863987398839893990399139923993399439953996399739983999400040014002400340044005400640074008400940104011401240134014401540164017401840194020402140224023402440254026402740284029403040314032403340344035403640374038403940404041404240434044404540464047404840494050405140524053405440554056405740584059406040614062406340644065406640674068406940704071407240734074407540764077407840794080408140824083408440854086408740884089409040914092409340944095409640974098409941004101410241034104410541064107410841094110411141124113411441154116411741184119412041214122412341244125412641274128412941304131413241334134413541364137413841394140414141424143414441454146414741484149415041514152415341544155415641574158415941604161416241634164416541664167416841694170417141724173417441754176417741784179418041814182418341844185418641874188418941904191419241934194419541964197419841994200420142024203420442054206420742084209421042114212421342144215421642174218421942204221422242234224422542264227422842294230423142324233423442354236423742384239424042414242424342444245424642474248424942504251425242534254425542564257425842594260426142624263426442654266426742684269427042714272427342744275427642774278427942804281428242834284428542864287428842894290429142924293429442954296429742984299430043014302430343044305430643074308430943104311431243134314431543164317431843194320432143224323432443254326432743284329433043314332433343344335433643374338433943404341434243434344434543464347434843494350435143524353435443554356435743584359436043614362436343644365436643674368436943704371437243734374437543764377437843794380438143824383438443854386438743884389439043914392439343944395439643974398439944004401440244034404440544064407440844094410441144124413441444154416441744184419442044214422442344244425442644274428442944304431443244334434443544364437443844394440444144424443444444454446444744484449445044514452445344544455445644574458445944604461446244634464446544664467446844694470447144724473447444754476447744784479448044814482448344844485448644874488448944904491449244934494449544964497449844994500450145024503450445054506450745084509451045114512451345144515451645174518451945204521452245234524452545264527452845294530453145324533453445354536453745384539454045414542454345444545454645474548454945504551455245534554455545564557455845594560456145624563456445654566456745684569457045714572457345744575457645774578457945804581458245834584458545864587458845894590459145924593459445954596459745984599460046014602460346044605460646074608460946104611461246134614461546164617461846194620462146224623462446254626462746284629463046314632463346344635463646374638463946404641464246434644464546464647464846494650465146524653465446554656465746584659466046614662466346644665466646674668466946704671467246734674467546764677467846794680468146824683468446854686468746884689469046914692469346944695469646974698469947004701470247034704470547064707470847094710471147124713471447154716471747184719472047214722472347244725472647274728472947304731473247334734473547364737473847394740474147424743474447454746474747484749475047514752475347544755475647574758475947604761476247634764476547664767476847694770477147724773477447754776477747784779478047814782478347844785478647874788478947904791479247934794479547964797479847994800480148024803480448054806480748084809481048114812481348144815481648174818481948204821482248234824482548264827482848294830483148324833483448354836483748384839484048414842484348444845484648474848484948504851485248534854485548564857485848594860486148624863486448654866486748684869487048714872487348744875487648774878487948804881488248834884488548864887488848894890489148924893489448954896489748984899490049014902490349044905490649074908490949104911491249134914491549164917491849194920492149224923492449254926492749284929493049314932493349344935493649374938493949404941494249434944494549464947494849494950495149524953495449554956495749584959496049614962496349644965496649674968496949704971497249734974497549764977497849794980498149824983498449854986498749884989499049914992499349944995499649974998
  1. /*************************************************************************/ /*!
  2. @Title Hardware definition file vha_cr_gyrus.h
  3. @Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved
  4. */ /**************************************************************************/
  5. /* **** Autogenerated C -- do not edit **** */
  6. /*
  7. */
  8. #ifndef _VHA_CR_GYRUS_H_
  9. #define _VHA_CR_GYRUS_H_
  10. #define VHA_CR_GYRUS_REVISION 1
  11. #define VHA_CR_MH_CONTROL_PERSISTENCE_TYPE_MASK (0x00000003U)
  12. #define VHA_CR_MH_CONTROL_MAX_BURST_LENGTH_MASK (0x00000003U)
  13. /*
  14. Clock is gated and the module is inactive */
  15. #define VHA_CR_CLK_STATUS0_MODE_GATED (0x00000000U)
  16. /*
  17. Clock is running */
  18. #define VHA_CR_CLK_STATUS0_MODE_RUNNING (0x00000001U)
  19. /*
  20. Register VHA_CR_CLK_STATUS0
  21. */
  22. #define VHA_CR_CLK_STATUS0 (0x0008U)
  23. #define VHA_CR_CLK_STATUS0_MASKFULL (IMG_UINT64_C(0x00000017FFD00104))
  24. #define VHA_CR_CLK_STATUS0_CNN_MMM_SHIFT (36U)
  25. #define VHA_CR_CLK_STATUS0_CNN_MMM_CLRMSK (IMG_UINT64_C(0XFFFFFFEFFFFFFFFF))
  26. #define VHA_CR_CLK_STATUS0_CNN_MMM_GATED (IMG_UINT64_C(0000000000000000))
  27. #define VHA_CR_CLK_STATUS0_CNN_MMM_RUNNING (IMG_UINT64_C(0x0000001000000000))
  28. #define VHA_CR_CLK_STATUS0_CNN_EWO_SHIFT (34U)
  29. #define VHA_CR_CLK_STATUS0_CNN_EWO_CLRMSK (IMG_UINT64_C(0XFFFFFFFBFFFFFFFF))
  30. #define VHA_CR_CLK_STATUS0_CNN_EWO_GATED (IMG_UINT64_C(0000000000000000))
  31. #define VHA_CR_CLK_STATUS0_CNN_EWO_RUNNING (IMG_UINT64_C(0x0000000400000000))
  32. #define VHA_CR_CLK_STATUS0_CNN_PACK_SHIFT (33U)
  33. #define VHA_CR_CLK_STATUS0_CNN_PACK_CLRMSK (IMG_UINT64_C(0XFFFFFFFDFFFFFFFF))
  34. #define VHA_CR_CLK_STATUS0_CNN_PACK_GATED (IMG_UINT64_C(0000000000000000))
  35. #define VHA_CR_CLK_STATUS0_CNN_PACK_RUNNING (IMG_UINT64_C(0x0000000200000000))
  36. #define VHA_CR_CLK_STATUS0_CNN_OIN_SHIFT (32U)
  37. #define VHA_CR_CLK_STATUS0_CNN_OIN_CLRMSK (IMG_UINT64_C(0XFFFFFFFEFFFFFFFF))
  38. #define VHA_CR_CLK_STATUS0_CNN_OIN_GATED (IMG_UINT64_C(0000000000000000))
  39. #define VHA_CR_CLK_STATUS0_CNN_OIN_RUNNING (IMG_UINT64_C(0x0000000100000000))
  40. #define VHA_CR_CLK_STATUS0_CNN_POOL_SHIFT (31U)
  41. #define VHA_CR_CLK_STATUS0_CNN_POOL_CLRMSK (IMG_UINT64_C(0XFFFFFFFF7FFFFFFF))
  42. #define VHA_CR_CLK_STATUS0_CNN_POOL_GATED (IMG_UINT64_C(0000000000000000))
  43. #define VHA_CR_CLK_STATUS0_CNN_POOL_RUNNING (IMG_UINT64_C(0x0000000080000000))
  44. #define VHA_CR_CLK_STATUS0_CNN_SB_SHIFT (30U)
  45. #define VHA_CR_CLK_STATUS0_CNN_SB_CLRMSK (IMG_UINT64_C(0XFFFFFFFFBFFFFFFF))
  46. #define VHA_CR_CLK_STATUS0_CNN_SB_GATED (IMG_UINT64_C(0000000000000000))
  47. #define VHA_CR_CLK_STATUS0_CNN_SB_RUNNING (IMG_UINT64_C(0x0000000040000000))
  48. #define VHA_CR_CLK_STATUS0_CNN_XBAR_SHIFT (29U)
  49. #define VHA_CR_CLK_STATUS0_CNN_XBAR_CLRMSK (IMG_UINT64_C(0XFFFFFFFFDFFFFFFF))
  50. #define VHA_CR_CLK_STATUS0_CNN_XBAR_GATED (IMG_UINT64_C(0000000000000000))
  51. #define VHA_CR_CLK_STATUS0_CNN_XBAR_RUNNING (IMG_UINT64_C(0x0000000020000000))
  52. #define VHA_CR_CLK_STATUS0_CNN_NORM_SHIFT (28U)
  53. #define VHA_CR_CLK_STATUS0_CNN_NORM_CLRMSK (IMG_UINT64_C(0XFFFFFFFFEFFFFFFF))
  54. #define VHA_CR_CLK_STATUS0_CNN_NORM_GATED (IMG_UINT64_C(0000000000000000))
  55. #define VHA_CR_CLK_STATUS0_CNN_NORM_RUNNING (IMG_UINT64_C(0x0000000010000000))
  56. #define VHA_CR_CLK_STATUS0_CNN_ACT_SHIFT (27U)
  57. #define VHA_CR_CLK_STATUS0_CNN_ACT_CLRMSK (IMG_UINT64_C(0XFFFFFFFFF7FFFFFF))
  58. #define VHA_CR_CLK_STATUS0_CNN_ACT_GATED (IMG_UINT64_C(0000000000000000))
  59. #define VHA_CR_CLK_STATUS0_CNN_ACT_RUNNING (IMG_UINT64_C(0x0000000008000000))
  60. #define VHA_CR_CLK_STATUS0_CNN_ACCUM_SHIFT (26U)
  61. #define VHA_CR_CLK_STATUS0_CNN_ACCUM_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFBFFFFFF))
  62. #define VHA_CR_CLK_STATUS0_CNN_ACCUM_GATED (IMG_UINT64_C(0000000000000000))
  63. #define VHA_CR_CLK_STATUS0_CNN_ACCUM_RUNNING (IMG_UINT64_C(0x0000000004000000))
  64. #define VHA_CR_CLK_STATUS0_CNN_CNV_SHIFT (25U)
  65. #define VHA_CR_CLK_STATUS0_CNN_CNV_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFDFFFFFF))
  66. #define VHA_CR_CLK_STATUS0_CNN_CNV_GATED (IMG_UINT64_C(0000000000000000))
  67. #define VHA_CR_CLK_STATUS0_CNN_CNV_RUNNING (IMG_UINT64_C(0x0000000002000000))
  68. #define VHA_CR_CLK_STATUS0_CNN_CBUF_SHIFT (24U)
  69. #define VHA_CR_CLK_STATUS0_CNN_CBUF_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFEFFFFFF))
  70. #define VHA_CR_CLK_STATUS0_CNN_CBUF_GATED (IMG_UINT64_C(0000000000000000))
  71. #define VHA_CR_CLK_STATUS0_CNN_CBUF_RUNNING (IMG_UINT64_C(0x0000000001000000))
  72. #define VHA_CR_CLK_STATUS0_CNN_IBUF_SHIFT (23U)
  73. #define VHA_CR_CLK_STATUS0_CNN_IBUF_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF7FFFFF))
  74. #define VHA_CR_CLK_STATUS0_CNN_IBUF_GATED (IMG_UINT64_C(0000000000000000))
  75. #define VHA_CR_CLK_STATUS0_CNN_IBUF_RUNNING (IMG_UINT64_C(0x0000000000800000))
  76. #define VHA_CR_CLK_STATUS0_CNN_CMD_SHIFT (22U)
  77. #define VHA_CR_CLK_STATUS0_CNN_CMD_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFBFFFFF))
  78. #define VHA_CR_CLK_STATUS0_CNN_CMD_GATED (IMG_UINT64_C(0000000000000000))
  79. #define VHA_CR_CLK_STATUS0_CNN_CMD_RUNNING (IMG_UINT64_C(0x0000000000400000))
  80. #define VHA_CR_CLK_STATUS0_CNN_SHIFT (20U)
  81. #define VHA_CR_CLK_STATUS0_CNN_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFEFFFFF))
  82. #define VHA_CR_CLK_STATUS0_CNN_GATED (IMG_UINT64_C(0000000000000000))
  83. #define VHA_CR_CLK_STATUS0_CNN_RUNNING (IMG_UINT64_C(0x0000000000100000))
  84. #define VHA_CR_CLK_STATUS0_SLC_SHIFT (8U)
  85. #define VHA_CR_CLK_STATUS0_SLC_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFEFF))
  86. #define VHA_CR_CLK_STATUS0_SLC_GATED (IMG_UINT64_C(0000000000000000))
  87. #define VHA_CR_CLK_STATUS0_SLC_RUNNING (IMG_UINT64_C(0x0000000000000100))
  88. #define VHA_CR_CLK_STATUS0_BIF_SHIFT (2U)
  89. #define VHA_CR_CLK_STATUS0_BIF_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFB))
  90. #define VHA_CR_CLK_STATUS0_BIF_GATED (IMG_UINT64_C(0000000000000000))
  91. #define VHA_CR_CLK_STATUS0_BIF_RUNNING (IMG_UINT64_C(0x0000000000000004))
  92. /*
  93. Register VHA_CR_PRODUCT_ID
  94. */
  95. #define VHA_CR_PRODUCT_ID (0x0018U)
  96. #define VHA_CR_PRODUCT_ID_MASKFULL (IMG_UINT64_C(0x00000000FFFF0000))
  97. #define VHA_CR_PRODUCT_ID_IMG_PRODUCT_ID_SHIFT (16U)
  98. #define VHA_CR_PRODUCT_ID_IMG_PRODUCT_ID_CLRMSK (IMG_UINT64_C(0XFFFFFFFF0000FFFF))
  99. /*
  100. Register VHA_CR_CORE_ID
  101. */
  102. #define VHA_CR_CORE_ID (0x0020U)
  103. #define VHA_CR_CORE_ID_MASKFULL (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
  104. #define VHA_CR_CORE_ID_BRANCH_ID_SHIFT (48U)
  105. #define VHA_CR_CORE_ID_BRANCH_ID_CLRMSK (IMG_UINT64_C(0X0000FFFFFFFFFFFF))
  106. #define VHA_CR_CORE_ID_VERSION_ID_SHIFT (32U)
  107. #define VHA_CR_CORE_ID_VERSION_ID_CLRMSK (IMG_UINT64_C(0XFFFF0000FFFFFFFF))
  108. #define VHA_CR_CORE_ID_NUMBER_OF_SCALABLE_UNITS_SHIFT (16U)
  109. #define VHA_CR_CORE_ID_NUMBER_OF_SCALABLE_UNITS_CLRMSK (IMG_UINT64_C(0XFFFFFFFF0000FFFF))
  110. #define VHA_CR_CORE_ID_CONFIG_ID_SHIFT (0U)
  111. #define VHA_CR_CORE_ID_CONFIG_ID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF0000))
  112. /*
  113. Register VHA_CR_CORE_IP_INTEGRATOR_ID
  114. */
  115. #define VHA_CR_CORE_IP_INTEGRATOR_ID (0x0028U)
  116. #define VHA_CR_CORE_IP_INTEGRATOR_ID_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  117. #define VHA_CR_CORE_IP_INTEGRATOR_ID_VALUE_SHIFT (0U)
  118. #define VHA_CR_CORE_IP_INTEGRATOR_ID_VALUE_CLRMSK (IMG_UINT64_C(0XFFFFFFFF00000000))
  119. /*
  120. Register VHA_CR_CORE_IP_CHANGELIST
  121. */
  122. #define VHA_CR_CORE_IP_CHANGELIST (0x0030U)
  123. #define VHA_CR_CORE_IP_CHANGELIST_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  124. #define VHA_CR_CORE_IP_CHANGELIST_VALUE_SHIFT (0U)
  125. #define VHA_CR_CORE_IP_CHANGELIST_VALUE_CLRMSK (IMG_UINT64_C(0XFFFFFFFF00000000))
  126. /*
  127. Register VHA_CR_CORE_IP_CONFIG
  128. */
  129. #define VHA_CR_CORE_IP_CONFIG (0x0038U)
  130. #define VHA_CR_CORE_IP_CONFIG_MASKFULL (IMG_UINT64_C(0x0000000000000F03))
  131. #define VHA_CR_CORE_IP_CONFIG_SIGNATURES_SUPPORTED_SUBSET_SHIFT (11U)
  132. #define VHA_CR_CORE_IP_CONFIG_SIGNATURES_SUPPORTED_SUBSET_CLRMSK (0XFFFFF7FFU)
  133. #define VHA_CR_CORE_IP_CONFIG_SIGNATURES_SUPPORTED_SUBSET_EN (0X00000800U)
  134. #define VHA_CR_CORE_IP_CONFIG_SIGNATURES_SUPPORTED_ALL_SHIFT (10U)
  135. #define VHA_CR_CORE_IP_CONFIG_SIGNATURES_SUPPORTED_ALL_CLRMSK (0XFFFFFBFFU)
  136. #define VHA_CR_CORE_IP_CONFIG_SIGNATURES_SUPPORTED_ALL_EN (0X00000400U)
  137. #define VHA_CR_CORE_IP_CONFIG_RANDOM_STALLERS_SUPPORTED_SHIFT (9U)
  138. #define VHA_CR_CORE_IP_CONFIG_RANDOM_STALLERS_SUPPORTED_CLRMSK (0XFFFFFDFFU)
  139. #define VHA_CR_CORE_IP_CONFIG_RANDOM_STALLERS_SUPPORTED_EN (0X00000200U)
  140. #define VHA_CR_CORE_IP_CONFIG_RTM_SUPPORTED_SHIFT (8U)
  141. #define VHA_CR_CORE_IP_CONFIG_RTM_SUPPORTED_CLRMSK (0XFFFFFEFFU)
  142. #define VHA_CR_CORE_IP_CONFIG_RTM_SUPPORTED_EN (0X00000100U)
  143. #define VHA_CR_CORE_IP_CONFIG_SCL_SUPPORTED_SHIFT (1U)
  144. #define VHA_CR_CORE_IP_CONFIG_SCL_SUPPORTED_CLRMSK (0XFFFFFFFDU)
  145. #define VHA_CR_CORE_IP_CONFIG_SCL_SUPPORTED_EN (0X00000002U)
  146. #define VHA_CR_CORE_IP_CONFIG_CNN_SUPPORTED_SHIFT (0U)
  147. #define VHA_CR_CORE_IP_CONFIG_CNN_SUPPORTED_CLRMSK (0XFFFFFFFEU)
  148. #define VHA_CR_CORE_IP_CONFIG_CNN_SUPPORTED_EN (0X00000001U)
  149. /*
  150. Register VHA_CR_CNN_MEM_WDT_TIMER
  151. */
  152. #define VHA_CR_CNN_MEM_WDT_TIMER (0x0048U)
  153. #define VHA_CR_CNN_MEM_WDT_TIMER_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  154. #define VHA_CR_CNN_MEM_WDT_TIMER_VALUE_SHIFT (0U)
  155. #define VHA_CR_CNN_MEM_WDT_TIMER_VALUE_CLRMSK (00000000U)
  156. /*
  157. Register VHA_CR_CNN_HL_WDT_TIMER
  158. */
  159. #define VHA_CR_CNN_HL_WDT_TIMER (0x0050U)
  160. #define VHA_CR_CNN_HL_WDT_TIMER_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  161. #define VHA_CR_CNN_HL_WDT_TIMER_VALUE_SHIFT (0U)
  162. #define VHA_CR_CNN_HL_WDT_TIMER_VALUE_CLRMSK (00000000U)
  163. /*
  164. Register VHA_CR_RTM_CTRL
  165. */
  166. #define VHA_CR_RTM_CTRL (0x0058U)
  167. #define VHA_CR_RTM_CTRL_MASKFULL (IMG_UINT64_C(0x00000000CFFFFFF8))
  168. #define VHA_CR_RTM_CTRL_RTM_ENABLE_SHIFT (31U)
  169. #define VHA_CR_RTM_CTRL_RTM_ENABLE_CLRMSK (0X7FFFFFFFU)
  170. #define VHA_CR_RTM_CTRL_RTM_ENABLE_EN (0X80000000U)
  171. #define VHA_CR_RTM_CTRL_RTM_CHECK_SHIFT (30U)
  172. #define VHA_CR_RTM_CTRL_RTM_CHECK_CLRMSK (0XBFFFFFFFU)
  173. #define VHA_CR_RTM_CTRL_RTM_CHECK_EN (0X40000000U)
  174. #define VHA_CR_RTM_CTRL_RTM_SELECTOR_SHIFT (3U)
  175. #define VHA_CR_RTM_CTRL_RTM_SELECTOR_CLRMSK (0XF0000007U)
  176. /*
  177. Register VHA_CR_RTM_DATA
  178. */
  179. #define VHA_CR_RTM_DATA (0x0060U)
  180. #define VHA_CR_RTM_DATA_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  181. #define VHA_CR_RTM_DATA_RTM_DATA_SHIFT (0U)
  182. #define VHA_CR_RTM_DATA_RTM_DATA_CLRMSK (00000000U)
  183. /*
  184. Register VHA_CR_CNN_IP_CONFIG0
  185. */
  186. #define VHA_CR_CNN_IP_CONFIG0 (0x0068U)
  187. #define VHA_CR_CNN_IP_CONFIG0_MASKFULL (IMG_UINT64_C(0x00000000007FFFFF))
  188. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_MMM_SUPPORTED_SHIFT (22U)
  189. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_MMM_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFBFFFFF))
  190. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_MMM_SUPPORTED_EN (IMG_UINT64_C(0X0000000000400000))
  191. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_SCHEDULING_SUPPORTED_SHIFT (21U)
  192. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_SCHEDULING_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFDFFFFF))
  193. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_SCHEDULING_SUPPORTED_EN (IMG_UINT64_C(0X0000000000200000))
  194. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_SECURITY_SHIFT (20U)
  195. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_SECURITY_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFEFFFFF))
  196. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_SECURITY_EN (IMG_UINT64_C(0X0000000000100000))
  197. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_CBUF_DECOMPRESSION_SUPPORTED_SHIFT (19U)
  198. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_CBUF_DECOMPRESSION_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF7FFFF))
  199. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_CBUF_DECOMPRESSION_SUPPORTED_EN (IMG_UINT64_C(0X0000000000080000))
  200. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_POOL_MIN_SUPPORTED_SHIFT (18U)
  201. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_POOL_MIN_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFBFFFF))
  202. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_POOL_MIN_SUPPORTED_EN (IMG_UINT64_C(0X0000000000040000))
  203. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_UNSIGNED_SUPPORTED_SHIFT (17U)
  204. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_UNSIGNED_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFDFFFF))
  205. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_UNSIGNED_SUPPORTED_EN (IMG_UINT64_C(0X0000000000020000))
  206. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_MIRROR_PADDING_SUPPORTED_SHIFT (16U)
  207. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_MIRROR_PADDING_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFEFFFF))
  208. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_MIRROR_PADDING_SUPPORTED_EN (IMG_UINT64_C(0X0000000000010000))
  209. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_EWO_BROADCAST_SUPPORTED_SHIFT (15U)
  210. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_EWO_BROADCAST_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF7FFF))
  211. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_EWO_BROADCAST_SUPPORTED_EN (IMG_UINT64_C(0X0000000000008000))
  212. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_HALF_16BIT_CONV_SUPPORTED_SHIFT (14U)
  213. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_HALF_16BIT_CONV_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFBFFF))
  214. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_HALF_16BIT_CONV_SUPPORTED_EN (IMG_UINT64_C(0X0000000000004000))
  215. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_OUTPUT_FIXTOFIX_SUPPORTED_SHIFT (13U)
  216. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_OUTPUT_FIXTOFIX_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFDFFF))
  217. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_OUTPUT_FIXTOFIX_SUPPORTED_EN (IMG_UINT64_C(0X0000000000002000))
  218. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DUAL_8BIT_CONV_SUPPORTED_SHIFT (12U)
  219. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DUAL_8BIT_CONV_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFEFFF))
  220. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DUAL_8BIT_CONV_SUPPORTED_EN (IMG_UINT64_C(0X0000000000001000))
  221. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DATA_DECOMPRESSION_SUPPORTED_SHIFT (11U)
  222. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DATA_DECOMPRESSION_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF7FF))
  223. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DATA_DECOMPRESSION_SUPPORTED_EN (IMG_UINT64_C(0X0000000000000800))
  224. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DATA_COMPRESSION_SUPPORTED_SHIFT (10U)
  225. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DATA_COMPRESSION_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFBFF))
  226. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DATA_COMPRESSION_SUPPORTED_EN (IMG_UINT64_C(0X0000000000000400))
  227. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_ELEMENT_OPS_CALC_SUPPORTED_SHIFT (9U)
  228. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_ELEMENT_OPS_CALC_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFDFF))
  229. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_ELEMENT_OPS_CALC_SUPPORTED_EN (IMG_UINT64_C(0X0000000000000200))
  230. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_ELEMENT_OPS_FETCH_SUPPORTED_SHIFT (8U)
  231. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_ELEMENT_OPS_FETCH_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFEFF))
  232. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_ELEMENT_OPS_FETCH_SUPPORTED_EN (IMG_UINT64_C(0X0000000000000100))
  233. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_ELEMENT_OPS_SUPPORTED_SHIFT (7U)
  234. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_ELEMENT_OPS_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFF7F))
  235. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_ELEMENT_OPS_SUPPORTED_EN (IMG_UINT64_C(0X0000000000000080))
  236. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_POOL_AVG_SUPPORTED_SHIFT (6U)
  237. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_POOL_AVG_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFBF))
  238. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_POOL_AVG_SUPPORTED_EN (IMG_UINT64_C(0X0000000000000040))
  239. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_POOL_MAX_SUPPORTED_SHIFT (5U)
  240. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_POOL_MAX_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFDF))
  241. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_POOL_MAX_SUPPORTED_EN (IMG_UINT64_C(0X0000000000000020))
  242. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_NORM_ICN_SUPPORTED_SHIFT (4U)
  243. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_NORM_ICN_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFEF))
  244. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_NORM_ICN_SUPPORTED_EN (IMG_UINT64_C(0X0000000000000010))
  245. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_NORM_ACN_SUPPORTED_SHIFT (3U)
  246. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_NORM_ACN_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF7))
  247. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_NORM_ACN_SUPPORTED_EN (IMG_UINT64_C(0X0000000000000008))
  248. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_ACT_LUT_SUPPORTED_SHIFT (2U)
  249. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_ACT_LUT_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFB))
  250. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_ACT_LUT_SUPPORTED_EN (IMG_UINT64_C(0X0000000000000004))
  251. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DECONV_SUPPORTED_SHIFT (1U)
  252. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DECONV_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFD))
  253. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DECONV_SUPPORTED_EN (IMG_UINT64_C(0X0000000000000002))
  254. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_CONV_SUPPORTED_SHIFT (0U)
  255. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_CONV_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  256. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_CONV_SUPPORTED_EN (IMG_UINT64_C(0X0000000000000001))
  257. /*
  258. Register VHA_CR_CNN_IP_CONFIG1
  259. */
  260. #define VHA_CR_CNN_IP_CONFIG1 (0x0070U)
  261. #define VHA_CR_CNN_IP_CONFIG1_MASKFULL (IMG_UINT64_C(0x0FFFFFFF3F0FFFFF))
  262. #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_MAX_FILTERS_PER_SET_MIN1_SHIFT (52U)
  263. #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_MAX_FILTERS_PER_SET_MIN1_CLRMSK (IMG_UINT64_C(0XF00FFFFFFFFFFFFF))
  264. #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_MAX_FILTERS_MIN1_SHIFT (39U)
  265. #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_MAX_FILTERS_MIN1_CLRMSK (IMG_UINT64_C(0XFFF0007FFFFFFFFF))
  266. #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_SCHEDULING_NUM_PRIORITY_MIN1_SHIFT (37U)
  267. #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_SCHEDULING_NUM_PRIORITY_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFF9FFFFFFFFF))
  268. #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_CONV_ENGINE_CALC_BLOCKS_MIN1_SHIFT (32U)
  269. #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_CONV_ENGINE_CALC_BLOCKS_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFE0FFFFFFFF))
  270. #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_WEIGHT_DATA_WIDTH_MIN1_SHIFT (24U)
  271. #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_WEIGHT_DATA_WIDTH_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFC0FFFFFF))
  272. #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_ACTIVATION_DATA_WIDTH_MIN1_SHIFT (16U)
  273. #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_ACTIVATION_DATA_WIDTH_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF0FFFF))
  274. #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_CONV_ENGINE_NUM_FILTERS_MIN1_SHIFT (12U)
  275. #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_CONV_ENGINE_NUM_FILTERS_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF0FFF))
  276. #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_CONV_ENGINE_NUM_COEFFS_MIN1_SHIFT (4U)
  277. #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_CONV_ENGINE_NUM_COEFFS_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF00F))
  278. #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_SCHEDULING_NUM_HOSTS_MIN1_SHIFT (0U)
  279. #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_SCHEDULING_NUM_HOSTS_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF0))
  280. /*
  281. Register VHA_CR_CNN_IP_CONFIG2
  282. */
  283. #define VHA_CR_CNN_IP_CONFIG2 (0x0078U)
  284. #define VHA_CR_CNN_IP_CONFIG2_MASKFULL (IMG_UINT64_C(0x00000FFFFFFFFFFF))
  285. #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_MAX_FILTERS_WITH_BIAS_MIN1_SHIFT (34U)
  286. #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_MAX_FILTERS_WITH_BIAS_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFF003FFFFFFFF))
  287. #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_NORM_UNITS_MIN1_SHIFT (28U)
  288. #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_NORM_UNITS_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFC0FFFFFFF))
  289. #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_SHARED_BUFFER_SIZE_MIN1_SHIFT (20U)
  290. #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_SHARED_BUFFER_SIZE_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFF00FFFFF))
  291. #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_COEFF_BUFFER_SIZE_MIN1_SHIFT (4U)
  292. #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_COEFF_BUFFER_SIZE_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF0000F))
  293. #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_COEFF_BUFFER_BANKS_MIN1_SHIFT (0U)
  294. #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_COEFF_BUFFER_BANKS_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF0))
  295. /*
  296. Register VHA_CR_CNN_IP_CONFIG3
  297. */
  298. #define VHA_CR_CNN_IP_CONFIG3 (0x0080U)
  299. #define VHA_CR_CNN_IP_CONFIG3_MASKFULL (IMG_UINT64_C(0x000001FFFFFFFFFF))
  300. #define VHA_CR_CNN_IP_CONFIG3_VHA_CNN_MMM_PARALLELISM_L1_MIN1_SHIFT (38U)
  301. #define VHA_CR_CNN_IP_CONFIG3_VHA_CNN_MMM_PARALLELISM_L1_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFE3FFFFFFFFF))
  302. #define VHA_CR_CNN_IP_CONFIG3_VHA_CNN_MMM_PARALLELISM_L0_MIN1_SHIFT (34U)
  303. #define VHA_CR_CNN_IP_CONFIG3_VHA_CNN_MMM_PARALLELISM_L0_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFC3FFFFFFFF))
  304. #define VHA_CR_CNN_IP_CONFIG3_VHA_CNN_MMM_BUFFER_SIZE_MIN1_SHIFT (29U)
  305. #define VHA_CR_CNN_IP_CONFIG3_VHA_CNN_MMM_BUFFER_SIZE_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFC1FFFFFFF))
  306. #define VHA_CR_CNN_IP_CONFIG3_VHA_CNN_MMM_BUFFER_BANKS_MIN1_SHIFT (24U)
  307. #define VHA_CR_CNN_IP_CONFIG3_VHA_CNN_MMM_BUFFER_BANKS_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFE0FFFFFF))
  308. #define VHA_CR_CNN_IP_CONFIG3_VHA_CNN_ACT_LUT_SIZE_MIN1_SHIFT (16U)
  309. #define VHA_CR_CNN_IP_CONFIG3_VHA_CNN_ACT_LUT_SIZE_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF00FFFF))
  310. #define VHA_CR_CNN_IP_CONFIG3_VHA_CNN_INPUT_BUFFER_SIZE_MIN1_SHIFT (8U)
  311. #define VHA_CR_CNN_IP_CONFIG3_VHA_CNN_INPUT_BUFFER_SIZE_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF00FF))
  312. #define VHA_CR_CNN_IP_CONFIG3_VHA_CNN_INPUT_BUFFER_BANKS_MIN1_SHIFT (0U)
  313. #define VHA_CR_CNN_IP_CONFIG3_VHA_CNN_INPUT_BUFFER_BANKS_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFF00))
  314. /*
  315. Clock is gated and the module is inactive */
  316. #define VHA_CR_SYS_CLK_STATUS0_MODE_GATED (0x00000000U)
  317. /*
  318. Clock is running */
  319. #define VHA_CR_SYS_CLK_STATUS0_MODE_RUNNING (0x00000001U)
  320. /*
  321. Register VHA_CR_SYS_CLK_STATUS0
  322. */
  323. #define VHA_CR_SYS_CLK_STATUS0 (0x0088U)
  324. #define VHA_CR_SYS_CLK_STATUS0_MASKFULL (IMG_UINT64_C(0x0000000000000004))
  325. #define VHA_CR_SYS_CLK_STATUS0_SLC_SHIFT (2U)
  326. #define VHA_CR_SYS_CLK_STATUS0_SLC_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFB))
  327. #define VHA_CR_SYS_CLK_STATUS0_SLC_GATED (IMG_UINT64_C(0000000000000000))
  328. #define VHA_CR_SYS_CLK_STATUS0_SLC_RUNNING (IMG_UINT64_C(0x0000000000000004))
  329. /*
  330. Register VHA_CR_PERF_SLC0_READ
  331. */
  332. #define VHA_CR_PERF_SLC0_READ (0x0200U)
  333. #define VHA_CR_PERF_SLC0_READ_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  334. #define VHA_CR_PERF_SLC0_READ_COUNT_SHIFT (0U)
  335. #define VHA_CR_PERF_SLC0_READ_COUNT_CLRMSK (00000000U)
  336. /*
  337. Register VHA_CR_PERF_SLC0_WRITE
  338. */
  339. #define VHA_CR_PERF_SLC0_WRITE (0x0208U)
  340. #define VHA_CR_PERF_SLC0_WRITE_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  341. #define VHA_CR_PERF_SLC0_WRITE_COUNT_SHIFT (0U)
  342. #define VHA_CR_PERF_SLC0_WRITE_COUNT_CLRMSK (00000000U)
  343. /*
  344. Register VHA_CR_PERF_SLC0_WRITE_DATA_STALL
  345. */
  346. #define VHA_CR_PERF_SLC0_WRITE_DATA_STALL (0x0210U)
  347. #define VHA_CR_PERF_SLC0_WRITE_DATA_STALL_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  348. #define VHA_CR_PERF_SLC0_WRITE_DATA_STALL_COUNT_SHIFT (0U)
  349. #define VHA_CR_PERF_SLC0_WRITE_DATA_STALL_COUNT_CLRMSK (00000000U)
  350. /*
  351. Register VHA_CR_PERF_SLC0_READ_STALL
  352. */
  353. #define VHA_CR_PERF_SLC0_READ_STALL (0x0218U)
  354. #define VHA_CR_PERF_SLC0_READ_STALL_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  355. #define VHA_CR_PERF_SLC0_READ_STALL_COUNT_SHIFT (0U)
  356. #define VHA_CR_PERF_SLC0_READ_STALL_COUNT_CLRMSK (00000000U)
  357. /*
  358. Register VHA_CR_PERF_SLC0_WRITE_STALL
  359. */
  360. #define VHA_CR_PERF_SLC0_WRITE_STALL (0x0220U)
  361. #define VHA_CR_PERF_SLC0_WRITE_STALL_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  362. #define VHA_CR_PERF_SLC0_WRITE_STALL_COUNT_SHIFT (0U)
  363. #define VHA_CR_PERF_SLC0_WRITE_STALL_COUNT_CLRMSK (00000000U)
  364. /*
  365. Register VHA_CR_PERF_SLC0_READ_ID_STALL
  366. */
  367. #define VHA_CR_PERF_SLC0_READ_ID_STALL (0x0228U)
  368. #define VHA_CR_PERF_SLC0_READ_ID_STALL_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  369. #define VHA_CR_PERF_SLC0_READ_ID_STALL_COUNT_SHIFT (0U)
  370. #define VHA_CR_PERF_SLC0_READ_ID_STALL_COUNT_CLRMSK (00000000U)
  371. /*
  372. Register VHA_CR_PERF_SLC0_WRITE_ID_STALL
  373. */
  374. #define VHA_CR_PERF_SLC0_WRITE_ID_STALL (0x0230U)
  375. #define VHA_CR_PERF_SLC0_WRITE_ID_STALL_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  376. #define VHA_CR_PERF_SLC0_WRITE_ID_STALL_COUNT_SHIFT (0U)
  377. #define VHA_CR_PERF_SLC0_WRITE_ID_STALL_COUNT_CLRMSK (00000000U)
  378. /*
  379. Register VHA_CR_PERF_SLC0_RD_BURST_SIZE1
  380. */
  381. #define VHA_CR_PERF_SLC0_RD_BURST_SIZE1 (0x0238U)
  382. #define VHA_CR_PERF_SLC0_RD_BURST_SIZE1_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  383. #define VHA_CR_PERF_SLC0_RD_BURST_SIZE1_COUNT_SHIFT (0U)
  384. #define VHA_CR_PERF_SLC0_RD_BURST_SIZE1_COUNT_CLRMSK (00000000U)
  385. /*
  386. Register VHA_CR_PERF_SLC0_WR_BURST_SIZE1
  387. */
  388. #define VHA_CR_PERF_SLC0_WR_BURST_SIZE1 (0x0240U)
  389. #define VHA_CR_PERF_SLC0_WR_BURST_SIZE1_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  390. #define VHA_CR_PERF_SLC0_WR_BURST_SIZE1_COUNT_SHIFT (0U)
  391. #define VHA_CR_PERF_SLC0_WR_BURST_SIZE1_COUNT_CLRMSK (00000000U)
  392. /*
  393. Register VHA_CR_PERF_SLC0_RD_BURST_SIZE2
  394. */
  395. #define VHA_CR_PERF_SLC0_RD_BURST_SIZE2 (0x0248U)
  396. #define VHA_CR_PERF_SLC0_RD_BURST_SIZE2_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  397. #define VHA_CR_PERF_SLC0_RD_BURST_SIZE2_COUNT_SHIFT (0U)
  398. #define VHA_CR_PERF_SLC0_RD_BURST_SIZE2_COUNT_CLRMSK (00000000U)
  399. /*
  400. Register VHA_CR_PERF_SLC0_WR_BURST_SIZE2
  401. */
  402. #define VHA_CR_PERF_SLC0_WR_BURST_SIZE2 (0x0250U)
  403. #define VHA_CR_PERF_SLC0_WR_BURST_SIZE2_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  404. #define VHA_CR_PERF_SLC0_WR_BURST_SIZE2_COUNT_SHIFT (0U)
  405. #define VHA_CR_PERF_SLC0_WR_BURST_SIZE2_COUNT_CLRMSK (00000000U)
  406. /*
  407. Register VHA_CR_PERF_SLC0_RD_BURST_SIZE3
  408. */
  409. #define VHA_CR_PERF_SLC0_RD_BURST_SIZE3 (0x0258U)
  410. #define VHA_CR_PERF_SLC0_RD_BURST_SIZE3_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  411. #define VHA_CR_PERF_SLC0_RD_BURST_SIZE3_COUNT_SHIFT (0U)
  412. #define VHA_CR_PERF_SLC0_RD_BURST_SIZE3_COUNT_CLRMSK (00000000U)
  413. /*
  414. Register VHA_CR_PERF_SLC0_WR_BURST_SIZE3
  415. */
  416. #define VHA_CR_PERF_SLC0_WR_BURST_SIZE3 (0x0260U)
  417. #define VHA_CR_PERF_SLC0_WR_BURST_SIZE3_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  418. #define VHA_CR_PERF_SLC0_WR_BURST_SIZE3_COUNT_SHIFT (0U)
  419. #define VHA_CR_PERF_SLC0_WR_BURST_SIZE3_COUNT_CLRMSK (00000000U)
  420. /*
  421. Register VHA_CR_PERF_SLC0_RD_BURST_SIZE4
  422. */
  423. #define VHA_CR_PERF_SLC0_RD_BURST_SIZE4 (0x0268U)
  424. #define VHA_CR_PERF_SLC0_RD_BURST_SIZE4_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  425. #define VHA_CR_PERF_SLC0_RD_BURST_SIZE4_COUNT_SHIFT (0U)
  426. #define VHA_CR_PERF_SLC0_RD_BURST_SIZE4_COUNT_CLRMSK (00000000U)
  427. /*
  428. Register VHA_CR_PERF_SLC0_WR_BURST_SIZE4
  429. */
  430. #define VHA_CR_PERF_SLC0_WR_BURST_SIZE4 (0x0270U)
  431. #define VHA_CR_PERF_SLC0_WR_BURST_SIZE4_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  432. #define VHA_CR_PERF_SLC0_WR_BURST_SIZE4_COUNT_SHIFT (0U)
  433. #define VHA_CR_PERF_SLC0_WR_BURST_SIZE4_COUNT_CLRMSK (00000000U)
  434. /*
  435. Register VHA_CR_PERF_RESET_FULL
  436. */
  437. #define VHA_CR_PERF_RESET_FULL (0x0278U)
  438. #define VHA_CR_PERF_RESET_FULL_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  439. #define VHA_CR_PERF_RESET_FULL_RANGE_SHIFT (0U)
  440. #define VHA_CR_PERF_RESET_FULL_RANGE_CLRMSK (0XFFFFFFFEU)
  441. #define VHA_CR_PERF_RESET_FULL_RANGE_EN (0X00000001U)
  442. /*
  443. Register VHA_CR_PERF_ENABLE_FULL
  444. */
  445. #define VHA_CR_PERF_ENABLE_FULL (0x0280U)
  446. #define VHA_CR_PERF_ENABLE_FULL_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  447. #define VHA_CR_PERF_ENABLE_FULL_RANGE_SHIFT (0U)
  448. #define VHA_CR_PERF_ENABLE_FULL_RANGE_CLRMSK (0XFFFFFFFEU)
  449. #define VHA_CR_PERF_ENABLE_FULL_RANGE_EN (0X00000001U)
  450. /*
  451. Register VHA_CR_MMU_STATUS
  452. */
  453. #define VHA_CR_MMU_STATUS (0x0288U)
  454. #define VHA_CR_MMU_STATUS_MASKFULL (IMG_UINT64_C(0x000001FFFFFFFFFF))
  455. #define VHA_CR_MMU_STATUS_MMU_STALLED_SHIFT (40U)
  456. #define VHA_CR_MMU_STATUS_MMU_STALLED_CLRMSK (IMG_UINT64_C(0XFFFFFEFFFFFFFFFF))
  457. #define VHA_CR_MMU_STATUS_MMU_STALLED_EN (IMG_UINT64_C(0X0000010000000000))
  458. #define VHA_CR_MMU_STATUS_PM_WRITES_SHIFT (38U)
  459. #define VHA_CR_MMU_STATUS_PM_WRITES_CLRMSK (IMG_UINT64_C(0XFFFFFF3FFFFFFFFF))
  460. #define VHA_CR_MMU_STATUS_PM_READS_SHIFT (36U)
  461. #define VHA_CR_MMU_STATUS_PM_READS_CLRMSK (IMG_UINT64_C(0XFFFFFFCFFFFFFFFF))
  462. #define VHA_CR_MMU_STATUS_PC_READS_SHIFT (24U)
  463. #define VHA_CR_MMU_STATUS_PC_READS_CLRMSK (IMG_UINT64_C(0XFFFFFFF000FFFFFF))
  464. #define VHA_CR_MMU_STATUS_PD_READS_SHIFT (12U)
  465. #define VHA_CR_MMU_STATUS_PD_READS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF000FFF))
  466. #define VHA_CR_MMU_STATUS_PT_READS_SHIFT (0U)
  467. #define VHA_CR_MMU_STATUS_PT_READS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF000))
  468. /*
  469. Register VHA_CR_SLC_STATUS1
  470. */
  471. #define VHA_CR_SLC_STATUS1 (0x0290U)
  472. #define VHA_CR_SLC_STATUS1_MASKFULL (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
  473. #define VHA_CR_SLC_STATUS1_XBAR_CFI_TIMEOUTS_SHIFT (48U)
  474. #define VHA_CR_SLC_STATUS1_XBAR_CFI_TIMEOUTS_CLRMSK (IMG_UINT64_C(0X0000FFFFFFFFFFFF))
  475. #define VHA_CR_SLC_STATUS1_BUS1_OUTSTANDING_WRITES_SHIFT (36U)
  476. #define VHA_CR_SLC_STATUS1_BUS1_OUTSTANDING_WRITES_CLRMSK (IMG_UINT64_C(0XFFFF000FFFFFFFFF))
  477. #define VHA_CR_SLC_STATUS1_BUS0_OUTSTANDING_WRITES_SHIFT (24U)
  478. #define VHA_CR_SLC_STATUS1_BUS0_OUTSTANDING_WRITES_CLRMSK (IMG_UINT64_C(0XFFFFFFF000FFFFFF))
  479. #define VHA_CR_SLC_STATUS1_BUS1_OUTSTANDING_READS_SHIFT (12U)
  480. #define VHA_CR_SLC_STATUS1_BUS1_OUTSTANDING_READS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF000FFF))
  481. #define VHA_CR_SLC_STATUS1_BUS0_OUTSTANDING_READS_SHIFT (0U)
  482. #define VHA_CR_SLC_STATUS1_BUS0_OUTSTANDING_READS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF000))
  483. /*
  484. Register VHA_CR_SLC_STATUS2
  485. */
  486. #define VHA_CR_SLC_STATUS2 (0x0298U)
  487. #define VHA_CR_SLC_STATUS2_MASKFULL (IMG_UINT64_C(0x0000FFFFFFFFFFFF))
  488. #define VHA_CR_SLC_STATUS2_BUS3_OUTSTANDING_WRITES_SHIFT (36U)
  489. #define VHA_CR_SLC_STATUS2_BUS3_OUTSTANDING_WRITES_CLRMSK (IMG_UINT64_C(0XFFFF000FFFFFFFFF))
  490. #define VHA_CR_SLC_STATUS2_BUS2_OUTSTANDING_WRITES_SHIFT (24U)
  491. #define VHA_CR_SLC_STATUS2_BUS2_OUTSTANDING_WRITES_CLRMSK (IMG_UINT64_C(0XFFFFFFF000FFFFFF))
  492. #define VHA_CR_SLC_STATUS2_BUS3_OUTSTANDING_READS_SHIFT (12U)
  493. #define VHA_CR_SLC_STATUS2_BUS3_OUTSTANDING_READS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF000FFF))
  494. #define VHA_CR_SLC_STATUS2_BUS2_OUTSTANDING_READS_SHIFT (0U)
  495. #define VHA_CR_SLC_STATUS2_BUS2_OUTSTANDING_READS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF000))
  496. /*
  497. Register VHA_CR_SLC_IDLE
  498. */
  499. #define VHA_CR_SLC_IDLE (0x02A0U)
  500. #define VHA_CR_SLC_IDLE_MASKFULL (IMG_UINT64_C(0x000000000000FFFF))
  501. #define VHA_CR_SLC_IDLE_ACE_CONVERTERS_SHIFT (12U)
  502. #define VHA_CR_SLC_IDLE_ACE_CONVERTERS_CLRMSK (0XFFFF0FFFU)
  503. #define VHA_CR_SLC_IDLE_CACHE_BANKS_SHIFT (4U)
  504. #define VHA_CR_SLC_IDLE_CACHE_BANKS_CLRMSK (0XFFFFF00FU)
  505. #define VHA_CR_SLC_IDLE_MMU_SHIFT (3U)
  506. #define VHA_CR_SLC_IDLE_MMU_CLRMSK (0XFFFFFFF7U)
  507. #define VHA_CR_SLC_IDLE_MMU_EN (0X00000008U)
  508. #define VHA_CR_SLC_IDLE_CCM_SHIFT (2U)
  509. #define VHA_CR_SLC_IDLE_CCM_CLRMSK (0XFFFFFFFBU)
  510. #define VHA_CR_SLC_IDLE_CCM_EN (0X00000004U)
  511. #define VHA_CR_SLC_IDLE_RDI_SHIFT (1U)
  512. #define VHA_CR_SLC_IDLE_RDI_CLRMSK (0XFFFFFFFDU)
  513. #define VHA_CR_SLC_IDLE_RDI_EN (0X00000002U)
  514. #define VHA_CR_SLC_IDLE_XBAR_SHIFT (0U)
  515. #define VHA_CR_SLC_IDLE_XBAR_CLRMSK (0XFFFFFFFEU)
  516. #define VHA_CR_SLC_IDLE_XBAR_EN (0X00000001U)
  517. /*
  518. Register VHA_CR_SLC_STATUS3
  519. */
  520. #define VHA_CR_SLC_STATUS3 (0x02A8U)
  521. #define VHA_CR_SLC_STATUS3_MASKFULL (IMG_UINT64_C(0x0FFFFFFFFFFFFFFF))
  522. #define VHA_CR_SLC_STATUS3_MAX_CRITICAL_QOS_READ_LATENCY_SHIFT (50U)
  523. #define VHA_CR_SLC_STATUS3_MAX_CRITICAL_QOS_READ_LATENCY_CLRMSK (IMG_UINT64_C(0XF003FFFFFFFFFFFF))
  524. #define VHA_CR_SLC_STATUS3_MAX_LOW_QOS_READ_LATENCY_SHIFT (40U)
  525. #define VHA_CR_SLC_STATUS3_MAX_LOW_QOS_READ_LATENCY_CLRMSK (IMG_UINT64_C(0XFFFC00FFFFFFFFFF))
  526. #define VHA_CR_SLC_STATUS3_AVG_CRITICAL_QOS_READ_LATENCY_SHIFT (30U)
  527. #define VHA_CR_SLC_STATUS3_AVG_CRITICAL_QOS_READ_LATENCY_CLRMSK (IMG_UINT64_C(0XFFFFFF003FFFFFFF))
  528. #define VHA_CR_SLC_STATUS3_AVG_LOW_QOS_READ_LATENCY_SHIFT (20U)
  529. #define VHA_CR_SLC_STATUS3_AVG_LOW_QOS_READ_LATENCY_CLRMSK (IMG_UINT64_C(0XFFFFFFFFC00FFFFF))
  530. #define VHA_CR_SLC_STATUS3_MIN_CRITICAL_QOS_READ_LATENCY_SHIFT (10U)
  531. #define VHA_CR_SLC_STATUS3_MIN_CRITICAL_QOS_READ_LATENCY_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF003FF))
  532. #define VHA_CR_SLC_STATUS3_MIN_LOW_QOS_READ_LATENCY_SHIFT (0U)
  533. #define VHA_CR_SLC_STATUS3_MIN_LOW_QOS_READ_LATENCY_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFC00))
  534. /*
  535. Register VHA_CR_SLC_FAULT_STOP_STATUS
  536. */
  537. #define VHA_CR_SLC_FAULT_STOP_STATUS (0x02B0U)
  538. #define VHA_CR_SLC_FAULT_STOP_STATUS_MASKFULL (IMG_UINT64_C(0x000000000001FFFF))
  539. #define VHA_CR_SLC_FAULT_STOP_STATUS_BIF_SHIFT (0U)
  540. #define VHA_CR_SLC_FAULT_STOP_STATUS_BIF_CLRMSK (0XFFFE0000U)
  541. /*
  542. Register VHA_CR_SLC_STATUS_DEBUG
  543. */
  544. #define VHA_CR_SLC_STATUS_DEBUG (0x02B8U)
  545. #define VHA_CR_SLC_STATUS_DEBUG_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  546. #define VHA_CR_SLC_STATUS_DEBUG_ERR_COH_REQ_SHIFT (16U)
  547. #define VHA_CR_SLC_STATUS_DEBUG_ERR_COH_REQ_CLRMSK (0X0000FFFFU)
  548. #define VHA_CR_SLC_STATUS_DEBUG_ERR_ADDR_ALIAS_SHIFT (0U)
  549. #define VHA_CR_SLC_STATUS_DEBUG_ERR_ADDR_ALIAS_CLRMSK (0XFFFF0000U)
  550. /*
  551. Register VHA_CR_BIF_OUTSTANDING_READ
  552. */
  553. #define VHA_CR_BIF_OUTSTANDING_READ (0x02C0U)
  554. #define VHA_CR_BIF_OUTSTANDING_READ_MASKFULL (IMG_UINT64_C(0x000000000000FFFF))
  555. #define VHA_CR_BIF_OUTSTANDING_READ_COUNTER_SHIFT (0U)
  556. #define VHA_CR_BIF_OUTSTANDING_READ_COUNTER_CLRMSK (0XFFFF0000U)
  557. /*
  558. Register VHA_CR_BIF_PAGE_FAULT_STALL
  559. */
  560. #define VHA_CR_BIF_PAGE_FAULT_STALL (0x02C8U)
  561. #define VHA_CR_BIF_PAGE_FAULT_STALL_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  562. #define VHA_CR_BIF_PAGE_FAULT_STALL_STATUS_SHIFT (0U)
  563. #define VHA_CR_BIF_PAGE_FAULT_STALL_STATUS_CLRMSK (0XFFFFFFFEU)
  564. #define VHA_CR_BIF_PAGE_FAULT_STALL_STATUS_EN (0X00000001U)
  565. /*
  566. Register VHA_CR_PERF_SLC
  567. */
  568. #define VHA_CR_PERF_SLC (0x02D0U)
  569. #define VHA_CR_PERF_SLC_MASKFULL (IMG_UINT64_C(0x000000000FEFFEFF))
  570. #define VHA_CR_PERF_SLC_EWO_REQ_RD_WORD_COUNTER_RESET_SHIFT (27U)
  571. #define VHA_CR_PERF_SLC_EWO_REQ_RD_WORD_COUNTER_RESET_CLRMSK (0XF7FFFFFFU)
  572. #define VHA_CR_PERF_SLC_EWO_REQ_RD_WORD_COUNTER_RESET_EN (0X08000000U)
  573. #define VHA_CR_PERF_SLC_EWO_REQ_RD_COUNTER_RESET_SHIFT (26U)
  574. #define VHA_CR_PERF_SLC_EWO_REQ_RD_COUNTER_RESET_CLRMSK (0XFBFFFFFFU)
  575. #define VHA_CR_PERF_SLC_EWO_REQ_RD_COUNTER_RESET_EN (0X04000000U)
  576. #define VHA_CR_PERF_SLC_MMU_REQ_RD_WORD_COUNTER_RESET_SHIFT (25U)
  577. #define VHA_CR_PERF_SLC_MMU_REQ_RD_WORD_COUNTER_RESET_CLRMSK (0XFDFFFFFFU)
  578. #define VHA_CR_PERF_SLC_MMU_REQ_RD_WORD_COUNTER_RESET_EN (0X02000000U)
  579. #define VHA_CR_PERF_SLC_MMU_REQ_RD_COUNTER_RESET_SHIFT (24U)
  580. #define VHA_CR_PERF_SLC_MMU_REQ_RD_COUNTER_RESET_CLRMSK (0XFEFFFFFFU)
  581. #define VHA_CR_PERF_SLC_MMU_REQ_RD_COUNTER_RESET_EN (0X01000000U)
  582. #define VHA_CR_PERF_SLC_OPK_REQ_WR_WORD_COUNTER_RESET_SHIFT (23U)
  583. #define VHA_CR_PERF_SLC_OPK_REQ_WR_WORD_COUNTER_RESET_CLRMSK (0XFF7FFFFFU)
  584. #define VHA_CR_PERF_SLC_OPK_REQ_WR_WORD_COUNTER_RESET_EN (0X00800000U)
  585. #define VHA_CR_PERF_SLC_ABUF_REQ_RD_WORD_COUNTER_RESET_SHIFT (22U)
  586. #define VHA_CR_PERF_SLC_ABUF_REQ_RD_WORD_COUNTER_RESET_CLRMSK (0XFFBFFFFFU)
  587. #define VHA_CR_PERF_SLC_ABUF_REQ_RD_WORD_COUNTER_RESET_EN (0X00400000U)
  588. #define VHA_CR_PERF_SLC_CBUF_REQ_RD_WORD_COUNTER_RESET_SHIFT (21U)
  589. #define VHA_CR_PERF_SLC_CBUF_REQ_RD_WORD_COUNTER_RESET_CLRMSK (0XFFDFFFFFU)
  590. #define VHA_CR_PERF_SLC_CBUF_REQ_RD_WORD_COUNTER_RESET_EN (0X00200000U)
  591. #define VHA_CR_PERF_SLC_MMM_REQ_WR_WORD_COUNTER_RESET_SHIFT (19U)
  592. #define VHA_CR_PERF_SLC_MMM_REQ_WR_WORD_COUNTER_RESET_CLRMSK (0XFFF7FFFFU)
  593. #define VHA_CR_PERF_SLC_MMM_REQ_WR_WORD_COUNTER_RESET_EN (0X00080000U)
  594. #define VHA_CR_PERF_SLC_MMM_REQ_RD_WORD_COUNTER_RESET_SHIFT (18U)
  595. #define VHA_CR_PERF_SLC_MMM_REQ_RD_WORD_COUNTER_RESET_CLRMSK (0XFFFBFFFFU)
  596. #define VHA_CR_PERF_SLC_MMM_REQ_RD_WORD_COUNTER_RESET_EN (0X00040000U)
  597. #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_WORD_COUNTER_RESET_SHIFT (17U)
  598. #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_WORD_COUNTER_RESET_CLRMSK (0XFFFDFFFFU)
  599. #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_WORD_COUNTER_RESET_EN (0X00020000U)
  600. #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_WORD_COUNTER_RESET_SHIFT (16U)
  601. #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_WORD_COUNTER_RESET_CLRMSK (0XFFFEFFFFU)
  602. #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_WORD_COUNTER_RESET_EN (0X00010000U)
  603. #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_WORD_COUNTER_RESET_SHIFT (15U)
  604. #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_WORD_COUNTER_RESET_CLRMSK (0XFFFF7FFFU)
  605. #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_WORD_COUNTER_RESET_EN (0X00008000U)
  606. #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_WORD_COUNTER_RESET_SHIFT (14U)
  607. #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_WORD_COUNTER_RESET_CLRMSK (0XFFFFBFFFU)
  608. #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_WORD_COUNTER_RESET_EN (0X00004000U)
  609. #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_WORD_COUNTER_RESET_SHIFT (13U)
  610. #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_WORD_COUNTER_RESET_CLRMSK (0XFFFFDFFFU)
  611. #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_WORD_COUNTER_RESET_EN (0X00002000U)
  612. #define VHA_CR_PERF_SLC_CMD_REQ_RD_WORD_COUNTER_RESET_SHIFT (12U)
  613. #define VHA_CR_PERF_SLC_CMD_REQ_RD_WORD_COUNTER_RESET_CLRMSK (0XFFFFEFFFU)
  614. #define VHA_CR_PERF_SLC_CMD_REQ_RD_WORD_COUNTER_RESET_EN (0X00001000U)
  615. #define VHA_CR_PERF_SLC_OPK_REQ_WR_COUNTER_RESET_SHIFT (11U)
  616. #define VHA_CR_PERF_SLC_OPK_REQ_WR_COUNTER_RESET_CLRMSK (0XFFFFF7FFU)
  617. #define VHA_CR_PERF_SLC_OPK_REQ_WR_COUNTER_RESET_EN (0X00000800U)
  618. #define VHA_CR_PERF_SLC_ABUF_REQ_RD_COUNTER_RESET_SHIFT (10U)
  619. #define VHA_CR_PERF_SLC_ABUF_REQ_RD_COUNTER_RESET_CLRMSK (0XFFFFFBFFU)
  620. #define VHA_CR_PERF_SLC_ABUF_REQ_RD_COUNTER_RESET_EN (0X00000400U)
  621. #define VHA_CR_PERF_SLC_CBUF_REQ_RD_COUNTER_RESET_SHIFT (9U)
  622. #define VHA_CR_PERF_SLC_CBUF_REQ_RD_COUNTER_RESET_CLRMSK (0XFFFFFDFFU)
  623. #define VHA_CR_PERF_SLC_CBUF_REQ_RD_COUNTER_RESET_EN (0X00000200U)
  624. #define VHA_CR_PERF_SLC_MMM_REQ_WR_COUNTER_RESET_SHIFT (7U)
  625. #define VHA_CR_PERF_SLC_MMM_REQ_WR_COUNTER_RESET_CLRMSK (0XFFFFFF7FU)
  626. #define VHA_CR_PERF_SLC_MMM_REQ_WR_COUNTER_RESET_EN (0X00000080U)
  627. #define VHA_CR_PERF_SLC_MMM_REQ_RD_COUNTER_RESET_SHIFT (6U)
  628. #define VHA_CR_PERF_SLC_MMM_REQ_RD_COUNTER_RESET_CLRMSK (0XFFFFFFBFU)
  629. #define VHA_CR_PERF_SLC_MMM_REQ_RD_COUNTER_RESET_EN (0X00000040U)
  630. #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_COUNTER_RESET_SHIFT (5U)
  631. #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_COUNTER_RESET_CLRMSK (0XFFFFFFDFU)
  632. #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_COUNTER_RESET_EN (0X00000020U)
  633. #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_COUNTER_RESET_SHIFT (4U)
  634. #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_COUNTER_RESET_CLRMSK (0XFFFFFFEFU)
  635. #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_COUNTER_RESET_EN (0X00000010U)
  636. #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_COUNTER_RESET_SHIFT (3U)
  637. #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_COUNTER_RESET_CLRMSK (0XFFFFFFF7U)
  638. #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_COUNTER_RESET_EN (0X00000008U)
  639. #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_COUNTER_RESET_SHIFT (2U)
  640. #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_COUNTER_RESET_CLRMSK (0XFFFFFFFBU)
  641. #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_COUNTER_RESET_EN (0X00000004U)
  642. #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_COUNTER_RESET_SHIFT (1U)
  643. #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_COUNTER_RESET_CLRMSK (0XFFFFFFFDU)
  644. #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_COUNTER_RESET_EN (0X00000002U)
  645. #define VHA_CR_PERF_SLC_CMD_REQ_RD_COUNTER_RESET_SHIFT (0U)
  646. #define VHA_CR_PERF_SLC_CMD_REQ_RD_COUNTER_RESET_CLRMSK (0XFFFFFFFEU)
  647. #define VHA_CR_PERF_SLC_CMD_REQ_RD_COUNTER_RESET_EN (0X00000001U)
  648. /*
  649. Register VHA_CR_PERF_SLC_REQ_COUNT
  650. */
  651. #define VHA_CR_PERF_SLC_REQ_COUNT (0x02D8U)
  652. #define VHA_CR_PERF_SLC_REQ_COUNT_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  653. #define VHA_CR_PERF_SLC_REQ_COUNT_ENABLE_SHIFT (0U)
  654. #define VHA_CR_PERF_SLC_REQ_COUNT_ENABLE_CLRMSK (0XFFFFFFFEU)
  655. #define VHA_CR_PERF_SLC_REQ_COUNT_ENABLE_EN (0X00000001U)
  656. /*
  657. Register VHA_CR_PERF_SLC_CMD_REQ_RD
  658. */
  659. #define VHA_CR_PERF_SLC_CMD_REQ_RD (0x02E0U)
  660. #define VHA_CR_PERF_SLC_CMD_REQ_RD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  661. #define VHA_CR_PERF_SLC_CMD_REQ_RD_COUNTER_SHIFT (0U)
  662. #define VHA_CR_PERF_SLC_CMD_REQ_RD_COUNTER_CLRMSK (00000000U)
  663. /*
  664. Register VHA_CR_PERF_SLC_CMD_BCK_REQ_WR
  665. */
  666. #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR (0x02E8U)
  667. #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  668. #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_COUNTER_SHIFT (0U)
  669. #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_COUNTER_CLRMSK (00000000U)
  670. /*
  671. Register VHA_CR_PERF_SLC_CMD_CRC_REQ_WR
  672. */
  673. #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR (0x02F0U)
  674. #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  675. #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_COUNTER_SHIFT (0U)
  676. #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_COUNTER_CLRMSK (00000000U)
  677. /*
  678. Register VHA_CR_PERF_SLC_CMD_DBG_REQ_WR
  679. */
  680. #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR (0x02F8U)
  681. #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  682. #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_COUNTER_SHIFT (0U)
  683. #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_COUNTER_CLRMSK (00000000U)
  684. /*
  685. Register VHA_CR_PERF_SLC_CMD_REQ_FENCE
  686. */
  687. #define VHA_CR_PERF_SLC_CMD_REQ_FENCE (0x0300U)
  688. #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  689. #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_COUNTER_SHIFT (0U)
  690. #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_COUNTER_CLRMSK (00000000U)
  691. /*
  692. Register VHA_CR_PERF_SLC_IBUF_REQ0_RD
  693. */
  694. #define VHA_CR_PERF_SLC_IBUF_REQ0_RD (0x0308U)
  695. #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  696. #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_COUNTER_SHIFT (0U)
  697. #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_COUNTER_CLRMSK (00000000U)
  698. /*
  699. Register VHA_CR_PERF_SLC_MMM_REQ_RD
  700. */
  701. #define VHA_CR_PERF_SLC_MMM_REQ_RD (0x0310U)
  702. #define VHA_CR_PERF_SLC_MMM_REQ_RD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  703. #define VHA_CR_PERF_SLC_MMM_REQ_RD_COUNTER_SHIFT (0U)
  704. #define VHA_CR_PERF_SLC_MMM_REQ_RD_COUNTER_CLRMSK (00000000U)
  705. /*
  706. Register VHA_CR_PERF_SLC_MMM_REQ_WR
  707. */
  708. #define VHA_CR_PERF_SLC_MMM_REQ_WR (0x0318U)
  709. #define VHA_CR_PERF_SLC_MMM_REQ_WR_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  710. #define VHA_CR_PERF_SLC_MMM_REQ_WR_COUNTER_SHIFT (0U)
  711. #define VHA_CR_PERF_SLC_MMM_REQ_WR_COUNTER_CLRMSK (00000000U)
  712. /*
  713. Register VHA_CR_PERF_SLC_CBUF_REQ_RD
  714. */
  715. #define VHA_CR_PERF_SLC_CBUF_REQ_RD (0x0328U)
  716. #define VHA_CR_PERF_SLC_CBUF_REQ_RD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  717. #define VHA_CR_PERF_SLC_CBUF_REQ_RD_COUNTER_SHIFT (0U)
  718. #define VHA_CR_PERF_SLC_CBUF_REQ_RD_COUNTER_CLRMSK (00000000U)
  719. /*
  720. Register VHA_CR_PERF_SLC_ABUF_REQ_RD
  721. */
  722. #define VHA_CR_PERF_SLC_ABUF_REQ_RD (0x0330U)
  723. #define VHA_CR_PERF_SLC_ABUF_REQ_RD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  724. #define VHA_CR_PERF_SLC_ABUF_REQ_RD_COUNTER_SHIFT (0U)
  725. #define VHA_CR_PERF_SLC_ABUF_REQ_RD_COUNTER_CLRMSK (00000000U)
  726. /*
  727. Register VHA_CR_PERF_SLC_OPK_REQ_WR
  728. */
  729. #define VHA_CR_PERF_SLC_OPK_REQ_WR (0x0338U)
  730. #define VHA_CR_PERF_SLC_OPK_REQ_WR_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  731. #define VHA_CR_PERF_SLC_OPK_REQ_WR_COUNTER_SHIFT (0U)
  732. #define VHA_CR_PERF_SLC_OPK_REQ_WR_COUNTER_CLRMSK (00000000U)
  733. /*
  734. Register VHA_CR_PERF_SLC_CMD_REQ_RD_WORD
  735. */
  736. #define VHA_CR_PERF_SLC_CMD_REQ_RD_WORD (0x0340U)
  737. #define VHA_CR_PERF_SLC_CMD_REQ_RD_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  738. #define VHA_CR_PERF_SLC_CMD_REQ_RD_WORD_COUNTER_SHIFT (0U)
  739. #define VHA_CR_PERF_SLC_CMD_REQ_RD_WORD_COUNTER_CLRMSK (00000000U)
  740. /*
  741. Register VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_WORD
  742. */
  743. #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_WORD (0x0348U)
  744. #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  745. #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_WORD_COUNTER_SHIFT (0U)
  746. #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_WORD_COUNTER_CLRMSK (00000000U)
  747. /*
  748. Register VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_WORD
  749. */
  750. #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_WORD (0x0350U)
  751. #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  752. #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_WORD_COUNTER_SHIFT (0U)
  753. #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_WORD_COUNTER_CLRMSK (00000000U)
  754. /*
  755. Register VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_WORD
  756. */
  757. #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_WORD (0x0358U)
  758. #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  759. #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_WORD_COUNTER_SHIFT (0U)
  760. #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_WORD_COUNTER_CLRMSK (00000000U)
  761. /*
  762. Register VHA_CR_PERF_SLC_CMD_REQ_FENCE_WORD
  763. */
  764. #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_WORD (0x0360U)
  765. #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  766. #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_WORD_COUNTER_SHIFT (0U)
  767. #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_WORD_COUNTER_CLRMSK (00000000U)
  768. /*
  769. Register VHA_CR_PERF_SLC_IBUF_REQ0_RD_WORD
  770. */
  771. #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_WORD (0x0368U)
  772. #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  773. #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_WORD_COUNTER_SHIFT (0U)
  774. #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_WORD_COUNTER_CLRMSK (00000000U)
  775. /*
  776. Register VHA_CR_PERF_SLC_MMM_REQ_RD_WORD
  777. */
  778. #define VHA_CR_PERF_SLC_MMM_REQ_RD_WORD (0x0370U)
  779. #define VHA_CR_PERF_SLC_MMM_REQ_RD_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  780. #define VHA_CR_PERF_SLC_MMM_REQ_RD_WORD_COUNTER_SHIFT (0U)
  781. #define VHA_CR_PERF_SLC_MMM_REQ_RD_WORD_COUNTER_CLRMSK (00000000U)
  782. /*
  783. Register VHA_CR_PERF_SLC_MMM_REQ_WR_WORD
  784. */
  785. #define VHA_CR_PERF_SLC_MMM_REQ_WR_WORD (0x0378U)
  786. #define VHA_CR_PERF_SLC_MMM_REQ_WR_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  787. #define VHA_CR_PERF_SLC_MMM_REQ_WR_WORD_COUNTER_SHIFT (0U)
  788. #define VHA_CR_PERF_SLC_MMM_REQ_WR_WORD_COUNTER_CLRMSK (00000000U)
  789. /*
  790. Register VHA_CR_PERF_SLC_CBUF_REQ_RD_WORD
  791. */
  792. #define VHA_CR_PERF_SLC_CBUF_REQ_RD_WORD (0x0388U)
  793. #define VHA_CR_PERF_SLC_CBUF_REQ_RD_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  794. #define VHA_CR_PERF_SLC_CBUF_REQ_RD_WORD_COUNTER_SHIFT (0U)
  795. #define VHA_CR_PERF_SLC_CBUF_REQ_RD_WORD_COUNTER_CLRMSK (00000000U)
  796. /*
  797. Register VHA_CR_PERF_SLC_ABUF_REQ_RD_WORD
  798. */
  799. #define VHA_CR_PERF_SLC_ABUF_REQ_RD_WORD (0x0390U)
  800. #define VHA_CR_PERF_SLC_ABUF_REQ_RD_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  801. #define VHA_CR_PERF_SLC_ABUF_REQ_RD_WORD_COUNTER_SHIFT (0U)
  802. #define VHA_CR_PERF_SLC_ABUF_REQ_RD_WORD_COUNTER_CLRMSK (00000000U)
  803. /*
  804. Register VHA_CR_PERF_SLC_OPK_REQ_WR_WORD
  805. */
  806. #define VHA_CR_PERF_SLC_OPK_REQ_WR_WORD (0x0398U)
  807. #define VHA_CR_PERF_SLC_OPK_REQ_WR_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  808. #define VHA_CR_PERF_SLC_OPK_REQ_WR_WORD_COUNTER_SHIFT (0U)
  809. #define VHA_CR_PERF_SLC_OPK_REQ_WR_WORD_COUNTER_CLRMSK (00000000U)
  810. /*
  811. Register VHA_CR_PERF_SLC_MMU_REQ_RD
  812. */
  813. #define VHA_CR_PERF_SLC_MMU_REQ_RD (0x03A0U)
  814. #define VHA_CR_PERF_SLC_MMU_REQ_RD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  815. #define VHA_CR_PERF_SLC_MMU_REQ_RD_COUNTER_SHIFT (0U)
  816. #define VHA_CR_PERF_SLC_MMU_REQ_RD_COUNTER_CLRMSK (00000000U)
  817. /*
  818. Register VHA_CR_PERF_SLC_MMU_REQ_RD_WORD
  819. */
  820. #define VHA_CR_PERF_SLC_MMU_REQ_RD_WORD (0x03A8U)
  821. #define VHA_CR_PERF_SLC_MMU_REQ_RD_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  822. #define VHA_CR_PERF_SLC_MMU_REQ_RD_WORD_COUNTER_SHIFT (0U)
  823. #define VHA_CR_PERF_SLC_MMU_REQ_RD_WORD_COUNTER_CLRMSK (00000000U)
  824. /*
  825. Register VHA_CR_PERF_SLC_EWO_REQ_RD
  826. */
  827. #define VHA_CR_PERF_SLC_EWO_REQ_RD (0x03B0U)
  828. #define VHA_CR_PERF_SLC_EWO_REQ_RD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  829. #define VHA_CR_PERF_SLC_EWO_REQ_RD_COUNTER_SHIFT (0U)
  830. #define VHA_CR_PERF_SLC_EWO_REQ_RD_COUNTER_CLRMSK (00000000U)
  831. /*
  832. Register VHA_CR_PERF_SLC_EWO_REQ_RD_WORD
  833. */
  834. #define VHA_CR_PERF_SLC_EWO_REQ_RD_WORD (0x03B8U)
  835. #define VHA_CR_PERF_SLC_EWO_REQ_RD_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  836. #define VHA_CR_PERF_SLC_EWO_REQ_RD_WORD_COUNTER_SHIFT (0U)
  837. #define VHA_CR_PERF_SLC_EWO_REQ_RD_WORD_COUNTER_CLRMSK (00000000U)
  838. /*
  839. Register VHA_CR_BIF_RTN_FIFO_WORD_COUNT
  840. */
  841. #define VHA_CR_BIF_RTN_FIFO_WORD_COUNT (0x03C0U)
  842. #define VHA_CR_BIF_RTN_FIFO_WORD_COUNT_MASKFULL (IMG_UINT64_C(0x00000000000001FF))
  843. #define VHA_CR_BIF_RTN_FIFO_WORD_COUNT_COUNTER_SHIFT (0U)
  844. #define VHA_CR_BIF_RTN_FIFO_WORD_COUNT_COUNTER_CLRMSK (0XFFFFFE00U)
  845. #define VHA_CR_CLK_CTRL0_MODE_MASK (0x00000003U)
  846. /*
  847. The domain clock is forced off */
  848. #define VHA_CR_CLK_CTRL0_MODE_OFF (0x00000000U)
  849. /*
  850. The domain clock is forced on */
  851. #define VHA_CR_CLK_CTRL0_MODE_ON (0x00000001U)
  852. /*
  853. Automatic clock gating is active, the domain clock is only on whilst data is being processed */
  854. #define VHA_CR_CLK_CTRL0_MODE_AUTO (0x00000002U)
  855. /*
  856. Register VHA_CR_CLK_CTRL0
  857. */
  858. #define VHA_CR_CLK_CTRL0 (0x2000U)
  859. #define VHA_CR_CLK_CTRL0_MASKFULL (IMG_UINT64_C(0x33FFFFFF30000330))
  860. #define VHA_CR_CLK_CTRL0_CNN_MMM_SHIFT (60U)
  861. #define VHA_CR_CLK_CTRL0_CNN_MMM_CLRMSK (IMG_UINT64_C(0XCFFFFFFFFFFFFFFF))
  862. #define VHA_CR_CLK_CTRL0_CNN_MMM_OFF (IMG_UINT64_C(0000000000000000))
  863. #define VHA_CR_CLK_CTRL0_CNN_MMM_ON (IMG_UINT64_C(0x1000000000000000))
  864. #define VHA_CR_CLK_CTRL0_CNN_MMM_AUTO (IMG_UINT64_C(0x2000000000000000))
  865. #define VHA_CR_CLK_CTRL0_CNN_EWO_SHIFT (56U)
  866. #define VHA_CR_CLK_CTRL0_CNN_EWO_CLRMSK (IMG_UINT64_C(0XFCFFFFFFFFFFFFFF))
  867. #define VHA_CR_CLK_CTRL0_CNN_EWO_OFF (IMG_UINT64_C(0000000000000000))
  868. #define VHA_CR_CLK_CTRL0_CNN_EWO_ON (IMG_UINT64_C(0x0100000000000000))
  869. #define VHA_CR_CLK_CTRL0_CNN_EWO_AUTO (IMG_UINT64_C(0x0200000000000000))
  870. #define VHA_CR_CLK_CTRL0_CNN_PACK_SHIFT (54U)
  871. #define VHA_CR_CLK_CTRL0_CNN_PACK_CLRMSK (IMG_UINT64_C(0XFF3FFFFFFFFFFFFF))
  872. #define VHA_CR_CLK_CTRL0_CNN_PACK_OFF (IMG_UINT64_C(0000000000000000))
  873. #define VHA_CR_CLK_CTRL0_CNN_PACK_ON (IMG_UINT64_C(0x0040000000000000))
  874. #define VHA_CR_CLK_CTRL0_CNN_PACK_AUTO (IMG_UINT64_C(0x0080000000000000))
  875. #define VHA_CR_CLK_CTRL0_CNN_OIN_SHIFT (52U)
  876. #define VHA_CR_CLK_CTRL0_CNN_OIN_CLRMSK (IMG_UINT64_C(0XFFCFFFFFFFFFFFFF))
  877. #define VHA_CR_CLK_CTRL0_CNN_OIN_OFF (IMG_UINT64_C(0000000000000000))
  878. #define VHA_CR_CLK_CTRL0_CNN_OIN_ON (IMG_UINT64_C(0x0010000000000000))
  879. #define VHA_CR_CLK_CTRL0_CNN_OIN_AUTO (IMG_UINT64_C(0x0020000000000000))
  880. #define VHA_CR_CLK_CTRL0_CNN_POOL_SHIFT (50U)
  881. #define VHA_CR_CLK_CTRL0_CNN_POOL_CLRMSK (IMG_UINT64_C(0XFFF3FFFFFFFFFFFF))
  882. #define VHA_CR_CLK_CTRL0_CNN_POOL_OFF (IMG_UINT64_C(0000000000000000))
  883. #define VHA_CR_CLK_CTRL0_CNN_POOL_ON (IMG_UINT64_C(0x0004000000000000))
  884. #define VHA_CR_CLK_CTRL0_CNN_POOL_AUTO (IMG_UINT64_C(0x0008000000000000))
  885. #define VHA_CR_CLK_CTRL0_CNN_SB_SHIFT (48U)
  886. #define VHA_CR_CLK_CTRL0_CNN_SB_CLRMSK (IMG_UINT64_C(0XFFFCFFFFFFFFFFFF))
  887. #define VHA_CR_CLK_CTRL0_CNN_SB_OFF (IMG_UINT64_C(0000000000000000))
  888. #define VHA_CR_CLK_CTRL0_CNN_SB_ON (IMG_UINT64_C(0x0001000000000000))
  889. #define VHA_CR_CLK_CTRL0_CNN_SB_AUTO (IMG_UINT64_C(0x0002000000000000))
  890. #define VHA_CR_CLK_CTRL0_CNN_XBAR_SHIFT (46U)
  891. #define VHA_CR_CLK_CTRL0_CNN_XBAR_CLRMSK (IMG_UINT64_C(0XFFFF3FFFFFFFFFFF))
  892. #define VHA_CR_CLK_CTRL0_CNN_XBAR_OFF (IMG_UINT64_C(0000000000000000))
  893. #define VHA_CR_CLK_CTRL0_CNN_XBAR_ON (IMG_UINT64_C(0x0000400000000000))
  894. #define VHA_CR_CLK_CTRL0_CNN_XBAR_AUTO (IMG_UINT64_C(0x0000800000000000))
  895. #define VHA_CR_CLK_CTRL0_CNN_NORM_SHIFT (44U)
  896. #define VHA_CR_CLK_CTRL0_CNN_NORM_CLRMSK (IMG_UINT64_C(0XFFFFCFFFFFFFFFFF))
  897. #define VHA_CR_CLK_CTRL0_CNN_NORM_OFF (IMG_UINT64_C(0000000000000000))
  898. #define VHA_CR_CLK_CTRL0_CNN_NORM_ON (IMG_UINT64_C(0x0000100000000000))
  899. #define VHA_CR_CLK_CTRL0_CNN_NORM_AUTO (IMG_UINT64_C(0x0000200000000000))
  900. #define VHA_CR_CLK_CTRL0_CNN_ACT_SHIFT (42U)
  901. #define VHA_CR_CLK_CTRL0_CNN_ACT_CLRMSK (IMG_UINT64_C(0XFFFFF3FFFFFFFFFF))
  902. #define VHA_CR_CLK_CTRL0_CNN_ACT_OFF (IMG_UINT64_C(0000000000000000))
  903. #define VHA_CR_CLK_CTRL0_CNN_ACT_ON (IMG_UINT64_C(0x0000040000000000))
  904. #define VHA_CR_CLK_CTRL0_CNN_ACT_AUTO (IMG_UINT64_C(0x0000080000000000))
  905. #define VHA_CR_CLK_CTRL0_CNN_ACCUM_SHIFT (40U)
  906. #define VHA_CR_CLK_CTRL0_CNN_ACCUM_CLRMSK (IMG_UINT64_C(0XFFFFFCFFFFFFFFFF))
  907. #define VHA_CR_CLK_CTRL0_CNN_ACCUM_OFF (IMG_UINT64_C(0000000000000000))
  908. #define VHA_CR_CLK_CTRL0_CNN_ACCUM_ON (IMG_UINT64_C(0x0000010000000000))
  909. #define VHA_CR_CLK_CTRL0_CNN_ACCUM_AUTO (IMG_UINT64_C(0x0000020000000000))
  910. #define VHA_CR_CLK_CTRL0_CNN_CNV_SHIFT (38U)
  911. #define VHA_CR_CLK_CTRL0_CNN_CNV_CLRMSK (IMG_UINT64_C(0XFFFFFF3FFFFFFFFF))
  912. #define VHA_CR_CLK_CTRL0_CNN_CNV_OFF (IMG_UINT64_C(0000000000000000))
  913. #define VHA_CR_CLK_CTRL0_CNN_CNV_ON (IMG_UINT64_C(0x0000004000000000))
  914. #define VHA_CR_CLK_CTRL0_CNN_CNV_AUTO (IMG_UINT64_C(0x0000008000000000))
  915. #define VHA_CR_CLK_CTRL0_CNN_CBUF_SHIFT (36U)
  916. #define VHA_CR_CLK_CTRL0_CNN_CBUF_CLRMSK (IMG_UINT64_C(0XFFFFFFCFFFFFFFFF))
  917. #define VHA_CR_CLK_CTRL0_CNN_CBUF_OFF (IMG_UINT64_C(0000000000000000))
  918. #define VHA_CR_CLK_CTRL0_CNN_CBUF_ON (IMG_UINT64_C(0x0000001000000000))
  919. #define VHA_CR_CLK_CTRL0_CNN_CBUF_AUTO (IMG_UINT64_C(0x0000002000000000))
  920. #define VHA_CR_CLK_CTRL0_CNN_IBUF_SHIFT (34U)
  921. #define VHA_CR_CLK_CTRL0_CNN_IBUF_CLRMSK (IMG_UINT64_C(0XFFFFFFF3FFFFFFFF))
  922. #define VHA_CR_CLK_CTRL0_CNN_IBUF_OFF (IMG_UINT64_C(0000000000000000))
  923. #define VHA_CR_CLK_CTRL0_CNN_IBUF_ON (IMG_UINT64_C(0x0000000400000000))
  924. #define VHA_CR_CLK_CTRL0_CNN_IBUF_AUTO (IMG_UINT64_C(0x0000000800000000))
  925. #define VHA_CR_CLK_CTRL0_CNN_CMD_SHIFT (32U)
  926. #define VHA_CR_CLK_CTRL0_CNN_CMD_CLRMSK (IMG_UINT64_C(0XFFFFFFFCFFFFFFFF))
  927. #define VHA_CR_CLK_CTRL0_CNN_CMD_OFF (IMG_UINT64_C(0000000000000000))
  928. #define VHA_CR_CLK_CTRL0_CNN_CMD_ON (IMG_UINT64_C(0x0000000100000000))
  929. #define VHA_CR_CLK_CTRL0_CNN_CMD_AUTO (IMG_UINT64_C(0x0000000200000000))
  930. #define VHA_CR_CLK_CTRL0_CNN_SHIFT (28U)
  931. #define VHA_CR_CLK_CTRL0_CNN_CLRMSK (IMG_UINT64_C(0XFFFFFFFFCFFFFFFF))
  932. #define VHA_CR_CLK_CTRL0_CNN_OFF (IMG_UINT64_C(0000000000000000))
  933. #define VHA_CR_CLK_CTRL0_CNN_ON (IMG_UINT64_C(0x0000000010000000))
  934. #define VHA_CR_CLK_CTRL0_CNN_AUTO (IMG_UINT64_C(0x0000000020000000))
  935. #define VHA_CR_CLK_CTRL0_SLC_SHIFT (8U)
  936. #define VHA_CR_CLK_CTRL0_SLC_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFCFF))
  937. #define VHA_CR_CLK_CTRL0_SLC_OFF (IMG_UINT64_C(0000000000000000))
  938. #define VHA_CR_CLK_CTRL0_SLC_ON (IMG_UINT64_C(0x0000000000000100))
  939. #define VHA_CR_CLK_CTRL0_SLC_AUTO (IMG_UINT64_C(0x0000000000000200))
  940. #define VHA_CR_CLK_CTRL0_BIF_SHIFT (4U)
  941. #define VHA_CR_CLK_CTRL0_BIF_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFCF))
  942. #define VHA_CR_CLK_CTRL0_BIF_OFF (IMG_UINT64_C(0000000000000000))
  943. #define VHA_CR_CLK_CTRL0_BIF_ON (IMG_UINT64_C(0x0000000000000010))
  944. #define VHA_CR_CLK_CTRL0_BIF_AUTO (IMG_UINT64_C(0x0000000000000020))
  945. /*
  946. Register VHA_CR_VHA_AXI_RESET_CTRL
  947. */
  948. #define VHA_CR_VHA_AXI_RESET_CTRL (0x2008U)
  949. #define VHA_CR_VHA_AXI_RESET_CTRL_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  950. #define VHA_CR_VHA_AXI_RESET_CTRL_SOFT_RESET_CYCLES_SHIFT (0U)
  951. #define VHA_CR_VHA_AXI_RESET_CTRL_SOFT_RESET_CYCLES_CLRMSK (00000000U)
  952. /*
  953. Register VHA_CR_RESET_CTRL
  954. */
  955. #define VHA_CR_RESET_CTRL (0x2010U)
  956. #define VHA_CR_RESET_CTRL_MASKFULL (IMG_UINT64_C(0x00000000C0000107))
  957. #define VHA_CR_RESET_CTRL_VHA_SYS_SOFT_RESET_SHIFT (31U)
  958. #define VHA_CR_RESET_CTRL_VHA_SYS_SOFT_RESET_CLRMSK (0X7FFFFFFFU)
  959. #define VHA_CR_RESET_CTRL_VHA_SYS_SOFT_RESET_EN (0X80000000U)
  960. #define VHA_CR_RESET_CTRL_VHA_AXI_SOFT_RESET_SHIFT (30U)
  961. #define VHA_CR_RESET_CTRL_VHA_AXI_SOFT_RESET_CLRMSK (0XBFFFFFFFU)
  962. #define VHA_CR_RESET_CTRL_VHA_AXI_SOFT_RESET_EN (0X40000000U)
  963. #define VHA_CR_RESET_CTRL_VHA_CNN0_SOFT_RESET_SHIFT (8U)
  964. #define VHA_CR_RESET_CTRL_VHA_CNN0_SOFT_RESET_CLRMSK (0XFFFFFEFFU)
  965. #define VHA_CR_RESET_CTRL_VHA_CNN0_SOFT_RESET_EN (0X00000100U)
  966. #define VHA_CR_RESET_CTRL_VHA_SLC_SOFT_RESET_SHIFT (2U)
  967. #define VHA_CR_RESET_CTRL_VHA_SLC_SOFT_RESET_CLRMSK (0XFFFFFFFBU)
  968. #define VHA_CR_RESET_CTRL_VHA_SLC_SOFT_RESET_EN (0X00000004U)
  969. #define VHA_CR_RESET_CTRL_VHA_BIF_SOFT_RESET_SHIFT (1U)
  970. #define VHA_CR_RESET_CTRL_VHA_BIF_SOFT_RESET_CLRMSK (0XFFFFFFFDU)
  971. #define VHA_CR_RESET_CTRL_VHA_BIF_SOFT_RESET_EN (0X00000002U)
  972. #define VHA_CR_RESET_CTRL_VHA_SOFT_RESET_SHIFT (0U)
  973. #define VHA_CR_RESET_CTRL_VHA_SOFT_RESET_CLRMSK (0XFFFFFFFEU)
  974. #define VHA_CR_RESET_CTRL_VHA_SOFT_RESET_EN (0X00000001U)
  975. /*
  976. Register VHA_CR_CNN_CMD_MH_CONTROL
  977. */
  978. #define VHA_CR_CNN_CMD_MH_CONTROL (0x2018U)
  979. #define VHA_CR_CNN_CMD_MH_CONTROL_MASKFULL (IMG_UINT64_C(0x000000000000003F))
  980. #define VHA_CR_CNN_CMD_MH_CONTROL_MAX_BURST_LENGTH_SHIFT (4U)
  981. #define VHA_CR_CNN_CMD_MH_CONTROL_MAX_BURST_LENGTH_CLRMSK (0XFFFFFFCFU)
  982. #define VHA_CR_CNN_CMD_MH_CONTROL_GPU_PIPE_COHERENT_SHIFT (3U)
  983. #define VHA_CR_CNN_CMD_MH_CONTROL_GPU_PIPE_COHERENT_CLRMSK (0XFFFFFFF7U)
  984. #define VHA_CR_CNN_CMD_MH_CONTROL_GPU_PIPE_COHERENT_EN (0X00000008U)
  985. #define VHA_CR_CNN_CMD_MH_CONTROL_SLC_CACHE_POLICY_SHIFT (2U)
  986. #define VHA_CR_CNN_CMD_MH_CONTROL_SLC_CACHE_POLICY_CLRMSK (0XFFFFFFFBU)
  987. #define VHA_CR_CNN_CMD_MH_CONTROL_SLC_CACHE_POLICY_EN (0X00000004U)
  988. #define VHA_CR_CNN_CMD_MH_CONTROL_PERSISTENCE_SHIFT (0U)
  989. #define VHA_CR_CNN_CMD_MH_CONTROL_PERSISTENCE_CLRMSK (0XFFFFFFFCU)
  990. /*
  991. Register VHA_CR_CNN_IBUF_MH_CONTROL
  992. */
  993. #define VHA_CR_CNN_IBUF_MH_CONTROL (0x2020U)
  994. #define VHA_CR_CNN_IBUF_MH_CONTROL_MASKFULL (IMG_UINT64_C(0x000000000000001F))
  995. #define VHA_CR_CNN_IBUF_MH_CONTROL_MAX_BURST_LENGTH_SHIFT (3U)
  996. #define VHA_CR_CNN_IBUF_MH_CONTROL_MAX_BURST_LENGTH_CLRMSK (0XFFFFFFE7U)
  997. #define VHA_CR_CNN_IBUF_MH_CONTROL_GPU_PIPE_COHERENT_SHIFT (2U)
  998. #define VHA_CR_CNN_IBUF_MH_CONTROL_GPU_PIPE_COHERENT_CLRMSK (0XFFFFFFFBU)
  999. #define VHA_CR_CNN_IBUF_MH_CONTROL_GPU_PIPE_COHERENT_EN (0X00000004U)
  1000. #define VHA_CR_CNN_IBUF_MH_CONTROL_PERSISTENCE_SHIFT (0U)
  1001. #define VHA_CR_CNN_IBUF_MH_CONTROL_PERSISTENCE_CLRMSK (0XFFFFFFFCU)
  1002. /*
  1003. Register VHA_CR_CNN_CBUF_MH_CONTROL
  1004. */
  1005. #define VHA_CR_CNN_CBUF_MH_CONTROL (0x2028U)
  1006. #define VHA_CR_CNN_CBUF_MH_CONTROL_MASKFULL (IMG_UINT64_C(0x000000000000001F))
  1007. #define VHA_CR_CNN_CBUF_MH_CONTROL_MAX_BURST_LENGTH_SHIFT (3U)
  1008. #define VHA_CR_CNN_CBUF_MH_CONTROL_MAX_BURST_LENGTH_CLRMSK (0XFFFFFFE7U)
  1009. #define VHA_CR_CNN_CBUF_MH_CONTROL_GPU_PIPE_COHERENT_SHIFT (2U)
  1010. #define VHA_CR_CNN_CBUF_MH_CONTROL_GPU_PIPE_COHERENT_CLRMSK (0XFFFFFFFBU)
  1011. #define VHA_CR_CNN_CBUF_MH_CONTROL_GPU_PIPE_COHERENT_EN (0X00000004U)
  1012. #define VHA_CR_CNN_CBUF_MH_CONTROL_PERSISTENCE_SHIFT (0U)
  1013. #define VHA_CR_CNN_CBUF_MH_CONTROL_PERSISTENCE_CLRMSK (0XFFFFFFFCU)
  1014. /*
  1015. Register VHA_CR_CNN_ABUF_MH_CONTROL
  1016. */
  1017. #define VHA_CR_CNN_ABUF_MH_CONTROL (0x2030U)
  1018. #define VHA_CR_CNN_ABUF_MH_CONTROL_MASKFULL (IMG_UINT64_C(0x000000000000001F))
  1019. #define VHA_CR_CNN_ABUF_MH_CONTROL_MAX_BURST_LENGTH_SHIFT (3U)
  1020. #define VHA_CR_CNN_ABUF_MH_CONTROL_MAX_BURST_LENGTH_CLRMSK (0XFFFFFFE7U)
  1021. #define VHA_CR_CNN_ABUF_MH_CONTROL_GPU_PIPE_COHERENT_SHIFT (2U)
  1022. #define VHA_CR_CNN_ABUF_MH_CONTROL_GPU_PIPE_COHERENT_CLRMSK (0XFFFFFFFBU)
  1023. #define VHA_CR_CNN_ABUF_MH_CONTROL_GPU_PIPE_COHERENT_EN (0X00000004U)
  1024. #define VHA_CR_CNN_ABUF_MH_CONTROL_PERSISTENCE_SHIFT (0U)
  1025. #define VHA_CR_CNN_ABUF_MH_CONTROL_PERSISTENCE_CLRMSK (0XFFFFFFFCU)
  1026. /*
  1027. Register VHA_CR_CNN_OUTPACK_MH_CONTROL
  1028. */
  1029. #define VHA_CR_CNN_OUTPACK_MH_CONTROL (0x2038U)
  1030. #define VHA_CR_CNN_OUTPACK_MH_CONTROL_MASKFULL (IMG_UINT64_C(0x000000000000001F))
  1031. #define VHA_CR_CNN_OUTPACK_MH_CONTROL_MAX_BURST_LENGTH_SHIFT (3U)
  1032. #define VHA_CR_CNN_OUTPACK_MH_CONTROL_MAX_BURST_LENGTH_CLRMSK (0XFFFFFFE7U)
  1033. #define VHA_CR_CNN_OUTPACK_MH_CONTROL_GPU_PIPE_COHERENT_SHIFT (2U)
  1034. #define VHA_CR_CNN_OUTPACK_MH_CONTROL_GPU_PIPE_COHERENT_CLRMSK (0XFFFFFFFBU)
  1035. #define VHA_CR_CNN_OUTPACK_MH_CONTROL_GPU_PIPE_COHERENT_EN (0X00000004U)
  1036. #define VHA_CR_CNN_OUTPACK_MH_CONTROL_PERSISTENCE_SHIFT (0U)
  1037. #define VHA_CR_CNN_OUTPACK_MH_CONTROL_PERSISTENCE_CLRMSK (0XFFFFFFFCU)
  1038. /*
  1039. Register VHA_CR_CNN_ELEMENTOPS_MH_CONTROL
  1040. */
  1041. #define VHA_CR_CNN_ELEMENTOPS_MH_CONTROL (0x2040U)
  1042. #define VHA_CR_CNN_ELEMENTOPS_MH_CONTROL_MASKFULL (IMG_UINT64_C(0x000000000000001F))
  1043. #define VHA_CR_CNN_ELEMENTOPS_MH_CONTROL_MAX_BURST_LENGTH_SHIFT (3U)
  1044. #define VHA_CR_CNN_ELEMENTOPS_MH_CONTROL_MAX_BURST_LENGTH_CLRMSK (0XFFFFFFE7U)
  1045. #define VHA_CR_CNN_ELEMENTOPS_MH_CONTROL_GPU_PIPE_COHERENT_SHIFT (2U)
  1046. #define VHA_CR_CNN_ELEMENTOPS_MH_CONTROL_GPU_PIPE_COHERENT_CLRMSK (0XFFFFFFFBU)
  1047. #define VHA_CR_CNN_ELEMENTOPS_MH_CONTROL_GPU_PIPE_COHERENT_EN (0X00000004U)
  1048. #define VHA_CR_CNN_ELEMENTOPS_MH_CONTROL_PERSISTENCE_SHIFT (0U)
  1049. #define VHA_CR_CNN_ELEMENTOPS_MH_CONTROL_PERSISTENCE_CLRMSK (0XFFFFFFFCU)
  1050. /*
  1051. Register VHA_CR_CNN_MMM_MH_CONTROL
  1052. */
  1053. #define VHA_CR_CNN_MMM_MH_CONTROL (0x2048U)
  1054. #define VHA_CR_CNN_MMM_MH_CONTROL_MASKFULL (IMG_UINT64_C(0x000000000000001F))
  1055. #define VHA_CR_CNN_MMM_MH_CONTROL_MAX_BURST_LENGTH_SHIFT (3U)
  1056. #define VHA_CR_CNN_MMM_MH_CONTROL_MAX_BURST_LENGTH_CLRMSK (0XFFFFFFE7U)
  1057. #define VHA_CR_CNN_MMM_MH_CONTROL_GPU_PIPE_COHERENT_SHIFT (2U)
  1058. #define VHA_CR_CNN_MMM_MH_CONTROL_GPU_PIPE_COHERENT_CLRMSK (0XFFFFFFFBU)
  1059. #define VHA_CR_CNN_MMM_MH_CONTROL_GPU_PIPE_COHERENT_EN (0X00000004U)
  1060. #define VHA_CR_CNN_MMM_MH_CONTROL_PERSISTENCE_SHIFT (0U)
  1061. #define VHA_CR_CNN_MMM_MH_CONTROL_PERSISTENCE_CLRMSK (0XFFFFFFFCU)
  1062. /*
  1063. Register VHA_CR_PM_VFP_TRAN_EN
  1064. */
  1065. #define VHA_CR_PM_VFP_TRAN_EN (0x2100U)
  1066. #define VHA_CR_PM_VFP_TRAN_EN_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  1067. #define VHA_CR_PM_VFP_TRAN_EN_OP_SHIFT (0U)
  1068. #define VHA_CR_PM_VFP_TRAN_EN_OP_CLRMSK (0XFFFFFFFEU)
  1069. #define VHA_CR_PM_VFP_TRAN_EN_OP_EN (0X00000001U)
  1070. /*
  1071. Register VHA_CR_CNN_MEM_WDT_COMPAREMATCH
  1072. */
  1073. #define VHA_CR_CNN_MEM_WDT_COMPAREMATCH (0x2118U)
  1074. #define VHA_CR_CNN_MEM_WDT_COMPAREMATCH_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  1075. #define VHA_CR_CNN_MEM_WDT_COMPAREMATCH_REG_SHIFT (0U)
  1076. #define VHA_CR_CNN_MEM_WDT_COMPAREMATCH_REG_CLRMSK (00000000U)
  1077. #define VHA_CR_CNN_MEM_WDT_CTRL_CNN_MEM_WDT_CTRL_MASK (0x00000003U)
  1078. /*
  1079. WDT is Disabled */
  1080. #define VHA_CR_CNN_MEM_WDT_CTRL_CNN_MEM_WDT_CTRL_NONE (0x00000000U)
  1081. /*
  1082. WDT is Cleared when CMD Parser starts a pass or CMD parser is kicked*/
  1083. #define VHA_CR_CNN_MEM_WDT_CTRL_CNN_MEM_WDT_CTRL_KICK_PASS (0x00000001U)
  1084. /*
  1085. WDT is Cleared when CMD Parser is kicked */
  1086. #define VHA_CR_CNN_MEM_WDT_CTRL_CNN_MEM_WDT_CTRL_KICK (0x00000002U)
  1087. /*
  1088. Register VHA_CR_CNN_MEM_WDT_CTRL
  1089. */
  1090. #define VHA_CR_CNN_MEM_WDT_CTRL (0x2120U)
  1091. #define VHA_CR_CNN_MEM_WDT_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000000003))
  1092. #define VHA_CR_CNN_MEM_WDT_CTRL_MODE_SHIFT (0U)
  1093. #define VHA_CR_CNN_MEM_WDT_CTRL_MODE_CLRMSK (0XFFFFFFFCU)
  1094. #define VHA_CR_CNN_MEM_WDT_CTRL_MODE_NONE (00000000U)
  1095. #define VHA_CR_CNN_MEM_WDT_CTRL_MODE_KICK_PASS (0X00000001U)
  1096. #define VHA_CR_CNN_MEM_WDT_CTRL_MODE_KICK (0X00000002U)
  1097. #define VHA_CR_CNN_HL_WDT_CTRL_CNN_HL_WDT_CTRL_MASK (0x00000003U)
  1098. /*
  1099. WDT is Cleared when CMD Parser starts a pass or CMD parser is kicked*/
  1100. #define VHA_CR_CNN_HL_WDT_CTRL_CNN_HL_WDT_CTRL_KICK_PASS (0x00000001U)
  1101. /*
  1102. WDT is Cleared when CMD Parser is kicked */
  1103. #define VHA_CR_CNN_HL_WDT_CTRL_CNN_HL_WDT_CTRL_KICK (0x00000002U)
  1104. /*
  1105. Register VHA_CR_CNN_HL_WDT_CTRL
  1106. */
  1107. #define VHA_CR_CNN_HL_WDT_CTRL (0x2128U)
  1108. #define VHA_CR_CNN_HL_WDT_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000000003))
  1109. #define VHA_CR_CNN_HL_WDT_CTRL_MODE_SHIFT (0U)
  1110. #define VHA_CR_CNN_HL_WDT_CTRL_MODE_CLRMSK (0XFFFFFFFCU)
  1111. #define VHA_CR_CNN_HL_WDT_CTRL_MODE_KICK_PASS (0X00000001U)
  1112. #define VHA_CR_CNN_HL_WDT_CTRL_MODE_KICK (0X00000002U)
  1113. /*
  1114. Register VHA_CR_CNN_HL_WDT_COMPAREMATCH
  1115. */
  1116. #define VHA_CR_CNN_HL_WDT_COMPAREMATCH (0x2130U)
  1117. #define VHA_CR_CNN_HL_WDT_COMPAREMATCH_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  1118. #define VHA_CR_CNN_HL_WDT_COMPAREMATCH_REG_SHIFT (0U)
  1119. #define VHA_CR_CNN_HL_WDT_COMPAREMATCH_REG_CLRMSK (00000000U)
  1120. /*
  1121. Register VHA_CR_IDLE_HYSTERESIS_COUNT
  1122. */
  1123. #define VHA_CR_IDLE_HYSTERESIS_COUNT (0x2140U)
  1124. #define VHA_CR_IDLE_HYSTERESIS_COUNT_MASKFULL (IMG_UINT64_C(0x0000001F00001F1F))
  1125. #define VHA_CR_IDLE_HYSTERESIS_COUNT_VHA_SYS_SHIFT (32U)
  1126. #define VHA_CR_IDLE_HYSTERESIS_COUNT_VHA_SYS_CLRMSK (IMG_UINT64_C(0XFFFFFFE0FFFFFFFF))
  1127. #define VHA_CR_IDLE_HYSTERESIS_COUNT_CNN_TOP_SHIFT (8U)
  1128. #define VHA_CR_IDLE_HYSTERESIS_COUNT_CNN_TOP_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFE0FF))
  1129. #define VHA_CR_IDLE_HYSTERESIS_COUNT_VHA_CTRL_SHIFT (0U)
  1130. #define VHA_CR_IDLE_HYSTERESIS_COUNT_VHA_CTRL_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFE0))
  1131. /*
  1132. Register VHA_CR_SOCIF_WAKEUP_ENABLE
  1133. */
  1134. #define VHA_CR_SOCIF_WAKEUP_ENABLE (0x2148U)
  1135. #define VHA_CR_SOCIF_WAKEUP_ENABLE_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  1136. #define VHA_CR_SOCIF_WAKEUP_ENABLE_ALWAYS_SHIFT (0U)
  1137. #define VHA_CR_SOCIF_WAKEUP_ENABLE_ALWAYS_CLRMSK (0XFFFFFFFEU)
  1138. #define VHA_CR_SOCIF_WAKEUP_ENABLE_ALWAYS_EN (0X00000001U)
  1139. /*
  1140. Register VHA_CR_RESET_CLK_CTRL
  1141. */
  1142. #define VHA_CR_RESET_CLK_CTRL (0x2150U)
  1143. #define VHA_CR_RESET_CLK_CTRL_MASKFULL (IMG_UINT64_C(0x00000000000003FF))
  1144. #define VHA_CR_RESET_CLK_CTRL_VHA_SYS_SHIFT (8U)
  1145. #define VHA_CR_RESET_CLK_CTRL_VHA_SYS_CLRMSK (0XFFFFFCFFU)
  1146. #define VHA_CR_RESET_CLK_CTRL_CNN_FE_SHIFT (6U)
  1147. #define VHA_CR_RESET_CLK_CTRL_CNN_FE_CLRMSK (0XFFFFFF3FU)
  1148. #define VHA_CR_RESET_CLK_CTRL_CNN_BE_SHIFT (4U)
  1149. #define VHA_CR_RESET_CLK_CTRL_CNN_BE_CLRMSK (0XFFFFFFCFU)
  1150. #define VHA_CR_RESET_CLK_CTRL_CNN_TOP_SHIFT (2U)
  1151. #define VHA_CR_RESET_CLK_CTRL_CNN_TOP_CLRMSK (0XFFFFFFF3U)
  1152. #define VHA_CR_RESET_CLK_CTRL_VHA_CTRL_SHIFT (0U)
  1153. #define VHA_CR_RESET_CLK_CTRL_VHA_CTRL_CLRMSK (0XFFFFFFFCU)
  1154. #define VHA_CR_SYS_CLK_CTRL0_MODE_MASK (0x00000003U)
  1155. /*
  1156. The domain clock is forced off */
  1157. #define VHA_CR_SYS_CLK_CTRL0_MODE_OFF (0x00000000U)
  1158. /*
  1159. The domain clock is forced on */
  1160. #define VHA_CR_SYS_CLK_CTRL0_MODE_ON (0x00000001U)
  1161. /*
  1162. Automatic clock gating is active, the domain clock is only on whilst data is being processed */
  1163. #define VHA_CR_SYS_CLK_CTRL0_MODE_AUTO (0x00000002U)
  1164. /*
  1165. Register VHA_CR_SYS_CLK_CTRL0
  1166. */
  1167. #define VHA_CR_SYS_CLK_CTRL0 (0x2158U)
  1168. #define VHA_CR_SYS_CLK_CTRL0_MASKFULL (IMG_UINT64_C(0x0000000000000030))
  1169. #define VHA_CR_SYS_CLK_CTRL0_SLC_SHIFT (4U)
  1170. #define VHA_CR_SYS_CLK_CTRL0_SLC_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFCF))
  1171. #define VHA_CR_SYS_CLK_CTRL0_SLC_OFF (IMG_UINT64_C(0000000000000000))
  1172. #define VHA_CR_SYS_CLK_CTRL0_SLC_ON (IMG_UINT64_C(0x0000000000000010))
  1173. #define VHA_CR_SYS_CLK_CTRL0_SLC_AUTO (IMG_UINT64_C(0x0000000000000020))
  1174. /*
  1175. Register VHA_CR_AXI_EXACCESS
  1176. */
  1177. #define VHA_CR_AXI_EXACCESS (0x2168U)
  1178. #define VHA_CR_AXI_EXACCESS_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  1179. #define VHA_CR_AXI_EXACCESS_SOCIF_ENABLE_SHIFT (0U)
  1180. #define VHA_CR_AXI_EXACCESS_SOCIF_ENABLE_CLRMSK (0XFFFFFFFEU)
  1181. #define VHA_CR_AXI_EXACCESS_SOCIF_ENABLE_EN (0X00000001U)
  1182. /*
  1183. Register VHA_CR_REGBANK_REQUEST_INVALID
  1184. */
  1185. #define VHA_CR_REGBANK_REQUEST_INVALID (0x2170U)
  1186. #define VHA_CR_REGBANK_REQUEST_INVALID_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  1187. #define VHA_CR_REGBANK_REQUEST_INVALID_FLAG_SHIFT (0U)
  1188. #define VHA_CR_REGBANK_REQUEST_INVALID_FLAG_CLRMSK (0XFFFFFFFEU)
  1189. #define VHA_CR_REGBANK_REQUEST_INVALID_FLAG_EN (0X00000001U)
  1190. /*
  1191. Register VHA_CR_CNN_CMD_PRIORITY_LIMITS_LEGACY
  1192. */
  1193. #define VHA_CR_CNN_CMD_PRIORITY_LIMITS_LEGACY (0x2180U)
  1194. #define VHA_CR_CNN_CMD_PRIORITY_LIMITS_LEGACY_MASKFULL (IMG_UINT64_C(0x000000000000019B))
  1195. #define VHA_CR_CNN_CMD_PRIORITY_LIMITS_LEGACY_OS2_LIMIT_SHIFT (7U)
  1196. #define VHA_CR_CNN_CMD_PRIORITY_LIMITS_LEGACY_OS2_LIMIT_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFE7F))
  1197. #define VHA_CR_CNN_CMD_PRIORITY_LIMITS_LEGACY_OS1_LIMIT_SHIFT (3U)
  1198. #define VHA_CR_CNN_CMD_PRIORITY_LIMITS_LEGACY_OS1_LIMIT_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFE7))
  1199. #define VHA_CR_CNN_CMD_PRIORITY_LIMITS_LEGACY_OS0_LIMIT_SHIFT (0U)
  1200. #define VHA_CR_CNN_CMD_PRIORITY_LIMITS_LEGACY_OS0_LIMIT_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFC))
  1201. /*
  1202. Register VHA_CR_VHA_CNN_CMD_SECURITY_CONTROL
  1203. */
  1204. #define VHA_CR_VHA_CNN_CMD_SECURITY_CONTROL (0x2188U)
  1205. #define VHA_CR_VHA_CNN_CMD_SECURITY_CONTROL_MASKFULL (IMG_UINT64_C(0x0000000000000007))
  1206. #define VHA_CR_VHA_CNN_CMD_SECURITY_CONTROL_FORCE_DISABLE_CRC_SHIFT (2U)
  1207. #define VHA_CR_VHA_CNN_CMD_SECURITY_CONTROL_FORCE_DISABLE_CRC_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFB))
  1208. #define VHA_CR_VHA_CNN_CMD_SECURITY_CONTROL_FORCE_DISABLE_CRC_EN (IMG_UINT64_C(0X0000000000000004))
  1209. #define VHA_CR_VHA_CNN_CMD_SECURITY_CONTROL_RAM_SCRUB_ON_SWITCH_SHIFT (1U)
  1210. #define VHA_CR_VHA_CNN_CMD_SECURITY_CONTROL_RAM_SCRUB_ON_SWITCH_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFD))
  1211. #define VHA_CR_VHA_CNN_CMD_SECURITY_CONTROL_RAM_SCRUB_ON_SWITCH_EN (IMG_UINT64_C(0X0000000000000002))
  1212. #define VHA_CR_VHA_CNN_CMD_SECURITY_CONTROL_FORCE_RAM_SCRUB_SHIFT (0U)
  1213. #define VHA_CR_VHA_CNN_CMD_SECURITY_CONTROL_FORCE_RAM_SCRUB_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  1214. #define VHA_CR_VHA_CNN_CMD_SECURITY_CONTROL_FORCE_RAM_SCRUB_EN (IMG_UINT64_C(0X0000000000000001))
  1215. /*
  1216. Register VHA_CR_CNN_ARB_STALL_RATIO
  1217. */
  1218. #define VHA_CR_CNN_ARB_STALL_RATIO (0x2200U)
  1219. #define VHA_CR_CNN_ARB_STALL_RATIO_MASKFULL (IMG_UINT64_C(0x0000000FFFFFFFFF))
  1220. #define VHA_CR_CNN_ARB_STALL_RATIO_OUTPUT_SHIFT (32U)
  1221. #define VHA_CR_CNN_ARB_STALL_RATIO_OUTPUT_CLRMSK (IMG_UINT64_C(0XFFFFFFF0FFFFFFFF))
  1222. #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_8_SHIFT (28U)
  1223. #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_8_CLRMSK (IMG_UINT64_C(0XFFFFFFFF0FFFFFFF))
  1224. #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_7_SHIFT (24U)
  1225. #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_7_CLRMSK (IMG_UINT64_C(0XFFFFFFFFF0FFFFFF))
  1226. #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_6_SHIFT (20U)
  1227. #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_6_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF0FFFFF))
  1228. #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_5_SHIFT (16U)
  1229. #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_5_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF0FFFF))
  1230. #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_4_SHIFT (12U)
  1231. #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_4_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF0FFF))
  1232. #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_3_SHIFT (8U)
  1233. #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_3_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF0FF))
  1234. #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_2_SHIFT (4U)
  1235. #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_2_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFF0F))
  1236. #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_1_SHIFT (0U)
  1237. #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF0))
  1238. /*
  1239. Register VHA_CR_CNN_DATAPATH_STALL_RATIO_FE
  1240. */
  1241. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_FE (0x2208U)
  1242. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_FE_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  1243. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_FE_CNV_ABUF_SHIFT (28U)
  1244. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_FE_CNV_ABUF_CLRMSK (0X0FFFFFFFU)
  1245. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_FE_IBUF_CNV_SHIFT (24U)
  1246. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_FE_IBUF_CNV_CLRMSK (0XF0FFFFFFU)
  1247. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_FE_ABUF_ACT_SHIFT (20U)
  1248. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_FE_ABUF_ACT_CLRMSK (0XFF0FFFFFU)
  1249. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_FE_ACT_NORM_SHIFT (16U)
  1250. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_FE_ACT_NORM_CLRMSK (0XFFF0FFFFU)
  1251. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_FE_IBUF_NORM_SHIFT (12U)
  1252. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_FE_IBUF_NORM_CLRMSK (0XFFFF0FFFU)
  1253. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_FE_CBUF_CNV_SHIFT (8U)
  1254. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_FE_CBUF_CNV_CLRMSK (0XFFFFF0FFU)
  1255. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_FE_ABUF_OUTPACK_SHIFT (4U)
  1256. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_FE_ABUF_OUTPACK_CLRMSK (0XFFFFFF0FU)
  1257. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_FE_CBUF_ABUF_SHIFT (0U)
  1258. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_FE_CBUF_ABUF_CLRMSK (0XFFFFFFF0U)
  1259. /*
  1260. Register VHA_CR_CNN_DATAPATH_STALL_RATIO_BE
  1261. */
  1262. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_BE (0x2210U)
  1263. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_BE_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  1264. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_BE_NORM_XBAR_SHIFT (28U)
  1265. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_BE_NORM_XBAR_CLRMSK (0X0FFFFFFFU)
  1266. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_BE_XBAR_OIN_SHIFT (24U)
  1267. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_BE_XBAR_OIN_CLRMSK (0XF0FFFFFFU)
  1268. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_BE_OIN_OUTPACK_SHIFT (20U)
  1269. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_BE_OIN_OUTPACK_CLRMSK (0XFF0FFFFFU)
  1270. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_BE_POOL_XBAR_SHIFT (16U)
  1271. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_BE_POOL_XBAR_CLRMSK (0XFFF0FFFFU)
  1272. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_BE_XBAR_POOL_SHIFT (12U)
  1273. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_BE_XBAR_POOL_CLRMSK (0XFFFF0FFFU)
  1274. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_BE_NORM_SB_SHIFT (8U)
  1275. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_BE_NORM_SB_CLRMSK (0XFFFFF0FFU)
  1276. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_BE_POOL_SB_SHIFT (4U)
  1277. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_BE_POOL_SB_CLRMSK (0XFFFFFF0FU)
  1278. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_BE_OIN_SB_SHIFT (0U)
  1279. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_BE_OIN_SB_CLRMSK (0XFFFFFFF0U)
  1280. /*
  1281. Register VHA_CR_CNN_ARB_MAX_PAGE
  1282. */
  1283. #define VHA_CR_CNN_ARB_MAX_PAGE (0x2218U)
  1284. #define VHA_CR_CNN_ARB_MAX_PAGE_MASKFULL (IMG_UINT64_C(0x0000000000000007))
  1285. #define VHA_CR_CNN_ARB_MAX_PAGE_MAX_PAGE_COUNT_MIN1_SHIFT (0U)
  1286. #define VHA_CR_CNN_ARB_MAX_PAGE_MAX_PAGE_COUNT_MIN1_CLRMSK (0XFFFFFFF8U)
  1287. /*
  1288. Register VHA_CR_PERF_SLC_SNOOP_HITS
  1289. */
  1290. #define VHA_CR_PERF_SLC_SNOOP_HITS (0x61A0U)
  1291. #define VHA_CR_PERF_SLC_SNOOP_HITS_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  1292. #define VHA_CR_PERF_SLC_SNOOP_HITS_COUNT_SHIFT (0U)
  1293. #define VHA_CR_PERF_SLC_SNOOP_HITS_COUNT_CLRMSK (00000000U)
  1294. /*
  1295. Register VHA_CR_PERF_SLC_SNOOP_MISSES
  1296. */
  1297. #define VHA_CR_PERF_SLC_SNOOP_MISSES (0x61A8U)
  1298. #define VHA_CR_PERF_SLC_SNOOP_MISSES_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  1299. #define VHA_CR_PERF_SLC_SNOOP_MISSES_COUNT_SHIFT (0U)
  1300. #define VHA_CR_PERF_SLC_SNOOP_MISSES_COUNT_CLRMSK (00000000U)
  1301. /*
  1302. Register VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0
  1303. */
  1304. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0 (0xE008U)
  1305. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0_MASKFULL (IMG_UINT64_C(0x0FFFFFFFFFFFF001))
  1306. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0_INIT_PAGE_SHIFT (40U)
  1307. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0_INIT_PAGE_CLRMSK (IMG_UINT64_C(0XF00000FFFFFFFFFF))
  1308. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0_ADDR_SHIFT (12U)
  1309. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000FFF))
  1310. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0_VALID_SHIFT (0U)
  1311. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0_VALID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  1312. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0_VALID_EN (IMG_UINT64_C(0X0000000000000001))
  1313. /*
  1314. Register VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE1
  1315. */
  1316. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE1 (0xE010U)
  1317. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE1_MASKFULL (IMG_UINT64_C(0x00000003FFFFC001))
  1318. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE1_INIT_PAGE_SHIFT (14U)
  1319. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE1_INIT_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1320. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE1_VALID_SHIFT (0U)
  1321. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE1_VALID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  1322. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE1_VALID_EN (IMG_UINT64_C(0X0000000000000001))
  1323. /*
  1324. Register VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE2
  1325. */
  1326. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE2 (0xE018U)
  1327. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE2_MASKFULL (IMG_UINT64_C(0x00000003FFFFC001))
  1328. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE2_INIT_PAGE_SHIFT (14U)
  1329. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE2_INIT_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1330. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE2_VALID_SHIFT (0U)
  1331. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE2_VALID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  1332. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE2_VALID_EN (IMG_UINT64_C(0X0000000000000001))
  1333. /*
  1334. Register VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE3
  1335. */
  1336. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE3 (0xE020U)
  1337. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE3_MASKFULL (IMG_UINT64_C(0x00000003FFFFC001))
  1338. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE3_INIT_PAGE_SHIFT (14U)
  1339. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE3_INIT_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1340. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE3_VALID_SHIFT (0U)
  1341. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE3_VALID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  1342. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE3_VALID_EN (IMG_UINT64_C(0X0000000000000001))
  1343. /*
  1344. Register VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0
  1345. */
  1346. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0 (0xE028U)
  1347. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0_MASKFULL (IMG_UINT64_C(0x0FFFFFFFFFFFF001))
  1348. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0_INIT_PAGE_SHIFT (40U)
  1349. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0_INIT_PAGE_CLRMSK (IMG_UINT64_C(0XF00000FFFFFFFFFF))
  1350. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0_ADDR_SHIFT (12U)
  1351. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000FFF))
  1352. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0_VALID_SHIFT (0U)
  1353. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0_VALID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  1354. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0_VALID_EN (IMG_UINT64_C(0X0000000000000001))
  1355. /*
  1356. Register VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE1
  1357. */
  1358. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE1 (0xE030U)
  1359. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE1_MASKFULL (IMG_UINT64_C(0x00000003FFFFC001))
  1360. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE1_INIT_PAGE_SHIFT (14U)
  1361. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE1_INIT_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1362. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE1_VALID_SHIFT (0U)
  1363. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE1_VALID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  1364. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE1_VALID_EN (IMG_UINT64_C(0X0000000000000001))
  1365. /*
  1366. Register VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE2
  1367. */
  1368. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE2 (0xE038U)
  1369. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE2_MASKFULL (IMG_UINT64_C(0x00000003FFFFC001))
  1370. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE2_INIT_PAGE_SHIFT (14U)
  1371. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE2_INIT_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1372. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE2_VALID_SHIFT (0U)
  1373. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE2_VALID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  1374. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE2_VALID_EN (IMG_UINT64_C(0X0000000000000001))
  1375. /*
  1376. Register VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE3
  1377. */
  1378. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE3 (0xE040U)
  1379. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE3_MASKFULL (IMG_UINT64_C(0x00000003FFFFC001))
  1380. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE3_INIT_PAGE_SHIFT (14U)
  1381. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE3_INIT_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1382. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE3_VALID_SHIFT (0U)
  1383. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE3_VALID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  1384. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE3_VALID_EN (IMG_UINT64_C(0X0000000000000001))
  1385. /*
  1386. Register VHA_CR_MMU_PM_CAT_BASE_ALIST0
  1387. */
  1388. #define VHA_CR_MMU_PM_CAT_BASE_ALIST0 (0xE048U)
  1389. #define VHA_CR_MMU_PM_CAT_BASE_ALIST0_MASKFULL (IMG_UINT64_C(0x0FFFFFFFFFFFF001))
  1390. #define VHA_CR_MMU_PM_CAT_BASE_ALIST0_INIT_PAGE_SHIFT (40U)
  1391. #define VHA_CR_MMU_PM_CAT_BASE_ALIST0_INIT_PAGE_CLRMSK (IMG_UINT64_C(0XF00000FFFFFFFFFF))
  1392. #define VHA_CR_MMU_PM_CAT_BASE_ALIST0_ADDR_SHIFT (12U)
  1393. #define VHA_CR_MMU_PM_CAT_BASE_ALIST0_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000FFF))
  1394. #define VHA_CR_MMU_PM_CAT_BASE_ALIST0_VALID_SHIFT (0U)
  1395. #define VHA_CR_MMU_PM_CAT_BASE_ALIST0_VALID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  1396. #define VHA_CR_MMU_PM_CAT_BASE_ALIST0_VALID_EN (IMG_UINT64_C(0X0000000000000001))
  1397. /*
  1398. Register VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0
  1399. */
  1400. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0 (0xE050U)
  1401. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0_MASKFULL (IMG_UINT64_C(0x0FFFFFFFFFFFF001))
  1402. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0_INIT_PAGE_SHIFT (40U)
  1403. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0_INIT_PAGE_CLRMSK (IMG_UINT64_C(0XF00000FFFFFFFFFF))
  1404. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0_ADDR_SHIFT (12U)
  1405. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000FFF))
  1406. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0_VALID_SHIFT (0U)
  1407. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0_VALID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  1408. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0_VALID_EN (IMG_UINT64_C(0X0000000000000001))
  1409. /*
  1410. Register VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE1
  1411. */
  1412. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE1 (0xE058U)
  1413. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE1_MASKFULL (IMG_UINT64_C(0x00000003FFFFC001))
  1414. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE1_INIT_PAGE_SHIFT (14U)
  1415. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE1_INIT_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1416. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE1_VALID_SHIFT (0U)
  1417. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE1_VALID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  1418. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE1_VALID_EN (IMG_UINT64_C(0X0000000000000001))
  1419. /*
  1420. Register VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE2
  1421. */
  1422. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE2 (0xE060U)
  1423. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE2_MASKFULL (IMG_UINT64_C(0x00000003FFFFC001))
  1424. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE2_INIT_PAGE_SHIFT (14U)
  1425. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE2_INIT_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1426. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE2_VALID_SHIFT (0U)
  1427. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE2_VALID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  1428. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE2_VALID_EN (IMG_UINT64_C(0X0000000000000001))
  1429. /*
  1430. Register VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE3
  1431. */
  1432. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE3 (0xE068U)
  1433. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE3_MASKFULL (IMG_UINT64_C(0x00000003FFFFC001))
  1434. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE3_INIT_PAGE_SHIFT (14U)
  1435. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE3_INIT_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1436. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE3_VALID_SHIFT (0U)
  1437. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE3_VALID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  1438. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE3_VALID_EN (IMG_UINT64_C(0X0000000000000001))
  1439. /*
  1440. Register VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0
  1441. */
  1442. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0 (0xE070U)
  1443. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0_MASKFULL (IMG_UINT64_C(0x0FFFFFFFFFFFF001))
  1444. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0_INIT_PAGE_SHIFT (40U)
  1445. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0_INIT_PAGE_CLRMSK (IMG_UINT64_C(0XF00000FFFFFFFFFF))
  1446. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0_ADDR_SHIFT (12U)
  1447. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000FFF))
  1448. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0_VALID_SHIFT (0U)
  1449. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0_VALID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  1450. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0_VALID_EN (IMG_UINT64_C(0X0000000000000001))
  1451. /*
  1452. Register VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE1
  1453. */
  1454. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE1 (0xE078U)
  1455. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE1_MASKFULL (IMG_UINT64_C(0x00000003FFFFC001))
  1456. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE1_INIT_PAGE_SHIFT (14U)
  1457. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE1_INIT_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1458. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE1_VALID_SHIFT (0U)
  1459. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE1_VALID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  1460. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE1_VALID_EN (IMG_UINT64_C(0X0000000000000001))
  1461. /*
  1462. Register VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE2
  1463. */
  1464. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE2 (0xE080U)
  1465. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE2_MASKFULL (IMG_UINT64_C(0x00000003FFFFC001))
  1466. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE2_INIT_PAGE_SHIFT (14U)
  1467. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE2_INIT_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1468. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE2_VALID_SHIFT (0U)
  1469. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE2_VALID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  1470. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE2_VALID_EN (IMG_UINT64_C(0X0000000000000001))
  1471. /*
  1472. Register VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE3
  1473. */
  1474. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE3 (0xE088U)
  1475. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE3_MASKFULL (IMG_UINT64_C(0x00000003FFFFC001))
  1476. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE3_INIT_PAGE_SHIFT (14U)
  1477. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE3_INIT_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1478. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE3_VALID_SHIFT (0U)
  1479. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE3_VALID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  1480. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE3_VALID_EN (IMG_UINT64_C(0X0000000000000001))
  1481. /*
  1482. Register VHA_CR_MMU_PM_CAT_BASE_ALIST1
  1483. */
  1484. #define VHA_CR_MMU_PM_CAT_BASE_ALIST1 (0xE090U)
  1485. #define VHA_CR_MMU_PM_CAT_BASE_ALIST1_MASKFULL (IMG_UINT64_C(0x0FFFFFFFFFFFF001))
  1486. #define VHA_CR_MMU_PM_CAT_BASE_ALIST1_INIT_PAGE_SHIFT (40U)
  1487. #define VHA_CR_MMU_PM_CAT_BASE_ALIST1_INIT_PAGE_CLRMSK (IMG_UINT64_C(0XF00000FFFFFFFFFF))
  1488. #define VHA_CR_MMU_PM_CAT_BASE_ALIST1_ADDR_SHIFT (12U)
  1489. #define VHA_CR_MMU_PM_CAT_BASE_ALIST1_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000FFF))
  1490. #define VHA_CR_MMU_PM_CAT_BASE_ALIST1_VALID_SHIFT (0U)
  1491. #define VHA_CR_MMU_PM_CAT_BASE_ALIST1_VALID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  1492. #define VHA_CR_MMU_PM_CAT_BASE_ALIST1_VALID_EN (IMG_UINT64_C(0X0000000000000001))
  1493. /*
  1494. Register VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0_LAST
  1495. */
  1496. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0_LAST (0xE098U)
  1497. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0_LAST_MASKFULL (IMG_UINT64_C(0x00000003FFFFC000))
  1498. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0_LAST_PAGE_SHIFT (14U)
  1499. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0_LAST_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1500. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0_LAST_PAGE_ALIGNSHIFT (14U)
  1501. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0_LAST_PAGE_ALIGNSIZE (16384U)
  1502. /*
  1503. Register VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE1_LAST
  1504. */
  1505. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE1_LAST (0xE0A0U)
  1506. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE1_LAST_MASKFULL (IMG_UINT64_C(0x00000003FFFFC000))
  1507. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE1_LAST_PAGE_SHIFT (14U)
  1508. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE1_LAST_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1509. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE1_LAST_PAGE_ALIGNSHIFT (14U)
  1510. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE1_LAST_PAGE_ALIGNSIZE (16384U)
  1511. /*
  1512. Register VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE2_LAST
  1513. */
  1514. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE2_LAST (0xE0A8U)
  1515. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE2_LAST_MASKFULL (IMG_UINT64_C(0x00000003FFFFC000))
  1516. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE2_LAST_PAGE_SHIFT (14U)
  1517. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE2_LAST_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1518. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE2_LAST_PAGE_ALIGNSHIFT (14U)
  1519. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE2_LAST_PAGE_ALIGNSIZE (16384U)
  1520. /*
  1521. Register VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE3_LAST
  1522. */
  1523. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE3_LAST (0xE0B0U)
  1524. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE3_LAST_MASKFULL (IMG_UINT64_C(0x00000003FFFFC000))
  1525. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE3_LAST_PAGE_SHIFT (14U)
  1526. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE3_LAST_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1527. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE3_LAST_PAGE_ALIGNSHIFT (14U)
  1528. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE3_LAST_PAGE_ALIGNSIZE (16384U)
  1529. /*
  1530. Register VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0_LAST
  1531. */
  1532. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0_LAST (0xE0B8U)
  1533. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0_LAST_MASKFULL (IMG_UINT64_C(0x00000003FFFFC000))
  1534. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0_LAST_PAGE_SHIFT (14U)
  1535. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0_LAST_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1536. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0_LAST_PAGE_ALIGNSHIFT (14U)
  1537. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0_LAST_PAGE_ALIGNSIZE (16384U)
  1538. /*
  1539. Register VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE1_LAST
  1540. */
  1541. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE1_LAST (0xE0C0U)
  1542. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE1_LAST_MASKFULL (IMG_UINT64_C(0x00000003FFFFC000))
  1543. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE1_LAST_PAGE_SHIFT (14U)
  1544. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE1_LAST_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1545. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE1_LAST_PAGE_ALIGNSHIFT (14U)
  1546. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE1_LAST_PAGE_ALIGNSIZE (16384U)
  1547. /*
  1548. Register VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE2_LAST
  1549. */
  1550. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE2_LAST (0xE0C8U)
  1551. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE2_LAST_MASKFULL (IMG_UINT64_C(0x00000003FFFFC000))
  1552. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE2_LAST_PAGE_SHIFT (14U)
  1553. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE2_LAST_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1554. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE2_LAST_PAGE_ALIGNSHIFT (14U)
  1555. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE2_LAST_PAGE_ALIGNSIZE (16384U)
  1556. /*
  1557. Register VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE3_LAST
  1558. */
  1559. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE3_LAST (0xE0D0U)
  1560. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE3_LAST_MASKFULL (IMG_UINT64_C(0x00000003FFFFC000))
  1561. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE3_LAST_PAGE_SHIFT (14U)
  1562. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE3_LAST_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1563. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE3_LAST_PAGE_ALIGNSHIFT (14U)
  1564. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE3_LAST_PAGE_ALIGNSIZE (16384U)
  1565. /*
  1566. Register VHA_CR_MMU_PM_CAT_BASE_ALIST0_LAST
  1567. */
  1568. #define VHA_CR_MMU_PM_CAT_BASE_ALIST0_LAST (0xE0D8U)
  1569. #define VHA_CR_MMU_PM_CAT_BASE_ALIST0_LAST_MASKFULL (IMG_UINT64_C(0x00000003FFFFC000))
  1570. #define VHA_CR_MMU_PM_CAT_BASE_ALIST0_LAST_PAGE_SHIFT (14U)
  1571. #define VHA_CR_MMU_PM_CAT_BASE_ALIST0_LAST_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1572. #define VHA_CR_MMU_PM_CAT_BASE_ALIST0_LAST_PAGE_ALIGNSHIFT (14U)
  1573. #define VHA_CR_MMU_PM_CAT_BASE_ALIST0_LAST_PAGE_ALIGNSIZE (16384U)
  1574. /*
  1575. Register VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0_LAST
  1576. */
  1577. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0_LAST (0xE0E0U)
  1578. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0_LAST_MASKFULL (IMG_UINT64_C(0x00000003FFFFC000))
  1579. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0_LAST_PAGE_SHIFT (14U)
  1580. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0_LAST_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1581. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0_LAST_PAGE_ALIGNSHIFT (14U)
  1582. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0_LAST_PAGE_ALIGNSIZE (16384U)
  1583. /*
  1584. Register VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE1_LAST
  1585. */
  1586. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE1_LAST (0xE0E8U)
  1587. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE1_LAST_MASKFULL (IMG_UINT64_C(0x00000003FFFFC000))
  1588. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE1_LAST_PAGE_SHIFT (14U)
  1589. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE1_LAST_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1590. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE1_LAST_PAGE_ALIGNSHIFT (14U)
  1591. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE1_LAST_PAGE_ALIGNSIZE (16384U)
  1592. /*
  1593. Register VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE2_LAST
  1594. */
  1595. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE2_LAST (0xE0F0U)
  1596. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE2_LAST_MASKFULL (IMG_UINT64_C(0x00000003FFFFC000))
  1597. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE2_LAST_PAGE_SHIFT (14U)
  1598. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE2_LAST_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1599. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE2_LAST_PAGE_ALIGNSHIFT (14U)
  1600. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE2_LAST_PAGE_ALIGNSIZE (16384U)
  1601. /*
  1602. Register VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE3_LAST
  1603. */
  1604. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE3_LAST (0xE0F8U)
  1605. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE3_LAST_MASKFULL (IMG_UINT64_C(0x00000003FFFFC000))
  1606. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE3_LAST_PAGE_SHIFT (14U)
  1607. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE3_LAST_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1608. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE3_LAST_PAGE_ALIGNSHIFT (14U)
  1609. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE3_LAST_PAGE_ALIGNSIZE (16384U)
  1610. /*
  1611. Register VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0_LAST
  1612. */
  1613. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0_LAST (0xE100U)
  1614. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0_LAST_MASKFULL (IMG_UINT64_C(0x00000003FFFFC000))
  1615. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0_LAST_PAGE_SHIFT (14U)
  1616. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0_LAST_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1617. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0_LAST_PAGE_ALIGNSHIFT (14U)
  1618. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0_LAST_PAGE_ALIGNSIZE (16384U)
  1619. /*
  1620. Register VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE1_LAST
  1621. */
  1622. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE1_LAST (0xE108U)
  1623. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE1_LAST_MASKFULL (IMG_UINT64_C(0x00000003FFFFC000))
  1624. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE1_LAST_PAGE_SHIFT (14U)
  1625. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE1_LAST_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1626. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE1_LAST_PAGE_ALIGNSHIFT (14U)
  1627. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE1_LAST_PAGE_ALIGNSIZE (16384U)
  1628. /*
  1629. Register VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE2_LAST
  1630. */
  1631. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE2_LAST (0xE110U)
  1632. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE2_LAST_MASKFULL (IMG_UINT64_C(0x00000003FFFFC000))
  1633. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE2_LAST_PAGE_SHIFT (14U)
  1634. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE2_LAST_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1635. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE2_LAST_PAGE_ALIGNSHIFT (14U)
  1636. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE2_LAST_PAGE_ALIGNSIZE (16384U)
  1637. /*
  1638. Register VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE3_LAST
  1639. */
  1640. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE3_LAST (0xE118U)
  1641. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE3_LAST_MASKFULL (IMG_UINT64_C(0x00000003FFFFC000))
  1642. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE3_LAST_PAGE_SHIFT (14U)
  1643. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE3_LAST_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1644. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE3_LAST_PAGE_ALIGNSHIFT (14U)
  1645. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE3_LAST_PAGE_ALIGNSIZE (16384U)
  1646. /*
  1647. Register VHA_CR_MMU_PM_CAT_BASE_ALIST1_LAST
  1648. */
  1649. #define VHA_CR_MMU_PM_CAT_BASE_ALIST1_LAST (0xE120U)
  1650. #define VHA_CR_MMU_PM_CAT_BASE_ALIST1_LAST_MASKFULL (IMG_UINT64_C(0x00000003FFFFC000))
  1651. #define VHA_CR_MMU_PM_CAT_BASE_ALIST1_LAST_PAGE_SHIFT (14U)
  1652. #define VHA_CR_MMU_PM_CAT_BASE_ALIST1_LAST_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1653. #define VHA_CR_MMU_PM_CAT_BASE_ALIST1_LAST_PAGE_ALIGNSHIFT (14U)
  1654. #define VHA_CR_MMU_PM_CAT_BASE_ALIST1_LAST_PAGE_ALIGNSIZE (16384U)
  1655. /*
  1656. Register VHA_CR_MMU_FAULT_STATUS_META
  1657. */
  1658. #define VHA_CR_MMU_FAULT_STATUS_META (0xE160U)
  1659. #define VHA_CR_MMU_FAULT_STATUS_META_MASKFULL (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
  1660. #define VHA_CR_MMU_FAULT_STATUS_META_LEVEL_SHIFT (62U)
  1661. #define VHA_CR_MMU_FAULT_STATUS_META_LEVEL_CLRMSK (IMG_UINT64_C(0X3FFFFFFFFFFFFFFF))
  1662. #define VHA_CR_MMU_FAULT_STATUS_META_REQ_ID_SHIFT (56U)
  1663. #define VHA_CR_MMU_FAULT_STATUS_META_REQ_ID_CLRMSK (IMG_UINT64_C(0XC0FFFFFFFFFFFFFF))
  1664. #define VHA_CR_MMU_FAULT_STATUS_META_CONTEXT_SHIFT (48U)
  1665. #define VHA_CR_MMU_FAULT_STATUS_META_CONTEXT_CLRMSK (IMG_UINT64_C(0XFF00FFFFFFFFFFFF))
  1666. #define VHA_CR_MMU_FAULT_STATUS_META_ADDRESS_SHIFT (4U)
  1667. #define VHA_CR_MMU_FAULT_STATUS_META_ADDRESS_CLRMSK (IMG_UINT64_C(0XFFFF00000000000F))
  1668. #define VHA_CR_MMU_FAULT_STATUS_META_RNW_SHIFT (3U)
  1669. #define VHA_CR_MMU_FAULT_STATUS_META_RNW_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF7))
  1670. #define VHA_CR_MMU_FAULT_STATUS_META_RNW_EN (IMG_UINT64_C(0X0000000000000008))
  1671. #define VHA_CR_MMU_FAULT_STATUS_META_TYPE_SHIFT (1U)
  1672. #define VHA_CR_MMU_FAULT_STATUS_META_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF9))
  1673. #define VHA_CR_MMU_FAULT_STATUS_META_FAULT_SHIFT (0U)
  1674. #define VHA_CR_MMU_FAULT_STATUS_META_FAULT_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  1675. #define VHA_CR_MMU_FAULT_STATUS_META_FAULT_EN (IMG_UINT64_C(0X0000000000000001))
  1676. /*
  1677. Register VHA_CR_MMU_FAULT_STATUS2_META
  1678. */
  1679. #define VHA_CR_MMU_FAULT_STATUS2_META (0xE198U)
  1680. #define VHA_CR_MMU_FAULT_STATUS2_META_MASKFULL (IMG_UINT64_C(0x0000000000003FFF))
  1681. #define VHA_CR_MMU_FAULT_STATUS2_META_WRITEBACK_SHIFT (13U)
  1682. #define VHA_CR_MMU_FAULT_STATUS2_META_WRITEBACK_CLRMSK (0XFFFFDFFFU)
  1683. #define VHA_CR_MMU_FAULT_STATUS2_META_WRITEBACK_EN (0X00002000U)
  1684. #define VHA_CR_MMU_FAULT_STATUS2_META_CLEANUNIQUE_SHIFT (12U)
  1685. #define VHA_CR_MMU_FAULT_STATUS2_META_CLEANUNIQUE_CLRMSK (0XFFFFEFFFU)
  1686. #define VHA_CR_MMU_FAULT_STATUS2_META_CLEANUNIQUE_EN (0X00001000U)
  1687. #define VHA_CR_MMU_FAULT_STATUS2_META_BANK_SHIFT (8U)
  1688. #define VHA_CR_MMU_FAULT_STATUS2_META_BANK_CLRMSK (0XFFFFF0FFU)
  1689. #define VHA_CR_MMU_FAULT_STATUS2_META_TLB_ENTRY_SHIFT (0U)
  1690. #define VHA_CR_MMU_FAULT_STATUS2_META_TLB_ENTRY_CLRMSK (0XFFFFFF00U)
  1691. /*
  1692. Register VHA_CR_MMU_FAULT_STATUS_PM
  1693. */
  1694. #define VHA_CR_MMU_FAULT_STATUS_PM (0xE130U)
  1695. #define VHA_CR_MMU_FAULT_STATUS_PM_MASKFULL (IMG_UINT64_C(0x0000000007FFFFFF))
  1696. #define VHA_CR_MMU_FAULT_STATUS_PM_DM_SHIFT (24U)
  1697. #define VHA_CR_MMU_FAULT_STATUS_PM_DM_CLRMSK (IMG_UINT64_C(0XFFFFFFFFF8FFFFFF))
  1698. #define VHA_CR_MMU_FAULT_STATUS_PM_RNW_SHIFT (23U)
  1699. #define VHA_CR_MMU_FAULT_STATUS_PM_RNW_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF7FFFFF))
  1700. #define VHA_CR_MMU_FAULT_STATUS_PM_RNW_EN (IMG_UINT64_C(0X0000000000800000))
  1701. #define VHA_CR_MMU_FAULT_STATUS_PM_ADDRESS_SHIFT (3U)
  1702. #define VHA_CR_MMU_FAULT_STATUS_PM_ADDRESS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF800007))
  1703. #define VHA_CR_MMU_FAULT_STATUS_PM_LEVEL_SHIFT (1U)
  1704. #define VHA_CR_MMU_FAULT_STATUS_PM_LEVEL_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF9))
  1705. #define VHA_CR_MMU_FAULT_STATUS_PM_FAULT_SHIFT (0U)
  1706. #define VHA_CR_MMU_FAULT_STATUS_PM_FAULT_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  1707. #define VHA_CR_MMU_FAULT_STATUS_PM_FAULT_EN (IMG_UINT64_C(0X0000000000000001))
  1708. /*
  1709. Register VHA_CR_MMU_ABORT_PM_CTRL
  1710. */
  1711. #define VHA_CR_MMU_ABORT_PM_CTRL (0xE188U)
  1712. #define VHA_CR_MMU_ABORT_PM_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  1713. #define VHA_CR_MMU_ABORT_PM_CTRL_ENABLE_SHIFT (0U)
  1714. #define VHA_CR_MMU_ABORT_PM_CTRL_ENABLE_CLRMSK (0XFFFFFFFEU)
  1715. #define VHA_CR_MMU_ABORT_PM_CTRL_ENABLE_EN (0X00000001U)
  1716. /*
  1717. Register VHA_CR_MMU_ABORT_PM_STATUS
  1718. */
  1719. #define VHA_CR_MMU_ABORT_PM_STATUS (0xE190U)
  1720. #define VHA_CR_MMU_ABORT_PM_STATUS_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  1721. #define VHA_CR_MMU_ABORT_PM_STATUS_ABORT_SHIFT (0U)
  1722. #define VHA_CR_MMU_ABORT_PM_STATUS_ABORT_CLRMSK (0XFFFFFFFEU)
  1723. #define VHA_CR_MMU_ABORT_PM_STATUS_ABORT_EN (0X00000001U)
  1724. /*
  1725. Register VHA_CR_MMU_HOST_IRQ_ENABLE
  1726. */
  1727. #define VHA_CR_MMU_HOST_IRQ_ENABLE (0xE1A0U)
  1728. #define VHA_CR_MMU_HOST_IRQ_ENABLE_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  1729. #define VHA_CR_MMU_HOST_IRQ_ENABLE_FAULT_PM_SHIFT (0U)
  1730. #define VHA_CR_MMU_HOST_IRQ_ENABLE_FAULT_PM_CLRMSK (0XFFFFFFFEU)
  1731. #define VHA_CR_MMU_HOST_IRQ_ENABLE_FAULT_PM_EN (0X00000001U)
  1732. /*
  1733. Register VHA_CR_MMU_PAGE_SIZE_RANGE_ONE
  1734. */
  1735. #define VHA_CR_MMU_PAGE_SIZE_RANGE_ONE (0xE350U)
  1736. #define VHA_CR_MMU_PAGE_SIZE_RANGE_ONE_MASKFULL (IMG_UINT64_C(0x000001FFFFFFFFFF))
  1737. #define VHA_CR_MMU_PAGE_SIZE_RANGE_ONE_PAGE_SIZE_SHIFT (38U)
  1738. #define VHA_CR_MMU_PAGE_SIZE_RANGE_ONE_PAGE_SIZE_CLRMSK (IMG_UINT64_C(0XFFFFFE3FFFFFFFFF))
  1739. #define VHA_CR_MMU_PAGE_SIZE_RANGE_ONE_END_ADDR_SHIFT (19U)
  1740. #define VHA_CR_MMU_PAGE_SIZE_RANGE_ONE_END_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFFC00007FFFF))
  1741. #define VHA_CR_MMU_PAGE_SIZE_RANGE_ONE_END_ADDR_ALIGNSHIFT (21U)
  1742. #define VHA_CR_MMU_PAGE_SIZE_RANGE_ONE_END_ADDR_ALIGNSIZE (2097152U)
  1743. #define VHA_CR_MMU_PAGE_SIZE_RANGE_ONE_BASE_ADDR_SHIFT (0U)
  1744. #define VHA_CR_MMU_PAGE_SIZE_RANGE_ONE_BASE_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF80000))
  1745. #define VHA_CR_MMU_PAGE_SIZE_RANGE_ONE_BASE_ADDR_ALIGNSHIFT (21U)
  1746. #define VHA_CR_MMU_PAGE_SIZE_RANGE_ONE_BASE_ADDR_ALIGNSIZE (2097152U)
  1747. /*
  1748. Register VHA_CR_MMU_PAGE_SIZE_RANGE_TWO
  1749. */
  1750. #define VHA_CR_MMU_PAGE_SIZE_RANGE_TWO (0xE358U)
  1751. #define VHA_CR_MMU_PAGE_SIZE_RANGE_TWO_MASKFULL (IMG_UINT64_C(0x000001FFFFFFFFFF))
  1752. #define VHA_CR_MMU_PAGE_SIZE_RANGE_TWO_PAGE_SIZE_SHIFT (38U)
  1753. #define VHA_CR_MMU_PAGE_SIZE_RANGE_TWO_PAGE_SIZE_CLRMSK (IMG_UINT64_C(0XFFFFFE3FFFFFFFFF))
  1754. #define VHA_CR_MMU_PAGE_SIZE_RANGE_TWO_END_ADDR_SHIFT (19U)
  1755. #define VHA_CR_MMU_PAGE_SIZE_RANGE_TWO_END_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFFC00007FFFF))
  1756. #define VHA_CR_MMU_PAGE_SIZE_RANGE_TWO_END_ADDR_ALIGNSHIFT (21U)
  1757. #define VHA_CR_MMU_PAGE_SIZE_RANGE_TWO_END_ADDR_ALIGNSIZE (2097152U)
  1758. #define VHA_CR_MMU_PAGE_SIZE_RANGE_TWO_BASE_ADDR_SHIFT (0U)
  1759. #define VHA_CR_MMU_PAGE_SIZE_RANGE_TWO_BASE_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF80000))
  1760. #define VHA_CR_MMU_PAGE_SIZE_RANGE_TWO_BASE_ADDR_ALIGNSHIFT (21U)
  1761. #define VHA_CR_MMU_PAGE_SIZE_RANGE_TWO_BASE_ADDR_ALIGNSIZE (2097152U)
  1762. /*
  1763. Register VHA_CR_MMU_PAGE_SIZE_RANGE_THREE
  1764. */
  1765. #define VHA_CR_MMU_PAGE_SIZE_RANGE_THREE (0xE360U)
  1766. #define VHA_CR_MMU_PAGE_SIZE_RANGE_THREE_MASKFULL (IMG_UINT64_C(0x000001FFFFFFFFFF))
  1767. #define VHA_CR_MMU_PAGE_SIZE_RANGE_THREE_PAGE_SIZE_SHIFT (38U)
  1768. #define VHA_CR_MMU_PAGE_SIZE_RANGE_THREE_PAGE_SIZE_CLRMSK (IMG_UINT64_C(0XFFFFFE3FFFFFFFFF))
  1769. #define VHA_CR_MMU_PAGE_SIZE_RANGE_THREE_END_ADDR_SHIFT (19U)
  1770. #define VHA_CR_MMU_PAGE_SIZE_RANGE_THREE_END_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFFC00007FFFF))
  1771. #define VHA_CR_MMU_PAGE_SIZE_RANGE_THREE_END_ADDR_ALIGNSHIFT (21U)
  1772. #define VHA_CR_MMU_PAGE_SIZE_RANGE_THREE_END_ADDR_ALIGNSIZE (2097152U)
  1773. #define VHA_CR_MMU_PAGE_SIZE_RANGE_THREE_BASE_ADDR_SHIFT (0U)
  1774. #define VHA_CR_MMU_PAGE_SIZE_RANGE_THREE_BASE_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF80000))
  1775. #define VHA_CR_MMU_PAGE_SIZE_RANGE_THREE_BASE_ADDR_ALIGNSHIFT (21U)
  1776. #define VHA_CR_MMU_PAGE_SIZE_RANGE_THREE_BASE_ADDR_ALIGNSIZE (2097152U)
  1777. /*
  1778. Register VHA_CR_MMU_PAGE_SIZE_RANGE_FOUR
  1779. */
  1780. #define VHA_CR_MMU_PAGE_SIZE_RANGE_FOUR (0xE368U)
  1781. #define VHA_CR_MMU_PAGE_SIZE_RANGE_FOUR_MASKFULL (IMG_UINT64_C(0x000001FFFFFFFFFF))
  1782. #define VHA_CR_MMU_PAGE_SIZE_RANGE_FOUR_PAGE_SIZE_SHIFT (38U)
  1783. #define VHA_CR_MMU_PAGE_SIZE_RANGE_FOUR_PAGE_SIZE_CLRMSK (IMG_UINT64_C(0XFFFFFE3FFFFFFFFF))
  1784. #define VHA_CR_MMU_PAGE_SIZE_RANGE_FOUR_END_ADDR_SHIFT (19U)
  1785. #define VHA_CR_MMU_PAGE_SIZE_RANGE_FOUR_END_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFFC00007FFFF))
  1786. #define VHA_CR_MMU_PAGE_SIZE_RANGE_FOUR_END_ADDR_ALIGNSHIFT (21U)
  1787. #define VHA_CR_MMU_PAGE_SIZE_RANGE_FOUR_END_ADDR_ALIGNSIZE (2097152U)
  1788. #define VHA_CR_MMU_PAGE_SIZE_RANGE_FOUR_BASE_ADDR_SHIFT (0U)
  1789. #define VHA_CR_MMU_PAGE_SIZE_RANGE_FOUR_BASE_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF80000))
  1790. #define VHA_CR_MMU_PAGE_SIZE_RANGE_FOUR_BASE_ADDR_ALIGNSHIFT (21U)
  1791. #define VHA_CR_MMU_PAGE_SIZE_RANGE_FOUR_BASE_ADDR_ALIGNSIZE (2097152U)
  1792. #define VHA_CR_SLC_CTRL_ENUM_HASH_MODE_MASK (0x00000003U)
  1793. /*
  1794. Reserved value */
  1795. #define VHA_CR_SLC_CTRL_ENUM_HASH_MODE_RESERVED (0x00000000U)
  1796. /*
  1797. Addresses interleaved between Cache Bank using a combined Set & Bank hash of the upper address bits */
  1798. #define VHA_CR_SLC_CTRL_ENUM_HASH_MODE_PVR_V3_HASHING (0x00000001U)
  1799. /*
  1800. Addresses are interleaved between Cache Banks on a Cacheline boundary */
  1801. #define VHA_CR_SLC_CTRL_ENUM_HASH_MODE_LINEAR (0x00000002U)
  1802. /*
  1803. Addresses interleaved between Cache Banks using an XOR hash of the address bits below the 4KB page granularity */
  1804. #define VHA_CR_SLC_CTRL_ENUM_HASH_MODE_IN_PAGE_HASH (0x00000003U)
  1805. /*
  1806. Register VHA_CR_SLC_CTRL
  1807. */
  1808. #define VHA_CR_SLC_CTRL (0xE200U)
  1809. #define VHA_CR_SLC_CTRL_MASKFULL (IMG_UINT64_C(0x000000000001FFF3))
  1810. #define VHA_CR_SLC_CTRL_ISCHED_CREDIT_THRESHOLD_SHIFT (13U)
  1811. #define VHA_CR_SLC_CTRL_ISCHED_CREDIT_THRESHOLD_CLRMSK (0XFFFE1FFFU)
  1812. #define VHA_CR_SLC_CTRL_CFI_TIMEOUT_ENABLE_SHIFT (12U)
  1813. #define VHA_CR_SLC_CTRL_CFI_TIMEOUT_ENABLE_CLRMSK (0XFFFFEFFFU)
  1814. #define VHA_CR_SLC_CTRL_CFI_TIMEOUT_ENABLE_EN (0X00001000U)
  1815. #define VHA_CR_SLC_CTRL_CFI_TIMEOUT_CYCLES_SHIFT (8U)
  1816. #define VHA_CR_SLC_CTRL_CFI_TIMEOUT_CYCLES_CLRMSK (0XFFFFF0FFU)
  1817. #define VHA_CR_SLC_CTRL_PERSISTENCE_DECAY_ENABLE_SHIFT (7U)
  1818. #define VHA_CR_SLC_CTRL_PERSISTENCE_DECAY_ENABLE_CLRMSK (0XFFFFFF7FU)
  1819. #define VHA_CR_SLC_CTRL_PERSISTENCE_DECAY_ENABLE_EN (0X00000080U)
  1820. #define VHA_CR_SLC_CTRL_MAX_FENCES_SHIFT (4U)
  1821. #define VHA_CR_SLC_CTRL_MAX_FENCES_CLRMSK (0XFFFFFF8FU)
  1822. #define VHA_CR_SLC_CTRL_HASH_MODE_SHIFT (0U)
  1823. #define VHA_CR_SLC_CTRL_HASH_MODE_CLRMSK (0XFFFFFFFCU)
  1824. #define VHA_CR_SLC_CTRL_HASH_MODE_RESERVED (00000000U)
  1825. #define VHA_CR_SLC_CTRL_HASH_MODE_PVR_V3_HASHING (0X00000001U)
  1826. #define VHA_CR_SLC_CTRL_HASH_MODE_LINEAR (0X00000002U)
  1827. #define VHA_CR_SLC_CTRL_HASH_MODE_IN_PAGE_HASH (0X00000003U)
  1828. /*
  1829. Register VHA_CR_SLC_STATUS_BYP_COH_ERROR_READS
  1830. */
  1831. #define VHA_CR_SLC_STATUS_BYP_COH_ERROR_READS (0xE220U)
  1832. #define VHA_CR_SLC_STATUS_BYP_COH_ERROR_READS_MASKFULL (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
  1833. #define VHA_CR_SLC_STATUS_BYP_COH_ERROR_READS_BANK3_SHIFT (48U)
  1834. #define VHA_CR_SLC_STATUS_BYP_COH_ERROR_READS_BANK3_CLRMSK (IMG_UINT64_C(0X0000FFFFFFFFFFFF))
  1835. #define VHA_CR_SLC_STATUS_BYP_COH_ERROR_READS_BANK2_SHIFT (32U)
  1836. #define VHA_CR_SLC_STATUS_BYP_COH_ERROR_READS_BANK2_CLRMSK (IMG_UINT64_C(0XFFFF0000FFFFFFFF))
  1837. #define VHA_CR_SLC_STATUS_BYP_COH_ERROR_READS_BANK1_SHIFT (16U)
  1838. #define VHA_CR_SLC_STATUS_BYP_COH_ERROR_READS_BANK1_CLRMSK (IMG_UINT64_C(0XFFFFFFFF0000FFFF))
  1839. #define VHA_CR_SLC_STATUS_BYP_COH_ERROR_READS_BANK0_SHIFT (0U)
  1840. #define VHA_CR_SLC_STATUS_BYP_COH_ERROR_READS_BANK0_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF0000))
  1841. /*
  1842. Register VHA_CR_SLC_STATUS_BYP_COH_ERROR_WRITES
  1843. */
  1844. #define VHA_CR_SLC_STATUS_BYP_COH_ERROR_WRITES (0xE228U)
  1845. #define VHA_CR_SLC_STATUS_BYP_COH_ERROR_WRITES_MASKFULL (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
  1846. #define VHA_CR_SLC_STATUS_BYP_COH_ERROR_WRITES_BANK3_SHIFT (48U)
  1847. #define VHA_CR_SLC_STATUS_BYP_COH_ERROR_WRITES_BANK3_CLRMSK (IMG_UINT64_C(0X0000FFFFFFFFFFFF))
  1848. #define VHA_CR_SLC_STATUS_BYP_COH_ERROR_WRITES_BANK2_SHIFT (32U)
  1849. #define VHA_CR_SLC_STATUS_BYP_COH_ERROR_WRITES_BANK2_CLRMSK (IMG_UINT64_C(0XFFFF0000FFFFFFFF))
  1850. #define VHA_CR_SLC_STATUS_BYP_COH_ERROR_WRITES_BANK1_SHIFT (16U)
  1851. #define VHA_CR_SLC_STATUS_BYP_COH_ERROR_WRITES_BANK1_CLRMSK (IMG_UINT64_C(0XFFFFFFFF0000FFFF))
  1852. #define VHA_CR_SLC_STATUS_BYP_COH_ERROR_WRITES_BANK0_SHIFT (0U)
  1853. #define VHA_CR_SLC_STATUS_BYP_COH_ERROR_WRITES_BANK0_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF0000))
  1854. /*
  1855. Register VHA_CR_SLC_FAULT_STOP_CTRL
  1856. */
  1857. #define VHA_CR_SLC_FAULT_STOP_CTRL (0xE248U)
  1858. #define VHA_CR_SLC_FAULT_STOP_CTRL_MASKFULL (IMG_UINT64_C(0x000000000003FFFF))
  1859. #define VHA_CR_SLC_FAULT_STOP_CTRL_ALL_SHIFT (17U)
  1860. #define VHA_CR_SLC_FAULT_STOP_CTRL_ALL_CLRMSK (0XFFFDFFFFU)
  1861. #define VHA_CR_SLC_FAULT_STOP_CTRL_ALL_EN (0X00020000U)
  1862. #define VHA_CR_SLC_FAULT_STOP_CTRL_ENABLE_SHIFT (0U)
  1863. #define VHA_CR_SLC_FAULT_STOP_CTRL_ENABLE_CLRMSK (0XFFFE0000U)
  1864. /*
  1865. Register VHA_CR_MMU_OSID_CTXT_MAPPING0
  1866. */
  1867. #define VHA_CR_MMU_OSID_CTXT_MAPPING0 (0xE280U)
  1868. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_MASKFULL (IMG_UINT64_C(0x7777777777777777))
  1869. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_15_SHIFT (60U)
  1870. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_15_CLRMSK (IMG_UINT64_C(0X8FFFFFFFFFFFFFFF))
  1871. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_14_SHIFT (56U)
  1872. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_14_CLRMSK (IMG_UINT64_C(0XF8FFFFFFFFFFFFFF))
  1873. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_13_SHIFT (52U)
  1874. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_13_CLRMSK (IMG_UINT64_C(0XFF8FFFFFFFFFFFFF))
  1875. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_12_SHIFT (48U)
  1876. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_12_CLRMSK (IMG_UINT64_C(0XFFF8FFFFFFFFFFFF))
  1877. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_11_SHIFT (44U)
  1878. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_11_CLRMSK (IMG_UINT64_C(0XFFFF8FFFFFFFFFFF))
  1879. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_10_SHIFT (40U)
  1880. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_10_CLRMSK (IMG_UINT64_C(0XFFFFF8FFFFFFFFFF))
  1881. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_9_SHIFT (36U)
  1882. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_9_CLRMSK (IMG_UINT64_C(0XFFFFFF8FFFFFFFFF))
  1883. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_8_SHIFT (32U)
  1884. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_8_CLRMSK (IMG_UINT64_C(0XFFFFFFF8FFFFFFFF))
  1885. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_7_SHIFT (28U)
  1886. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_7_CLRMSK (IMG_UINT64_C(0XFFFFFFFF8FFFFFFF))
  1887. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_6_SHIFT (24U)
  1888. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_6_CLRMSK (IMG_UINT64_C(0XFFFFFFFFF8FFFFFF))
  1889. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_5_SHIFT (20U)
  1890. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_5_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF8FFFFF))
  1891. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_4_SHIFT (16U)
  1892. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_4_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF8FFFF))
  1893. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_3_SHIFT (12U)
  1894. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_3_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF8FFF))
  1895. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_2_SHIFT (8U)
  1896. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_2_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF8FF))
  1897. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_1_SHIFT (4U)
  1898. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFF8F))
  1899. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_0_SHIFT (0U)
  1900. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_0_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF8))
  1901. /*
  1902. Register VHA_CR_MMU_OSID_CTXT_MAPPING1
  1903. */
  1904. #define VHA_CR_MMU_OSID_CTXT_MAPPING1 (0xE288U)
  1905. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_MASKFULL (IMG_UINT64_C(0x7777777777777777))
  1906. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_31_SHIFT (60U)
  1907. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_31_CLRMSK (IMG_UINT64_C(0X8FFFFFFFFFFFFFFF))
  1908. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_30_SHIFT (56U)
  1909. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_30_CLRMSK (IMG_UINT64_C(0XF8FFFFFFFFFFFFFF))
  1910. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_29_SHIFT (52U)
  1911. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_29_CLRMSK (IMG_UINT64_C(0XFF8FFFFFFFFFFFFF))
  1912. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_28_SHIFT (48U)
  1913. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_28_CLRMSK (IMG_UINT64_C(0XFFF8FFFFFFFFFFFF))
  1914. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_27_SHIFT (44U)
  1915. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_27_CLRMSK (IMG_UINT64_C(0XFFFF8FFFFFFFFFFF))
  1916. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_26_SHIFT (40U)
  1917. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_26_CLRMSK (IMG_UINT64_C(0XFFFFF8FFFFFFFFFF))
  1918. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_25_SHIFT (36U)
  1919. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_25_CLRMSK (IMG_UINT64_C(0XFFFFFF8FFFFFFFFF))
  1920. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_24_SHIFT (32U)
  1921. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_24_CLRMSK (IMG_UINT64_C(0XFFFFFFF8FFFFFFFF))
  1922. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_23_SHIFT (28U)
  1923. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_23_CLRMSK (IMG_UINT64_C(0XFFFFFFFF8FFFFFFF))
  1924. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_22_SHIFT (24U)
  1925. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_22_CLRMSK (IMG_UINT64_C(0XFFFFFFFFF8FFFFFF))
  1926. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_21_SHIFT (20U)
  1927. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_21_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF8FFFFF))
  1928. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_20_SHIFT (16U)
  1929. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_20_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF8FFFF))
  1930. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_19_SHIFT (12U)
  1931. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_19_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF8FFF))
  1932. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_18_SHIFT (8U)
  1933. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_18_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF8FF))
  1934. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_17_SHIFT (4U)
  1935. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_17_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFF8F))
  1936. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_16_SHIFT (0U)
  1937. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_16_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF8))
  1938. /*
  1939. Register VHA_CR_SLC_CCM_CTRL
  1940. */
  1941. #define VHA_CR_SLC_CCM_CTRL (0xE300U)
  1942. #define VHA_CR_SLC_CCM_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000FF00FF))
  1943. #define VHA_CR_SLC_CCM_CTRL_SPILL_AMOUNT_SHIFT (16U)
  1944. #define VHA_CR_SLC_CCM_CTRL_SPILL_AMOUNT_CLRMSK (0XFF00FFFFU)
  1945. #define VHA_CR_SLC_CCM_CTRL_SPILL_THRESHOLD_SHIFT (0U)
  1946. #define VHA_CR_SLC_CCM_CTRL_SPILL_THRESHOLD_CLRMSK (0XFFFFFF00U)
  1947. /*
  1948. Register VHA_CR_SLC_CCM_STATUS
  1949. */
  1950. #define VHA_CR_SLC_CCM_STATUS (0xE308U)
  1951. #define VHA_CR_SLC_CCM_STATUS_MASKFULL (IMG_UINT64_C(0x0FFFFFFFF10FF0FF))
  1952. #define VHA_CR_SLC_CCM_STATUS_SNOOP_COUNT3_SHIFT (52U)
  1953. #define VHA_CR_SLC_CCM_STATUS_SNOOP_COUNT3_CLRMSK (IMG_UINT64_C(0XF00FFFFFFFFFFFFF))
  1954. #define VHA_CR_SLC_CCM_STATUS_SNOOP_COUNT2_SHIFT (44U)
  1955. #define VHA_CR_SLC_CCM_STATUS_SNOOP_COUNT2_CLRMSK (IMG_UINT64_C(0XFFF00FFFFFFFFFFF))
  1956. #define VHA_CR_SLC_CCM_STATUS_SNOOP_COUNT1_SHIFT (36U)
  1957. #define VHA_CR_SLC_CCM_STATUS_SNOOP_COUNT1_CLRMSK (IMG_UINT64_C(0XFFFFF00FFFFFFFFF))
  1958. #define VHA_CR_SLC_CCM_STATUS_SNOOP_COUNT0_SHIFT (28U)
  1959. #define VHA_CR_SLC_CCM_STATUS_SNOOP_COUNT0_CLRMSK (IMG_UINT64_C(0XFFFFFFF00FFFFFFF))
  1960. #define VHA_CR_SLC_CCM_STATUS_SPILLING_SHIFT (24U)
  1961. #define VHA_CR_SLC_CCM_STATUS_SPILLING_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFEFFFFFF))
  1962. #define VHA_CR_SLC_CCM_STATUS_SPILLING_EN (IMG_UINT64_C(0X0000000001000000))
  1963. #define VHA_CR_SLC_CCM_STATUS_SPILL_ENTRIES_SHIFT (12U)
  1964. #define VHA_CR_SLC_CCM_STATUS_SPILL_ENTRIES_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF00FFF))
  1965. #define VHA_CR_SLC_CCM_STATUS_ACTIVE_ENTRIES_SHIFT (0U)
  1966. #define VHA_CR_SLC_CCM_STATUS_ACTIVE_ENTRIES_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFF00))
  1967. /*
  1968. Register VHA_CR_ACE_QOS_CTRL
  1969. */
  1970. #define VHA_CR_ACE_QOS_CTRL (0xE310U)
  1971. #define VHA_CR_ACE_QOS_CTRL_MASKFULL (IMG_UINT64_C(0x000000000000FFFF))
  1972. #define VHA_CR_ACE_QOS_CTRL_CRITICAL_SHIFT (12U)
  1973. #define VHA_CR_ACE_QOS_CTRL_CRITICAL_CLRMSK (0XFFFF0FFFU)
  1974. #define VHA_CR_ACE_QOS_CTRL_HIGH_SHIFT (8U)
  1975. #define VHA_CR_ACE_QOS_CTRL_HIGH_CLRMSK (0XFFFFF0FFU)
  1976. #define VHA_CR_ACE_QOS_CTRL_MEDIUM_SHIFT (4U)
  1977. #define VHA_CR_ACE_QOS_CTRL_MEDIUM_CLRMSK (0XFFFFFF0FU)
  1978. #define VHA_CR_ACE_QOS_CTRL_LOW_SHIFT (0U)
  1979. #define VHA_CR_ACE_QOS_CTRL_LOW_CLRMSK (0XFFFFFFF0U)
  1980. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_ENUM_PRIORITIES_MASK (0x00000003U)
  1981. /*
  1982. Low */
  1983. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_ENUM_PRIORITIES_LOW (0x00000000U)
  1984. /*
  1985. Medium */
  1986. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_ENUM_PRIORITIES_MEDIUM (0x00000001U)
  1987. /*
  1988. High */
  1989. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_ENUM_PRIORITIES_HIGH (0x00000002U)
  1990. /*
  1991. Critical */
  1992. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_ENUM_PRIORITIES_CRITICAL (0x00000003U)
  1993. /*
  1994. Register VHA_CR_ACE_PRIORITY_MAPPING_CTRL
  1995. */
  1996. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL (0xE318U)
  1997. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MASKFULL (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
  1998. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMU_SHIFT (62U)
  1999. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMU_CLRMSK (IMG_UINT64_C(0X3FFFFFFFFFFFFFFF))
  2000. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMU_LOW (IMG_UINT64_C(0000000000000000))
  2001. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMU_MEDIUM (IMG_UINT64_C(0x4000000000000000))
  2002. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMU_HIGH (IMG_UINT64_C(0x8000000000000000))
  2003. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMU_CRITICAL (IMG_UINT64_C(0xc000000000000000))
  2004. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_RESERVED_SHIFT (26U)
  2005. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_RESERVED_CLRMSK (IMG_UINT64_C(0XC000000003FFFFFF))
  2006. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_EWO_PSF_SHIFT (24U)
  2007. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_EWO_PSF_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFCFFFFFF))
  2008. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_EWO_PSF_LOW (IMG_UINT64_C(0000000000000000))
  2009. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_EWO_PSF_MEDIUM (IMG_UINT64_C(0x0000000001000000))
  2010. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_EWO_PSF_HIGH (IMG_UINT64_C(0x0000000002000000))
  2011. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_EWO_PSF_CRITICAL (IMG_UINT64_C(0x0000000003000000))
  2012. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMM_WR_SHIFT (22U)
  2013. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMM_WR_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF3FFFFF))
  2014. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMM_WR_LOW (IMG_UINT64_C(0000000000000000))
  2015. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMM_WR_MEDIUM (IMG_UINT64_C(0x0000000000400000))
  2016. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMM_WR_HIGH (IMG_UINT64_C(0x0000000000800000))
  2017. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMM_WR_CRITICAL (IMG_UINT64_C(0x0000000000c00000))
  2018. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMM_RD_SHIFT (20U)
  2019. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMM_RD_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFCFFFFF))
  2020. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMM_RD_LOW (IMG_UINT64_C(0000000000000000))
  2021. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMM_RD_MEDIUM (IMG_UINT64_C(0x0000000000100000))
  2022. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMM_RD_HIGH (IMG_UINT64_C(0x0000000000200000))
  2023. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMM_RD_CRITICAL (IMG_UINT64_C(0x0000000000300000))
  2024. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_EWO_SHIFT (18U)
  2025. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_EWO_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF3FFFF))
  2026. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_EWO_LOW (IMG_UINT64_C(0000000000000000))
  2027. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_EWO_MEDIUM (IMG_UINT64_C(0x0000000000040000))
  2028. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_EWO_HIGH (IMG_UINT64_C(0x0000000000080000))
  2029. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_EWO_CRITICAL (IMG_UINT64_C(0x00000000000c0000))
  2030. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_OUTPACK_SHIFT (16U)
  2031. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_OUTPACK_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFCFFFF))
  2032. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_OUTPACK_LOW (IMG_UINT64_C(0000000000000000))
  2033. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_OUTPACK_MEDIUM (IMG_UINT64_C(0x0000000000010000))
  2034. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_OUTPACK_HIGH (IMG_UINT64_C(0x0000000000020000))
  2035. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_OUTPACK_CRITICAL (IMG_UINT64_C(0x0000000000030000))
  2036. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_ABUF_SHIFT (14U)
  2037. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_ABUF_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF3FFF))
  2038. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_ABUF_LOW (IMG_UINT64_C(0000000000000000))
  2039. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_ABUF_MEDIUM (IMG_UINT64_C(0x0000000000004000))
  2040. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_ABUF_HIGH (IMG_UINT64_C(0x0000000000008000))
  2041. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_ABUF_CRITICAL (IMG_UINT64_C(0x000000000000c000))
  2042. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CBUF_SHIFT (12U)
  2043. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CBUF_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFCFFF))
  2044. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CBUF_LOW (IMG_UINT64_C(0000000000000000))
  2045. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CBUF_MEDIUM (IMG_UINT64_C(0x0000000000001000))
  2046. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CBUF_HIGH (IMG_UINT64_C(0x0000000000002000))
  2047. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CBUF_CRITICAL (IMG_UINT64_C(0x0000000000003000))
  2048. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_IBUF_0_SHIFT (10U)
  2049. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_IBUF_0_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF3FF))
  2050. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_IBUF_0_LOW (IMG_UINT64_C(0000000000000000))
  2051. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_IBUF_0_MEDIUM (IMG_UINT64_C(0x0000000000000400))
  2052. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_IBUF_0_HIGH (IMG_UINT64_C(0x0000000000000800))
  2053. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_IBUF_0_CRITICAL (IMG_UINT64_C(0x0000000000000c00))
  2054. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_4_SHIFT (8U)
  2055. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_4_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFCFF))
  2056. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_4_LOW (IMG_UINT64_C(0000000000000000))
  2057. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_4_MEDIUM (IMG_UINT64_C(0x0000000000000100))
  2058. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_4_HIGH (IMG_UINT64_C(0x0000000000000200))
  2059. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_4_CRITICAL (IMG_UINT64_C(0x0000000000000300))
  2060. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_3_SHIFT (6U)
  2061. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_3_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFF3F))
  2062. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_3_LOW (IMG_UINT64_C(0000000000000000))
  2063. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_3_MEDIUM (IMG_UINT64_C(0x0000000000000040))
  2064. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_3_HIGH (IMG_UINT64_C(0x0000000000000080))
  2065. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_3_CRITICAL (IMG_UINT64_C(0x00000000000000c0))
  2066. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_2_SHIFT (4U)
  2067. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_2_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFCF))
  2068. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_2_LOW (IMG_UINT64_C(0000000000000000))
  2069. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_2_MEDIUM (IMG_UINT64_C(0x0000000000000010))
  2070. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_2_HIGH (IMG_UINT64_C(0x0000000000000020))
  2071. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_2_CRITICAL (IMG_UINT64_C(0x0000000000000030))
  2072. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_1_SHIFT (2U)
  2073. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF3))
  2074. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_1_LOW (IMG_UINT64_C(0000000000000000))
  2075. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_1_MEDIUM (IMG_UINT64_C(0x0000000000000004))
  2076. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_1_HIGH (IMG_UINT64_C(0x0000000000000008))
  2077. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_1_CRITICAL (IMG_UINT64_C(0x000000000000000c))
  2078. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_0_SHIFT (0U)
  2079. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_0_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFC))
  2080. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_0_LOW (IMG_UINT64_C(0000000000000000))
  2081. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_0_MEDIUM (IMG_UINT64_C(0x0000000000000001))
  2082. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_0_HIGH (IMG_UINT64_C(0x0000000000000002))
  2083. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_0_CRITICAL (IMG_UINT64_C(0x0000000000000003))
  2084. #define VHA_CR_ACE_CTRL_ENUM_WR_CACHEABLE_MASK (0x0000000FU)
  2085. /*
  2086. Device Non-bufferable */
  2087. #define VHA_CR_ACE_CTRL_ENUM_WR_CACHEABLE_DEVICE_NON_BUFFERABLE (0x00000000U)
  2088. /*
  2089. Device Bufferable */
  2090. #define VHA_CR_ACE_CTRL_ENUM_WR_CACHEABLE_DEVICE_BUFFERABLE (0x00000001U)
  2091. /*
  2092. Normal Non-cacheable Non-bufferable */
  2093. #define VHA_CR_ACE_CTRL_ENUM_WR_CACHEABLE_NORMAL_NC_NON_BUFFERABLE (0x00000002U)
  2094. /*
  2095. Normal Non-cacheable Bufferable */
  2096. #define VHA_CR_ACE_CTRL_ENUM_WR_CACHEABLE_NORMAL_NC_BUFFERABLE (0x00000003U)
  2097. /*
  2098. Write-through No-allocate */
  2099. #define VHA_CR_ACE_CTRL_ENUM_WR_CACHEABLE_WRITE_THROUGH_NO_ALLOCATE (0x00000006U)
  2100. /*
  2101. Write-through Write-allocate */
  2102. #define VHA_CR_ACE_CTRL_ENUM_WR_CACHEABLE_WRITE_THROUGH_WRITE_ALLOCATE (0x0000000eU)
  2103. /*
  2104. Write-back No-allocate */
  2105. #define VHA_CR_ACE_CTRL_ENUM_WR_CACHEABLE_WRITE_BACK_NO_ALLOCATE (0x00000007U)
  2106. /*
  2107. Write-back Write-allocate */
  2108. #define VHA_CR_ACE_CTRL_ENUM_WR_CACHEABLE_WRITE_BACK_WRITE_ALLOCATE (0x0000000fU)
  2109. #define VHA_CR_ACE_CTRL_ENUM_RD_CACHEABLE_MASK (0x0000000FU)
  2110. /*
  2111. Device Non-bufferable */
  2112. #define VHA_CR_ACE_CTRL_ENUM_RD_CACHEABLE_DEVICE_NON_BUFFERABLE (0x00000000U)
  2113. /*
  2114. Device Bufferable */
  2115. #define VHA_CR_ACE_CTRL_ENUM_RD_CACHEABLE_DEVICE_BUFFERABLE (0x00000001U)
  2116. /*
  2117. Normal Non-cacheable Non-bufferable */
  2118. #define VHA_CR_ACE_CTRL_ENUM_RD_CACHEABLE_NORMAL_NC_NON_BUFFERABLE (0x00000002U)
  2119. /*
  2120. Normal Non-cacheable Bufferable */
  2121. #define VHA_CR_ACE_CTRL_ENUM_RD_CACHEABLE_NORMAL_NC_BUFFERABLE (0x00000003U)
  2122. /*
  2123. Write-through No-allocate */
  2124. #define VHA_CR_ACE_CTRL_ENUM_RD_CACHEABLE_WRITE_THROUGH_NO_ALLOCATE (0x0000000aU)
  2125. /*
  2126. Write-through Read-allocate */
  2127. #define VHA_CR_ACE_CTRL_ENUM_RD_CACHEABLE_WRITE_THROUGH_READ_ALLOCATE (0x0000000eU)
  2128. /*
  2129. Write-back No-allocate */
  2130. #define VHA_CR_ACE_CTRL_ENUM_RD_CACHEABLE_WRITE_BACK_NO_ALLOCATE (0x0000000bU)
  2131. /*
  2132. Write-back Read-allocate */
  2133. #define VHA_CR_ACE_CTRL_ENUM_RD_CACHEABLE_WRITE_BACK_READ_ALLOCATE (0x0000000fU)
  2134. /*
  2135. Non-Shareable */
  2136. #define VHA_CR_ACE_CTRL_ENUM_NCOH_DOMAIN_NON_SHAREABLE (0x00000000U)
  2137. /*
  2138. System */
  2139. #define VHA_CR_ACE_CTRL_ENUM_NCOH_DOMAIN_SYSTEM (0x00000001U)
  2140. /*
  2141. Inner-Shareable */
  2142. #define VHA_CR_ACE_CTRL_ENUM_COH_DOMAIN_INNER_SHAREABLE (0x00000000U)
  2143. /*
  2144. Outer-Shareable */
  2145. #define VHA_CR_ACE_CTRL_ENUM_COH_DOMAIN_OUTER_SHAREABLE (0x00000001U)
  2146. /*
  2147. Register VHA_CR_ACE_CTRL
  2148. */
  2149. #define VHA_CR_ACE_CTRL (0xE320U)
  2150. #define VHA_CR_ACE_CTRL_MASKFULL (IMG_UINT64_C(0x00000000007FCFFF))
  2151. #define VHA_CR_ACE_CTRL_CLB_AXQOS_SHIFT (19U)
  2152. #define VHA_CR_ACE_CTRL_CLB_AXQOS_CLRMSK (0XFF87FFFFU)
  2153. #define VHA_CR_ACE_CTRL_PM_MMU_AXCACHE_SHIFT (15U)
  2154. #define VHA_CR_ACE_CTRL_PM_MMU_AXCACHE_CLRMSK (0XFFF87FFFU)
  2155. #define VHA_CR_ACE_CTRL_ENABLE_NONSECURE_PROT_MATCH_SHIFT (14U)
  2156. #define VHA_CR_ACE_CTRL_ENABLE_NONSECURE_PROT_MATCH_CLRMSK (0XFFFFBFFFU)
  2157. #define VHA_CR_ACE_CTRL_ENABLE_NONSECURE_PROT_MATCH_EN (0X00004000U)
  2158. #define VHA_CR_ACE_CTRL_MMU_AWCACHE_SHIFT (8U)
  2159. #define VHA_CR_ACE_CTRL_MMU_AWCACHE_CLRMSK (0XFFFFF0FFU)
  2160. #define VHA_CR_ACE_CTRL_MMU_AWCACHE_DEVICE_NON_BUFFERABLE (00000000U)
  2161. #define VHA_CR_ACE_CTRL_MMU_AWCACHE_DEVICE_BUFFERABLE (0X00000100U)
  2162. #define VHA_CR_ACE_CTRL_MMU_AWCACHE_NORMAL_NC_NON_BUFFERABLE (0X00000200U)
  2163. #define VHA_CR_ACE_CTRL_MMU_AWCACHE_NORMAL_NC_BUFFERABLE (0X00000300U)
  2164. #define VHA_CR_ACE_CTRL_MMU_AWCACHE_WRITE_THROUGH_NO_ALLOCATE (0X00000600U)
  2165. #define VHA_CR_ACE_CTRL_MMU_AWCACHE_WRITE_THROUGH_WRITE_ALLOCATE (0X00000E00U)
  2166. #define VHA_CR_ACE_CTRL_MMU_AWCACHE_WRITE_BACK_NO_ALLOCATE (0X00000700U)
  2167. #define VHA_CR_ACE_CTRL_MMU_AWCACHE_WRITE_BACK_WRITE_ALLOCATE (0X00000F00U)
  2168. #define VHA_CR_ACE_CTRL_MMU_ARCACHE_SHIFT (4U)
  2169. #define VHA_CR_ACE_CTRL_MMU_ARCACHE_CLRMSK (0XFFFFFF0FU)
  2170. #define VHA_CR_ACE_CTRL_MMU_ARCACHE_DEVICE_NON_BUFFERABLE (00000000U)
  2171. #define VHA_CR_ACE_CTRL_MMU_ARCACHE_DEVICE_BUFFERABLE (0X00000010U)
  2172. #define VHA_CR_ACE_CTRL_MMU_ARCACHE_NORMAL_NC_NON_BUFFERABLE (0X00000020U)
  2173. #define VHA_CR_ACE_CTRL_MMU_ARCACHE_NORMAL_NC_BUFFERABLE (0X00000030U)
  2174. #define VHA_CR_ACE_CTRL_MMU_ARCACHE_WRITE_THROUGH_NO_ALLOCATE (0X000000A0U)
  2175. #define VHA_CR_ACE_CTRL_MMU_ARCACHE_WRITE_THROUGH_READ_ALLOCATE (0X000000E0U)
  2176. #define VHA_CR_ACE_CTRL_MMU_ARCACHE_WRITE_BACK_NO_ALLOCATE (0X000000B0U)
  2177. #define VHA_CR_ACE_CTRL_MMU_ARCACHE_WRITE_BACK_READ_ALLOCATE (0X000000F0U)
  2178. #define VHA_CR_ACE_CTRL_MMU_DOMAIN_SHIFT (2U)
  2179. #define VHA_CR_ACE_CTRL_MMU_DOMAIN_CLRMSK (0XFFFFFFF3U)
  2180. #define VHA_CR_ACE_CTRL_COH_DOMAIN_SHIFT (1U)
  2181. #define VHA_CR_ACE_CTRL_COH_DOMAIN_CLRMSK (0XFFFFFFFDU)
  2182. #define VHA_CR_ACE_CTRL_COH_DOMAIN_INNER_SHAREABLE (00000000U)
  2183. #define VHA_CR_ACE_CTRL_COH_DOMAIN_OUTER_SHAREABLE (0X00000002U)
  2184. #define VHA_CR_ACE_CTRL_NON_COH_DOMAIN_SHIFT (0U)
  2185. #define VHA_CR_ACE_CTRL_NON_COH_DOMAIN_CLRMSK (0XFFFFFFFEU)
  2186. #define VHA_CR_ACE_CTRL_NON_COH_DOMAIN_NON_SHAREABLE (00000000U)
  2187. #define VHA_CR_ACE_CTRL_NON_COH_DOMAIN_SYSTEM (0X00000001U)
  2188. /*
  2189. Register VHA_CR_ACE_STATUS
  2190. */
  2191. #define VHA_CR_ACE_STATUS (0xE330U)
  2192. #define VHA_CR_ACE_STATUS_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  2193. #define VHA_CR_ACE_STATUS_WR_BUS3_ERROR_SHIFT (28U)
  2194. #define VHA_CR_ACE_STATUS_WR_BUS3_ERROR_CLRMSK (0X0FFFFFFFU)
  2195. #define VHA_CR_ACE_STATUS_RD_BUS3_ERROR_SHIFT (24U)
  2196. #define VHA_CR_ACE_STATUS_RD_BUS3_ERROR_CLRMSK (0XF0FFFFFFU)
  2197. #define VHA_CR_ACE_STATUS_WR_BUS2_ERROR_SHIFT (20U)
  2198. #define VHA_CR_ACE_STATUS_WR_BUS2_ERROR_CLRMSK (0XFF0FFFFFU)
  2199. #define VHA_CR_ACE_STATUS_RD_BUS2_ERROR_SHIFT (16U)
  2200. #define VHA_CR_ACE_STATUS_RD_BUS2_ERROR_CLRMSK (0XFFF0FFFFU)
  2201. #define VHA_CR_ACE_STATUS_WR_BUS1_ERROR_SHIFT (12U)
  2202. #define VHA_CR_ACE_STATUS_WR_BUS1_ERROR_CLRMSK (0XFFFF0FFFU)
  2203. #define VHA_CR_ACE_STATUS_RD_BUS1_ERROR_SHIFT (8U)
  2204. #define VHA_CR_ACE_STATUS_RD_BUS1_ERROR_CLRMSK (0XFFFFF0FFU)
  2205. #define VHA_CR_ACE_STATUS_WR_BUS0_ERROR_SHIFT (4U)
  2206. #define VHA_CR_ACE_STATUS_WR_BUS0_ERROR_CLRMSK (0XFFFFFF0FU)
  2207. #define VHA_CR_ACE_STATUS_RD_BUS0_ERROR_SHIFT (0U)
  2208. #define VHA_CR_ACE_STATUS_RD_BUS0_ERROR_CLRMSK (0XFFFFFFF0U)
  2209. #define VHA_CR_SOC_AXI_ENUM_COH_MASK (0x00000003U)
  2210. /*
  2211. The SoC does not support any form of Coherency*/
  2212. #define VHA_CR_SOC_AXI_ENUM_COH_NO_COHERENCY (0x00000000U)
  2213. /*
  2214. The SoC supports ACE-Lite or I/O Coherency*/
  2215. #define VHA_CR_SOC_AXI_ENUM_COH_ACE_LITE_COHERENCY (0x00000001U)
  2216. /*
  2217. The SoC supports full ACE or 2-Way Coherency*/
  2218. #define VHA_CR_SOC_AXI_ENUM_COH_FULL_ACE_COHERENCY (0x00000002U)
  2219. /*
  2220. Register VHA_CR_SOC_AXI
  2221. */
  2222. #define VHA_CR_SOC_AXI (0xE338U)
  2223. #define VHA_CR_SOC_AXI_MASKFULL (IMG_UINT64_C(0x000000000000000F))
  2224. #define VHA_CR_SOC_AXI_NON_COHERENT_128_BYTE_BURST_SUPPORT_SHIFT (3U)
  2225. #define VHA_CR_SOC_AXI_NON_COHERENT_128_BYTE_BURST_SUPPORT_CLRMSK (0XFFFFFFF7U)
  2226. #define VHA_CR_SOC_AXI_NON_COHERENT_128_BYTE_BURST_SUPPORT_EN (0X00000008U)
  2227. #define VHA_CR_SOC_AXI_COHERENT_128_BYTE_BURST_SUPPORT_SHIFT (2U)
  2228. #define VHA_CR_SOC_AXI_COHERENT_128_BYTE_BURST_SUPPORT_CLRMSK (0XFFFFFFFBU)
  2229. #define VHA_CR_SOC_AXI_COHERENT_128_BYTE_BURST_SUPPORT_EN (0X00000004U)
  2230. #define VHA_CR_SOC_AXI_COHERENCY_SUPPORT_SHIFT (0U)
  2231. #define VHA_CR_SOC_AXI_COHERENCY_SUPPORT_CLRMSK (0XFFFFFFFCU)
  2232. #define VHA_CR_SOC_AXI_COHERENCY_SUPPORT_NO_COHERENCY (00000000U)
  2233. #define VHA_CR_SOC_AXI_COHERENCY_SUPPORT_ACE_LITE_COHERENCY (0X00000001U)
  2234. #define VHA_CR_SOC_AXI_COHERENCY_SUPPORT_FULL_ACE_COHERENCY (0X00000002U)
  2235. #define VHA_CR_L1_GLB_CTRL_ENUM_HASH_MODE_MASK (0x00000003U)
  2236. /*
  2237. Addresses interleaved between Cache Banks using a weaved XOR hash of address bits */
  2238. #define VHA_CR_L1_GLB_CTRL_ENUM_HASH_MODE_WEAVED_HASH (0x00000000U)
  2239. /*
  2240. Addresses interleaved between Cache Bank using a combined Set & Bank hash of the upper address bits */
  2241. #define VHA_CR_L1_GLB_CTRL_ENUM_HASH_MODE_PVR_V3_HASHING (0x00000001U)
  2242. /*
  2243. Register VHA_CR_L1_GLB_CTRL
  2244. */
  2245. #define VHA_CR_L1_GLB_CTRL (0xE400U)
  2246. #define VHA_CR_L1_GLB_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000000003))
  2247. #define VHA_CR_L1_GLB_CTRL_HASH_MODE_SHIFT (0U)
  2248. #define VHA_CR_L1_GLB_CTRL_HASH_MODE_CLRMSK (0XFFFFFFFCU)
  2249. #define VHA_CR_L1_GLB_CTRL_HASH_MODE_WEAVED_HASH (00000000U)
  2250. #define VHA_CR_L1_GLB_CTRL_HASH_MODE_PVR_V3_HASHING (0X00000001U)
  2251. /*
  2252. Register VHA_CR_CONTEXT_MAPPING2
  2253. */
  2254. #define VHA_CR_CONTEXT_MAPPING2 (0xF088U)
  2255. #define VHA_CR_CONTEXT_MAPPING2_MASKFULL (IMG_UINT64_C(0x0000000000FFFFFF))
  2256. #define VHA_CR_CONTEXT_MAPPING2_ALIST0_SHIFT (16U)
  2257. #define VHA_CR_CONTEXT_MAPPING2_ALIST0_CLRMSK (0XFF00FFFFU)
  2258. #define VHA_CR_CONTEXT_MAPPING2_TE0_SHIFT (8U)
  2259. #define VHA_CR_CONTEXT_MAPPING2_TE0_CLRMSK (0XFFFF00FFU)
  2260. #define VHA_CR_CONTEXT_MAPPING2_VCE0_SHIFT (0U)
  2261. #define VHA_CR_CONTEXT_MAPPING2_VCE0_CLRMSK (0XFFFFFF00U)
  2262. /*
  2263. Register VHA_CR_CONTEXT_MAPPING3
  2264. */
  2265. #define VHA_CR_CONTEXT_MAPPING3 (0xF090U)
  2266. #define VHA_CR_CONTEXT_MAPPING3_MASKFULL (IMG_UINT64_C(0x0000000000FFFFFF))
  2267. #define VHA_CR_CONTEXT_MAPPING3_ALIST1_SHIFT (16U)
  2268. #define VHA_CR_CONTEXT_MAPPING3_ALIST1_CLRMSK (0XFF00FFFFU)
  2269. #define VHA_CR_CONTEXT_MAPPING3_TE1_SHIFT (8U)
  2270. #define VHA_CR_CONTEXT_MAPPING3_TE1_CLRMSK (0XFFFF00FFU)
  2271. #define VHA_CR_CONTEXT_MAPPING3_VCE1_SHIFT (0U)
  2272. #define VHA_CR_CONTEXT_MAPPING3_VCE1_CLRMSK (0XFFFFFF00U)
  2273. /*
  2274. Register VHA_CR_SLC_FIX
  2275. */
  2276. #define VHA_CR_SLC_FIX (0xF0D8U)
  2277. #define VHA_CR_SLC_FIX_MASKFULL (IMG_UINT64_C(0x000000000000FFFF))
  2278. #define VHA_CR_SLC_FIX_DISABLE_SHIFT (0U)
  2279. #define VHA_CR_SLC_FIX_DISABLE_CLRMSK (0XFFFF0000U)
  2280. /*
  2281. Register VHA_CR_PWR_MAN_HYSTERESIS
  2282. */
  2283. #define VHA_CR_PWR_MAN_HYSTERESIS (0xF100U)
  2284. #define VHA_CR_PWR_MAN_HYSTERESIS_MASKFULL (IMG_UINT64_C(0x000000000000001F))
  2285. #define VHA_CR_PWR_MAN_HYSTERESIS_VALUE_SHIFT (0U)
  2286. #define VHA_CR_PWR_MAN_HYSTERESIS_VALUE_CLRMSK (0XFFFFFFE0U)
  2287. #define VHA_CR_CNN_DEBUG_CTRL_MASK (0x00000003U)
  2288. /*
  2289. Debug is switched off */
  2290. #define VHA_CR_CNN_DEBUG_CTRL_DISABLE (0x00000000U)
  2291. /*
  2292. Debug is output at the end of each stream */
  2293. #define VHA_CR_CNN_DEBUG_CTRL_STREAM (0x00000001U)
  2294. /*
  2295. Debug is output at the end of each layer */
  2296. #define VHA_CR_CNN_DEBUG_CTRL_LAYER (0x00000002U)
  2297. /*
  2298. Debug is output at the end of each pass */
  2299. #define VHA_CR_CNN_DEBUG_CTRL_PASS (0x00000003U)
  2300. #define VHA_CR_CNN_PRELOAD_CTRL_MASK (0x00000007U)
  2301. /*
  2302. Preloads are switched off */
  2303. #define VHA_CR_CNN_PRELOAD_CTRL_DISABLE (0x00000000U)
  2304. /*
  2305. Preloads are triggered 64 requests after the previous 32k boundary */
  2306. #define VHA_CR_CNN_PRELOAD_CTRL_N_64 (0x00000001U)
  2307. /*
  2308. Preloads are triggered 128 requests after the previous 32k boundary */
  2309. #define VHA_CR_CNN_PRELOAD_CTRL_N_128 (0x00000002U)
  2310. /*
  2311. Preloads are triggered 192 requests after the previous 32k boundary */
  2312. #define VHA_CR_CNN_PRELOAD_CTRL_N_192 (0x00000003U)
  2313. /*
  2314. Preloads are triggered 256 requests after the previous 32k boundary */
  2315. #define VHA_CR_CNN_PRELOAD_CTRL_N_256 (0x00000004U)
  2316. /*
  2317. Preloads are triggered 320 requests after the previous 32k boundary */
  2318. #define VHA_CR_CNN_PRELOAD_CTRL_N_320 (0x00000005U)
  2319. /*
  2320. Preloads are triggered 384 requests after the previous 32k boundary */
  2321. #define VHA_CR_CNN_PRELOAD_CTRL_N_384 (0x00000006U)
  2322. /*
  2323. Preloads are triggered 448 requests after the previous 32k boundary */
  2324. #define VHA_CR_CNN_PRELOAD_CTRL_N_448 (0x00000007U)
  2325. #define VHA_CR_VHA_EVENT_TYPE_VHA_READY_SHIFT (21U)
  2326. #define VHA_CR_VHA_EVENT_TYPE_VHA_READY_CLRMSK (0XFFDFFFFFU)
  2327. #define VHA_CR_VHA_EVENT_TYPE_VHA_READY_EN (0X00200000U)
  2328. #define VHA_CR_VHA_EVENT_TYPE_VHA_ERROR_SHIFT (20U)
  2329. #define VHA_CR_VHA_EVENT_TYPE_VHA_ERROR_CLRMSK (0XFFEFFFFFU)
  2330. #define VHA_CR_VHA_EVENT_TYPE_VHA_ERROR_EN (0X00100000U)
  2331. #define VHA_CR_VHA_EVENT_TYPE_VHA_HL_WDT_SHIFT (19U)
  2332. #define VHA_CR_VHA_EVENT_TYPE_VHA_HL_WDT_CLRMSK (0XFFF7FFFFU)
  2333. #define VHA_CR_VHA_EVENT_TYPE_VHA_HL_WDT_EN (0X00080000U)
  2334. #define VHA_CR_VHA_EVENT_TYPE_VHA_AXI_ERROR_SHIFT (18U)
  2335. #define VHA_CR_VHA_EVENT_TYPE_VHA_AXI_ERROR_CLRMSK (0XFFFBFFFFU)
  2336. #define VHA_CR_VHA_EVENT_TYPE_VHA_AXI_ERROR_EN (0X00040000U)
  2337. #define VHA_CR_VHA_EVENT_TYPE_VHA_MMU_PAGE_FAULT_SHIFT (16U)
  2338. #define VHA_CR_VHA_EVENT_TYPE_VHA_MMU_PAGE_FAULT_CLRMSK (0XFFFEFFFFU)
  2339. #define VHA_CR_VHA_EVENT_TYPE_VHA_MMU_PAGE_FAULT_EN (0X00010000U)
  2340. #define VHA_CR_VHA_EVENT_TYPE_VHA_CNN0_MEM_WDT_SHIFT (3U)
  2341. #define VHA_CR_VHA_EVENT_TYPE_VHA_CNN0_MEM_WDT_CLRMSK (0XFFFFFFF7U)
  2342. #define VHA_CR_VHA_EVENT_TYPE_VHA_CNN0_MEM_WDT_EN (0X00000008U)
  2343. #define VHA_CR_VHA_EVENT_TYPE_VHA_CNN0_ERROR_SHIFT (1U)
  2344. #define VHA_CR_VHA_EVENT_TYPE_VHA_CNN0_ERROR_CLRMSK (0XFFFFFFFDU)
  2345. #define VHA_CR_VHA_EVENT_TYPE_VHA_CNN0_ERROR_EN (0X00000002U)
  2346. #define VHA_CR_VHA_EVENT_TYPE_VHA_CNN0_COMPLETE_SHIFT (0U)
  2347. #define VHA_CR_VHA_EVENT_TYPE_VHA_CNN0_COMPLETE_CLRMSK (0XFFFFFFFEU)
  2348. #define VHA_CR_VHA_EVENT_TYPE_VHA_CNN0_COMPLETE_EN (0X00000001U)
  2349. /*
  2350. Memory buffer will be used for MODEL only (CBUF, CMD , DEBUG, PERF) */
  2351. #define VHA_CR_ALT_ADDR_BUF_TYPE_MODEL_ONLY (0x00000000U)
  2352. /*
  2353. Memory buffer will be used for IO Only( OUTPACK , IBUF , ABUF, EWO ) or Both MODEL and IO */
  2354. #define VHA_CR_ALT_ADDR_BUF_TYPE_IO_OR_SHARED (0x00000001U)
  2355. /*
  2356. Register VHA_CR_OS0_CNN_CONTROL
  2357. */
  2358. #define VHA_CR_OS0_CNN_CONTROL (0x10000U)
  2359. #define VHA_CR_OS0_CNN_CONTROL_MASKFULL (IMG_UINT64_C(0x000000000000337F))
  2360. #define VHA_CR_OS0_CNN_CONTROL_CTXT_PASID_SHIFT (12U)
  2361. #define VHA_CR_OS0_CNN_CONTROL_CTXT_PASID_CLRMSK (0XFFFFCFFFU)
  2362. #define VHA_CR_OS0_CNN_CONTROL_PRIORITY_SHIFT (8U)
  2363. #define VHA_CR_OS0_CNN_CONTROL_PRIORITY_CLRMSK (0XFFFFFCFFU)
  2364. #define VHA_CR_OS0_CNN_CONTROL_CMD_SIZE_MIN1_SHIFT (1U)
  2365. #define VHA_CR_OS0_CNN_CONTROL_CMD_SIZE_MIN1_CLRMSK (0XFFFFFF81U)
  2366. #define VHA_CR_OS0_CNN_CONTROL_START_SHIFT (0U)
  2367. #define VHA_CR_OS0_CNN_CONTROL_START_CLRMSK (0XFFFFFFFEU)
  2368. #define VHA_CR_OS0_CNN_CONTROL_START_EN (0X00000001U)
  2369. #define VHA_CR_OS0_CNN_STATUS_STATE_MASK (0x00000003U)
  2370. /*
  2371. No requests are pending for this host*/
  2372. #define VHA_CR_OS0_CNN_STATUS_STATE_IDLE (0x00000000U)
  2373. /*
  2374. A command stream from this host is being processed*/
  2375. #define VHA_CR_OS0_CNN_STATUS_STATE_RUN (0x00000001U)
  2376. /*
  2377. The command stream from this host has been suspended due to higher priority request from another host*/
  2378. #define VHA_CR_OS0_CNN_STATUS_STATE_SUSPEND (0x00000002U)
  2379. /*
  2380. A command stream from this host is pending but not been started */
  2381. #define VHA_CR_OS0_CNN_STATUS_STATE_PENDING (0x00000003U)
  2382. /*
  2383. Register VHA_CR_OS0_CNN_STATUS
  2384. */
  2385. #define VHA_CR_OS0_CNN_STATUS (0x10008U)
  2386. #define VHA_CR_OS0_CNN_STATUS_MASKFULL (IMG_UINT64_C(0x00000000C0FFFFFF))
  2387. #define VHA_CR_OS0_CNN_STATUS_CURRENT_STATE_SHIFT (30U)
  2388. #define VHA_CR_OS0_CNN_STATUS_CURRENT_STATE_CLRMSK (0X3FFFFFFFU)
  2389. #define VHA_CR_OS0_CNN_STATUS_CURRENT_STATE_IDLE (00000000U)
  2390. #define VHA_CR_OS0_CNN_STATUS_CURRENT_STATE_RUN (0X40000000U)
  2391. #define VHA_CR_OS0_CNN_STATUS_CURRENT_STATE_SUSPEND (0X80000000U)
  2392. #define VHA_CR_OS0_CNN_STATUS_CURRENT_STATE_PENDING (0XC0000000U)
  2393. #define VHA_CR_OS0_CNN_STATUS_PASS_COUNT_SHIFT (16U)
  2394. #define VHA_CR_OS0_CNN_STATUS_PASS_COUNT_CLRMSK (0XFF00FFFFU)
  2395. #define VHA_CR_OS0_CNN_STATUS_LAYER_COUNT_SHIFT (8U)
  2396. #define VHA_CR_OS0_CNN_STATUS_LAYER_COUNT_CLRMSK (0XFFFF00FFU)
  2397. #define VHA_CR_OS0_CNN_STATUS_STREAM_COUNT_SHIFT (0U)
  2398. #define VHA_CR_OS0_CNN_STATUS_STREAM_COUNT_CLRMSK (0XFFFFFF00U)
  2399. /*
  2400. Register VHA_CR_OS0_CNN_CMD_BASE_ADDRESS
  2401. */
  2402. #define VHA_CR_OS0_CNN_CMD_BASE_ADDRESS (0x10020U)
  2403. #define VHA_CR_OS0_CNN_CMD_BASE_ADDRESS_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFF00))
  2404. #define VHA_CR_OS0_CNN_CMD_BASE_ADDRESS_BASE_ADDR_SHIFT (8U)
  2405. #define VHA_CR_OS0_CNN_CMD_BASE_ADDRESS_BASE_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF00000000FF))
  2406. /*
  2407. Register VHA_CR_OS0_CNN_ALT_ADDRESS_USED
  2408. */
  2409. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED (0x10038U)
  2410. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  2411. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR15_BUF_TYPE_SHIFT (31U)
  2412. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR15_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFF7FFFFFFF))
  2413. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR15_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  2414. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR15_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000080000000))
  2415. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR14_BUF_TYPE_SHIFT (30U)
  2416. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR14_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFBFFFFFFF))
  2417. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR14_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  2418. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR14_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000040000000))
  2419. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR13_BUF_TYPE_SHIFT (29U)
  2420. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR13_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFDFFFFFFF))
  2421. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR13_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  2422. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR13_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000020000000))
  2423. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR12_BUF_TYPE_SHIFT (28U)
  2424. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR12_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFEFFFFFFF))
  2425. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR12_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  2426. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR12_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000010000000))
  2427. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR11_BUF_TYPE_SHIFT (27U)
  2428. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR11_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFF7FFFFFF))
  2429. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR11_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  2430. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR11_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000008000000))
  2431. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR10_BUF_TYPE_SHIFT (26U)
  2432. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR10_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFBFFFFFF))
  2433. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR10_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  2434. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR10_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000004000000))
  2435. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR9_BUF_TYPE_SHIFT (25U)
  2436. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR9_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFDFFFFFF))
  2437. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR9_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  2438. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR9_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000002000000))
  2439. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR8_BUF_TYPE_SHIFT (24U)
  2440. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR8_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFEFFFFFF))
  2441. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR8_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  2442. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR8_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000001000000))
  2443. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR7_BUF_TYPE_SHIFT (23U)
  2444. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR7_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF7FFFFF))
  2445. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR7_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  2446. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR7_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000000800000))
  2447. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR6_BUF_TYPE_SHIFT (22U)
  2448. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR6_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFBFFFFF))
  2449. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR6_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  2450. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR6_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000000400000))
  2451. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR5_BUF_TYPE_SHIFT (21U)
  2452. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR5_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFDFFFFF))
  2453. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR5_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  2454. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR5_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000000200000))
  2455. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR4_BUF_TYPE_SHIFT (20U)
  2456. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR4_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFEFFFFF))
  2457. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR4_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  2458. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR4_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000000100000))
  2459. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR3_BUF_TYPE_SHIFT (19U)
  2460. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR3_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF7FFFF))
  2461. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR3_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  2462. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR3_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000000080000))
  2463. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR2_BUF_TYPE_SHIFT (18U)
  2464. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR2_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFBFFFF))
  2465. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR2_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  2466. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR2_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000000040000))
  2467. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR1_BUF_TYPE_SHIFT (17U)
  2468. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR1_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFDFFFF))
  2469. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR1_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  2470. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR1_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000000020000))
  2471. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR0_BUF_TYPE_SHIFT (16U)
  2472. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR0_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFEFFFF))
  2473. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR0_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  2474. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR0_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000000010000))
  2475. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR15_USED_SHIFT (15U)
  2476. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR15_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF7FFF))
  2477. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR15_USED_EN (IMG_UINT64_C(0X0000000000008000))
  2478. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR14_USED_SHIFT (14U)
  2479. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR14_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFBFFF))
  2480. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR14_USED_EN (IMG_UINT64_C(0X0000000000004000))
  2481. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR13_USED_SHIFT (13U)
  2482. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR13_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFDFFF))
  2483. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR13_USED_EN (IMG_UINT64_C(0X0000000000002000))
  2484. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR12_USED_SHIFT (12U)
  2485. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR12_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFEFFF))
  2486. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR12_USED_EN (IMG_UINT64_C(0X0000000000001000))
  2487. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR11_USED_SHIFT (11U)
  2488. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR11_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF7FF))
  2489. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR11_USED_EN (IMG_UINT64_C(0X0000000000000800))
  2490. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR10_USED_SHIFT (10U)
  2491. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR10_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFBFF))
  2492. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR10_USED_EN (IMG_UINT64_C(0X0000000000000400))
  2493. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR9_USED_SHIFT (9U)
  2494. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR9_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFDFF))
  2495. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR9_USED_EN (IMG_UINT64_C(0X0000000000000200))
  2496. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR8_USED_SHIFT (8U)
  2497. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR8_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFEFF))
  2498. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR8_USED_EN (IMG_UINT64_C(0X0000000000000100))
  2499. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR7_USED_SHIFT (7U)
  2500. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR7_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFF7F))
  2501. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR7_USED_EN (IMG_UINT64_C(0X0000000000000080))
  2502. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR6_USED_SHIFT (6U)
  2503. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR6_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFBF))
  2504. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR6_USED_EN (IMG_UINT64_C(0X0000000000000040))
  2505. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR5_USED_SHIFT (5U)
  2506. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR5_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFDF))
  2507. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR5_USED_EN (IMG_UINT64_C(0X0000000000000020))
  2508. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR4_USED_SHIFT (4U)
  2509. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR4_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFEF))
  2510. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR4_USED_EN (IMG_UINT64_C(0X0000000000000010))
  2511. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR3_USED_SHIFT (3U)
  2512. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR3_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF7))
  2513. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR3_USED_EN (IMG_UINT64_C(0X0000000000000008))
  2514. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR2_USED_SHIFT (2U)
  2515. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR2_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFB))
  2516. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR2_USED_EN (IMG_UINT64_C(0X0000000000000004))
  2517. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR1_USED_SHIFT (1U)
  2518. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR1_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFD))
  2519. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR1_USED_EN (IMG_UINT64_C(0X0000000000000002))
  2520. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR0_USED_SHIFT (0U)
  2521. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR0_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  2522. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR0_USED_EN (IMG_UINT64_C(0X0000000000000001))
  2523. /*
  2524. Register VHA_CR_OS0_CNN_ALT_ADDRESS0
  2525. */
  2526. #define VHA_CR_OS0_CNN_ALT_ADDRESS0 (0x10040U)
  2527. #define VHA_CR_OS0_CNN_ALT_ADDRESS0_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  2528. #define VHA_CR_OS0_CNN_ALT_ADDRESS0_ALT_ADDR_SHIFT (0U)
  2529. #define VHA_CR_OS0_CNN_ALT_ADDRESS0_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  2530. /*
  2531. Register VHA_CR_OS0_CNN_ALT_ADDRESS1
  2532. */
  2533. #define VHA_CR_OS0_CNN_ALT_ADDRESS1 (0x10048U)
  2534. #define VHA_CR_OS0_CNN_ALT_ADDRESS1_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  2535. #define VHA_CR_OS0_CNN_ALT_ADDRESS1_ALT_ADDR_SHIFT (0U)
  2536. #define VHA_CR_OS0_CNN_ALT_ADDRESS1_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  2537. /*
  2538. Register VHA_CR_OS0_CNN_ALT_ADDRESS2
  2539. */
  2540. #define VHA_CR_OS0_CNN_ALT_ADDRESS2 (0x10050U)
  2541. #define VHA_CR_OS0_CNN_ALT_ADDRESS2_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  2542. #define VHA_CR_OS0_CNN_ALT_ADDRESS2_ALT_ADDR_SHIFT (0U)
  2543. #define VHA_CR_OS0_CNN_ALT_ADDRESS2_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  2544. /*
  2545. Register VHA_CR_OS0_CNN_ALT_ADDRESS3
  2546. */
  2547. #define VHA_CR_OS0_CNN_ALT_ADDRESS3 (0x10058U)
  2548. #define VHA_CR_OS0_CNN_ALT_ADDRESS3_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  2549. #define VHA_CR_OS0_CNN_ALT_ADDRESS3_ALT_ADDR_SHIFT (0U)
  2550. #define VHA_CR_OS0_CNN_ALT_ADDRESS3_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  2551. /*
  2552. Register VHA_CR_OS0_CNN_ALT_ADDRESS4
  2553. */
  2554. #define VHA_CR_OS0_CNN_ALT_ADDRESS4 (0x10060U)
  2555. #define VHA_CR_OS0_CNN_ALT_ADDRESS4_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  2556. #define VHA_CR_OS0_CNN_ALT_ADDRESS4_ALT_ADDR_SHIFT (0U)
  2557. #define VHA_CR_OS0_CNN_ALT_ADDRESS4_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  2558. /*
  2559. Register VHA_CR_OS0_CNN_ALT_ADDRESS5
  2560. */
  2561. #define VHA_CR_OS0_CNN_ALT_ADDRESS5 (0x10068U)
  2562. #define VHA_CR_OS0_CNN_ALT_ADDRESS5_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  2563. #define VHA_CR_OS0_CNN_ALT_ADDRESS5_ALT_ADDR_SHIFT (0U)
  2564. #define VHA_CR_OS0_CNN_ALT_ADDRESS5_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  2565. /*
  2566. Register VHA_CR_OS0_CNN_ALT_ADDRESS6
  2567. */
  2568. #define VHA_CR_OS0_CNN_ALT_ADDRESS6 (0x10070U)
  2569. #define VHA_CR_OS0_CNN_ALT_ADDRESS6_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  2570. #define VHA_CR_OS0_CNN_ALT_ADDRESS6_ALT_ADDR_SHIFT (0U)
  2571. #define VHA_CR_OS0_CNN_ALT_ADDRESS6_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  2572. /*
  2573. Register VHA_CR_OS0_CNN_ALT_ADDRESS7
  2574. */
  2575. #define VHA_CR_OS0_CNN_ALT_ADDRESS7 (0x10078U)
  2576. #define VHA_CR_OS0_CNN_ALT_ADDRESS7_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  2577. #define VHA_CR_OS0_CNN_ALT_ADDRESS7_ALT_ADDR_SHIFT (0U)
  2578. #define VHA_CR_OS0_CNN_ALT_ADDRESS7_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  2579. /*
  2580. Register VHA_CR_OS0_CNN_WRITEBACK_CONTROL
  2581. */
  2582. #define VHA_CR_OS0_CNN_WRITEBACK_CONTROL (0x10080U)
  2583. #define VHA_CR_OS0_CNN_WRITEBACK_CONTROL_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  2584. #define VHA_CR_OS0_CNN_WRITEBACK_CONTROL_WRITE_BACK_VALUE_SHIFT (0U)
  2585. #define VHA_CR_OS0_CNN_WRITEBACK_CONTROL_WRITE_BACK_VALUE_CLRMSK (00000000U)
  2586. /*
  2587. Register VHA_CR_OS0_VHA_EVENT_ENABLE
  2588. */
  2589. #define VHA_CR_OS0_VHA_EVENT_ENABLE (0x10088U)
  2590. #define VHA_CR_OS0_VHA_EVENT_ENABLE_MASKFULL (IMG_UINT64_C(0x00000000003D000B))
  2591. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_READY_SHIFT (21U)
  2592. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_READY_CLRMSK (0XFFDFFFFFU)
  2593. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_READY_EN (0X00200000U)
  2594. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_ERROR_SHIFT (20U)
  2595. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_ERROR_CLRMSK (0XFFEFFFFFU)
  2596. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_ERROR_EN (0X00100000U)
  2597. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_HL_WDT_SHIFT (19U)
  2598. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_HL_WDT_CLRMSK (0XFFF7FFFFU)
  2599. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_HL_WDT_EN (0X00080000U)
  2600. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_AXI_ERROR_SHIFT (18U)
  2601. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_AXI_ERROR_CLRMSK (0XFFFBFFFFU)
  2602. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_AXI_ERROR_EN (0X00040000U)
  2603. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_MMU_PAGE_FAULT_SHIFT (16U)
  2604. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_MMU_PAGE_FAULT_CLRMSK (0XFFFEFFFFU)
  2605. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_MMU_PAGE_FAULT_EN (0X00010000U)
  2606. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_CNN0_MEM_WDT_SHIFT (3U)
  2607. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_CNN0_MEM_WDT_CLRMSK (0XFFFFFFF7U)
  2608. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_CNN0_MEM_WDT_EN (0X00000008U)
  2609. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_CNN0_ERROR_SHIFT (1U)
  2610. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_CNN0_ERROR_CLRMSK (0XFFFFFFFDU)
  2611. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_CNN0_ERROR_EN (0X00000002U)
  2612. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_CNN0_COMPLETE_SHIFT (0U)
  2613. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_CNN0_COMPLETE_CLRMSK (0XFFFFFFFEU)
  2614. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_CNN0_COMPLETE_EN (0X00000001U)
  2615. /*
  2616. Register VHA_CR_OS0_VHA_EVENT_STATUS
  2617. */
  2618. #define VHA_CR_OS0_VHA_EVENT_STATUS (0x10090U)
  2619. #define VHA_CR_OS0_VHA_EVENT_STATUS_MASKFULL (IMG_UINT64_C(0x00000000003D000B))
  2620. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_READY_SHIFT (21U)
  2621. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_READY_CLRMSK (0XFFDFFFFFU)
  2622. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_READY_EN (0X00200000U)
  2623. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_ERROR_SHIFT (20U)
  2624. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_ERROR_CLRMSK (0XFFEFFFFFU)
  2625. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_ERROR_EN (0X00100000U)
  2626. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_HL_WDT_SHIFT (19U)
  2627. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_HL_WDT_CLRMSK (0XFFF7FFFFU)
  2628. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_HL_WDT_EN (0X00080000U)
  2629. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_AXI_ERROR_SHIFT (18U)
  2630. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_AXI_ERROR_CLRMSK (0XFFFBFFFFU)
  2631. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_AXI_ERROR_EN (0X00040000U)
  2632. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_MMU_PAGE_FAULT_SHIFT (16U)
  2633. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_MMU_PAGE_FAULT_CLRMSK (0XFFFEFFFFU)
  2634. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_MMU_PAGE_FAULT_EN (0X00010000U)
  2635. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_CNN0_MEM_WDT_SHIFT (3U)
  2636. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_CNN0_MEM_WDT_CLRMSK (0XFFFFFFF7U)
  2637. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_CNN0_MEM_WDT_EN (0X00000008U)
  2638. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_CNN0_ERROR_SHIFT (1U)
  2639. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_CNN0_ERROR_CLRMSK (0XFFFFFFFDU)
  2640. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_CNN0_ERROR_EN (0X00000002U)
  2641. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_CNN0_COMPLETE_SHIFT (0U)
  2642. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_CNN0_COMPLETE_CLRMSK (0XFFFFFFFEU)
  2643. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_CNN0_COMPLETE_EN (0X00000001U)
  2644. /*
  2645. Register VHA_CR_OS0_VHA_EVENT_CLEAR
  2646. */
  2647. #define VHA_CR_OS0_VHA_EVENT_CLEAR (0x10098U)
  2648. #define VHA_CR_OS0_VHA_EVENT_CLEAR_MASKFULL (IMG_UINT64_C(0x00000000003D000B))
  2649. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_READY_SHIFT (21U)
  2650. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_READY_CLRMSK (0XFFDFFFFFU)
  2651. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_READY_EN (0X00200000U)
  2652. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_ERROR_SHIFT (20U)
  2653. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_ERROR_CLRMSK (0XFFEFFFFFU)
  2654. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_ERROR_EN (0X00100000U)
  2655. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_HL_WDT_SHIFT (19U)
  2656. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_HL_WDT_CLRMSK (0XFFF7FFFFU)
  2657. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_HL_WDT_EN (0X00080000U)
  2658. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_AXI_ERROR_SHIFT (18U)
  2659. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_AXI_ERROR_CLRMSK (0XFFFBFFFFU)
  2660. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_AXI_ERROR_EN (0X00040000U)
  2661. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_MMU_PAGE_FAULT_SHIFT (16U)
  2662. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_MMU_PAGE_FAULT_CLRMSK (0XFFFEFFFFU)
  2663. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_MMU_PAGE_FAULT_EN (0X00010000U)
  2664. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_CNN0_MEM_WDT_SHIFT (3U)
  2665. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_CNN0_MEM_WDT_CLRMSK (0XFFFFFFF7U)
  2666. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_CNN0_MEM_WDT_EN (0X00000008U)
  2667. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_CNN0_ERROR_SHIFT (1U)
  2668. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_CNN0_ERROR_CLRMSK (0XFFFFFFFDU)
  2669. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_CNN0_ERROR_EN (0X00000002U)
  2670. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_CNN0_COMPLETE_SHIFT (0U)
  2671. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_CNN0_COMPLETE_CLRMSK (0XFFFFFFFEU)
  2672. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_CNN0_COMPLETE_EN (0X00000001U)
  2673. /*
  2674. Register VHA_CR_OS0_CNN_CRC_CONTROL
  2675. */
  2676. #define VHA_CR_OS0_CNN_CRC_CONTROL (0x10100U)
  2677. #define VHA_CR_OS0_CNN_CRC_CONTROL_MASKFULL (IMG_UINT64_C(0x0000000000000003))
  2678. #define VHA_CR_OS0_CNN_CRC_CONTROL_CNN_CRC_ENABLE_SHIFT (0U)
  2679. #define VHA_CR_OS0_CNN_CRC_CONTROL_CNN_CRC_ENABLE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFC))
  2680. #define VHA_CR_OS0_CNN_CRC_CONTROL_CNN_CRC_ENABLE_DISABLE (IMG_UINT64_C(0000000000000000))
  2681. #define VHA_CR_OS0_CNN_CRC_CONTROL_CNN_CRC_ENABLE_STREAM (IMG_UINT64_C(0x0000000000000001))
  2682. #define VHA_CR_OS0_CNN_CRC_CONTROL_CNN_CRC_ENABLE_LAYER (IMG_UINT64_C(0x0000000000000002))
  2683. #define VHA_CR_OS0_CNN_CRC_CONTROL_CNN_CRC_ENABLE_PASS (IMG_UINT64_C(0x0000000000000003))
  2684. /*
  2685. Register VHA_CR_OS0_CNN_CRC_ADDRESS
  2686. */
  2687. #define VHA_CR_OS0_CNN_CRC_ADDRESS (0x10108U)
  2688. #define VHA_CR_OS0_CNN_CRC_ADDRESS_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFF00))
  2689. #define VHA_CR_OS0_CNN_CRC_ADDRESS_CNN_CRC_ADDR_SHIFT (8U)
  2690. #define VHA_CR_OS0_CNN_CRC_ADDRESS_CNN_CRC_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF00000000FF))
  2691. #define VHA_CR_OS0_CNN_CRC_ADDRESS_CNN_CRC_ADDR_ALIGNSHIFT (8U)
  2692. #define VHA_CR_OS0_CNN_CRC_ADDRESS_CNN_CRC_ADDR_ALIGNSIZE (256U)
  2693. /*
  2694. Register VHA_CR_OS0_CNN_DEBUG_ADDRESS
  2695. */
  2696. #define VHA_CR_OS0_CNN_DEBUG_ADDRESS (0x10110U)
  2697. #define VHA_CR_OS0_CNN_DEBUG_ADDRESS_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFF00))
  2698. #define VHA_CR_OS0_CNN_DEBUG_ADDRESS_CNN_DEBUG_ADDR_SHIFT (8U)
  2699. #define VHA_CR_OS0_CNN_DEBUG_ADDRESS_CNN_DEBUG_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF00000000FF))
  2700. #define VHA_CR_OS0_CNN_DEBUG_ADDRESS_CNN_DEBUG_ADDR_ALIGNSHIFT (8U)
  2701. #define VHA_CR_OS0_CNN_DEBUG_ADDRESS_CNN_DEBUG_ADDR_ALIGNSIZE (256U)
  2702. /*
  2703. Register VHA_CR_OS0_CNN_DEBUG_SIZE
  2704. */
  2705. #define VHA_CR_OS0_CNN_DEBUG_SIZE (0x10118U)
  2706. #define VHA_CR_OS0_CNN_DEBUG_SIZE_MASKFULL (IMG_UINT64_C(0x0000000000FFFFE0))
  2707. #define VHA_CR_OS0_CNN_DEBUG_SIZE_CNN_DEBUG_SIZE_SHIFT (5U)
  2708. #define VHA_CR_OS0_CNN_DEBUG_SIZE_CNN_DEBUG_SIZE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF00001F))
  2709. #define VHA_CR_OS0_CNN_DEBUG_SIZE_CNN_DEBUG_SIZE_ALIGNSHIFT (5U)
  2710. #define VHA_CR_OS0_CNN_DEBUG_SIZE_CNN_DEBUG_SIZE_ALIGNSIZE (32U)
  2711. /*
  2712. Register VHA_CR_OS0_CNN_DEBUG_CONTROL
  2713. */
  2714. #define VHA_CR_OS0_CNN_DEBUG_CONTROL (0x10120U)
  2715. #define VHA_CR_OS0_CNN_DEBUG_CONTROL_MASKFULL (IMG_UINT64_C(0x000000000000000F))
  2716. #define VHA_CR_OS0_CNN_DEBUG_CONTROL_CNN_PERF_ENABLE_SHIFT (2U)
  2717. #define VHA_CR_OS0_CNN_DEBUG_CONTROL_CNN_PERF_ENABLE_CLRMSK (0XFFFFFFF3U)
  2718. #define VHA_CR_OS0_CNN_DEBUG_CONTROL_CNN_PERF_ENABLE_DISABLE (00000000U)
  2719. #define VHA_CR_OS0_CNN_DEBUG_CONTROL_CNN_PERF_ENABLE_STREAM (0X00000004U)
  2720. #define VHA_CR_OS0_CNN_DEBUG_CONTROL_CNN_PERF_ENABLE_LAYER (0X00000008U)
  2721. #define VHA_CR_OS0_CNN_DEBUG_CONTROL_CNN_PERF_ENABLE_PASS (0X0000000CU)
  2722. #define VHA_CR_OS0_CNN_DEBUG_CONTROL_CNN_BAND_ENABLE_SHIFT (0U)
  2723. #define VHA_CR_OS0_CNN_DEBUG_CONTROL_CNN_BAND_ENABLE_CLRMSK (0XFFFFFFFCU)
  2724. #define VHA_CR_OS0_CNN_DEBUG_CONTROL_CNN_BAND_ENABLE_DISABLE (00000000U)
  2725. #define VHA_CR_OS0_CNN_DEBUG_CONTROL_CNN_BAND_ENABLE_STREAM (0X00000001U)
  2726. #define VHA_CR_OS0_CNN_DEBUG_CONTROL_CNN_BAND_ENABLE_LAYER (0X00000002U)
  2727. #define VHA_CR_OS0_CNN_DEBUG_CONTROL_CNN_BAND_ENABLE_PASS (0X00000003U)
  2728. /*
  2729. Register VHA_CR_OS0_CNN_DEBUG_STATUS
  2730. */
  2731. #define VHA_CR_OS0_CNN_DEBUG_STATUS (0x10128U)
  2732. #define VHA_CR_OS0_CNN_DEBUG_STATUS_MASKFULL (IMG_UINT64_C(0x000000000007FFFF))
  2733. #define VHA_CR_OS0_CNN_DEBUG_STATUS_CNN_DEBUG_OFFSET_SHIFT (0U)
  2734. #define VHA_CR_OS0_CNN_DEBUG_STATUS_CNN_DEBUG_OFFSET_CLRMSK (0XFFF80000U)
  2735. /*
  2736. Register VHA_CR_OS0_CNN_PRELOAD_CONTROL
  2737. */
  2738. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL (0x10130U)
  2739. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MASKFULL (IMG_UINT64_C(0x0000000001FF7777))
  2740. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_SHIFT (22U)
  2741. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFE3FFFFF))
  2742. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_DISABLE (IMG_UINT64_C(0000000000000000))
  2743. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_N_64 (IMG_UINT64_C(0x0000000000400000))
  2744. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_N_128 (IMG_UINT64_C(0x0000000000800000))
  2745. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_N_192 (IMG_UINT64_C(0x0000000000c00000))
  2746. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_N_256 (IMG_UINT64_C(0x0000000001000000))
  2747. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_N_320 (IMG_UINT64_C(0x0000000001400000))
  2748. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_N_384 (IMG_UINT64_C(0x0000000001800000))
  2749. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_N_448 (IMG_UINT64_C(0x0000000001c00000))
  2750. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_SHIFT (19U)
  2751. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFC7FFFF))
  2752. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_DISABLE (IMG_UINT64_C(0000000000000000))
  2753. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_N_64 (IMG_UINT64_C(0x0000000000080000))
  2754. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_N_128 (IMG_UINT64_C(0x0000000000100000))
  2755. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_N_192 (IMG_UINT64_C(0x0000000000180000))
  2756. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_N_256 (IMG_UINT64_C(0x0000000000200000))
  2757. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_N_320 (IMG_UINT64_C(0x0000000000280000))
  2758. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_N_384 (IMG_UINT64_C(0x0000000000300000))
  2759. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_N_448 (IMG_UINT64_C(0x0000000000380000))
  2760. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_SHIFT (16U)
  2761. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF8FFFF))
  2762. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_DISABLE (IMG_UINT64_C(0000000000000000))
  2763. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_N_64 (IMG_UINT64_C(0x0000000000010000))
  2764. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_N_128 (IMG_UINT64_C(0x0000000000020000))
  2765. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_N_192 (IMG_UINT64_C(0x0000000000030000))
  2766. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_N_256 (IMG_UINT64_C(0x0000000000040000))
  2767. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_N_320 (IMG_UINT64_C(0x0000000000050000))
  2768. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_N_384 (IMG_UINT64_C(0x0000000000060000))
  2769. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_N_448 (IMG_UINT64_C(0x0000000000070000))
  2770. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_EWO_N_REQS_SHIFT (12U)
  2771. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_EWO_N_REQS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF8FFF))
  2772. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_EWO_N_REQS_DISABLE (IMG_UINT64_C(0000000000000000))
  2773. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_EWO_N_REQS_N_64 (IMG_UINT64_C(0x0000000000001000))
  2774. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_EWO_N_REQS_N_128 (IMG_UINT64_C(0x0000000000002000))
  2775. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_EWO_N_REQS_N_192 (IMG_UINT64_C(0x0000000000003000))
  2776. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_EWO_N_REQS_N_256 (IMG_UINT64_C(0x0000000000004000))
  2777. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_EWO_N_REQS_N_320 (IMG_UINT64_C(0x0000000000005000))
  2778. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_EWO_N_REQS_N_384 (IMG_UINT64_C(0x0000000000006000))
  2779. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_EWO_N_REQS_N_448 (IMG_UINT64_C(0x0000000000007000))
  2780. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_ABUF_N_REQS_SHIFT (8U)
  2781. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_ABUF_N_REQS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF8FF))
  2782. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_ABUF_N_REQS_DISABLE (IMG_UINT64_C(0000000000000000))
  2783. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_ABUF_N_REQS_N_64 (IMG_UINT64_C(0x0000000000000100))
  2784. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_ABUF_N_REQS_N_128 (IMG_UINT64_C(0x0000000000000200))
  2785. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_ABUF_N_REQS_N_192 (IMG_UINT64_C(0x0000000000000300))
  2786. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_ABUF_N_REQS_N_256 (IMG_UINT64_C(0x0000000000000400))
  2787. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_ABUF_N_REQS_N_320 (IMG_UINT64_C(0x0000000000000500))
  2788. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_ABUF_N_REQS_N_384 (IMG_UINT64_C(0x0000000000000600))
  2789. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_ABUF_N_REQS_N_448 (IMG_UINT64_C(0x0000000000000700))
  2790. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_CBUF_N_REQS_SHIFT (4U)
  2791. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_CBUF_N_REQS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFF8F))
  2792. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_CBUF_N_REQS_DISABLE (IMG_UINT64_C(0000000000000000))
  2793. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_CBUF_N_REQS_N_64 (IMG_UINT64_C(0x0000000000000010))
  2794. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_CBUF_N_REQS_N_128 (IMG_UINT64_C(0x0000000000000020))
  2795. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_CBUF_N_REQS_N_192 (IMG_UINT64_C(0x0000000000000030))
  2796. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_CBUF_N_REQS_N_256 (IMG_UINT64_C(0x0000000000000040))
  2797. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_CBUF_N_REQS_N_320 (IMG_UINT64_C(0x0000000000000050))
  2798. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_CBUF_N_REQS_N_384 (IMG_UINT64_C(0x0000000000000060))
  2799. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_CBUF_N_REQS_N_448 (IMG_UINT64_C(0x0000000000000070))
  2800. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_IBUF_N_REQS_SHIFT (0U)
  2801. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_IBUF_N_REQS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF8))
  2802. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_IBUF_N_REQS_DISABLE (IMG_UINT64_C(0000000000000000))
  2803. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_IBUF_N_REQS_N_64 (IMG_UINT64_C(0x0000000000000001))
  2804. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_IBUF_N_REQS_N_128 (IMG_UINT64_C(0x0000000000000002))
  2805. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_IBUF_N_REQS_N_192 (IMG_UINT64_C(0x0000000000000003))
  2806. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_IBUF_N_REQS_N_256 (IMG_UINT64_C(0x0000000000000004))
  2807. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_IBUF_N_REQS_N_320 (IMG_UINT64_C(0x0000000000000005))
  2808. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_IBUF_N_REQS_N_384 (IMG_UINT64_C(0x0000000000000006))
  2809. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_IBUF_N_REQS_N_448 (IMG_UINT64_C(0x0000000000000007))
  2810. /*
  2811. Register VHA_CR_OS0_CNN_ALT_ADDRESS8
  2812. */
  2813. #define VHA_CR_OS0_CNN_ALT_ADDRESS8 (0x10140U)
  2814. #define VHA_CR_OS0_CNN_ALT_ADDRESS8_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  2815. #define VHA_CR_OS0_CNN_ALT_ADDRESS8_ALT_ADDR_SHIFT (0U)
  2816. #define VHA_CR_OS0_CNN_ALT_ADDRESS8_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  2817. /*
  2818. Register VHA_CR_OS0_CNN_ALT_ADDRESS9
  2819. */
  2820. #define VHA_CR_OS0_CNN_ALT_ADDRESS9 (0x10148U)
  2821. #define VHA_CR_OS0_CNN_ALT_ADDRESS9_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  2822. #define VHA_CR_OS0_CNN_ALT_ADDRESS9_ALT_ADDR_SHIFT (0U)
  2823. #define VHA_CR_OS0_CNN_ALT_ADDRESS9_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  2824. /*
  2825. Register VHA_CR_OS0_CNN_ALT_ADDRESS10
  2826. */
  2827. #define VHA_CR_OS0_CNN_ALT_ADDRESS10 (0x10150U)
  2828. #define VHA_CR_OS0_CNN_ALT_ADDRESS10_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  2829. #define VHA_CR_OS0_CNN_ALT_ADDRESS10_ALT_ADDR_SHIFT (0U)
  2830. #define VHA_CR_OS0_CNN_ALT_ADDRESS10_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  2831. /*
  2832. Register VHA_CR_OS0_CNN_ALT_ADDRESS11
  2833. */
  2834. #define VHA_CR_OS0_CNN_ALT_ADDRESS11 (0x10158U)
  2835. #define VHA_CR_OS0_CNN_ALT_ADDRESS11_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  2836. #define VHA_CR_OS0_CNN_ALT_ADDRESS11_ALT_ADDR_SHIFT (0U)
  2837. #define VHA_CR_OS0_CNN_ALT_ADDRESS11_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  2838. /*
  2839. Register VHA_CR_OS0_CNN_ALT_ADDRESS12
  2840. */
  2841. #define VHA_CR_OS0_CNN_ALT_ADDRESS12 (0x10160U)
  2842. #define VHA_CR_OS0_CNN_ALT_ADDRESS12_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  2843. #define VHA_CR_OS0_CNN_ALT_ADDRESS12_ALT_ADDR_SHIFT (0U)
  2844. #define VHA_CR_OS0_CNN_ALT_ADDRESS12_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  2845. /*
  2846. Register VHA_CR_OS0_CNN_ALT_ADDRESS13
  2847. */
  2848. #define VHA_CR_OS0_CNN_ALT_ADDRESS13 (0x10168U)
  2849. #define VHA_CR_OS0_CNN_ALT_ADDRESS13_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  2850. #define VHA_CR_OS0_CNN_ALT_ADDRESS13_ALT_ADDR_SHIFT (0U)
  2851. #define VHA_CR_OS0_CNN_ALT_ADDRESS13_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  2852. /*
  2853. Register VHA_CR_OS0_CNN_ALT_ADDRESS14
  2854. */
  2855. #define VHA_CR_OS0_CNN_ALT_ADDRESS14 (0x10170U)
  2856. #define VHA_CR_OS0_CNN_ALT_ADDRESS14_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  2857. #define VHA_CR_OS0_CNN_ALT_ADDRESS14_ALT_ADDR_SHIFT (0U)
  2858. #define VHA_CR_OS0_CNN_ALT_ADDRESS14_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  2859. /*
  2860. Register VHA_CR_OS0_CNN_ALT_ADDRESS15
  2861. */
  2862. #define VHA_CR_OS0_CNN_ALT_ADDRESS15 (0x10178U)
  2863. #define VHA_CR_OS0_CNN_ALT_ADDRESS15_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  2864. #define VHA_CR_OS0_CNN_ALT_ADDRESS15_ALT_ADDR_SHIFT (0U)
  2865. #define VHA_CR_OS0_CNN_ALT_ADDRESS15_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  2866. /*
  2867. Register VHA_CR_OS0_CNN_PERFORMANCE
  2868. */
  2869. #define VHA_CR_OS0_CNN_PERFORMANCE (0x101A0U)
  2870. #define VHA_CR_OS0_CNN_PERFORMANCE_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  2871. #define VHA_CR_OS0_CNN_PERFORMANCE_VALUE_SHIFT (0U)
  2872. #define VHA_CR_OS0_CNN_PERFORMANCE_VALUE_CLRMSK (00000000U)
  2873. /*
  2874. Register VHA_CR_OS0_MMU_CTRL_INVAL
  2875. */
  2876. #define VHA_CR_OS0_MMU_CTRL_INVAL (0x1E000U)
  2877. #define VHA_CR_OS0_MMU_CTRL_INVAL_MASKFULL (IMG_UINT64_C(0x0000000000000FFF))
  2878. #define VHA_CR_OS0_MMU_CTRL_INVAL_ALL_CONTEXTS_SHIFT (11U)
  2879. #define VHA_CR_OS0_MMU_CTRL_INVAL_ALL_CONTEXTS_CLRMSK (0XFFFFF7FFU)
  2880. #define VHA_CR_OS0_MMU_CTRL_INVAL_ALL_CONTEXTS_EN (0X00000800U)
  2881. #define VHA_CR_OS0_MMU_CTRL_INVAL_CONTEXT_SHIFT (3U)
  2882. #define VHA_CR_OS0_MMU_CTRL_INVAL_CONTEXT_CLRMSK (0XFFFFF807U)
  2883. #define VHA_CR_OS0_MMU_CTRL_INVAL_PC_SHIFT (2U)
  2884. #define VHA_CR_OS0_MMU_CTRL_INVAL_PC_CLRMSK (0XFFFFFFFBU)
  2885. #define VHA_CR_OS0_MMU_CTRL_INVAL_PC_EN (0X00000004U)
  2886. #define VHA_CR_OS0_MMU_CTRL_INVAL_PD_SHIFT (1U)
  2887. #define VHA_CR_OS0_MMU_CTRL_INVAL_PD_CLRMSK (0XFFFFFFFDU)
  2888. #define VHA_CR_OS0_MMU_CTRL_INVAL_PD_EN (0X00000002U)
  2889. #define VHA_CR_OS0_MMU_CTRL_INVAL_PT_SHIFT (0U)
  2890. #define VHA_CR_OS0_MMU_CTRL_INVAL_PT_CLRMSK (0XFFFFFFFEU)
  2891. #define VHA_CR_OS0_MMU_CTRL_INVAL_PT_EN (0X00000001U)
  2892. /*
  2893. Register VHA_CR_OS0_MMU_CTRL_INVAL_STATUS
  2894. */
  2895. #define VHA_CR_OS0_MMU_CTRL_INVAL_STATUS (0x1E038U)
  2896. #define VHA_CR_OS0_MMU_CTRL_INVAL_STATUS_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  2897. #define VHA_CR_OS0_MMU_CTRL_INVAL_STATUS_PENDING_SHIFT (0U)
  2898. #define VHA_CR_OS0_MMU_CTRL_INVAL_STATUS_PENDING_CLRMSK (0XFFFFFFFEU)
  2899. #define VHA_CR_OS0_MMU_CTRL_INVAL_STATUS_PENDING_EN (0X00000001U)
  2900. /*
  2901. Register VHA_CR_OS0_MMU_CBASE_MAPPING_CONTEXT
  2902. */
  2903. #define VHA_CR_OS0_MMU_CBASE_MAPPING_CONTEXT (0x1E008U)
  2904. #define VHA_CR_OS0_MMU_CBASE_MAPPING_CONTEXT_MASKFULL (IMG_UINT64_C(0x00000000000000FF))
  2905. #define VHA_CR_OS0_MMU_CBASE_MAPPING_CONTEXT_ID_SHIFT (0U)
  2906. #define VHA_CR_OS0_MMU_CBASE_MAPPING_CONTEXT_ID_CLRMSK (0XFFFFFF00U)
  2907. /*
  2908. Register VHA_CR_OS0_MMU_CBASE_MAPPING
  2909. */
  2910. #define VHA_CR_OS0_MMU_CBASE_MAPPING (0x1E010U)
  2911. #define VHA_CR_OS0_MMU_CBASE_MAPPING_MASKFULL (IMG_UINT64_C(0x000000001FFFFFFF))
  2912. #define VHA_CR_OS0_MMU_CBASE_MAPPING_INVALID_SHIFT (28U)
  2913. #define VHA_CR_OS0_MMU_CBASE_MAPPING_INVALID_CLRMSK (0XEFFFFFFFU)
  2914. #define VHA_CR_OS0_MMU_CBASE_MAPPING_INVALID_EN (0X10000000U)
  2915. #define VHA_CR_OS0_MMU_CBASE_MAPPING_BASE_ADDR_SHIFT (0U)
  2916. #define VHA_CR_OS0_MMU_CBASE_MAPPING_BASE_ADDR_CLRMSK (0XF0000000U)
  2917. #define VHA_CR_OS0_MMU_CBASE_MAPPING_BASE_ADDR_ALIGNSHIFT (12U)
  2918. #define VHA_CR_OS0_MMU_CBASE_MAPPING_BASE_ADDR_ALIGNSIZE (4096U)
  2919. /*
  2920. Register VHA_CR_OS0_MMU_FAULT_STATUS1
  2921. */
  2922. #define VHA_CR_OS0_MMU_FAULT_STATUS1 (0x1E018U)
  2923. #define VHA_CR_OS0_MMU_FAULT_STATUS1_MASKFULL (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
  2924. #define VHA_CR_OS0_MMU_FAULT_STATUS1_LEVEL_SHIFT (62U)
  2925. #define VHA_CR_OS0_MMU_FAULT_STATUS1_LEVEL_CLRMSK (IMG_UINT64_C(0X3FFFFFFFFFFFFFFF))
  2926. #define VHA_CR_OS0_MMU_FAULT_STATUS1_REQ_ID_SHIFT (56U)
  2927. #define VHA_CR_OS0_MMU_FAULT_STATUS1_REQ_ID_CLRMSK (IMG_UINT64_C(0XC0FFFFFFFFFFFFFF))
  2928. #define VHA_CR_OS0_MMU_FAULT_STATUS1_CONTEXT_SHIFT (48U)
  2929. #define VHA_CR_OS0_MMU_FAULT_STATUS1_CONTEXT_CLRMSK (IMG_UINT64_C(0XFF00FFFFFFFFFFFF))
  2930. #define VHA_CR_OS0_MMU_FAULT_STATUS1_ADDRESS_SHIFT (4U)
  2931. #define VHA_CR_OS0_MMU_FAULT_STATUS1_ADDRESS_CLRMSK (IMG_UINT64_C(0XFFFF00000000000F))
  2932. #define VHA_CR_OS0_MMU_FAULT_STATUS1_RNW_SHIFT (3U)
  2933. #define VHA_CR_OS0_MMU_FAULT_STATUS1_RNW_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF7))
  2934. #define VHA_CR_OS0_MMU_FAULT_STATUS1_RNW_EN (IMG_UINT64_C(0X0000000000000008))
  2935. #define VHA_CR_OS0_MMU_FAULT_STATUS1_TYPE_SHIFT (1U)
  2936. #define VHA_CR_OS0_MMU_FAULT_STATUS1_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF9))
  2937. #define VHA_CR_OS0_MMU_FAULT_STATUS1_FAULT_SHIFT (0U)
  2938. #define VHA_CR_OS0_MMU_FAULT_STATUS1_FAULT_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  2939. #define VHA_CR_OS0_MMU_FAULT_STATUS1_FAULT_EN (IMG_UINT64_C(0X0000000000000001))
  2940. /*
  2941. Register VHA_CR_OS0_MMU_FAULT_STATUS2
  2942. */
  2943. #define VHA_CR_OS0_MMU_FAULT_STATUS2 (0x1E020U)
  2944. #define VHA_CR_OS0_MMU_FAULT_STATUS2_MASKFULL (IMG_UINT64_C(0x000000003FFF07FF))
  2945. #define VHA_CR_OS0_MMU_FAULT_STATUS2_WRITEBACK_SHIFT (29U)
  2946. #define VHA_CR_OS0_MMU_FAULT_STATUS2_WRITEBACK_CLRMSK (0XDFFFFFFFU)
  2947. #define VHA_CR_OS0_MMU_FAULT_STATUS2_WRITEBACK_EN (0X20000000U)
  2948. #define VHA_CR_OS0_MMU_FAULT_STATUS2_CLEANUNIQUE_SHIFT (28U)
  2949. #define VHA_CR_OS0_MMU_FAULT_STATUS2_CLEANUNIQUE_CLRMSK (0XEFFFFFFFU)
  2950. #define VHA_CR_OS0_MMU_FAULT_STATUS2_CLEANUNIQUE_EN (0X10000000U)
  2951. #define VHA_CR_OS0_MMU_FAULT_STATUS2_BANK_SHIFT (24U)
  2952. #define VHA_CR_OS0_MMU_FAULT_STATUS2_BANK_CLRMSK (0XF0FFFFFFU)
  2953. #define VHA_CR_OS0_MMU_FAULT_STATUS2_TLB_ENTRY_SHIFT (16U)
  2954. #define VHA_CR_OS0_MMU_FAULT_STATUS2_TLB_ENTRY_CLRMSK (0XFF00FFFFU)
  2955. #define VHA_CR_OS0_MMU_FAULT_STATUS2_FBM_FAULT_SHIFT (10U)
  2956. #define VHA_CR_OS0_MMU_FAULT_STATUS2_FBM_FAULT_CLRMSK (0XFFFFFBFFU)
  2957. #define VHA_CR_OS0_MMU_FAULT_STATUS2_FBM_FAULT_EN (0X00000400U)
  2958. #define VHA_CR_OS0_MMU_FAULT_STATUS2_BIF_ID_SHIFT (0U)
  2959. #define VHA_CR_OS0_MMU_FAULT_STATUS2_BIF_ID_CLRMSK (0XFFFFFC00U)
  2960. /*
  2961. Register VHA_CR_OS0_MMU_CTRL_LEGACY
  2962. */
  2963. #define VHA_CR_OS0_MMU_CTRL_LEGACY (0x1E040U)
  2964. #define VHA_CR_OS0_MMU_CTRL_LEGACY_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  2965. #define VHA_CR_OS0_MMU_CTRL_LEGACY_RESERVED_SHIFT (0U)
  2966. #define VHA_CR_OS0_MMU_CTRL_LEGACY_RESERVED_CLRMSK (0XFFFFFFFEU)
  2967. #define VHA_CR_OS0_MMU_CTRL_LEGACY_RESERVED_EN (0X00000001U)
  2968. /*
  2969. Register VHA_CR_OS1_CNN_CONTROL
  2970. */
  2971. #define VHA_CR_OS1_CNN_CONTROL (0x20000U)
  2972. #define VHA_CR_OS1_CNN_CONTROL_MASKFULL (IMG_UINT64_C(0x000000000000337F))
  2973. #define VHA_CR_OS1_CNN_CONTROL_CTXT_PASID_SHIFT (12U)
  2974. #define VHA_CR_OS1_CNN_CONTROL_CTXT_PASID_CLRMSK (0XFFFFCFFFU)
  2975. #define VHA_CR_OS1_CNN_CONTROL_PRIORITY_SHIFT (8U)
  2976. #define VHA_CR_OS1_CNN_CONTROL_PRIORITY_CLRMSK (0XFFFFFCFFU)
  2977. #define VHA_CR_OS1_CNN_CONTROL_CMD_SIZE_MIN1_SHIFT (1U)
  2978. #define VHA_CR_OS1_CNN_CONTROL_CMD_SIZE_MIN1_CLRMSK (0XFFFFFF81U)
  2979. #define VHA_CR_OS1_CNN_CONTROL_START_SHIFT (0U)
  2980. #define VHA_CR_OS1_CNN_CONTROL_START_CLRMSK (0XFFFFFFFEU)
  2981. #define VHA_CR_OS1_CNN_CONTROL_START_EN (0X00000001U)
  2982. #define VHA_CR_OS1_CNN_STATUS_STATE_MASK (0x00000003U)
  2983. /*
  2984. No requests are pending for this host*/
  2985. #define VHA_CR_OS1_CNN_STATUS_STATE_IDLE (0x00000000U)
  2986. /*
  2987. A command stream from this host is being processed*/
  2988. #define VHA_CR_OS1_CNN_STATUS_STATE_RUN (0x00000001U)
  2989. /*
  2990. The command stream from this host has been suspended due to higher priority request from another host*/
  2991. #define VHA_CR_OS1_CNN_STATUS_STATE_SUSPEND (0x00000002U)
  2992. /*
  2993. A command stream from this host is pending but not been started */
  2994. #define VHA_CR_OS1_CNN_STATUS_STATE_PENDING (0x00000003U)
  2995. /*
  2996. Register VHA_CR_OS1_CNN_STATUS
  2997. */
  2998. #define VHA_CR_OS1_CNN_STATUS (0x20008U)
  2999. #define VHA_CR_OS1_CNN_STATUS_MASKFULL (IMG_UINT64_C(0x00000000C0FFFFFF))
  3000. #define VHA_CR_OS1_CNN_STATUS_CURRENT_STATE_SHIFT (30U)
  3001. #define VHA_CR_OS1_CNN_STATUS_CURRENT_STATE_CLRMSK (0X3FFFFFFFU)
  3002. #define VHA_CR_OS1_CNN_STATUS_CURRENT_STATE_IDLE (00000000U)
  3003. #define VHA_CR_OS1_CNN_STATUS_CURRENT_STATE_RUN (0X40000000U)
  3004. #define VHA_CR_OS1_CNN_STATUS_CURRENT_STATE_SUSPEND (0X80000000U)
  3005. #define VHA_CR_OS1_CNN_STATUS_CURRENT_STATE_PENDING (0XC0000000U)
  3006. #define VHA_CR_OS1_CNN_STATUS_PASS_COUNT_SHIFT (16U)
  3007. #define VHA_CR_OS1_CNN_STATUS_PASS_COUNT_CLRMSK (0XFF00FFFFU)
  3008. #define VHA_CR_OS1_CNN_STATUS_LAYER_COUNT_SHIFT (8U)
  3009. #define VHA_CR_OS1_CNN_STATUS_LAYER_COUNT_CLRMSK (0XFFFF00FFU)
  3010. #define VHA_CR_OS1_CNN_STATUS_STREAM_COUNT_SHIFT (0U)
  3011. #define VHA_CR_OS1_CNN_STATUS_STREAM_COUNT_CLRMSK (0XFFFFFF00U)
  3012. /*
  3013. Register VHA_CR_OS1_CNN_CMD_BASE_ADDRESS
  3014. */
  3015. #define VHA_CR_OS1_CNN_CMD_BASE_ADDRESS (0x20020U)
  3016. #define VHA_CR_OS1_CNN_CMD_BASE_ADDRESS_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFF00))
  3017. #define VHA_CR_OS1_CNN_CMD_BASE_ADDRESS_BASE_ADDR_SHIFT (8U)
  3018. #define VHA_CR_OS1_CNN_CMD_BASE_ADDRESS_BASE_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF00000000FF))
  3019. /*
  3020. Register VHA_CR_OS1_CNN_ALT_ADDRESS_USED
  3021. */
  3022. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED (0x20038U)
  3023. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  3024. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR15_BUF_TYPE_SHIFT (31U)
  3025. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR15_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFF7FFFFFFF))
  3026. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR15_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  3027. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR15_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000080000000))
  3028. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR14_BUF_TYPE_SHIFT (30U)
  3029. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR14_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFBFFFFFFF))
  3030. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR14_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  3031. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR14_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000040000000))
  3032. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR13_BUF_TYPE_SHIFT (29U)
  3033. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR13_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFDFFFFFFF))
  3034. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR13_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  3035. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR13_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000020000000))
  3036. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR12_BUF_TYPE_SHIFT (28U)
  3037. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR12_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFEFFFFFFF))
  3038. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR12_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  3039. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR12_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000010000000))
  3040. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR11_BUF_TYPE_SHIFT (27U)
  3041. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR11_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFF7FFFFFF))
  3042. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR11_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  3043. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR11_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000008000000))
  3044. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR10_BUF_TYPE_SHIFT (26U)
  3045. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR10_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFBFFFFFF))
  3046. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR10_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  3047. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR10_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000004000000))
  3048. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR9_BUF_TYPE_SHIFT (25U)
  3049. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR9_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFDFFFFFF))
  3050. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR9_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  3051. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR9_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000002000000))
  3052. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR8_BUF_TYPE_SHIFT (24U)
  3053. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR8_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFEFFFFFF))
  3054. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR8_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  3055. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR8_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000001000000))
  3056. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR7_BUF_TYPE_SHIFT (23U)
  3057. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR7_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF7FFFFF))
  3058. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR7_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  3059. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR7_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000000800000))
  3060. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR6_BUF_TYPE_SHIFT (22U)
  3061. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR6_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFBFFFFF))
  3062. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR6_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  3063. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR6_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000000400000))
  3064. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR5_BUF_TYPE_SHIFT (21U)
  3065. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR5_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFDFFFFF))
  3066. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR5_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  3067. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR5_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000000200000))
  3068. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR4_BUF_TYPE_SHIFT (20U)
  3069. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR4_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFEFFFFF))
  3070. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR4_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  3071. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR4_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000000100000))
  3072. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR3_BUF_TYPE_SHIFT (19U)
  3073. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR3_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF7FFFF))
  3074. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR3_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  3075. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR3_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000000080000))
  3076. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR2_BUF_TYPE_SHIFT (18U)
  3077. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR2_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFBFFFF))
  3078. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR2_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  3079. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR2_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000000040000))
  3080. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR1_BUF_TYPE_SHIFT (17U)
  3081. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR1_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFDFFFF))
  3082. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR1_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  3083. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR1_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000000020000))
  3084. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR0_BUF_TYPE_SHIFT (16U)
  3085. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR0_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFEFFFF))
  3086. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR0_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  3087. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR0_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000000010000))
  3088. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR15_USED_SHIFT (15U)
  3089. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR15_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF7FFF))
  3090. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR15_USED_EN (IMG_UINT64_C(0X0000000000008000))
  3091. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR14_USED_SHIFT (14U)
  3092. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR14_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFBFFF))
  3093. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR14_USED_EN (IMG_UINT64_C(0X0000000000004000))
  3094. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR13_USED_SHIFT (13U)
  3095. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR13_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFDFFF))
  3096. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR13_USED_EN (IMG_UINT64_C(0X0000000000002000))
  3097. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR12_USED_SHIFT (12U)
  3098. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR12_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFEFFF))
  3099. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR12_USED_EN (IMG_UINT64_C(0X0000000000001000))
  3100. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR11_USED_SHIFT (11U)
  3101. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR11_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF7FF))
  3102. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR11_USED_EN (IMG_UINT64_C(0X0000000000000800))
  3103. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR10_USED_SHIFT (10U)
  3104. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR10_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFBFF))
  3105. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR10_USED_EN (IMG_UINT64_C(0X0000000000000400))
  3106. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR9_USED_SHIFT (9U)
  3107. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR9_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFDFF))
  3108. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR9_USED_EN (IMG_UINT64_C(0X0000000000000200))
  3109. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR8_USED_SHIFT (8U)
  3110. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR8_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFEFF))
  3111. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR8_USED_EN (IMG_UINT64_C(0X0000000000000100))
  3112. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR7_USED_SHIFT (7U)
  3113. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR7_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFF7F))
  3114. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR7_USED_EN (IMG_UINT64_C(0X0000000000000080))
  3115. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR6_USED_SHIFT (6U)
  3116. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR6_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFBF))
  3117. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR6_USED_EN (IMG_UINT64_C(0X0000000000000040))
  3118. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR5_USED_SHIFT (5U)
  3119. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR5_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFDF))
  3120. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR5_USED_EN (IMG_UINT64_C(0X0000000000000020))
  3121. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR4_USED_SHIFT (4U)
  3122. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR4_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFEF))
  3123. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR4_USED_EN (IMG_UINT64_C(0X0000000000000010))
  3124. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR3_USED_SHIFT (3U)
  3125. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR3_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF7))
  3126. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR3_USED_EN (IMG_UINT64_C(0X0000000000000008))
  3127. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR2_USED_SHIFT (2U)
  3128. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR2_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFB))
  3129. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR2_USED_EN (IMG_UINT64_C(0X0000000000000004))
  3130. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR1_USED_SHIFT (1U)
  3131. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR1_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFD))
  3132. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR1_USED_EN (IMG_UINT64_C(0X0000000000000002))
  3133. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR0_USED_SHIFT (0U)
  3134. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR0_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  3135. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR0_USED_EN (IMG_UINT64_C(0X0000000000000001))
  3136. /*
  3137. Register VHA_CR_OS1_CNN_ALT_ADDRESS0
  3138. */
  3139. #define VHA_CR_OS1_CNN_ALT_ADDRESS0 (0x20040U)
  3140. #define VHA_CR_OS1_CNN_ALT_ADDRESS0_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  3141. #define VHA_CR_OS1_CNN_ALT_ADDRESS0_ALT_ADDR_SHIFT (0U)
  3142. #define VHA_CR_OS1_CNN_ALT_ADDRESS0_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  3143. /*
  3144. Register VHA_CR_OS1_CNN_ALT_ADDRESS1
  3145. */
  3146. #define VHA_CR_OS1_CNN_ALT_ADDRESS1 (0x20048U)
  3147. #define VHA_CR_OS1_CNN_ALT_ADDRESS1_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  3148. #define VHA_CR_OS1_CNN_ALT_ADDRESS1_ALT_ADDR_SHIFT (0U)
  3149. #define VHA_CR_OS1_CNN_ALT_ADDRESS1_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  3150. /*
  3151. Register VHA_CR_OS1_CNN_ALT_ADDRESS2
  3152. */
  3153. #define VHA_CR_OS1_CNN_ALT_ADDRESS2 (0x20050U)
  3154. #define VHA_CR_OS1_CNN_ALT_ADDRESS2_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  3155. #define VHA_CR_OS1_CNN_ALT_ADDRESS2_ALT_ADDR_SHIFT (0U)
  3156. #define VHA_CR_OS1_CNN_ALT_ADDRESS2_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  3157. /*
  3158. Register VHA_CR_OS1_CNN_ALT_ADDRESS3
  3159. */
  3160. #define VHA_CR_OS1_CNN_ALT_ADDRESS3 (0x20058U)
  3161. #define VHA_CR_OS1_CNN_ALT_ADDRESS3_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  3162. #define VHA_CR_OS1_CNN_ALT_ADDRESS3_ALT_ADDR_SHIFT (0U)
  3163. #define VHA_CR_OS1_CNN_ALT_ADDRESS3_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  3164. /*
  3165. Register VHA_CR_OS1_CNN_ALT_ADDRESS4
  3166. */
  3167. #define VHA_CR_OS1_CNN_ALT_ADDRESS4 (0x20060U)
  3168. #define VHA_CR_OS1_CNN_ALT_ADDRESS4_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  3169. #define VHA_CR_OS1_CNN_ALT_ADDRESS4_ALT_ADDR_SHIFT (0U)
  3170. #define VHA_CR_OS1_CNN_ALT_ADDRESS4_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  3171. /*
  3172. Register VHA_CR_OS1_CNN_ALT_ADDRESS5
  3173. */
  3174. #define VHA_CR_OS1_CNN_ALT_ADDRESS5 (0x20068U)
  3175. #define VHA_CR_OS1_CNN_ALT_ADDRESS5_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  3176. #define VHA_CR_OS1_CNN_ALT_ADDRESS5_ALT_ADDR_SHIFT (0U)
  3177. #define VHA_CR_OS1_CNN_ALT_ADDRESS5_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  3178. /*
  3179. Register VHA_CR_OS1_CNN_ALT_ADDRESS6
  3180. */
  3181. #define VHA_CR_OS1_CNN_ALT_ADDRESS6 (0x20070U)
  3182. #define VHA_CR_OS1_CNN_ALT_ADDRESS6_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  3183. #define VHA_CR_OS1_CNN_ALT_ADDRESS6_ALT_ADDR_SHIFT (0U)
  3184. #define VHA_CR_OS1_CNN_ALT_ADDRESS6_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  3185. /*
  3186. Register VHA_CR_OS1_CNN_ALT_ADDRESS7
  3187. */
  3188. #define VHA_CR_OS1_CNN_ALT_ADDRESS7 (0x20078U)
  3189. #define VHA_CR_OS1_CNN_ALT_ADDRESS7_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  3190. #define VHA_CR_OS1_CNN_ALT_ADDRESS7_ALT_ADDR_SHIFT (0U)
  3191. #define VHA_CR_OS1_CNN_ALT_ADDRESS7_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  3192. /*
  3193. Register VHA_CR_OS1_CNN_WRITEBACK_CONTROL
  3194. */
  3195. #define VHA_CR_OS1_CNN_WRITEBACK_CONTROL (0x20080U)
  3196. #define VHA_CR_OS1_CNN_WRITEBACK_CONTROL_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  3197. #define VHA_CR_OS1_CNN_WRITEBACK_CONTROL_WRITE_BACK_VALUE_SHIFT (0U)
  3198. #define VHA_CR_OS1_CNN_WRITEBACK_CONTROL_WRITE_BACK_VALUE_CLRMSK (00000000U)
  3199. /*
  3200. Register VHA_CR_OS1_VHA_EVENT_ENABLE
  3201. */
  3202. #define VHA_CR_OS1_VHA_EVENT_ENABLE (0x20088U)
  3203. #define VHA_CR_OS1_VHA_EVENT_ENABLE_MASKFULL (IMG_UINT64_C(0x00000000003D000B))
  3204. #define VHA_CR_OS1_VHA_EVENT_ENABLE_VHA_READY_SHIFT (21U)
  3205. #define VHA_CR_OS1_VHA_EVENT_ENABLE_VHA_READY_CLRMSK (0XFFDFFFFFU)
  3206. #define VHA_CR_OS1_VHA_EVENT_ENABLE_VHA_READY_EN (0X00200000U)
  3207. #define VHA_CR_OS1_VHA_EVENT_ENABLE_VHA_ERROR_SHIFT (20U)
  3208. #define VHA_CR_OS1_VHA_EVENT_ENABLE_VHA_ERROR_CLRMSK (0XFFEFFFFFU)
  3209. #define VHA_CR_OS1_VHA_EVENT_ENABLE_VHA_ERROR_EN (0X00100000U)
  3210. #define VHA_CR_OS1_VHA_EVENT_ENABLE_VHA_HL_WDT_SHIFT (19U)
  3211. #define VHA_CR_OS1_VHA_EVENT_ENABLE_VHA_HL_WDT_CLRMSK (0XFFF7FFFFU)
  3212. #define VHA_CR_OS1_VHA_EVENT_ENABLE_VHA_HL_WDT_EN (0X00080000U)
  3213. #define VHA_CR_OS1_VHA_EVENT_ENABLE_VHA_AXI_ERROR_SHIFT (18U)
  3214. #define VHA_CR_OS1_VHA_EVENT_ENABLE_VHA_AXI_ERROR_CLRMSK (0XFFFBFFFFU)
  3215. #define VHA_CR_OS1_VHA_EVENT_ENABLE_VHA_AXI_ERROR_EN (0X00040000U)
  3216. #define VHA_CR_OS1_VHA_EVENT_ENABLE_VHA_MMU_PAGE_FAULT_SHIFT (16U)
  3217. #define VHA_CR_OS1_VHA_EVENT_ENABLE_VHA_MMU_PAGE_FAULT_CLRMSK (0XFFFEFFFFU)
  3218. #define VHA_CR_OS1_VHA_EVENT_ENABLE_VHA_MMU_PAGE_FAULT_EN (0X00010000U)
  3219. #define VHA_CR_OS1_VHA_EVENT_ENABLE_VHA_CNN0_MEM_WDT_SHIFT (3U)
  3220. #define VHA_CR_OS1_VHA_EVENT_ENABLE_VHA_CNN0_MEM_WDT_CLRMSK (0XFFFFFFF7U)
  3221. #define VHA_CR_OS1_VHA_EVENT_ENABLE_VHA_CNN0_MEM_WDT_EN (0X00000008U)
  3222. #define VHA_CR_OS1_VHA_EVENT_ENABLE_VHA_CNN0_ERROR_SHIFT (1U)
  3223. #define VHA_CR_OS1_VHA_EVENT_ENABLE_VHA_CNN0_ERROR_CLRMSK (0XFFFFFFFDU)
  3224. #define VHA_CR_OS1_VHA_EVENT_ENABLE_VHA_CNN0_ERROR_EN (0X00000002U)
  3225. #define VHA_CR_OS1_VHA_EVENT_ENABLE_VHA_CNN0_COMPLETE_SHIFT (0U)
  3226. #define VHA_CR_OS1_VHA_EVENT_ENABLE_VHA_CNN0_COMPLETE_CLRMSK (0XFFFFFFFEU)
  3227. #define VHA_CR_OS1_VHA_EVENT_ENABLE_VHA_CNN0_COMPLETE_EN (0X00000001U)
  3228. /*
  3229. Register VHA_CR_OS1_VHA_EVENT_STATUS
  3230. */
  3231. #define VHA_CR_OS1_VHA_EVENT_STATUS (0x20090U)
  3232. #define VHA_CR_OS1_VHA_EVENT_STATUS_MASKFULL (IMG_UINT64_C(0x00000000003D000B))
  3233. #define VHA_CR_OS1_VHA_EVENT_STATUS_VHA_READY_SHIFT (21U)
  3234. #define VHA_CR_OS1_VHA_EVENT_STATUS_VHA_READY_CLRMSK (0XFFDFFFFFU)
  3235. #define VHA_CR_OS1_VHA_EVENT_STATUS_VHA_READY_EN (0X00200000U)
  3236. #define VHA_CR_OS1_VHA_EVENT_STATUS_VHA_ERROR_SHIFT (20U)
  3237. #define VHA_CR_OS1_VHA_EVENT_STATUS_VHA_ERROR_CLRMSK (0XFFEFFFFFU)
  3238. #define VHA_CR_OS1_VHA_EVENT_STATUS_VHA_ERROR_EN (0X00100000U)
  3239. #define VHA_CR_OS1_VHA_EVENT_STATUS_VHA_HL_WDT_SHIFT (19U)
  3240. #define VHA_CR_OS1_VHA_EVENT_STATUS_VHA_HL_WDT_CLRMSK (0XFFF7FFFFU)
  3241. #define VHA_CR_OS1_VHA_EVENT_STATUS_VHA_HL_WDT_EN (0X00080000U)
  3242. #define VHA_CR_OS1_VHA_EVENT_STATUS_VHA_AXI_ERROR_SHIFT (18U)
  3243. #define VHA_CR_OS1_VHA_EVENT_STATUS_VHA_AXI_ERROR_CLRMSK (0XFFFBFFFFU)
  3244. #define VHA_CR_OS1_VHA_EVENT_STATUS_VHA_AXI_ERROR_EN (0X00040000U)
  3245. #define VHA_CR_OS1_VHA_EVENT_STATUS_VHA_MMU_PAGE_FAULT_SHIFT (16U)
  3246. #define VHA_CR_OS1_VHA_EVENT_STATUS_VHA_MMU_PAGE_FAULT_CLRMSK (0XFFFEFFFFU)
  3247. #define VHA_CR_OS1_VHA_EVENT_STATUS_VHA_MMU_PAGE_FAULT_EN (0X00010000U)
  3248. #define VHA_CR_OS1_VHA_EVENT_STATUS_VHA_CNN0_MEM_WDT_SHIFT (3U)
  3249. #define VHA_CR_OS1_VHA_EVENT_STATUS_VHA_CNN0_MEM_WDT_CLRMSK (0XFFFFFFF7U)
  3250. #define VHA_CR_OS1_VHA_EVENT_STATUS_VHA_CNN0_MEM_WDT_EN (0X00000008U)
  3251. #define VHA_CR_OS1_VHA_EVENT_STATUS_VHA_CNN0_ERROR_SHIFT (1U)
  3252. #define VHA_CR_OS1_VHA_EVENT_STATUS_VHA_CNN0_ERROR_CLRMSK (0XFFFFFFFDU)
  3253. #define VHA_CR_OS1_VHA_EVENT_STATUS_VHA_CNN0_ERROR_EN (0X00000002U)
  3254. #define VHA_CR_OS1_VHA_EVENT_STATUS_VHA_CNN0_COMPLETE_SHIFT (0U)
  3255. #define VHA_CR_OS1_VHA_EVENT_STATUS_VHA_CNN0_COMPLETE_CLRMSK (0XFFFFFFFEU)
  3256. #define VHA_CR_OS1_VHA_EVENT_STATUS_VHA_CNN0_COMPLETE_EN (0X00000001U)
  3257. /*
  3258. Register VHA_CR_OS1_VHA_EVENT_CLEAR
  3259. */
  3260. #define VHA_CR_OS1_VHA_EVENT_CLEAR (0x20098U)
  3261. #define VHA_CR_OS1_VHA_EVENT_CLEAR_MASKFULL (IMG_UINT64_C(0x00000000003D000B))
  3262. #define VHA_CR_OS1_VHA_EVENT_CLEAR_VHA_READY_SHIFT (21U)
  3263. #define VHA_CR_OS1_VHA_EVENT_CLEAR_VHA_READY_CLRMSK (0XFFDFFFFFU)
  3264. #define VHA_CR_OS1_VHA_EVENT_CLEAR_VHA_READY_EN (0X00200000U)
  3265. #define VHA_CR_OS1_VHA_EVENT_CLEAR_VHA_ERROR_SHIFT (20U)
  3266. #define VHA_CR_OS1_VHA_EVENT_CLEAR_VHA_ERROR_CLRMSK (0XFFEFFFFFU)
  3267. #define VHA_CR_OS1_VHA_EVENT_CLEAR_VHA_ERROR_EN (0X00100000U)
  3268. #define VHA_CR_OS1_VHA_EVENT_CLEAR_VHA_HL_WDT_SHIFT (19U)
  3269. #define VHA_CR_OS1_VHA_EVENT_CLEAR_VHA_HL_WDT_CLRMSK (0XFFF7FFFFU)
  3270. #define VHA_CR_OS1_VHA_EVENT_CLEAR_VHA_HL_WDT_EN (0X00080000U)
  3271. #define VHA_CR_OS1_VHA_EVENT_CLEAR_VHA_AXI_ERROR_SHIFT (18U)
  3272. #define VHA_CR_OS1_VHA_EVENT_CLEAR_VHA_AXI_ERROR_CLRMSK (0XFFFBFFFFU)
  3273. #define VHA_CR_OS1_VHA_EVENT_CLEAR_VHA_AXI_ERROR_EN (0X00040000U)
  3274. #define VHA_CR_OS1_VHA_EVENT_CLEAR_VHA_MMU_PAGE_FAULT_SHIFT (16U)
  3275. #define VHA_CR_OS1_VHA_EVENT_CLEAR_VHA_MMU_PAGE_FAULT_CLRMSK (0XFFFEFFFFU)
  3276. #define VHA_CR_OS1_VHA_EVENT_CLEAR_VHA_MMU_PAGE_FAULT_EN (0X00010000U)
  3277. #define VHA_CR_OS1_VHA_EVENT_CLEAR_VHA_CNN0_MEM_WDT_SHIFT (3U)
  3278. #define VHA_CR_OS1_VHA_EVENT_CLEAR_VHA_CNN0_MEM_WDT_CLRMSK (0XFFFFFFF7U)
  3279. #define VHA_CR_OS1_VHA_EVENT_CLEAR_VHA_CNN0_MEM_WDT_EN (0X00000008U)
  3280. #define VHA_CR_OS1_VHA_EVENT_CLEAR_VHA_CNN0_ERROR_SHIFT (1U)
  3281. #define VHA_CR_OS1_VHA_EVENT_CLEAR_VHA_CNN0_ERROR_CLRMSK (0XFFFFFFFDU)
  3282. #define VHA_CR_OS1_VHA_EVENT_CLEAR_VHA_CNN0_ERROR_EN (0X00000002U)
  3283. #define VHA_CR_OS1_VHA_EVENT_CLEAR_VHA_CNN0_COMPLETE_SHIFT (0U)
  3284. #define VHA_CR_OS1_VHA_EVENT_CLEAR_VHA_CNN0_COMPLETE_CLRMSK (0XFFFFFFFEU)
  3285. #define VHA_CR_OS1_VHA_EVENT_CLEAR_VHA_CNN0_COMPLETE_EN (0X00000001U)
  3286. /*
  3287. Register VHA_CR_OS1_CNN_CRC_CONTROL
  3288. */
  3289. #define VHA_CR_OS1_CNN_CRC_CONTROL (0x20100U)
  3290. #define VHA_CR_OS1_CNN_CRC_CONTROL_MASKFULL (IMG_UINT64_C(0x0000000000000003))
  3291. #define VHA_CR_OS1_CNN_CRC_CONTROL_CNN_CRC_ENABLE_SHIFT (0U)
  3292. #define VHA_CR_OS1_CNN_CRC_CONTROL_CNN_CRC_ENABLE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFC))
  3293. #define VHA_CR_OS1_CNN_CRC_CONTROL_CNN_CRC_ENABLE_DISABLE (IMG_UINT64_C(0000000000000000))
  3294. #define VHA_CR_OS1_CNN_CRC_CONTROL_CNN_CRC_ENABLE_STREAM (IMG_UINT64_C(0x0000000000000001))
  3295. #define VHA_CR_OS1_CNN_CRC_CONTROL_CNN_CRC_ENABLE_LAYER (IMG_UINT64_C(0x0000000000000002))
  3296. #define VHA_CR_OS1_CNN_CRC_CONTROL_CNN_CRC_ENABLE_PASS (IMG_UINT64_C(0x0000000000000003))
  3297. /*
  3298. Register VHA_CR_OS1_CNN_CRC_ADDRESS
  3299. */
  3300. #define VHA_CR_OS1_CNN_CRC_ADDRESS (0x20108U)
  3301. #define VHA_CR_OS1_CNN_CRC_ADDRESS_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFF00))
  3302. #define VHA_CR_OS1_CNN_CRC_ADDRESS_CNN_CRC_ADDR_SHIFT (8U)
  3303. #define VHA_CR_OS1_CNN_CRC_ADDRESS_CNN_CRC_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF00000000FF))
  3304. #define VHA_CR_OS1_CNN_CRC_ADDRESS_CNN_CRC_ADDR_ALIGNSHIFT (8U)
  3305. #define VHA_CR_OS1_CNN_CRC_ADDRESS_CNN_CRC_ADDR_ALIGNSIZE (256U)
  3306. /*
  3307. Register VHA_CR_OS1_CNN_DEBUG_ADDRESS
  3308. */
  3309. #define VHA_CR_OS1_CNN_DEBUG_ADDRESS (0x20110U)
  3310. #define VHA_CR_OS1_CNN_DEBUG_ADDRESS_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFF00))
  3311. #define VHA_CR_OS1_CNN_DEBUG_ADDRESS_CNN_DEBUG_ADDR_SHIFT (8U)
  3312. #define VHA_CR_OS1_CNN_DEBUG_ADDRESS_CNN_DEBUG_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF00000000FF))
  3313. #define VHA_CR_OS1_CNN_DEBUG_ADDRESS_CNN_DEBUG_ADDR_ALIGNSHIFT (8U)
  3314. #define VHA_CR_OS1_CNN_DEBUG_ADDRESS_CNN_DEBUG_ADDR_ALIGNSIZE (256U)
  3315. /*
  3316. Register VHA_CR_OS1_CNN_DEBUG_SIZE
  3317. */
  3318. #define VHA_CR_OS1_CNN_DEBUG_SIZE (0x20118U)
  3319. #define VHA_CR_OS1_CNN_DEBUG_SIZE_MASKFULL (IMG_UINT64_C(0x0000000000FFFFE0))
  3320. #define VHA_CR_OS1_CNN_DEBUG_SIZE_CNN_DEBUG_SIZE_SHIFT (5U)
  3321. #define VHA_CR_OS1_CNN_DEBUG_SIZE_CNN_DEBUG_SIZE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF00001F))
  3322. #define VHA_CR_OS1_CNN_DEBUG_SIZE_CNN_DEBUG_SIZE_ALIGNSHIFT (5U)
  3323. #define VHA_CR_OS1_CNN_DEBUG_SIZE_CNN_DEBUG_SIZE_ALIGNSIZE (32U)
  3324. /*
  3325. Register VHA_CR_OS1_CNN_DEBUG_CONTROL
  3326. */
  3327. #define VHA_CR_OS1_CNN_DEBUG_CONTROL (0x20120U)
  3328. #define VHA_CR_OS1_CNN_DEBUG_CONTROL_MASKFULL (IMG_UINT64_C(0x000000000000000F))
  3329. #define VHA_CR_OS1_CNN_DEBUG_CONTROL_CNN_PERF_ENABLE_SHIFT (2U)
  3330. #define VHA_CR_OS1_CNN_DEBUG_CONTROL_CNN_PERF_ENABLE_CLRMSK (0XFFFFFFF3U)
  3331. #define VHA_CR_OS1_CNN_DEBUG_CONTROL_CNN_PERF_ENABLE_DISABLE (00000000U)
  3332. #define VHA_CR_OS1_CNN_DEBUG_CONTROL_CNN_PERF_ENABLE_STREAM (0X00000004U)
  3333. #define VHA_CR_OS1_CNN_DEBUG_CONTROL_CNN_PERF_ENABLE_LAYER (0X00000008U)
  3334. #define VHA_CR_OS1_CNN_DEBUG_CONTROL_CNN_PERF_ENABLE_PASS (0X0000000CU)
  3335. #define VHA_CR_OS1_CNN_DEBUG_CONTROL_CNN_BAND_ENABLE_SHIFT (0U)
  3336. #define VHA_CR_OS1_CNN_DEBUG_CONTROL_CNN_BAND_ENABLE_CLRMSK (0XFFFFFFFCU)
  3337. #define VHA_CR_OS1_CNN_DEBUG_CONTROL_CNN_BAND_ENABLE_DISABLE (00000000U)
  3338. #define VHA_CR_OS1_CNN_DEBUG_CONTROL_CNN_BAND_ENABLE_STREAM (0X00000001U)
  3339. #define VHA_CR_OS1_CNN_DEBUG_CONTROL_CNN_BAND_ENABLE_LAYER (0X00000002U)
  3340. #define VHA_CR_OS1_CNN_DEBUG_CONTROL_CNN_BAND_ENABLE_PASS (0X00000003U)
  3341. /*
  3342. Register VHA_CR_OS1_CNN_DEBUG_STATUS
  3343. */
  3344. #define VHA_CR_OS1_CNN_DEBUG_STATUS (0x20128U)
  3345. #define VHA_CR_OS1_CNN_DEBUG_STATUS_MASKFULL (IMG_UINT64_C(0x000000000007FFFF))
  3346. #define VHA_CR_OS1_CNN_DEBUG_STATUS_CNN_DEBUG_OFFSET_SHIFT (0U)
  3347. #define VHA_CR_OS1_CNN_DEBUG_STATUS_CNN_DEBUG_OFFSET_CLRMSK (0XFFF80000U)
  3348. /*
  3349. Register VHA_CR_OS1_CNN_PRELOAD_CONTROL
  3350. */
  3351. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL (0x20130U)
  3352. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_MASKFULL (IMG_UINT64_C(0x0000000001FF7777))
  3353. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_SHIFT (22U)
  3354. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFE3FFFFF))
  3355. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_DISABLE (IMG_UINT64_C(0000000000000000))
  3356. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_N_64 (IMG_UINT64_C(0x0000000000400000))
  3357. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_N_128 (IMG_UINT64_C(0x0000000000800000))
  3358. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_N_192 (IMG_UINT64_C(0x0000000000c00000))
  3359. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_N_256 (IMG_UINT64_C(0x0000000001000000))
  3360. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_N_320 (IMG_UINT64_C(0x0000000001400000))
  3361. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_N_384 (IMG_UINT64_C(0x0000000001800000))
  3362. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_N_448 (IMG_UINT64_C(0x0000000001c00000))
  3363. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_SHIFT (19U)
  3364. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFC7FFFF))
  3365. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_DISABLE (IMG_UINT64_C(0000000000000000))
  3366. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_N_64 (IMG_UINT64_C(0x0000000000080000))
  3367. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_N_128 (IMG_UINT64_C(0x0000000000100000))
  3368. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_N_192 (IMG_UINT64_C(0x0000000000180000))
  3369. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_N_256 (IMG_UINT64_C(0x0000000000200000))
  3370. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_N_320 (IMG_UINT64_C(0x0000000000280000))
  3371. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_N_384 (IMG_UINT64_C(0x0000000000300000))
  3372. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_N_448 (IMG_UINT64_C(0x0000000000380000))
  3373. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_SHIFT (16U)
  3374. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF8FFFF))
  3375. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_DISABLE (IMG_UINT64_C(0000000000000000))
  3376. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_N_64 (IMG_UINT64_C(0x0000000000010000))
  3377. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_N_128 (IMG_UINT64_C(0x0000000000020000))
  3378. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_N_192 (IMG_UINT64_C(0x0000000000030000))
  3379. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_N_256 (IMG_UINT64_C(0x0000000000040000))
  3380. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_N_320 (IMG_UINT64_C(0x0000000000050000))
  3381. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_N_384 (IMG_UINT64_C(0x0000000000060000))
  3382. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_N_448 (IMG_UINT64_C(0x0000000000070000))
  3383. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_EWO_N_REQS_SHIFT (12U)
  3384. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_EWO_N_REQS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF8FFF))
  3385. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_EWO_N_REQS_DISABLE (IMG_UINT64_C(0000000000000000))
  3386. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_EWO_N_REQS_N_64 (IMG_UINT64_C(0x0000000000001000))
  3387. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_EWO_N_REQS_N_128 (IMG_UINT64_C(0x0000000000002000))
  3388. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_EWO_N_REQS_N_192 (IMG_UINT64_C(0x0000000000003000))
  3389. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_EWO_N_REQS_N_256 (IMG_UINT64_C(0x0000000000004000))
  3390. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_EWO_N_REQS_N_320 (IMG_UINT64_C(0x0000000000005000))
  3391. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_EWO_N_REQS_N_384 (IMG_UINT64_C(0x0000000000006000))
  3392. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_EWO_N_REQS_N_448 (IMG_UINT64_C(0x0000000000007000))
  3393. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_ABUF_N_REQS_SHIFT (8U)
  3394. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_ABUF_N_REQS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF8FF))
  3395. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_ABUF_N_REQS_DISABLE (IMG_UINT64_C(0000000000000000))
  3396. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_ABUF_N_REQS_N_64 (IMG_UINT64_C(0x0000000000000100))
  3397. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_ABUF_N_REQS_N_128 (IMG_UINT64_C(0x0000000000000200))
  3398. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_ABUF_N_REQS_N_192 (IMG_UINT64_C(0x0000000000000300))
  3399. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_ABUF_N_REQS_N_256 (IMG_UINT64_C(0x0000000000000400))
  3400. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_ABUF_N_REQS_N_320 (IMG_UINT64_C(0x0000000000000500))
  3401. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_ABUF_N_REQS_N_384 (IMG_UINT64_C(0x0000000000000600))
  3402. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_ABUF_N_REQS_N_448 (IMG_UINT64_C(0x0000000000000700))
  3403. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_CBUF_N_REQS_SHIFT (4U)
  3404. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_CBUF_N_REQS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFF8F))
  3405. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_CBUF_N_REQS_DISABLE (IMG_UINT64_C(0000000000000000))
  3406. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_CBUF_N_REQS_N_64 (IMG_UINT64_C(0x0000000000000010))
  3407. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_CBUF_N_REQS_N_128 (IMG_UINT64_C(0x0000000000000020))
  3408. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_CBUF_N_REQS_N_192 (IMG_UINT64_C(0x0000000000000030))
  3409. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_CBUF_N_REQS_N_256 (IMG_UINT64_C(0x0000000000000040))
  3410. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_CBUF_N_REQS_N_320 (IMG_UINT64_C(0x0000000000000050))
  3411. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_CBUF_N_REQS_N_384 (IMG_UINT64_C(0x0000000000000060))
  3412. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_CBUF_N_REQS_N_448 (IMG_UINT64_C(0x0000000000000070))
  3413. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_IBUF_N_REQS_SHIFT (0U)
  3414. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_IBUF_N_REQS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF8))
  3415. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_IBUF_N_REQS_DISABLE (IMG_UINT64_C(0000000000000000))
  3416. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_IBUF_N_REQS_N_64 (IMG_UINT64_C(0x0000000000000001))
  3417. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_IBUF_N_REQS_N_128 (IMG_UINT64_C(0x0000000000000002))
  3418. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_IBUF_N_REQS_N_192 (IMG_UINT64_C(0x0000000000000003))
  3419. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_IBUF_N_REQS_N_256 (IMG_UINT64_C(0x0000000000000004))
  3420. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_IBUF_N_REQS_N_320 (IMG_UINT64_C(0x0000000000000005))
  3421. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_IBUF_N_REQS_N_384 (IMG_UINT64_C(0x0000000000000006))
  3422. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_IBUF_N_REQS_N_448 (IMG_UINT64_C(0x0000000000000007))
  3423. /*
  3424. Register VHA_CR_OS1_CNN_ALT_ADDRESS8
  3425. */
  3426. #define VHA_CR_OS1_CNN_ALT_ADDRESS8 (0x20140U)
  3427. #define VHA_CR_OS1_CNN_ALT_ADDRESS8_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  3428. #define VHA_CR_OS1_CNN_ALT_ADDRESS8_ALT_ADDR_SHIFT (0U)
  3429. #define VHA_CR_OS1_CNN_ALT_ADDRESS8_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  3430. /*
  3431. Register VHA_CR_OS1_CNN_ALT_ADDRESS9
  3432. */
  3433. #define VHA_CR_OS1_CNN_ALT_ADDRESS9 (0x20148U)
  3434. #define VHA_CR_OS1_CNN_ALT_ADDRESS9_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  3435. #define VHA_CR_OS1_CNN_ALT_ADDRESS9_ALT_ADDR_SHIFT (0U)
  3436. #define VHA_CR_OS1_CNN_ALT_ADDRESS9_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  3437. /*
  3438. Register VHA_CR_OS1_CNN_ALT_ADDRESS10
  3439. */
  3440. #define VHA_CR_OS1_CNN_ALT_ADDRESS10 (0x20150U)
  3441. #define VHA_CR_OS1_CNN_ALT_ADDRESS10_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  3442. #define VHA_CR_OS1_CNN_ALT_ADDRESS10_ALT_ADDR_SHIFT (0U)
  3443. #define VHA_CR_OS1_CNN_ALT_ADDRESS10_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  3444. /*
  3445. Register VHA_CR_OS1_CNN_ALT_ADDRESS11
  3446. */
  3447. #define VHA_CR_OS1_CNN_ALT_ADDRESS11 (0x20158U)
  3448. #define VHA_CR_OS1_CNN_ALT_ADDRESS11_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  3449. #define VHA_CR_OS1_CNN_ALT_ADDRESS11_ALT_ADDR_SHIFT (0U)
  3450. #define VHA_CR_OS1_CNN_ALT_ADDRESS11_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  3451. /*
  3452. Register VHA_CR_OS1_CNN_ALT_ADDRESS12
  3453. */
  3454. #define VHA_CR_OS1_CNN_ALT_ADDRESS12 (0x20160U)
  3455. #define VHA_CR_OS1_CNN_ALT_ADDRESS12_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  3456. #define VHA_CR_OS1_CNN_ALT_ADDRESS12_ALT_ADDR_SHIFT (0U)
  3457. #define VHA_CR_OS1_CNN_ALT_ADDRESS12_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  3458. /*
  3459. Register VHA_CR_OS1_CNN_ALT_ADDRESS13
  3460. */
  3461. #define VHA_CR_OS1_CNN_ALT_ADDRESS13 (0x20168U)
  3462. #define VHA_CR_OS1_CNN_ALT_ADDRESS13_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  3463. #define VHA_CR_OS1_CNN_ALT_ADDRESS13_ALT_ADDR_SHIFT (0U)
  3464. #define VHA_CR_OS1_CNN_ALT_ADDRESS13_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  3465. /*
  3466. Register VHA_CR_OS1_CNN_ALT_ADDRESS14
  3467. */
  3468. #define VHA_CR_OS1_CNN_ALT_ADDRESS14 (0x20170U)
  3469. #define VHA_CR_OS1_CNN_ALT_ADDRESS14_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  3470. #define VHA_CR_OS1_CNN_ALT_ADDRESS14_ALT_ADDR_SHIFT (0U)
  3471. #define VHA_CR_OS1_CNN_ALT_ADDRESS14_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  3472. /*
  3473. Register VHA_CR_OS1_CNN_ALT_ADDRESS15
  3474. */
  3475. #define VHA_CR_OS1_CNN_ALT_ADDRESS15 (0x20178U)
  3476. #define VHA_CR_OS1_CNN_ALT_ADDRESS15_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  3477. #define VHA_CR_OS1_CNN_ALT_ADDRESS15_ALT_ADDR_SHIFT (0U)
  3478. #define VHA_CR_OS1_CNN_ALT_ADDRESS15_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  3479. /*
  3480. Register VHA_CR_OS1_CNN_PERFORMANCE
  3481. */
  3482. #define VHA_CR_OS1_CNN_PERFORMANCE (0x201A0U)
  3483. #define VHA_CR_OS1_CNN_PERFORMANCE_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  3484. #define VHA_CR_OS1_CNN_PERFORMANCE_VALUE_SHIFT (0U)
  3485. #define VHA_CR_OS1_CNN_PERFORMANCE_VALUE_CLRMSK (00000000U)
  3486. /*
  3487. Register VHA_CR_OS1_MMU_CTRL_INVAL
  3488. */
  3489. #define VHA_CR_OS1_MMU_CTRL_INVAL (0x2E000U)
  3490. #define VHA_CR_OS1_MMU_CTRL_INVAL_MASKFULL (IMG_UINT64_C(0x0000000000000FFF))
  3491. #define VHA_CR_OS1_MMU_CTRL_INVAL_ALL_CONTEXTS_SHIFT (11U)
  3492. #define VHA_CR_OS1_MMU_CTRL_INVAL_ALL_CONTEXTS_CLRMSK (0XFFFFF7FFU)
  3493. #define VHA_CR_OS1_MMU_CTRL_INVAL_ALL_CONTEXTS_EN (0X00000800U)
  3494. #define VHA_CR_OS1_MMU_CTRL_INVAL_CONTEXT_SHIFT (3U)
  3495. #define VHA_CR_OS1_MMU_CTRL_INVAL_CONTEXT_CLRMSK (0XFFFFF807U)
  3496. #define VHA_CR_OS1_MMU_CTRL_INVAL_PC_SHIFT (2U)
  3497. #define VHA_CR_OS1_MMU_CTRL_INVAL_PC_CLRMSK (0XFFFFFFFBU)
  3498. #define VHA_CR_OS1_MMU_CTRL_INVAL_PC_EN (0X00000004U)
  3499. #define VHA_CR_OS1_MMU_CTRL_INVAL_PD_SHIFT (1U)
  3500. #define VHA_CR_OS1_MMU_CTRL_INVAL_PD_CLRMSK (0XFFFFFFFDU)
  3501. #define VHA_CR_OS1_MMU_CTRL_INVAL_PD_EN (0X00000002U)
  3502. #define VHA_CR_OS1_MMU_CTRL_INVAL_PT_SHIFT (0U)
  3503. #define VHA_CR_OS1_MMU_CTRL_INVAL_PT_CLRMSK (0XFFFFFFFEU)
  3504. #define VHA_CR_OS1_MMU_CTRL_INVAL_PT_EN (0X00000001U)
  3505. /*
  3506. Register VHA_CR_OS1_MMU_CTRL_INVAL_STATUS
  3507. */
  3508. #define VHA_CR_OS1_MMU_CTRL_INVAL_STATUS (0x2E038U)
  3509. #define VHA_CR_OS1_MMU_CTRL_INVAL_STATUS_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  3510. #define VHA_CR_OS1_MMU_CTRL_INVAL_STATUS_PENDING_SHIFT (0U)
  3511. #define VHA_CR_OS1_MMU_CTRL_INVAL_STATUS_PENDING_CLRMSK (0XFFFFFFFEU)
  3512. #define VHA_CR_OS1_MMU_CTRL_INVAL_STATUS_PENDING_EN (0X00000001U)
  3513. /*
  3514. Register VHA_CR_OS1_MMU_CBASE_MAPPING_CONTEXT
  3515. */
  3516. #define VHA_CR_OS1_MMU_CBASE_MAPPING_CONTEXT (0x2E008U)
  3517. #define VHA_CR_OS1_MMU_CBASE_MAPPING_CONTEXT_MASKFULL (IMG_UINT64_C(0x00000000000000FF))
  3518. #define VHA_CR_OS1_MMU_CBASE_MAPPING_CONTEXT_ID_SHIFT (0U)
  3519. #define VHA_CR_OS1_MMU_CBASE_MAPPING_CONTEXT_ID_CLRMSK (0XFFFFFF00U)
  3520. /*
  3521. Register VHA_CR_OS1_MMU_CBASE_MAPPING
  3522. */
  3523. #define VHA_CR_OS1_MMU_CBASE_MAPPING (0x2E010U)
  3524. #define VHA_CR_OS1_MMU_CBASE_MAPPING_MASKFULL (IMG_UINT64_C(0x000000001FFFFFFF))
  3525. #define VHA_CR_OS1_MMU_CBASE_MAPPING_INVALID_SHIFT (28U)
  3526. #define VHA_CR_OS1_MMU_CBASE_MAPPING_INVALID_CLRMSK (0XEFFFFFFFU)
  3527. #define VHA_CR_OS1_MMU_CBASE_MAPPING_INVALID_EN (0X10000000U)
  3528. #define VHA_CR_OS1_MMU_CBASE_MAPPING_BASE_ADDR_SHIFT (0U)
  3529. #define VHA_CR_OS1_MMU_CBASE_MAPPING_BASE_ADDR_CLRMSK (0XF0000000U)
  3530. #define VHA_CR_OS1_MMU_CBASE_MAPPING_BASE_ADDR_ALIGNSHIFT (12U)
  3531. #define VHA_CR_OS1_MMU_CBASE_MAPPING_BASE_ADDR_ALIGNSIZE (4096U)
  3532. /*
  3533. Register VHA_CR_OS1_MMU_FAULT_STATUS1
  3534. */
  3535. #define VHA_CR_OS1_MMU_FAULT_STATUS1 (0x2E018U)
  3536. #define VHA_CR_OS1_MMU_FAULT_STATUS1_MASKFULL (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
  3537. #define VHA_CR_OS1_MMU_FAULT_STATUS1_LEVEL_SHIFT (62U)
  3538. #define VHA_CR_OS1_MMU_FAULT_STATUS1_LEVEL_CLRMSK (IMG_UINT64_C(0X3FFFFFFFFFFFFFFF))
  3539. #define VHA_CR_OS1_MMU_FAULT_STATUS1_REQ_ID_SHIFT (56U)
  3540. #define VHA_CR_OS1_MMU_FAULT_STATUS1_REQ_ID_CLRMSK (IMG_UINT64_C(0XC0FFFFFFFFFFFFFF))
  3541. #define VHA_CR_OS1_MMU_FAULT_STATUS1_CONTEXT_SHIFT (48U)
  3542. #define VHA_CR_OS1_MMU_FAULT_STATUS1_CONTEXT_CLRMSK (IMG_UINT64_C(0XFF00FFFFFFFFFFFF))
  3543. #define VHA_CR_OS1_MMU_FAULT_STATUS1_ADDRESS_SHIFT (4U)
  3544. #define VHA_CR_OS1_MMU_FAULT_STATUS1_ADDRESS_CLRMSK (IMG_UINT64_C(0XFFFF00000000000F))
  3545. #define VHA_CR_OS1_MMU_FAULT_STATUS1_RNW_SHIFT (3U)
  3546. #define VHA_CR_OS1_MMU_FAULT_STATUS1_RNW_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF7))
  3547. #define VHA_CR_OS1_MMU_FAULT_STATUS1_RNW_EN (IMG_UINT64_C(0X0000000000000008))
  3548. #define VHA_CR_OS1_MMU_FAULT_STATUS1_TYPE_SHIFT (1U)
  3549. #define VHA_CR_OS1_MMU_FAULT_STATUS1_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF9))
  3550. #define VHA_CR_OS1_MMU_FAULT_STATUS1_FAULT_SHIFT (0U)
  3551. #define VHA_CR_OS1_MMU_FAULT_STATUS1_FAULT_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  3552. #define VHA_CR_OS1_MMU_FAULT_STATUS1_FAULT_EN (IMG_UINT64_C(0X0000000000000001))
  3553. /*
  3554. Register VHA_CR_OS1_MMU_FAULT_STATUS2
  3555. */
  3556. #define VHA_CR_OS1_MMU_FAULT_STATUS2 (0x2E020U)
  3557. #define VHA_CR_OS1_MMU_FAULT_STATUS2_MASKFULL (IMG_UINT64_C(0x000000003FFF07FF))
  3558. #define VHA_CR_OS1_MMU_FAULT_STATUS2_WRITEBACK_SHIFT (29U)
  3559. #define VHA_CR_OS1_MMU_FAULT_STATUS2_WRITEBACK_CLRMSK (0XDFFFFFFFU)
  3560. #define VHA_CR_OS1_MMU_FAULT_STATUS2_WRITEBACK_EN (0X20000000U)
  3561. #define VHA_CR_OS1_MMU_FAULT_STATUS2_CLEANUNIQUE_SHIFT (28U)
  3562. #define VHA_CR_OS1_MMU_FAULT_STATUS2_CLEANUNIQUE_CLRMSK (0XEFFFFFFFU)
  3563. #define VHA_CR_OS1_MMU_FAULT_STATUS2_CLEANUNIQUE_EN (0X10000000U)
  3564. #define VHA_CR_OS1_MMU_FAULT_STATUS2_BANK_SHIFT (24U)
  3565. #define VHA_CR_OS1_MMU_FAULT_STATUS2_BANK_CLRMSK (0XF0FFFFFFU)
  3566. #define VHA_CR_OS1_MMU_FAULT_STATUS2_TLB_ENTRY_SHIFT (16U)
  3567. #define VHA_CR_OS1_MMU_FAULT_STATUS2_TLB_ENTRY_CLRMSK (0XFF00FFFFU)
  3568. #define VHA_CR_OS1_MMU_FAULT_STATUS2_FBM_FAULT_SHIFT (10U)
  3569. #define VHA_CR_OS1_MMU_FAULT_STATUS2_FBM_FAULT_CLRMSK (0XFFFFFBFFU)
  3570. #define VHA_CR_OS1_MMU_FAULT_STATUS2_FBM_FAULT_EN (0X00000400U)
  3571. #define VHA_CR_OS1_MMU_FAULT_STATUS2_BIF_ID_SHIFT (0U)
  3572. #define VHA_CR_OS1_MMU_FAULT_STATUS2_BIF_ID_CLRMSK (0XFFFFFC00U)
  3573. /*
  3574. Register VHA_CR_OS1_MMU_CTRL_LEGACY
  3575. */
  3576. #define VHA_CR_OS1_MMU_CTRL_LEGACY (0x2E040U)
  3577. #define VHA_CR_OS1_MMU_CTRL_LEGACY_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  3578. #define VHA_CR_OS1_MMU_CTRL_LEGACY_RESERVED_SHIFT (0U)
  3579. #define VHA_CR_OS1_MMU_CTRL_LEGACY_RESERVED_CLRMSK (0XFFFFFFFEU)
  3580. #define VHA_CR_OS1_MMU_CTRL_LEGACY_RESERVED_EN (0X00000001U)
  3581. /*
  3582. Register VHA_CR_OS2_CNN_CONTROL
  3583. */
  3584. #define VHA_CR_OS2_CNN_CONTROL (0x30000U)
  3585. #define VHA_CR_OS2_CNN_CONTROL_MASKFULL (IMG_UINT64_C(0x000000000000337F))
  3586. #define VHA_CR_OS2_CNN_CONTROL_CTXT_PASID_SHIFT (12U)
  3587. #define VHA_CR_OS2_CNN_CONTROL_CTXT_PASID_CLRMSK (0XFFFFCFFFU)
  3588. #define VHA_CR_OS2_CNN_CONTROL_PRIORITY_SHIFT (8U)
  3589. #define VHA_CR_OS2_CNN_CONTROL_PRIORITY_CLRMSK (0XFFFFFCFFU)
  3590. #define VHA_CR_OS2_CNN_CONTROL_CMD_SIZE_MIN1_SHIFT (1U)
  3591. #define VHA_CR_OS2_CNN_CONTROL_CMD_SIZE_MIN1_CLRMSK (0XFFFFFF81U)
  3592. #define VHA_CR_OS2_CNN_CONTROL_START_SHIFT (0U)
  3593. #define VHA_CR_OS2_CNN_CONTROL_START_CLRMSK (0XFFFFFFFEU)
  3594. #define VHA_CR_OS2_CNN_CONTROL_START_EN (0X00000001U)
  3595. #define VHA_CR_OS2_CNN_STATUS_STATE_MASK (0x00000003U)
  3596. /*
  3597. No requests are pending for this host*/
  3598. #define VHA_CR_OS2_CNN_STATUS_STATE_IDLE (0x00000000U)
  3599. /*
  3600. A command stream from this host is being processed*/
  3601. #define VHA_CR_OS2_CNN_STATUS_STATE_RUN (0x00000001U)
  3602. /*
  3603. The command stream from this host has been suspended due to higher priority request from another host*/
  3604. #define VHA_CR_OS2_CNN_STATUS_STATE_SUSPEND (0x00000002U)
  3605. /*
  3606. A command stream from this host is pending but not been started */
  3607. #define VHA_CR_OS2_CNN_STATUS_STATE_PENDING (0x00000003U)
  3608. /*
  3609. Register VHA_CR_OS2_CNN_STATUS
  3610. */
  3611. #define VHA_CR_OS2_CNN_STATUS (0x30008U)
  3612. #define VHA_CR_OS2_CNN_STATUS_MASKFULL (IMG_UINT64_C(0x00000000C0FFFFFF))
  3613. #define VHA_CR_OS2_CNN_STATUS_CURRENT_STATE_SHIFT (30U)
  3614. #define VHA_CR_OS2_CNN_STATUS_CURRENT_STATE_CLRMSK (0X3FFFFFFFU)
  3615. #define VHA_CR_OS2_CNN_STATUS_CURRENT_STATE_IDLE (00000000U)
  3616. #define VHA_CR_OS2_CNN_STATUS_CURRENT_STATE_RUN (0X40000000U)
  3617. #define VHA_CR_OS2_CNN_STATUS_CURRENT_STATE_SUSPEND (0X80000000U)
  3618. #define VHA_CR_OS2_CNN_STATUS_CURRENT_STATE_PENDING (0XC0000000U)
  3619. #define VHA_CR_OS2_CNN_STATUS_PASS_COUNT_SHIFT (16U)
  3620. #define VHA_CR_OS2_CNN_STATUS_PASS_COUNT_CLRMSK (0XFF00FFFFU)
  3621. #define VHA_CR_OS2_CNN_STATUS_LAYER_COUNT_SHIFT (8U)
  3622. #define VHA_CR_OS2_CNN_STATUS_LAYER_COUNT_CLRMSK (0XFFFF00FFU)
  3623. #define VHA_CR_OS2_CNN_STATUS_STREAM_COUNT_SHIFT (0U)
  3624. #define VHA_CR_OS2_CNN_STATUS_STREAM_COUNT_CLRMSK (0XFFFFFF00U)
  3625. /*
  3626. Register VHA_CR_OS2_CNN_CMD_BASE_ADDRESS
  3627. */
  3628. #define VHA_CR_OS2_CNN_CMD_BASE_ADDRESS (0x30020U)
  3629. #define VHA_CR_OS2_CNN_CMD_BASE_ADDRESS_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFF00))
  3630. #define VHA_CR_OS2_CNN_CMD_BASE_ADDRESS_BASE_ADDR_SHIFT (8U)
  3631. #define VHA_CR_OS2_CNN_CMD_BASE_ADDRESS_BASE_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF00000000FF))
  3632. /*
  3633. Register VHA_CR_OS2_CNN_ALT_ADDRESS_USED
  3634. */
  3635. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED (0x30038U)
  3636. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  3637. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR15_BUF_TYPE_SHIFT (31U)
  3638. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR15_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFF7FFFFFFF))
  3639. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR15_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  3640. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR15_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000080000000))
  3641. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR14_BUF_TYPE_SHIFT (30U)
  3642. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR14_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFBFFFFFFF))
  3643. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR14_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  3644. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR14_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000040000000))
  3645. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR13_BUF_TYPE_SHIFT (29U)
  3646. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR13_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFDFFFFFFF))
  3647. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR13_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  3648. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR13_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000020000000))
  3649. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR12_BUF_TYPE_SHIFT (28U)
  3650. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR12_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFEFFFFFFF))
  3651. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR12_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  3652. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR12_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000010000000))
  3653. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR11_BUF_TYPE_SHIFT (27U)
  3654. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR11_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFF7FFFFFF))
  3655. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR11_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  3656. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR11_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000008000000))
  3657. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR10_BUF_TYPE_SHIFT (26U)
  3658. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR10_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFBFFFFFF))
  3659. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR10_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  3660. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR10_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000004000000))
  3661. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR9_BUF_TYPE_SHIFT (25U)
  3662. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR9_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFDFFFFFF))
  3663. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR9_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  3664. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR9_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000002000000))
  3665. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR8_BUF_TYPE_SHIFT (24U)
  3666. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR8_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFEFFFFFF))
  3667. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR8_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  3668. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR8_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000001000000))
  3669. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR7_BUF_TYPE_SHIFT (23U)
  3670. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR7_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF7FFFFF))
  3671. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR7_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  3672. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR7_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000000800000))
  3673. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR6_BUF_TYPE_SHIFT (22U)
  3674. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR6_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFBFFFFF))
  3675. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR6_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  3676. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR6_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000000400000))
  3677. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR5_BUF_TYPE_SHIFT (21U)
  3678. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR5_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFDFFFFF))
  3679. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR5_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  3680. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR5_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000000200000))
  3681. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR4_BUF_TYPE_SHIFT (20U)
  3682. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR4_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFEFFFFF))
  3683. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR4_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  3684. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR4_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000000100000))
  3685. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR3_BUF_TYPE_SHIFT (19U)
  3686. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR3_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF7FFFF))
  3687. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR3_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  3688. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR3_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000000080000))
  3689. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR2_BUF_TYPE_SHIFT (18U)
  3690. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR2_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFBFFFF))
  3691. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR2_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  3692. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR2_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000000040000))
  3693. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR1_BUF_TYPE_SHIFT (17U)
  3694. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR1_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFDFFFF))
  3695. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR1_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  3696. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR1_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000000020000))
  3697. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR0_BUF_TYPE_SHIFT (16U)
  3698. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR0_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFEFFFF))
  3699. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR0_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  3700. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR0_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000000010000))
  3701. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR15_USED_SHIFT (15U)
  3702. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR15_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF7FFF))
  3703. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR15_USED_EN (IMG_UINT64_C(0X0000000000008000))
  3704. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR14_USED_SHIFT (14U)
  3705. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR14_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFBFFF))
  3706. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR14_USED_EN (IMG_UINT64_C(0X0000000000004000))
  3707. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR13_USED_SHIFT (13U)
  3708. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR13_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFDFFF))
  3709. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR13_USED_EN (IMG_UINT64_C(0X0000000000002000))
  3710. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR12_USED_SHIFT (12U)
  3711. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR12_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFEFFF))
  3712. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR12_USED_EN (IMG_UINT64_C(0X0000000000001000))
  3713. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR11_USED_SHIFT (11U)
  3714. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR11_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF7FF))
  3715. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR11_USED_EN (IMG_UINT64_C(0X0000000000000800))
  3716. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR10_USED_SHIFT (10U)
  3717. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR10_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFBFF))
  3718. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR10_USED_EN (IMG_UINT64_C(0X0000000000000400))
  3719. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR9_USED_SHIFT (9U)
  3720. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR9_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFDFF))
  3721. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR9_USED_EN (IMG_UINT64_C(0X0000000000000200))
  3722. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR8_USED_SHIFT (8U)
  3723. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR8_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFEFF))
  3724. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR8_USED_EN (IMG_UINT64_C(0X0000000000000100))
  3725. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR7_USED_SHIFT (7U)
  3726. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR7_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFF7F))
  3727. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR7_USED_EN (IMG_UINT64_C(0X0000000000000080))
  3728. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR6_USED_SHIFT (6U)
  3729. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR6_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFBF))
  3730. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR6_USED_EN (IMG_UINT64_C(0X0000000000000040))
  3731. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR5_USED_SHIFT (5U)
  3732. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR5_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFDF))
  3733. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR5_USED_EN (IMG_UINT64_C(0X0000000000000020))
  3734. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR4_USED_SHIFT (4U)
  3735. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR4_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFEF))
  3736. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR4_USED_EN (IMG_UINT64_C(0X0000000000000010))
  3737. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR3_USED_SHIFT (3U)
  3738. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR3_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF7))
  3739. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR3_USED_EN (IMG_UINT64_C(0X0000000000000008))
  3740. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR2_USED_SHIFT (2U)
  3741. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR2_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFB))
  3742. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR2_USED_EN (IMG_UINT64_C(0X0000000000000004))
  3743. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR1_USED_SHIFT (1U)
  3744. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR1_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFD))
  3745. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR1_USED_EN (IMG_UINT64_C(0X0000000000000002))
  3746. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR0_USED_SHIFT (0U)
  3747. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR0_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  3748. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR0_USED_EN (IMG_UINT64_C(0X0000000000000001))
  3749. /*
  3750. Register VHA_CR_OS2_CNN_ALT_ADDRESS0
  3751. */
  3752. #define VHA_CR_OS2_CNN_ALT_ADDRESS0 (0x30040U)
  3753. #define VHA_CR_OS2_CNN_ALT_ADDRESS0_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  3754. #define VHA_CR_OS2_CNN_ALT_ADDRESS0_ALT_ADDR_SHIFT (0U)
  3755. #define VHA_CR_OS2_CNN_ALT_ADDRESS0_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  3756. /*
  3757. Register VHA_CR_OS2_CNN_ALT_ADDRESS1
  3758. */
  3759. #define VHA_CR_OS2_CNN_ALT_ADDRESS1 (0x30048U)
  3760. #define VHA_CR_OS2_CNN_ALT_ADDRESS1_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  3761. #define VHA_CR_OS2_CNN_ALT_ADDRESS1_ALT_ADDR_SHIFT (0U)
  3762. #define VHA_CR_OS2_CNN_ALT_ADDRESS1_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  3763. /*
  3764. Register VHA_CR_OS2_CNN_ALT_ADDRESS2
  3765. */
  3766. #define VHA_CR_OS2_CNN_ALT_ADDRESS2 (0x30050U)
  3767. #define VHA_CR_OS2_CNN_ALT_ADDRESS2_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  3768. #define VHA_CR_OS2_CNN_ALT_ADDRESS2_ALT_ADDR_SHIFT (0U)
  3769. #define VHA_CR_OS2_CNN_ALT_ADDRESS2_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  3770. /*
  3771. Register VHA_CR_OS2_CNN_ALT_ADDRESS3
  3772. */
  3773. #define VHA_CR_OS2_CNN_ALT_ADDRESS3 (0x30058U)
  3774. #define VHA_CR_OS2_CNN_ALT_ADDRESS3_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  3775. #define VHA_CR_OS2_CNN_ALT_ADDRESS3_ALT_ADDR_SHIFT (0U)
  3776. #define VHA_CR_OS2_CNN_ALT_ADDRESS3_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  3777. /*
  3778. Register VHA_CR_OS2_CNN_ALT_ADDRESS4
  3779. */
  3780. #define VHA_CR_OS2_CNN_ALT_ADDRESS4 (0x30060U)
  3781. #define VHA_CR_OS2_CNN_ALT_ADDRESS4_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  3782. #define VHA_CR_OS2_CNN_ALT_ADDRESS4_ALT_ADDR_SHIFT (0U)
  3783. #define VHA_CR_OS2_CNN_ALT_ADDRESS4_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  3784. /*
  3785. Register VHA_CR_OS2_CNN_ALT_ADDRESS5
  3786. */
  3787. #define VHA_CR_OS2_CNN_ALT_ADDRESS5 (0x30068U)
  3788. #define VHA_CR_OS2_CNN_ALT_ADDRESS5_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  3789. #define VHA_CR_OS2_CNN_ALT_ADDRESS5_ALT_ADDR_SHIFT (0U)
  3790. #define VHA_CR_OS2_CNN_ALT_ADDRESS5_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  3791. /*
  3792. Register VHA_CR_OS2_CNN_ALT_ADDRESS6
  3793. */
  3794. #define VHA_CR_OS2_CNN_ALT_ADDRESS6 (0x30070U)
  3795. #define VHA_CR_OS2_CNN_ALT_ADDRESS6_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  3796. #define VHA_CR_OS2_CNN_ALT_ADDRESS6_ALT_ADDR_SHIFT (0U)
  3797. #define VHA_CR_OS2_CNN_ALT_ADDRESS6_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  3798. /*
  3799. Register VHA_CR_OS2_CNN_ALT_ADDRESS7
  3800. */
  3801. #define VHA_CR_OS2_CNN_ALT_ADDRESS7 (0x30078U)
  3802. #define VHA_CR_OS2_CNN_ALT_ADDRESS7_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  3803. #define VHA_CR_OS2_CNN_ALT_ADDRESS7_ALT_ADDR_SHIFT (0U)
  3804. #define VHA_CR_OS2_CNN_ALT_ADDRESS7_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  3805. /*
  3806. Register VHA_CR_OS2_CNN_WRITEBACK_CONTROL
  3807. */
  3808. #define VHA_CR_OS2_CNN_WRITEBACK_CONTROL (0x30080U)
  3809. #define VHA_CR_OS2_CNN_WRITEBACK_CONTROL_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  3810. #define VHA_CR_OS2_CNN_WRITEBACK_CONTROL_WRITE_BACK_VALUE_SHIFT (0U)
  3811. #define VHA_CR_OS2_CNN_WRITEBACK_CONTROL_WRITE_BACK_VALUE_CLRMSK (00000000U)
  3812. /*
  3813. Register VHA_CR_OS2_VHA_EVENT_ENABLE
  3814. */
  3815. #define VHA_CR_OS2_VHA_EVENT_ENABLE (0x30088U)
  3816. #define VHA_CR_OS2_VHA_EVENT_ENABLE_MASKFULL (IMG_UINT64_C(0x00000000003D000B))
  3817. #define VHA_CR_OS2_VHA_EVENT_ENABLE_VHA_READY_SHIFT (21U)
  3818. #define VHA_CR_OS2_VHA_EVENT_ENABLE_VHA_READY_CLRMSK (0XFFDFFFFFU)
  3819. #define VHA_CR_OS2_VHA_EVENT_ENABLE_VHA_READY_EN (0X00200000U)
  3820. #define VHA_CR_OS2_VHA_EVENT_ENABLE_VHA_ERROR_SHIFT (20U)
  3821. #define VHA_CR_OS2_VHA_EVENT_ENABLE_VHA_ERROR_CLRMSK (0XFFEFFFFFU)
  3822. #define VHA_CR_OS2_VHA_EVENT_ENABLE_VHA_ERROR_EN (0X00100000U)
  3823. #define VHA_CR_OS2_VHA_EVENT_ENABLE_VHA_HL_WDT_SHIFT (19U)
  3824. #define VHA_CR_OS2_VHA_EVENT_ENABLE_VHA_HL_WDT_CLRMSK (0XFFF7FFFFU)
  3825. #define VHA_CR_OS2_VHA_EVENT_ENABLE_VHA_HL_WDT_EN (0X00080000U)
  3826. #define VHA_CR_OS2_VHA_EVENT_ENABLE_VHA_AXI_ERROR_SHIFT (18U)
  3827. #define VHA_CR_OS2_VHA_EVENT_ENABLE_VHA_AXI_ERROR_CLRMSK (0XFFFBFFFFU)
  3828. #define VHA_CR_OS2_VHA_EVENT_ENABLE_VHA_AXI_ERROR_EN (0X00040000U)
  3829. #define VHA_CR_OS2_VHA_EVENT_ENABLE_VHA_MMU_PAGE_FAULT_SHIFT (16U)
  3830. #define VHA_CR_OS2_VHA_EVENT_ENABLE_VHA_MMU_PAGE_FAULT_CLRMSK (0XFFFEFFFFU)
  3831. #define VHA_CR_OS2_VHA_EVENT_ENABLE_VHA_MMU_PAGE_FAULT_EN (0X00010000U)
  3832. #define VHA_CR_OS2_VHA_EVENT_ENABLE_VHA_CNN0_MEM_WDT_SHIFT (3U)
  3833. #define VHA_CR_OS2_VHA_EVENT_ENABLE_VHA_CNN0_MEM_WDT_CLRMSK (0XFFFFFFF7U)
  3834. #define VHA_CR_OS2_VHA_EVENT_ENABLE_VHA_CNN0_MEM_WDT_EN (0X00000008U)
  3835. #define VHA_CR_OS2_VHA_EVENT_ENABLE_VHA_CNN0_ERROR_SHIFT (1U)
  3836. #define VHA_CR_OS2_VHA_EVENT_ENABLE_VHA_CNN0_ERROR_CLRMSK (0XFFFFFFFDU)
  3837. #define VHA_CR_OS2_VHA_EVENT_ENABLE_VHA_CNN0_ERROR_EN (0X00000002U)
  3838. #define VHA_CR_OS2_VHA_EVENT_ENABLE_VHA_CNN0_COMPLETE_SHIFT (0U)
  3839. #define VHA_CR_OS2_VHA_EVENT_ENABLE_VHA_CNN0_COMPLETE_CLRMSK (0XFFFFFFFEU)
  3840. #define VHA_CR_OS2_VHA_EVENT_ENABLE_VHA_CNN0_COMPLETE_EN (0X00000001U)
  3841. /*
  3842. Register VHA_CR_OS2_VHA_EVENT_STATUS
  3843. */
  3844. #define VHA_CR_OS2_VHA_EVENT_STATUS (0x30090U)
  3845. #define VHA_CR_OS2_VHA_EVENT_STATUS_MASKFULL (IMG_UINT64_C(0x00000000003D000B))
  3846. #define VHA_CR_OS2_VHA_EVENT_STATUS_VHA_READY_SHIFT (21U)
  3847. #define VHA_CR_OS2_VHA_EVENT_STATUS_VHA_READY_CLRMSK (0XFFDFFFFFU)
  3848. #define VHA_CR_OS2_VHA_EVENT_STATUS_VHA_READY_EN (0X00200000U)
  3849. #define VHA_CR_OS2_VHA_EVENT_STATUS_VHA_ERROR_SHIFT (20U)
  3850. #define VHA_CR_OS2_VHA_EVENT_STATUS_VHA_ERROR_CLRMSK (0XFFEFFFFFU)
  3851. #define VHA_CR_OS2_VHA_EVENT_STATUS_VHA_ERROR_EN (0X00100000U)
  3852. #define VHA_CR_OS2_VHA_EVENT_STATUS_VHA_HL_WDT_SHIFT (19U)
  3853. #define VHA_CR_OS2_VHA_EVENT_STATUS_VHA_HL_WDT_CLRMSK (0XFFF7FFFFU)
  3854. #define VHA_CR_OS2_VHA_EVENT_STATUS_VHA_HL_WDT_EN (0X00080000U)
  3855. #define VHA_CR_OS2_VHA_EVENT_STATUS_VHA_AXI_ERROR_SHIFT (18U)
  3856. #define VHA_CR_OS2_VHA_EVENT_STATUS_VHA_AXI_ERROR_CLRMSK (0XFFFBFFFFU)
  3857. #define VHA_CR_OS2_VHA_EVENT_STATUS_VHA_AXI_ERROR_EN (0X00040000U)
  3858. #define VHA_CR_OS2_VHA_EVENT_STATUS_VHA_MMU_PAGE_FAULT_SHIFT (16U)
  3859. #define VHA_CR_OS2_VHA_EVENT_STATUS_VHA_MMU_PAGE_FAULT_CLRMSK (0XFFFEFFFFU)
  3860. #define VHA_CR_OS2_VHA_EVENT_STATUS_VHA_MMU_PAGE_FAULT_EN (0X00010000U)
  3861. #define VHA_CR_OS2_VHA_EVENT_STATUS_VHA_CNN0_MEM_WDT_SHIFT (3U)
  3862. #define VHA_CR_OS2_VHA_EVENT_STATUS_VHA_CNN0_MEM_WDT_CLRMSK (0XFFFFFFF7U)
  3863. #define VHA_CR_OS2_VHA_EVENT_STATUS_VHA_CNN0_MEM_WDT_EN (0X00000008U)
  3864. #define VHA_CR_OS2_VHA_EVENT_STATUS_VHA_CNN0_ERROR_SHIFT (1U)
  3865. #define VHA_CR_OS2_VHA_EVENT_STATUS_VHA_CNN0_ERROR_CLRMSK (0XFFFFFFFDU)
  3866. #define VHA_CR_OS2_VHA_EVENT_STATUS_VHA_CNN0_ERROR_EN (0X00000002U)
  3867. #define VHA_CR_OS2_VHA_EVENT_STATUS_VHA_CNN0_COMPLETE_SHIFT (0U)
  3868. #define VHA_CR_OS2_VHA_EVENT_STATUS_VHA_CNN0_COMPLETE_CLRMSK (0XFFFFFFFEU)
  3869. #define VHA_CR_OS2_VHA_EVENT_STATUS_VHA_CNN0_COMPLETE_EN (0X00000001U)
  3870. /*
  3871. Register VHA_CR_OS2_VHA_EVENT_CLEAR
  3872. */
  3873. #define VHA_CR_OS2_VHA_EVENT_CLEAR (0x30098U)
  3874. #define VHA_CR_OS2_VHA_EVENT_CLEAR_MASKFULL (IMG_UINT64_C(0x00000000003D000B))
  3875. #define VHA_CR_OS2_VHA_EVENT_CLEAR_VHA_READY_SHIFT (21U)
  3876. #define VHA_CR_OS2_VHA_EVENT_CLEAR_VHA_READY_CLRMSK (0XFFDFFFFFU)
  3877. #define VHA_CR_OS2_VHA_EVENT_CLEAR_VHA_READY_EN (0X00200000U)
  3878. #define VHA_CR_OS2_VHA_EVENT_CLEAR_VHA_ERROR_SHIFT (20U)
  3879. #define VHA_CR_OS2_VHA_EVENT_CLEAR_VHA_ERROR_CLRMSK (0XFFEFFFFFU)
  3880. #define VHA_CR_OS2_VHA_EVENT_CLEAR_VHA_ERROR_EN (0X00100000U)
  3881. #define VHA_CR_OS2_VHA_EVENT_CLEAR_VHA_HL_WDT_SHIFT (19U)
  3882. #define VHA_CR_OS2_VHA_EVENT_CLEAR_VHA_HL_WDT_CLRMSK (0XFFF7FFFFU)
  3883. #define VHA_CR_OS2_VHA_EVENT_CLEAR_VHA_HL_WDT_EN (0X00080000U)
  3884. #define VHA_CR_OS2_VHA_EVENT_CLEAR_VHA_AXI_ERROR_SHIFT (18U)
  3885. #define VHA_CR_OS2_VHA_EVENT_CLEAR_VHA_AXI_ERROR_CLRMSK (0XFFFBFFFFU)
  3886. #define VHA_CR_OS2_VHA_EVENT_CLEAR_VHA_AXI_ERROR_EN (0X00040000U)
  3887. #define VHA_CR_OS2_VHA_EVENT_CLEAR_VHA_MMU_PAGE_FAULT_SHIFT (16U)
  3888. #define VHA_CR_OS2_VHA_EVENT_CLEAR_VHA_MMU_PAGE_FAULT_CLRMSK (0XFFFEFFFFU)
  3889. #define VHA_CR_OS2_VHA_EVENT_CLEAR_VHA_MMU_PAGE_FAULT_EN (0X00010000U)
  3890. #define VHA_CR_OS2_VHA_EVENT_CLEAR_VHA_CNN0_MEM_WDT_SHIFT (3U)
  3891. #define VHA_CR_OS2_VHA_EVENT_CLEAR_VHA_CNN0_MEM_WDT_CLRMSK (0XFFFFFFF7U)
  3892. #define VHA_CR_OS2_VHA_EVENT_CLEAR_VHA_CNN0_MEM_WDT_EN (0X00000008U)
  3893. #define VHA_CR_OS2_VHA_EVENT_CLEAR_VHA_CNN0_ERROR_SHIFT (1U)
  3894. #define VHA_CR_OS2_VHA_EVENT_CLEAR_VHA_CNN0_ERROR_CLRMSK (0XFFFFFFFDU)
  3895. #define VHA_CR_OS2_VHA_EVENT_CLEAR_VHA_CNN0_ERROR_EN (0X00000002U)
  3896. #define VHA_CR_OS2_VHA_EVENT_CLEAR_VHA_CNN0_COMPLETE_SHIFT (0U)
  3897. #define VHA_CR_OS2_VHA_EVENT_CLEAR_VHA_CNN0_COMPLETE_CLRMSK (0XFFFFFFFEU)
  3898. #define VHA_CR_OS2_VHA_EVENT_CLEAR_VHA_CNN0_COMPLETE_EN (0X00000001U)
  3899. /*
  3900. Register VHA_CR_OS2_CNN_CRC_CONTROL
  3901. */
  3902. #define VHA_CR_OS2_CNN_CRC_CONTROL (0x30100U)
  3903. #define VHA_CR_OS2_CNN_CRC_CONTROL_MASKFULL (IMG_UINT64_C(0x0000000000000003))
  3904. #define VHA_CR_OS2_CNN_CRC_CONTROL_CNN_CRC_ENABLE_SHIFT (0U)
  3905. #define VHA_CR_OS2_CNN_CRC_CONTROL_CNN_CRC_ENABLE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFC))
  3906. #define VHA_CR_OS2_CNN_CRC_CONTROL_CNN_CRC_ENABLE_DISABLE (IMG_UINT64_C(0000000000000000))
  3907. #define VHA_CR_OS2_CNN_CRC_CONTROL_CNN_CRC_ENABLE_STREAM (IMG_UINT64_C(0x0000000000000001))
  3908. #define VHA_CR_OS2_CNN_CRC_CONTROL_CNN_CRC_ENABLE_LAYER (IMG_UINT64_C(0x0000000000000002))
  3909. #define VHA_CR_OS2_CNN_CRC_CONTROL_CNN_CRC_ENABLE_PASS (IMG_UINT64_C(0x0000000000000003))
  3910. /*
  3911. Register VHA_CR_OS2_CNN_CRC_ADDRESS
  3912. */
  3913. #define VHA_CR_OS2_CNN_CRC_ADDRESS (0x30108U)
  3914. #define VHA_CR_OS2_CNN_CRC_ADDRESS_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFF00))
  3915. #define VHA_CR_OS2_CNN_CRC_ADDRESS_CNN_CRC_ADDR_SHIFT (8U)
  3916. #define VHA_CR_OS2_CNN_CRC_ADDRESS_CNN_CRC_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF00000000FF))
  3917. #define VHA_CR_OS2_CNN_CRC_ADDRESS_CNN_CRC_ADDR_ALIGNSHIFT (8U)
  3918. #define VHA_CR_OS2_CNN_CRC_ADDRESS_CNN_CRC_ADDR_ALIGNSIZE (256U)
  3919. /*
  3920. Register VHA_CR_OS2_CNN_DEBUG_ADDRESS
  3921. */
  3922. #define VHA_CR_OS2_CNN_DEBUG_ADDRESS (0x30110U)
  3923. #define VHA_CR_OS2_CNN_DEBUG_ADDRESS_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFF00))
  3924. #define VHA_CR_OS2_CNN_DEBUG_ADDRESS_CNN_DEBUG_ADDR_SHIFT (8U)
  3925. #define VHA_CR_OS2_CNN_DEBUG_ADDRESS_CNN_DEBUG_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF00000000FF))
  3926. #define VHA_CR_OS2_CNN_DEBUG_ADDRESS_CNN_DEBUG_ADDR_ALIGNSHIFT (8U)
  3927. #define VHA_CR_OS2_CNN_DEBUG_ADDRESS_CNN_DEBUG_ADDR_ALIGNSIZE (256U)
  3928. /*
  3929. Register VHA_CR_OS2_CNN_DEBUG_SIZE
  3930. */
  3931. #define VHA_CR_OS2_CNN_DEBUG_SIZE (0x30118U)
  3932. #define VHA_CR_OS2_CNN_DEBUG_SIZE_MASKFULL (IMG_UINT64_C(0x0000000000FFFFE0))
  3933. #define VHA_CR_OS2_CNN_DEBUG_SIZE_CNN_DEBUG_SIZE_SHIFT (5U)
  3934. #define VHA_CR_OS2_CNN_DEBUG_SIZE_CNN_DEBUG_SIZE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF00001F))
  3935. #define VHA_CR_OS2_CNN_DEBUG_SIZE_CNN_DEBUG_SIZE_ALIGNSHIFT (5U)
  3936. #define VHA_CR_OS2_CNN_DEBUG_SIZE_CNN_DEBUG_SIZE_ALIGNSIZE (32U)
  3937. /*
  3938. Register VHA_CR_OS2_CNN_DEBUG_CONTROL
  3939. */
  3940. #define VHA_CR_OS2_CNN_DEBUG_CONTROL (0x30120U)
  3941. #define VHA_CR_OS2_CNN_DEBUG_CONTROL_MASKFULL (IMG_UINT64_C(0x000000000000000F))
  3942. #define VHA_CR_OS2_CNN_DEBUG_CONTROL_CNN_PERF_ENABLE_SHIFT (2U)
  3943. #define VHA_CR_OS2_CNN_DEBUG_CONTROL_CNN_PERF_ENABLE_CLRMSK (0XFFFFFFF3U)
  3944. #define VHA_CR_OS2_CNN_DEBUG_CONTROL_CNN_PERF_ENABLE_DISABLE (00000000U)
  3945. #define VHA_CR_OS2_CNN_DEBUG_CONTROL_CNN_PERF_ENABLE_STREAM (0X00000004U)
  3946. #define VHA_CR_OS2_CNN_DEBUG_CONTROL_CNN_PERF_ENABLE_LAYER (0X00000008U)
  3947. #define VHA_CR_OS2_CNN_DEBUG_CONTROL_CNN_PERF_ENABLE_PASS (0X0000000CU)
  3948. #define VHA_CR_OS2_CNN_DEBUG_CONTROL_CNN_BAND_ENABLE_SHIFT (0U)
  3949. #define VHA_CR_OS2_CNN_DEBUG_CONTROL_CNN_BAND_ENABLE_CLRMSK (0XFFFFFFFCU)
  3950. #define VHA_CR_OS2_CNN_DEBUG_CONTROL_CNN_BAND_ENABLE_DISABLE (00000000U)
  3951. #define VHA_CR_OS2_CNN_DEBUG_CONTROL_CNN_BAND_ENABLE_STREAM (0X00000001U)
  3952. #define VHA_CR_OS2_CNN_DEBUG_CONTROL_CNN_BAND_ENABLE_LAYER (0X00000002U)
  3953. #define VHA_CR_OS2_CNN_DEBUG_CONTROL_CNN_BAND_ENABLE_PASS (0X00000003U)
  3954. /*
  3955. Register VHA_CR_OS2_CNN_DEBUG_STATUS
  3956. */
  3957. #define VHA_CR_OS2_CNN_DEBUG_STATUS (0x30128U)
  3958. #define VHA_CR_OS2_CNN_DEBUG_STATUS_MASKFULL (IMG_UINT64_C(0x000000000007FFFF))
  3959. #define VHA_CR_OS2_CNN_DEBUG_STATUS_CNN_DEBUG_OFFSET_SHIFT (0U)
  3960. #define VHA_CR_OS2_CNN_DEBUG_STATUS_CNN_DEBUG_OFFSET_CLRMSK (0XFFF80000U)
  3961. /*
  3962. Register VHA_CR_OS2_CNN_PRELOAD_CONTROL
  3963. */
  3964. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL (0x30130U)
  3965. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_MASKFULL (IMG_UINT64_C(0x0000000001FF7777))
  3966. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_SHIFT (22U)
  3967. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFE3FFFFF))
  3968. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_DISABLE (IMG_UINT64_C(0000000000000000))
  3969. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_N_64 (IMG_UINT64_C(0x0000000000400000))
  3970. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_N_128 (IMG_UINT64_C(0x0000000000800000))
  3971. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_N_192 (IMG_UINT64_C(0x0000000000c00000))
  3972. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_N_256 (IMG_UINT64_C(0x0000000001000000))
  3973. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_N_320 (IMG_UINT64_C(0x0000000001400000))
  3974. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_N_384 (IMG_UINT64_C(0x0000000001800000))
  3975. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_N_448 (IMG_UINT64_C(0x0000000001c00000))
  3976. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_SHIFT (19U)
  3977. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFC7FFFF))
  3978. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_DISABLE (IMG_UINT64_C(0000000000000000))
  3979. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_N_64 (IMG_UINT64_C(0x0000000000080000))
  3980. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_N_128 (IMG_UINT64_C(0x0000000000100000))
  3981. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_N_192 (IMG_UINT64_C(0x0000000000180000))
  3982. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_N_256 (IMG_UINT64_C(0x0000000000200000))
  3983. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_N_320 (IMG_UINT64_C(0x0000000000280000))
  3984. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_N_384 (IMG_UINT64_C(0x0000000000300000))
  3985. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_N_448 (IMG_UINT64_C(0x0000000000380000))
  3986. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_SHIFT (16U)
  3987. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF8FFFF))
  3988. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_DISABLE (IMG_UINT64_C(0000000000000000))
  3989. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_N_64 (IMG_UINT64_C(0x0000000000010000))
  3990. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_N_128 (IMG_UINT64_C(0x0000000000020000))
  3991. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_N_192 (IMG_UINT64_C(0x0000000000030000))
  3992. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_N_256 (IMG_UINT64_C(0x0000000000040000))
  3993. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_N_320 (IMG_UINT64_C(0x0000000000050000))
  3994. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_N_384 (IMG_UINT64_C(0x0000000000060000))
  3995. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_N_448 (IMG_UINT64_C(0x0000000000070000))
  3996. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_EWO_N_REQS_SHIFT (12U)
  3997. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_EWO_N_REQS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF8FFF))
  3998. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_EWO_N_REQS_DISABLE (IMG_UINT64_C(0000000000000000))
  3999. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_EWO_N_REQS_N_64 (IMG_UINT64_C(0x0000000000001000))
  4000. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_EWO_N_REQS_N_128 (IMG_UINT64_C(0x0000000000002000))
  4001. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_EWO_N_REQS_N_192 (IMG_UINT64_C(0x0000000000003000))
  4002. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_EWO_N_REQS_N_256 (IMG_UINT64_C(0x0000000000004000))
  4003. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_EWO_N_REQS_N_320 (IMG_UINT64_C(0x0000000000005000))
  4004. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_EWO_N_REQS_N_384 (IMG_UINT64_C(0x0000000000006000))
  4005. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_EWO_N_REQS_N_448 (IMG_UINT64_C(0x0000000000007000))
  4006. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_ABUF_N_REQS_SHIFT (8U)
  4007. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_ABUF_N_REQS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF8FF))
  4008. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_ABUF_N_REQS_DISABLE (IMG_UINT64_C(0000000000000000))
  4009. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_ABUF_N_REQS_N_64 (IMG_UINT64_C(0x0000000000000100))
  4010. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_ABUF_N_REQS_N_128 (IMG_UINT64_C(0x0000000000000200))
  4011. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_ABUF_N_REQS_N_192 (IMG_UINT64_C(0x0000000000000300))
  4012. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_ABUF_N_REQS_N_256 (IMG_UINT64_C(0x0000000000000400))
  4013. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_ABUF_N_REQS_N_320 (IMG_UINT64_C(0x0000000000000500))
  4014. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_ABUF_N_REQS_N_384 (IMG_UINT64_C(0x0000000000000600))
  4015. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_ABUF_N_REQS_N_448 (IMG_UINT64_C(0x0000000000000700))
  4016. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_CBUF_N_REQS_SHIFT (4U)
  4017. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_CBUF_N_REQS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFF8F))
  4018. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_CBUF_N_REQS_DISABLE (IMG_UINT64_C(0000000000000000))
  4019. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_CBUF_N_REQS_N_64 (IMG_UINT64_C(0x0000000000000010))
  4020. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_CBUF_N_REQS_N_128 (IMG_UINT64_C(0x0000000000000020))
  4021. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_CBUF_N_REQS_N_192 (IMG_UINT64_C(0x0000000000000030))
  4022. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_CBUF_N_REQS_N_256 (IMG_UINT64_C(0x0000000000000040))
  4023. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_CBUF_N_REQS_N_320 (IMG_UINT64_C(0x0000000000000050))
  4024. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_CBUF_N_REQS_N_384 (IMG_UINT64_C(0x0000000000000060))
  4025. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_CBUF_N_REQS_N_448 (IMG_UINT64_C(0x0000000000000070))
  4026. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_IBUF_N_REQS_SHIFT (0U)
  4027. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_IBUF_N_REQS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF8))
  4028. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_IBUF_N_REQS_DISABLE (IMG_UINT64_C(0000000000000000))
  4029. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_IBUF_N_REQS_N_64 (IMG_UINT64_C(0x0000000000000001))
  4030. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_IBUF_N_REQS_N_128 (IMG_UINT64_C(0x0000000000000002))
  4031. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_IBUF_N_REQS_N_192 (IMG_UINT64_C(0x0000000000000003))
  4032. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_IBUF_N_REQS_N_256 (IMG_UINT64_C(0x0000000000000004))
  4033. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_IBUF_N_REQS_N_320 (IMG_UINT64_C(0x0000000000000005))
  4034. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_IBUF_N_REQS_N_384 (IMG_UINT64_C(0x0000000000000006))
  4035. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_IBUF_N_REQS_N_448 (IMG_UINT64_C(0x0000000000000007))
  4036. /*
  4037. Register VHA_CR_OS2_CNN_ALT_ADDRESS8
  4038. */
  4039. #define VHA_CR_OS2_CNN_ALT_ADDRESS8 (0x30140U)
  4040. #define VHA_CR_OS2_CNN_ALT_ADDRESS8_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  4041. #define VHA_CR_OS2_CNN_ALT_ADDRESS8_ALT_ADDR_SHIFT (0U)
  4042. #define VHA_CR_OS2_CNN_ALT_ADDRESS8_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  4043. /*
  4044. Register VHA_CR_OS2_CNN_ALT_ADDRESS9
  4045. */
  4046. #define VHA_CR_OS2_CNN_ALT_ADDRESS9 (0x30148U)
  4047. #define VHA_CR_OS2_CNN_ALT_ADDRESS9_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  4048. #define VHA_CR_OS2_CNN_ALT_ADDRESS9_ALT_ADDR_SHIFT (0U)
  4049. #define VHA_CR_OS2_CNN_ALT_ADDRESS9_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  4050. /*
  4051. Register VHA_CR_OS2_CNN_ALT_ADDRESS10
  4052. */
  4053. #define VHA_CR_OS2_CNN_ALT_ADDRESS10 (0x30150U)
  4054. #define VHA_CR_OS2_CNN_ALT_ADDRESS10_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  4055. #define VHA_CR_OS2_CNN_ALT_ADDRESS10_ALT_ADDR_SHIFT (0U)
  4056. #define VHA_CR_OS2_CNN_ALT_ADDRESS10_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  4057. /*
  4058. Register VHA_CR_OS2_CNN_ALT_ADDRESS11
  4059. */
  4060. #define VHA_CR_OS2_CNN_ALT_ADDRESS11 (0x30158U)
  4061. #define VHA_CR_OS2_CNN_ALT_ADDRESS11_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  4062. #define VHA_CR_OS2_CNN_ALT_ADDRESS11_ALT_ADDR_SHIFT (0U)
  4063. #define VHA_CR_OS2_CNN_ALT_ADDRESS11_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  4064. /*
  4065. Register VHA_CR_OS2_CNN_ALT_ADDRESS12
  4066. */
  4067. #define VHA_CR_OS2_CNN_ALT_ADDRESS12 (0x30160U)
  4068. #define VHA_CR_OS2_CNN_ALT_ADDRESS12_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  4069. #define VHA_CR_OS2_CNN_ALT_ADDRESS12_ALT_ADDR_SHIFT (0U)
  4070. #define VHA_CR_OS2_CNN_ALT_ADDRESS12_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  4071. /*
  4072. Register VHA_CR_OS2_CNN_ALT_ADDRESS13
  4073. */
  4074. #define VHA_CR_OS2_CNN_ALT_ADDRESS13 (0x30168U)
  4075. #define VHA_CR_OS2_CNN_ALT_ADDRESS13_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  4076. #define VHA_CR_OS2_CNN_ALT_ADDRESS13_ALT_ADDR_SHIFT (0U)
  4077. #define VHA_CR_OS2_CNN_ALT_ADDRESS13_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  4078. /*
  4079. Register VHA_CR_OS2_CNN_ALT_ADDRESS14
  4080. */
  4081. #define VHA_CR_OS2_CNN_ALT_ADDRESS14 (0x30170U)
  4082. #define VHA_CR_OS2_CNN_ALT_ADDRESS14_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  4083. #define VHA_CR_OS2_CNN_ALT_ADDRESS14_ALT_ADDR_SHIFT (0U)
  4084. #define VHA_CR_OS2_CNN_ALT_ADDRESS14_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  4085. /*
  4086. Register VHA_CR_OS2_CNN_ALT_ADDRESS15
  4087. */
  4088. #define VHA_CR_OS2_CNN_ALT_ADDRESS15 (0x30178U)
  4089. #define VHA_CR_OS2_CNN_ALT_ADDRESS15_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  4090. #define VHA_CR_OS2_CNN_ALT_ADDRESS15_ALT_ADDR_SHIFT (0U)
  4091. #define VHA_CR_OS2_CNN_ALT_ADDRESS15_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  4092. /*
  4093. Register VHA_CR_OS2_CNN_PERFORMANCE
  4094. */
  4095. #define VHA_CR_OS2_CNN_PERFORMANCE (0x301A0U)
  4096. #define VHA_CR_OS2_CNN_PERFORMANCE_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  4097. #define VHA_CR_OS2_CNN_PERFORMANCE_VALUE_SHIFT (0U)
  4098. #define VHA_CR_OS2_CNN_PERFORMANCE_VALUE_CLRMSK (00000000U)
  4099. /*
  4100. Register VHA_CR_OS2_MMU_CTRL_INVAL
  4101. */
  4102. #define VHA_CR_OS2_MMU_CTRL_INVAL (0x3E000U)
  4103. #define VHA_CR_OS2_MMU_CTRL_INVAL_MASKFULL (IMG_UINT64_C(0x0000000000000FFF))
  4104. #define VHA_CR_OS2_MMU_CTRL_INVAL_ALL_CONTEXTS_SHIFT (11U)
  4105. #define VHA_CR_OS2_MMU_CTRL_INVAL_ALL_CONTEXTS_CLRMSK (0XFFFFF7FFU)
  4106. #define VHA_CR_OS2_MMU_CTRL_INVAL_ALL_CONTEXTS_EN (0X00000800U)
  4107. #define VHA_CR_OS2_MMU_CTRL_INVAL_CONTEXT_SHIFT (3U)
  4108. #define VHA_CR_OS2_MMU_CTRL_INVAL_CONTEXT_CLRMSK (0XFFFFF807U)
  4109. #define VHA_CR_OS2_MMU_CTRL_INVAL_PC_SHIFT (2U)
  4110. #define VHA_CR_OS2_MMU_CTRL_INVAL_PC_CLRMSK (0XFFFFFFFBU)
  4111. #define VHA_CR_OS2_MMU_CTRL_INVAL_PC_EN (0X00000004U)
  4112. #define VHA_CR_OS2_MMU_CTRL_INVAL_PD_SHIFT (1U)
  4113. #define VHA_CR_OS2_MMU_CTRL_INVAL_PD_CLRMSK (0XFFFFFFFDU)
  4114. #define VHA_CR_OS2_MMU_CTRL_INVAL_PD_EN (0X00000002U)
  4115. #define VHA_CR_OS2_MMU_CTRL_INVAL_PT_SHIFT (0U)
  4116. #define VHA_CR_OS2_MMU_CTRL_INVAL_PT_CLRMSK (0XFFFFFFFEU)
  4117. #define VHA_CR_OS2_MMU_CTRL_INVAL_PT_EN (0X00000001U)
  4118. /*
  4119. Register VHA_CR_OS2_MMU_CTRL_INVAL_STATUS
  4120. */
  4121. #define VHA_CR_OS2_MMU_CTRL_INVAL_STATUS (0x3E038U)
  4122. #define VHA_CR_OS2_MMU_CTRL_INVAL_STATUS_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  4123. #define VHA_CR_OS2_MMU_CTRL_INVAL_STATUS_PENDING_SHIFT (0U)
  4124. #define VHA_CR_OS2_MMU_CTRL_INVAL_STATUS_PENDING_CLRMSK (0XFFFFFFFEU)
  4125. #define VHA_CR_OS2_MMU_CTRL_INVAL_STATUS_PENDING_EN (0X00000001U)
  4126. /*
  4127. Register VHA_CR_OS2_MMU_CBASE_MAPPING_CONTEXT
  4128. */
  4129. #define VHA_CR_OS2_MMU_CBASE_MAPPING_CONTEXT (0x3E008U)
  4130. #define VHA_CR_OS2_MMU_CBASE_MAPPING_CONTEXT_MASKFULL (IMG_UINT64_C(0x00000000000000FF))
  4131. #define VHA_CR_OS2_MMU_CBASE_MAPPING_CONTEXT_ID_SHIFT (0U)
  4132. #define VHA_CR_OS2_MMU_CBASE_MAPPING_CONTEXT_ID_CLRMSK (0XFFFFFF00U)
  4133. /*
  4134. Register VHA_CR_OS2_MMU_CBASE_MAPPING
  4135. */
  4136. #define VHA_CR_OS2_MMU_CBASE_MAPPING (0x3E010U)
  4137. #define VHA_CR_OS2_MMU_CBASE_MAPPING_MASKFULL (IMG_UINT64_C(0x000000001FFFFFFF))
  4138. #define VHA_CR_OS2_MMU_CBASE_MAPPING_INVALID_SHIFT (28U)
  4139. #define VHA_CR_OS2_MMU_CBASE_MAPPING_INVALID_CLRMSK (0XEFFFFFFFU)
  4140. #define VHA_CR_OS2_MMU_CBASE_MAPPING_INVALID_EN (0X10000000U)
  4141. #define VHA_CR_OS2_MMU_CBASE_MAPPING_BASE_ADDR_SHIFT (0U)
  4142. #define VHA_CR_OS2_MMU_CBASE_MAPPING_BASE_ADDR_CLRMSK (0XF0000000U)
  4143. #define VHA_CR_OS2_MMU_CBASE_MAPPING_BASE_ADDR_ALIGNSHIFT (12U)
  4144. #define VHA_CR_OS2_MMU_CBASE_MAPPING_BASE_ADDR_ALIGNSIZE (4096U)
  4145. /*
  4146. Register VHA_CR_OS2_MMU_FAULT_STATUS1
  4147. */
  4148. #define VHA_CR_OS2_MMU_FAULT_STATUS1 (0x3E018U)
  4149. #define VHA_CR_OS2_MMU_FAULT_STATUS1_MASKFULL (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
  4150. #define VHA_CR_OS2_MMU_FAULT_STATUS1_LEVEL_SHIFT (62U)
  4151. #define VHA_CR_OS2_MMU_FAULT_STATUS1_LEVEL_CLRMSK (IMG_UINT64_C(0X3FFFFFFFFFFFFFFF))
  4152. #define VHA_CR_OS2_MMU_FAULT_STATUS1_REQ_ID_SHIFT (56U)
  4153. #define VHA_CR_OS2_MMU_FAULT_STATUS1_REQ_ID_CLRMSK (IMG_UINT64_C(0XC0FFFFFFFFFFFFFF))
  4154. #define VHA_CR_OS2_MMU_FAULT_STATUS1_CONTEXT_SHIFT (48U)
  4155. #define VHA_CR_OS2_MMU_FAULT_STATUS1_CONTEXT_CLRMSK (IMG_UINT64_C(0XFF00FFFFFFFFFFFF))
  4156. #define VHA_CR_OS2_MMU_FAULT_STATUS1_ADDRESS_SHIFT (4U)
  4157. #define VHA_CR_OS2_MMU_FAULT_STATUS1_ADDRESS_CLRMSK (IMG_UINT64_C(0XFFFF00000000000F))
  4158. #define VHA_CR_OS2_MMU_FAULT_STATUS1_RNW_SHIFT (3U)
  4159. #define VHA_CR_OS2_MMU_FAULT_STATUS1_RNW_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF7))
  4160. #define VHA_CR_OS2_MMU_FAULT_STATUS1_RNW_EN (IMG_UINT64_C(0X0000000000000008))
  4161. #define VHA_CR_OS2_MMU_FAULT_STATUS1_TYPE_SHIFT (1U)
  4162. #define VHA_CR_OS2_MMU_FAULT_STATUS1_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF9))
  4163. #define VHA_CR_OS2_MMU_FAULT_STATUS1_FAULT_SHIFT (0U)
  4164. #define VHA_CR_OS2_MMU_FAULT_STATUS1_FAULT_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  4165. #define VHA_CR_OS2_MMU_FAULT_STATUS1_FAULT_EN (IMG_UINT64_C(0X0000000000000001))
  4166. /*
  4167. Register VHA_CR_OS2_MMU_FAULT_STATUS2
  4168. */
  4169. #define VHA_CR_OS2_MMU_FAULT_STATUS2 (0x3E020U)
  4170. #define VHA_CR_OS2_MMU_FAULT_STATUS2_MASKFULL (IMG_UINT64_C(0x000000003FFF07FF))
  4171. #define VHA_CR_OS2_MMU_FAULT_STATUS2_WRITEBACK_SHIFT (29U)
  4172. #define VHA_CR_OS2_MMU_FAULT_STATUS2_WRITEBACK_CLRMSK (0XDFFFFFFFU)
  4173. #define VHA_CR_OS2_MMU_FAULT_STATUS2_WRITEBACK_EN (0X20000000U)
  4174. #define VHA_CR_OS2_MMU_FAULT_STATUS2_CLEANUNIQUE_SHIFT (28U)
  4175. #define VHA_CR_OS2_MMU_FAULT_STATUS2_CLEANUNIQUE_CLRMSK (0XEFFFFFFFU)
  4176. #define VHA_CR_OS2_MMU_FAULT_STATUS2_CLEANUNIQUE_EN (0X10000000U)
  4177. #define VHA_CR_OS2_MMU_FAULT_STATUS2_BANK_SHIFT (24U)
  4178. #define VHA_CR_OS2_MMU_FAULT_STATUS2_BANK_CLRMSK (0XF0FFFFFFU)
  4179. #define VHA_CR_OS2_MMU_FAULT_STATUS2_TLB_ENTRY_SHIFT (16U)
  4180. #define VHA_CR_OS2_MMU_FAULT_STATUS2_TLB_ENTRY_CLRMSK (0XFF00FFFFU)
  4181. #define VHA_CR_OS2_MMU_FAULT_STATUS2_FBM_FAULT_SHIFT (10U)
  4182. #define VHA_CR_OS2_MMU_FAULT_STATUS2_FBM_FAULT_CLRMSK (0XFFFFFBFFU)
  4183. #define VHA_CR_OS2_MMU_FAULT_STATUS2_FBM_FAULT_EN (0X00000400U)
  4184. #define VHA_CR_OS2_MMU_FAULT_STATUS2_BIF_ID_SHIFT (0U)
  4185. #define VHA_CR_OS2_MMU_FAULT_STATUS2_BIF_ID_CLRMSK (0XFFFFFC00U)
  4186. /*
  4187. Register VHA_CR_OS2_MMU_CTRL_LEGACY
  4188. */
  4189. #define VHA_CR_OS2_MMU_CTRL_LEGACY (0x3E040U)
  4190. #define VHA_CR_OS2_MMU_CTRL_LEGACY_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  4191. #define VHA_CR_OS2_MMU_CTRL_LEGACY_RESERVED_SHIFT (0U)
  4192. #define VHA_CR_OS2_MMU_CTRL_LEGACY_RESERVED_CLRMSK (0XFFFFFFFEU)
  4193. #define VHA_CR_OS2_MMU_CTRL_LEGACY_RESERVED_EN (0X00000001U)
  4194. #define VHA_CR_ACE_PROT_CTRL_ENUM_PROT_MASK (0x00000007U)
  4195. /*
  4196. Unprivileged secure data access*/
  4197. #define VHA_CR_ACE_PROT_CTRL_ENUM_PROT_UNPRIVILEGED_SECURE_DATA (0x00000000U)
  4198. /*
  4199. Privileged secure data access*/
  4200. #define VHA_CR_ACE_PROT_CTRL_ENUM_PROT_PRIVILEGED_SECURE_DATA (0x00000001U)
  4201. /*
  4202. Unprivileged non-secure data access*/
  4203. #define VHA_CR_ACE_PROT_CTRL_ENUM_PROT_UNPRIVILEGED_NONSECURE_DATA (0x00000002U)
  4204. /*
  4205. Privileged non-secure data access*/
  4206. #define VHA_CR_ACE_PROT_CTRL_ENUM_PROT_PRIVILEGED_NONSECURE_DATA (0x00000003U)
  4207. /*
  4208. Unprivileged secure instruction access*/
  4209. #define VHA_CR_ACE_PROT_CTRL_ENUM_PROT_UNPRIVILEGED_SECURE_INSTRUCTION (0x00000004U)
  4210. /*
  4211. Privileged secure instruction access*/
  4212. #define VHA_CR_ACE_PROT_CTRL_ENUM_PROT_PRIVILEGED_SECURE_INSTRUCTION (0x00000005U)
  4213. /*
  4214. Unprivileged non-secure instruction access*/
  4215. #define VHA_CR_ACE_PROT_CTRL_ENUM_PROT_UNPRIVILEGED_NONSECURE_INSTRUCTION (0x00000006U)
  4216. /*
  4217. Privileged non-secure instruction access*/
  4218. #define VHA_CR_ACE_PROT_CTRL_ENUM_PROT_PRIVILEGED_NONSECURE_INSTRUCTION (0x00000007U)
  4219. /*
  4220. Register VHA_CR_ACE_PROT_CTRL
  4221. */
  4222. #define VHA_CR_ACE_PROT_CTRL (0x40000U)
  4223. #define VHA_CR_ACE_PROT_CTRL_MASKFULL (IMG_UINT64_C(0x0707070707070707))
  4224. #define VHA_CR_ACE_PROT_CTRL_OSID7_SHIFT (56U)
  4225. #define VHA_CR_ACE_PROT_CTRL_OSID7_CLRMSK (IMG_UINT64_C(0XF8FFFFFFFFFFFFFF))
  4226. #define VHA_CR_ACE_PROT_CTRL_OSID7_UNPRIVILEGED_SECURE_DATA (IMG_UINT64_C(0000000000000000))
  4227. #define VHA_CR_ACE_PROT_CTRL_OSID7_PRIVILEGED_SECURE_DATA (IMG_UINT64_C(0x0100000000000000))
  4228. #define VHA_CR_ACE_PROT_CTRL_OSID7_UNPRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0200000000000000))
  4229. #define VHA_CR_ACE_PROT_CTRL_OSID7_PRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0300000000000000))
  4230. #define VHA_CR_ACE_PROT_CTRL_OSID7_UNPRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0400000000000000))
  4231. #define VHA_CR_ACE_PROT_CTRL_OSID7_PRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0500000000000000))
  4232. #define VHA_CR_ACE_PROT_CTRL_OSID7_UNPRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0600000000000000))
  4233. #define VHA_CR_ACE_PROT_CTRL_OSID7_PRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0700000000000000))
  4234. #define VHA_CR_ACE_PROT_CTRL_OSID6_SHIFT (48U)
  4235. #define VHA_CR_ACE_PROT_CTRL_OSID6_CLRMSK (IMG_UINT64_C(0XFFF8FFFFFFFFFFFF))
  4236. #define VHA_CR_ACE_PROT_CTRL_OSID6_UNPRIVILEGED_SECURE_DATA (IMG_UINT64_C(0000000000000000))
  4237. #define VHA_CR_ACE_PROT_CTRL_OSID6_PRIVILEGED_SECURE_DATA (IMG_UINT64_C(0x0001000000000000))
  4238. #define VHA_CR_ACE_PROT_CTRL_OSID6_UNPRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0002000000000000))
  4239. #define VHA_CR_ACE_PROT_CTRL_OSID6_PRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0003000000000000))
  4240. #define VHA_CR_ACE_PROT_CTRL_OSID6_UNPRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0004000000000000))
  4241. #define VHA_CR_ACE_PROT_CTRL_OSID6_PRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0005000000000000))
  4242. #define VHA_CR_ACE_PROT_CTRL_OSID6_UNPRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0006000000000000))
  4243. #define VHA_CR_ACE_PROT_CTRL_OSID6_PRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0007000000000000))
  4244. #define VHA_CR_ACE_PROT_CTRL_OSID5_SHIFT (40U)
  4245. #define VHA_CR_ACE_PROT_CTRL_OSID5_CLRMSK (IMG_UINT64_C(0XFFFFF8FFFFFFFFFF))
  4246. #define VHA_CR_ACE_PROT_CTRL_OSID5_UNPRIVILEGED_SECURE_DATA (IMG_UINT64_C(0000000000000000))
  4247. #define VHA_CR_ACE_PROT_CTRL_OSID5_PRIVILEGED_SECURE_DATA (IMG_UINT64_C(0x0000010000000000))
  4248. #define VHA_CR_ACE_PROT_CTRL_OSID5_UNPRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0000020000000000))
  4249. #define VHA_CR_ACE_PROT_CTRL_OSID5_PRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0000030000000000))
  4250. #define VHA_CR_ACE_PROT_CTRL_OSID5_UNPRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0000040000000000))
  4251. #define VHA_CR_ACE_PROT_CTRL_OSID5_PRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0000050000000000))
  4252. #define VHA_CR_ACE_PROT_CTRL_OSID5_UNPRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0000060000000000))
  4253. #define VHA_CR_ACE_PROT_CTRL_OSID5_PRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0000070000000000))
  4254. #define VHA_CR_ACE_PROT_CTRL_OSID4_SHIFT (32U)
  4255. #define VHA_CR_ACE_PROT_CTRL_OSID4_CLRMSK (IMG_UINT64_C(0XFFFFFFF8FFFFFFFF))
  4256. #define VHA_CR_ACE_PROT_CTRL_OSID4_UNPRIVILEGED_SECURE_DATA (IMG_UINT64_C(0000000000000000))
  4257. #define VHA_CR_ACE_PROT_CTRL_OSID4_PRIVILEGED_SECURE_DATA (IMG_UINT64_C(0x0000000100000000))
  4258. #define VHA_CR_ACE_PROT_CTRL_OSID4_UNPRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0000000200000000))
  4259. #define VHA_CR_ACE_PROT_CTRL_OSID4_PRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0000000300000000))
  4260. #define VHA_CR_ACE_PROT_CTRL_OSID4_UNPRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0000000400000000))
  4261. #define VHA_CR_ACE_PROT_CTRL_OSID4_PRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0000000500000000))
  4262. #define VHA_CR_ACE_PROT_CTRL_OSID4_UNPRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0000000600000000))
  4263. #define VHA_CR_ACE_PROT_CTRL_OSID4_PRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0000000700000000))
  4264. #define VHA_CR_ACE_PROT_CTRL_OSID3_SHIFT (24U)
  4265. #define VHA_CR_ACE_PROT_CTRL_OSID3_CLRMSK (IMG_UINT64_C(0XFFFFFFFFF8FFFFFF))
  4266. #define VHA_CR_ACE_PROT_CTRL_OSID3_UNPRIVILEGED_SECURE_DATA (IMG_UINT64_C(0000000000000000))
  4267. #define VHA_CR_ACE_PROT_CTRL_OSID3_PRIVILEGED_SECURE_DATA (IMG_UINT64_C(0x0000000001000000))
  4268. #define VHA_CR_ACE_PROT_CTRL_OSID3_UNPRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0000000002000000))
  4269. #define VHA_CR_ACE_PROT_CTRL_OSID3_PRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0000000003000000))
  4270. #define VHA_CR_ACE_PROT_CTRL_OSID3_UNPRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0000000004000000))
  4271. #define VHA_CR_ACE_PROT_CTRL_OSID3_PRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0000000005000000))
  4272. #define VHA_CR_ACE_PROT_CTRL_OSID3_UNPRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0000000006000000))
  4273. #define VHA_CR_ACE_PROT_CTRL_OSID3_PRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0000000007000000))
  4274. #define VHA_CR_ACE_PROT_CTRL_OSID2_SHIFT (16U)
  4275. #define VHA_CR_ACE_PROT_CTRL_OSID2_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF8FFFF))
  4276. #define VHA_CR_ACE_PROT_CTRL_OSID2_UNPRIVILEGED_SECURE_DATA (IMG_UINT64_C(0000000000000000))
  4277. #define VHA_CR_ACE_PROT_CTRL_OSID2_PRIVILEGED_SECURE_DATA (IMG_UINT64_C(0x0000000000010000))
  4278. #define VHA_CR_ACE_PROT_CTRL_OSID2_UNPRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0000000000020000))
  4279. #define VHA_CR_ACE_PROT_CTRL_OSID2_PRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0000000000030000))
  4280. #define VHA_CR_ACE_PROT_CTRL_OSID2_UNPRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0000000000040000))
  4281. #define VHA_CR_ACE_PROT_CTRL_OSID2_PRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0000000000050000))
  4282. #define VHA_CR_ACE_PROT_CTRL_OSID2_UNPRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0000000000060000))
  4283. #define VHA_CR_ACE_PROT_CTRL_OSID2_PRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0000000000070000))
  4284. #define VHA_CR_ACE_PROT_CTRL_OSID1_SHIFT (8U)
  4285. #define VHA_CR_ACE_PROT_CTRL_OSID1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF8FF))
  4286. #define VHA_CR_ACE_PROT_CTRL_OSID1_UNPRIVILEGED_SECURE_DATA (IMG_UINT64_C(0000000000000000))
  4287. #define VHA_CR_ACE_PROT_CTRL_OSID1_PRIVILEGED_SECURE_DATA (IMG_UINT64_C(0x0000000000000100))
  4288. #define VHA_CR_ACE_PROT_CTRL_OSID1_UNPRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0000000000000200))
  4289. #define VHA_CR_ACE_PROT_CTRL_OSID1_PRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0000000000000300))
  4290. #define VHA_CR_ACE_PROT_CTRL_OSID1_UNPRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0000000000000400))
  4291. #define VHA_CR_ACE_PROT_CTRL_OSID1_PRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0000000000000500))
  4292. #define VHA_CR_ACE_PROT_CTRL_OSID1_UNPRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0000000000000600))
  4293. #define VHA_CR_ACE_PROT_CTRL_OSID1_PRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0000000000000700))
  4294. #define VHA_CR_ACE_PROT_CTRL_OSID0_SHIFT (0U)
  4295. #define VHA_CR_ACE_PROT_CTRL_OSID0_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF8))
  4296. #define VHA_CR_ACE_PROT_CTRL_OSID0_UNPRIVILEGED_SECURE_DATA (IMG_UINT64_C(0000000000000000))
  4297. #define VHA_CR_ACE_PROT_CTRL_OSID0_PRIVILEGED_SECURE_DATA (IMG_UINT64_C(0x0000000000000001))
  4298. #define VHA_CR_ACE_PROT_CTRL_OSID0_UNPRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0000000000000002))
  4299. #define VHA_CR_ACE_PROT_CTRL_OSID0_PRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0000000000000003))
  4300. #define VHA_CR_ACE_PROT_CTRL_OSID0_UNPRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0000000000000004))
  4301. #define VHA_CR_ACE_PROT_CTRL_OSID0_PRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0000000000000005))
  4302. #define VHA_CR_ACE_PROT_CTRL_OSID0_UNPRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0000000000000006))
  4303. #define VHA_CR_ACE_PROT_CTRL_OSID0_PRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0000000000000007))
  4304. /*
  4305. Register VHA_CR_REQ_CTXT_OVERRIDE
  4306. */
  4307. #define VHA_CR_REQ_CTXT_OVERRIDE (0x40010U)
  4308. #define VHA_CR_REQ_CTXT_OVERRIDE_MASKFULL (IMG_UINT64_C(0x0000000000000007))
  4309. #define VHA_CR_REQ_CTXT_OVERRIDE_OVERRIDE_OS2_SHIFT (2U)
  4310. #define VHA_CR_REQ_CTXT_OVERRIDE_OVERRIDE_OS2_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFB))
  4311. #define VHA_CR_REQ_CTXT_OVERRIDE_OVERRIDE_OS2_EN (IMG_UINT64_C(0X0000000000000004))
  4312. #define VHA_CR_REQ_CTXT_OVERRIDE_OVERRIDE_OS1_SHIFT (1U)
  4313. #define VHA_CR_REQ_CTXT_OVERRIDE_OVERRIDE_OS1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFD))
  4314. #define VHA_CR_REQ_CTXT_OVERRIDE_OVERRIDE_OS1_EN (IMG_UINT64_C(0X0000000000000002))
  4315. #define VHA_CR_REQ_CTXT_OVERRIDE_OVERRIDE_OS0_SHIFT (0U)
  4316. #define VHA_CR_REQ_CTXT_OVERRIDE_OVERRIDE_OS0_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  4317. #define VHA_CR_REQ_CTXT_OVERRIDE_OVERRIDE_OS0_EN (IMG_UINT64_C(0X0000000000000001))
  4318. /*
  4319. Register VHA_CR_CNN_CMD_PRIORITY_LIMITS
  4320. */
  4321. #define VHA_CR_CNN_CMD_PRIORITY_LIMITS (0x40018U)
  4322. #define VHA_CR_CNN_CMD_PRIORITY_LIMITS_MASKFULL (IMG_UINT64_C(0x000000000000019B))
  4323. #define VHA_CR_CNN_CMD_PRIORITY_LIMITS_OS2_LIMIT_SHIFT (7U)
  4324. #define VHA_CR_CNN_CMD_PRIORITY_LIMITS_OS2_LIMIT_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFE7F))
  4325. #define VHA_CR_CNN_CMD_PRIORITY_LIMITS_OS1_LIMIT_SHIFT (3U)
  4326. #define VHA_CR_CNN_CMD_PRIORITY_LIMITS_OS1_LIMIT_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFE7))
  4327. #define VHA_CR_CNN_CMD_PRIORITY_LIMITS_OS0_LIMIT_SHIFT (0U)
  4328. #define VHA_CR_CNN_CMD_PRIORITY_LIMITS_OS0_LIMIT_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFC))
  4329. /*
  4330. Register VHA_CR_OS0_MMU_CTRL
  4331. */
  4332. #define VHA_CR_OS0_MMU_CTRL (0x40020U)
  4333. #define VHA_CR_OS0_MMU_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  4334. #define VHA_CR_OS0_MMU_CTRL_BYPASS_SHIFT (0U)
  4335. #define VHA_CR_OS0_MMU_CTRL_BYPASS_CLRMSK (0XFFFFFFFEU)
  4336. #define VHA_CR_OS0_MMU_CTRL_BYPASS_EN (0X00000001U)
  4337. /*
  4338. Register VHA_CR_OS1_MMU_CTRL
  4339. */
  4340. #define VHA_CR_OS1_MMU_CTRL (0x40028U)
  4341. #define VHA_CR_OS1_MMU_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  4342. #define VHA_CR_OS1_MMU_CTRL_BYPASS_SHIFT (0U)
  4343. #define VHA_CR_OS1_MMU_CTRL_BYPASS_CLRMSK (0XFFFFFFFEU)
  4344. #define VHA_CR_OS1_MMU_CTRL_BYPASS_EN (0X00000001U)
  4345. /*
  4346. Register VHA_CR_OS2_MMU_CTRL
  4347. */
  4348. #define VHA_CR_OS2_MMU_CTRL (0x40030U)
  4349. #define VHA_CR_OS2_MMU_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  4350. #define VHA_CR_OS2_MMU_CTRL_BYPASS_SHIFT (0U)
  4351. #define VHA_CR_OS2_MMU_CTRL_BYPASS_CLRMSK (0XFFFFFFFEU)
  4352. #define VHA_CR_OS2_MMU_CTRL_BYPASS_EN (0X00000001U)
  4353. /*
  4354. Register VHA_CR_SOCIF_BUS_SECURE
  4355. */
  4356. #define VHA_CR_SOCIF_BUS_SECURE (0x4A100U)
  4357. #define VHA_CR_SOCIF_BUS_SECURE_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  4358. #define VHA_CR_SOCIF_BUS_SECURE_ENABLE_SHIFT (0U)
  4359. #define VHA_CR_SOCIF_BUS_SECURE_ENABLE_CLRMSK (0XFFFFFFFEU)
  4360. #define VHA_CR_SOCIF_BUS_SECURE_ENABLE_EN (0X00000001U)
  4361. #endif /* _VHA_CR_GYRUS_H_ */
  4362. /*****************************************************************************
  4363. End of file (vha_cr_gyrus.h)
  4364. *****************************************************************************/