vha_cr_aura.h 308 KB

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  1. /*************************************************************************/ /*!
  2. @Title Hardware definition file vha_cr_aura.h
  3. @Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved
  4. */ /**************************************************************************/
  5. /* **** Autogenerated C -- do not edit **** */
  6. /*
  7. */
  8. #ifndef _VHA_CR_AURA_H_
  9. #define _VHA_CR_AURA_H_
  10. #define VHA_CR_AURA_REVISION 1
  11. #define VHA_CR_MH_CONTROL_MAX_BURST_LENGTH_MASK (0x00000003U)
  12. /*
  13. Clock is gated and the module is inactive */
  14. #define VHA_CR_CLK_STATUS0_MODE_GATED (0x00000000U)
  15. /*
  16. Clock is running */
  17. #define VHA_CR_CLK_STATUS0_MODE_RUNNING (0x00000001U)
  18. /*
  19. Register VHA_CR_CLK_STATUS0
  20. */
  21. #define VHA_CR_CLK_STATUS0 (0x0008U)
  22. #define VHA_CR_CLK_STATUS0_MASKFULL (IMG_UINT64_C(0x00000037FFDC0104))
  23. #define VHA_CR_CLK_STATUS0_CNN_CORE_XBAR_SHIFT (37U)
  24. #define VHA_CR_CLK_STATUS0_CNN_CORE_XBAR_CLRMSK (IMG_UINT64_C(0XFFFFFFDFFFFFFFFF))
  25. #define VHA_CR_CLK_STATUS0_CNN_CORE_XBAR_GATED (IMG_UINT64_C(0000000000000000))
  26. #define VHA_CR_CLK_STATUS0_CNN_CORE_XBAR_RUNNING (IMG_UINT64_C(0x0000002000000000))
  27. #define VHA_CR_CLK_STATUS0_CNN_MMM_SHIFT (36U)
  28. #define VHA_CR_CLK_STATUS0_CNN_MMM_CLRMSK (IMG_UINT64_C(0XFFFFFFEFFFFFFFFF))
  29. #define VHA_CR_CLK_STATUS0_CNN_MMM_GATED (IMG_UINT64_C(0000000000000000))
  30. #define VHA_CR_CLK_STATUS0_CNN_MMM_RUNNING (IMG_UINT64_C(0x0000001000000000))
  31. #define VHA_CR_CLK_STATUS0_CNN_EWO_SHIFT (34U)
  32. #define VHA_CR_CLK_STATUS0_CNN_EWO_CLRMSK (IMG_UINT64_C(0XFFFFFFFBFFFFFFFF))
  33. #define VHA_CR_CLK_STATUS0_CNN_EWO_GATED (IMG_UINT64_C(0000000000000000))
  34. #define VHA_CR_CLK_STATUS0_CNN_EWO_RUNNING (IMG_UINT64_C(0x0000000400000000))
  35. #define VHA_CR_CLK_STATUS0_CNN_PACK_SHIFT (33U)
  36. #define VHA_CR_CLK_STATUS0_CNN_PACK_CLRMSK (IMG_UINT64_C(0XFFFFFFFDFFFFFFFF))
  37. #define VHA_CR_CLK_STATUS0_CNN_PACK_GATED (IMG_UINT64_C(0000000000000000))
  38. #define VHA_CR_CLK_STATUS0_CNN_PACK_RUNNING (IMG_UINT64_C(0x0000000200000000))
  39. #define VHA_CR_CLK_STATUS0_CNN_OIN_SHIFT (32U)
  40. #define VHA_CR_CLK_STATUS0_CNN_OIN_CLRMSK (IMG_UINT64_C(0XFFFFFFFEFFFFFFFF))
  41. #define VHA_CR_CLK_STATUS0_CNN_OIN_GATED (IMG_UINT64_C(0000000000000000))
  42. #define VHA_CR_CLK_STATUS0_CNN_OIN_RUNNING (IMG_UINT64_C(0x0000000100000000))
  43. #define VHA_CR_CLK_STATUS0_CNN_POOL_SHIFT (31U)
  44. #define VHA_CR_CLK_STATUS0_CNN_POOL_CLRMSK (IMG_UINT64_C(0XFFFFFFFF7FFFFFFF))
  45. #define VHA_CR_CLK_STATUS0_CNN_POOL_GATED (IMG_UINT64_C(0000000000000000))
  46. #define VHA_CR_CLK_STATUS0_CNN_POOL_RUNNING (IMG_UINT64_C(0x0000000080000000))
  47. #define VHA_CR_CLK_STATUS0_CNN_SB_SHIFT (30U)
  48. #define VHA_CR_CLK_STATUS0_CNN_SB_CLRMSK (IMG_UINT64_C(0XFFFFFFFFBFFFFFFF))
  49. #define VHA_CR_CLK_STATUS0_CNN_SB_GATED (IMG_UINT64_C(0000000000000000))
  50. #define VHA_CR_CLK_STATUS0_CNN_SB_RUNNING (IMG_UINT64_C(0x0000000040000000))
  51. #define VHA_CR_CLK_STATUS0_CNN_XBAR_SHIFT (29U)
  52. #define VHA_CR_CLK_STATUS0_CNN_XBAR_CLRMSK (IMG_UINT64_C(0XFFFFFFFFDFFFFFFF))
  53. #define VHA_CR_CLK_STATUS0_CNN_XBAR_GATED (IMG_UINT64_C(0000000000000000))
  54. #define VHA_CR_CLK_STATUS0_CNN_XBAR_RUNNING (IMG_UINT64_C(0x0000000020000000))
  55. #define VHA_CR_CLK_STATUS0_CNN_NORM_SHIFT (28U)
  56. #define VHA_CR_CLK_STATUS0_CNN_NORM_CLRMSK (IMG_UINT64_C(0XFFFFFFFFEFFFFFFF))
  57. #define VHA_CR_CLK_STATUS0_CNN_NORM_GATED (IMG_UINT64_C(0000000000000000))
  58. #define VHA_CR_CLK_STATUS0_CNN_NORM_RUNNING (IMG_UINT64_C(0x0000000010000000))
  59. #define VHA_CR_CLK_STATUS0_CNN_ACT_SHIFT (27U)
  60. #define VHA_CR_CLK_STATUS0_CNN_ACT_CLRMSK (IMG_UINT64_C(0XFFFFFFFFF7FFFFFF))
  61. #define VHA_CR_CLK_STATUS0_CNN_ACT_GATED (IMG_UINT64_C(0000000000000000))
  62. #define VHA_CR_CLK_STATUS0_CNN_ACT_RUNNING (IMG_UINT64_C(0x0000000008000000))
  63. #define VHA_CR_CLK_STATUS0_CNN_ACCUM_SHIFT (26U)
  64. #define VHA_CR_CLK_STATUS0_CNN_ACCUM_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFBFFFFFF))
  65. #define VHA_CR_CLK_STATUS0_CNN_ACCUM_GATED (IMG_UINT64_C(0000000000000000))
  66. #define VHA_CR_CLK_STATUS0_CNN_ACCUM_RUNNING (IMG_UINT64_C(0x0000000004000000))
  67. #define VHA_CR_CLK_STATUS0_CNN_CNV_SHIFT (25U)
  68. #define VHA_CR_CLK_STATUS0_CNN_CNV_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFDFFFFFF))
  69. #define VHA_CR_CLK_STATUS0_CNN_CNV_GATED (IMG_UINT64_C(0000000000000000))
  70. #define VHA_CR_CLK_STATUS0_CNN_CNV_RUNNING (IMG_UINT64_C(0x0000000002000000))
  71. #define VHA_CR_CLK_STATUS0_CNN_CBUF_SHIFT (24U)
  72. #define VHA_CR_CLK_STATUS0_CNN_CBUF_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFEFFFFFF))
  73. #define VHA_CR_CLK_STATUS0_CNN_CBUF_GATED (IMG_UINT64_C(0000000000000000))
  74. #define VHA_CR_CLK_STATUS0_CNN_CBUF_RUNNING (IMG_UINT64_C(0x0000000001000000))
  75. #define VHA_CR_CLK_STATUS0_CNN_IBUF_SHIFT (23U)
  76. #define VHA_CR_CLK_STATUS0_CNN_IBUF_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF7FFFFF))
  77. #define VHA_CR_CLK_STATUS0_CNN_IBUF_GATED (IMG_UINT64_C(0000000000000000))
  78. #define VHA_CR_CLK_STATUS0_CNN_IBUF_RUNNING (IMG_UINT64_C(0x0000000000800000))
  79. #define VHA_CR_CLK_STATUS0_CNN_CMD_SHIFT (22U)
  80. #define VHA_CR_CLK_STATUS0_CNN_CMD_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFBFFFFF))
  81. #define VHA_CR_CLK_STATUS0_CNN_CMD_GATED (IMG_UINT64_C(0000000000000000))
  82. #define VHA_CR_CLK_STATUS0_CNN_CMD_RUNNING (IMG_UINT64_C(0x0000000000400000))
  83. #define VHA_CR_CLK_STATUS0_CNN_SHIFT (20U)
  84. #define VHA_CR_CLK_STATUS0_CNN_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFEFFFFF))
  85. #define VHA_CR_CLK_STATUS0_CNN_GATED (IMG_UINT64_C(0000000000000000))
  86. #define VHA_CR_CLK_STATUS0_CNN_RUNNING (IMG_UINT64_C(0x0000000000100000))
  87. #define VHA_CR_CLK_STATUS0_CNN_TRS_A_SHIFT (19U)
  88. #define VHA_CR_CLK_STATUS0_CNN_TRS_A_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF7FFFF))
  89. #define VHA_CR_CLK_STATUS0_CNN_TRS_A_GATED (IMG_UINT64_C(0000000000000000))
  90. #define VHA_CR_CLK_STATUS0_CNN_TRS_A_RUNNING (IMG_UINT64_C(0x0000000000080000))
  91. #define VHA_CR_CLK_STATUS0_CNN_TRS_B_SHIFT (18U)
  92. #define VHA_CR_CLK_STATUS0_CNN_TRS_B_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFBFFFF))
  93. #define VHA_CR_CLK_STATUS0_CNN_TRS_B_GATED (IMG_UINT64_C(0000000000000000))
  94. #define VHA_CR_CLK_STATUS0_CNN_TRS_B_RUNNING (IMG_UINT64_C(0x0000000000040000))
  95. #define VHA_CR_CLK_STATUS0_SLC_SHIFT (8U)
  96. #define VHA_CR_CLK_STATUS0_SLC_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFEFF))
  97. #define VHA_CR_CLK_STATUS0_SLC_GATED (IMG_UINT64_C(0000000000000000))
  98. #define VHA_CR_CLK_STATUS0_SLC_RUNNING (IMG_UINT64_C(0x0000000000000100))
  99. #define VHA_CR_CLK_STATUS0_BIF_SHIFT (2U)
  100. #define VHA_CR_CLK_STATUS0_BIF_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFB))
  101. #define VHA_CR_CLK_STATUS0_BIF_GATED (IMG_UINT64_C(0000000000000000))
  102. #define VHA_CR_CLK_STATUS0_BIF_RUNNING (IMG_UINT64_C(0x0000000000000004))
  103. /*
  104. Register VHA_CR_PRODUCT_ID
  105. */
  106. #define VHA_CR_PRODUCT_ID (0x0018U)
  107. #define VHA_CR_PRODUCT_ID_MASKFULL (IMG_UINT64_C(0x00000000FFFF0000))
  108. #define VHA_CR_PRODUCT_ID_IMG_PRODUCT_ID_SHIFT (16U)
  109. #define VHA_CR_PRODUCT_ID_IMG_PRODUCT_ID_CLRMSK (IMG_UINT64_C(0XFFFFFFFF0000FFFF))
  110. /*
  111. Register VHA_CR_CORE_ID
  112. */
  113. #define VHA_CR_CORE_ID (0x0020U)
  114. #define VHA_CR_CORE_ID_MASKFULL (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
  115. #define VHA_CR_CORE_ID_BRANCH_ID_SHIFT (48U)
  116. #define VHA_CR_CORE_ID_BRANCH_ID_CLRMSK (IMG_UINT64_C(0X0000FFFFFFFFFFFF))
  117. #define VHA_CR_CORE_ID_VERSION_ID_SHIFT (32U)
  118. #define VHA_CR_CORE_ID_VERSION_ID_CLRMSK (IMG_UINT64_C(0XFFFF0000FFFFFFFF))
  119. #define VHA_CR_CORE_ID_NUMBER_OF_SCALABLE_UNITS_SHIFT (16U)
  120. #define VHA_CR_CORE_ID_NUMBER_OF_SCALABLE_UNITS_CLRMSK (IMG_UINT64_C(0XFFFFFFFF0000FFFF))
  121. #define VHA_CR_CORE_ID_CONFIG_ID_SHIFT (0U)
  122. #define VHA_CR_CORE_ID_CONFIG_ID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF0000))
  123. /*
  124. Register VHA_CR_CORE_IP_INTEGRATOR_ID
  125. */
  126. #define VHA_CR_CORE_IP_INTEGRATOR_ID (0x0028U)
  127. #define VHA_CR_CORE_IP_INTEGRATOR_ID_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  128. #define VHA_CR_CORE_IP_INTEGRATOR_ID_VALUE_SHIFT (0U)
  129. #define VHA_CR_CORE_IP_INTEGRATOR_ID_VALUE_CLRMSK (IMG_UINT64_C(0XFFFFFFFF00000000))
  130. /*
  131. Register VHA_CR_CORE_IP_CHANGELIST
  132. */
  133. #define VHA_CR_CORE_IP_CHANGELIST (0x0030U)
  134. #define VHA_CR_CORE_IP_CHANGELIST_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  135. #define VHA_CR_CORE_IP_CHANGELIST_VALUE_SHIFT (0U)
  136. #define VHA_CR_CORE_IP_CHANGELIST_VALUE_CLRMSK (IMG_UINT64_C(0XFFFFFFFF00000000))
  137. /*
  138. Register VHA_CR_CORE_IP_CONFIG
  139. */
  140. #define VHA_CR_CORE_IP_CONFIG (0x0038U)
  141. #define VHA_CR_CORE_IP_CONFIG_MASKFULL (IMG_UINT64_C(0x00000000000FFF03))
  142. #define VHA_CR_CORE_IP_CONFIG_SIGNATURES_SUPPORTED_SAFETY_SHIFT (19U)
  143. #define VHA_CR_CORE_IP_CONFIG_SIGNATURES_SUPPORTED_SAFETY_CLRMSK (0XFFF7FFFFU)
  144. #define VHA_CR_CORE_IP_CONFIG_SIGNATURES_SUPPORTED_SAFETY_EN (0X00080000U)
  145. #define VHA_CR_CORE_IP_CONFIG_OCM_SECURITY_SHIFT (18U)
  146. #define VHA_CR_CORE_IP_CONFIG_OCM_SECURITY_CLRMSK (0XFFFBFFFFU)
  147. #define VHA_CR_CORE_IP_CONFIG_OCM_SECURITY_EN (0X00040000U)
  148. #define VHA_CR_CORE_IP_CONFIG_ECC_RAMS_SHIFT (16U)
  149. #define VHA_CR_CORE_IP_CONFIG_ECC_RAMS_CLRMSK (0XFFFCFFFFU)
  150. #define VHA_CR_CORE_IP_CONFIG_PARITY_REGISTERS_SHIFT (15U)
  151. #define VHA_CR_CORE_IP_CONFIG_PARITY_REGISTERS_CLRMSK (0XFFFF7FFFU)
  152. #define VHA_CR_CORE_IP_CONFIG_PARITY_REGISTERS_EN (0X00008000U)
  153. #define VHA_CR_CORE_IP_CONFIG_MMU_VERSION_SHIFT (12U)
  154. #define VHA_CR_CORE_IP_CONFIG_MMU_VERSION_CLRMSK (0XFFFF8FFFU)
  155. #define VHA_CR_CORE_IP_CONFIG_SIGNATURES_SUPPORTED_SUBSET_SHIFT (11U)
  156. #define VHA_CR_CORE_IP_CONFIG_SIGNATURES_SUPPORTED_SUBSET_CLRMSK (0XFFFFF7FFU)
  157. #define VHA_CR_CORE_IP_CONFIG_SIGNATURES_SUPPORTED_SUBSET_EN (0X00000800U)
  158. #define VHA_CR_CORE_IP_CONFIG_SIGNATURES_SUPPORTED_ALL_SHIFT (10U)
  159. #define VHA_CR_CORE_IP_CONFIG_SIGNATURES_SUPPORTED_ALL_CLRMSK (0XFFFFFBFFU)
  160. #define VHA_CR_CORE_IP_CONFIG_SIGNATURES_SUPPORTED_ALL_EN (0X00000400U)
  161. #define VHA_CR_CORE_IP_CONFIG_RANDOM_STALLERS_SUPPORTED_SHIFT (9U)
  162. #define VHA_CR_CORE_IP_CONFIG_RANDOM_STALLERS_SUPPORTED_CLRMSK (0XFFFFFDFFU)
  163. #define VHA_CR_CORE_IP_CONFIG_RANDOM_STALLERS_SUPPORTED_EN (0X00000200U)
  164. #define VHA_CR_CORE_IP_CONFIG_RTM_SUPPORTED_SHIFT (8U)
  165. #define VHA_CR_CORE_IP_CONFIG_RTM_SUPPORTED_CLRMSK (0XFFFFFEFFU)
  166. #define VHA_CR_CORE_IP_CONFIG_RTM_SUPPORTED_EN (0X00000100U)
  167. #define VHA_CR_CORE_IP_CONFIG_SCL_SUPPORTED_SHIFT (1U)
  168. #define VHA_CR_CORE_IP_CONFIG_SCL_SUPPORTED_CLRMSK (0XFFFFFFFDU)
  169. #define VHA_CR_CORE_IP_CONFIG_SCL_SUPPORTED_EN (0X00000002U)
  170. #define VHA_CR_CORE_IP_CONFIG_CNN_SUPPORTED_SHIFT (0U)
  171. #define VHA_CR_CORE_IP_CONFIG_CNN_SUPPORTED_CLRMSK (0XFFFFFFFEU)
  172. #define VHA_CR_CORE_IP_CONFIG_CNN_SUPPORTED_EN (0X00000001U)
  173. /*
  174. Register VHA_CR_CNN_MEM_WDT_TIMER
  175. */
  176. #define VHA_CR_CNN_MEM_WDT_TIMER (0x0048U)
  177. #define VHA_CR_CNN_MEM_WDT_TIMER_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  178. #define VHA_CR_CNN_MEM_WDT_TIMER_VALUE_SHIFT (0U)
  179. #define VHA_CR_CNN_MEM_WDT_TIMER_VALUE_CLRMSK (00000000U)
  180. /*
  181. Register VHA_CR_CNN_HL_WDT_TIMER
  182. */
  183. #define VHA_CR_CNN_HL_WDT_TIMER (0x0050U)
  184. #define VHA_CR_CNN_HL_WDT_TIMER_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  185. #define VHA_CR_CNN_HL_WDT_TIMER_VALUE_SHIFT (0U)
  186. #define VHA_CR_CNN_HL_WDT_TIMER_VALUE_CLRMSK (00000000U)
  187. /*
  188. Register VHA_CR_RTM_CTRL
  189. */
  190. #define VHA_CR_RTM_CTRL (0x0058U)
  191. #define VHA_CR_RTM_CTRL_MASKFULL (IMG_UINT64_C(0x00000000CFFFFFF8))
  192. #define VHA_CR_RTM_CTRL_RTM_ENABLE_SHIFT (31U)
  193. #define VHA_CR_RTM_CTRL_RTM_ENABLE_CLRMSK (0X7FFFFFFFU)
  194. #define VHA_CR_RTM_CTRL_RTM_ENABLE_EN (0X80000000U)
  195. #define VHA_CR_RTM_CTRL_RTM_CHECK_SHIFT (30U)
  196. #define VHA_CR_RTM_CTRL_RTM_CHECK_CLRMSK (0XBFFFFFFFU)
  197. #define VHA_CR_RTM_CTRL_RTM_CHECK_EN (0X40000000U)
  198. #define VHA_CR_RTM_CTRL_RTM_SELECTOR_SHIFT (3U)
  199. #define VHA_CR_RTM_CTRL_RTM_SELECTOR_CLRMSK (0XF0000007U)
  200. /*
  201. Register VHA_CR_RTM_DATA
  202. */
  203. #define VHA_CR_RTM_DATA (0x0060U)
  204. #define VHA_CR_RTM_DATA_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  205. #define VHA_CR_RTM_DATA_RTM_DATA_SHIFT (0U)
  206. #define VHA_CR_RTM_DATA_RTM_DATA_CLRMSK (00000000U)
  207. /*
  208. Register VHA_CR_CNN_IP_CONFIG0
  209. */
  210. #define VHA_CR_CNN_IP_CONFIG0 (0x0068U)
  211. #define VHA_CR_CNN_IP_CONFIG0_MASKFULL (IMG_UINT64_C(0x000000001FFFFFFF))
  212. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_CMD_CRC_FOOTER_SHIFT (28U)
  213. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_CMD_CRC_FOOTER_CLRMSK (IMG_UINT64_C(0XFFFFFFFFEFFFFFFF))
  214. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_CMD_CRC_FOOTER_EN (IMG_UINT64_C(0X0000000010000000))
  215. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_MEM_REQ_PRIORITISATION_SHIFT (27U)
  216. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_MEM_REQ_PRIORITISATION_CLRMSK (IMG_UINT64_C(0XFFFFFFFFF7FFFFFF))
  217. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_MEM_REQ_PRIORITISATION_EN (IMG_UINT64_C(0X0000000008000000))
  218. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_PIPELINE_ORDER_XBAR_SHIFT (26U)
  219. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_PIPELINE_ORDER_XBAR_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFBFFFFFF))
  220. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_PIPELINE_ORDER_XBAR_EN (IMG_UINT64_C(0X0000000004000000))
  221. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DEPTHWISE_POOLING_ENGINE_SHIFT (25U)
  222. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DEPTHWISE_POOLING_ENGINE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFDFFFFFF))
  223. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DEPTHWISE_POOLING_ENGINE_EN (IMG_UINT64_C(0X0000000002000000))
  224. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_PARALLEL_MMM_SUPPORTED_SHIFT (24U)
  225. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_PARALLEL_MMM_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFEFFFFFF))
  226. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_PARALLEL_MMM_SUPPORTED_EN (IMG_UINT64_C(0X0000000001000000))
  227. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_MMU_PRELOADS_SHIFT (23U)
  228. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_MMU_PRELOADS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF7FFFFF))
  229. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_MMU_PRELOADS_EN (IMG_UINT64_C(0X0000000000800000))
  230. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_MMM_SUPPORTED_SHIFT (22U)
  231. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_MMM_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFBFFFFF))
  232. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_MMM_SUPPORTED_EN (IMG_UINT64_C(0X0000000000400000))
  233. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_SCHEDULING_SUPPORTED_SHIFT (21U)
  234. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_SCHEDULING_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFDFFFFF))
  235. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_SCHEDULING_SUPPORTED_EN (IMG_UINT64_C(0X0000000000200000))
  236. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_SECURITY_SHIFT (20U)
  237. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_SECURITY_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFEFFFFF))
  238. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_SECURITY_EN (IMG_UINT64_C(0X0000000000100000))
  239. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_CBUF_DECOMPRESSION_SUPPORTED_SHIFT (19U)
  240. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_CBUF_DECOMPRESSION_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF7FFFF))
  241. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_CBUF_DECOMPRESSION_SUPPORTED_EN (IMG_UINT64_C(0X0000000000080000))
  242. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_POOL_MIN_SUPPORTED_SHIFT (18U)
  243. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_POOL_MIN_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFBFFFF))
  244. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_POOL_MIN_SUPPORTED_EN (IMG_UINT64_C(0X0000000000040000))
  245. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_UNSIGNED_SUPPORTED_SHIFT (17U)
  246. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_UNSIGNED_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFDFFFF))
  247. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_UNSIGNED_SUPPORTED_EN (IMG_UINT64_C(0X0000000000020000))
  248. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_MIRROR_PADDING_SUPPORTED_SHIFT (16U)
  249. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_MIRROR_PADDING_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFEFFFF))
  250. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_MIRROR_PADDING_SUPPORTED_EN (IMG_UINT64_C(0X0000000000010000))
  251. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_EWO_BROADCAST_SUPPORTED_SHIFT (15U)
  252. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_EWO_BROADCAST_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF7FFF))
  253. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_EWO_BROADCAST_SUPPORTED_EN (IMG_UINT64_C(0X0000000000008000))
  254. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_HALF_16BIT_CONV_SUPPORTED_SHIFT (14U)
  255. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_HALF_16BIT_CONV_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFBFFF))
  256. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_HALF_16BIT_CONV_SUPPORTED_EN (IMG_UINT64_C(0X0000000000004000))
  257. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_OUTPUT_FIXTOFIX_SUPPORTED_SHIFT (13U)
  258. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_OUTPUT_FIXTOFIX_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFDFFF))
  259. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_OUTPUT_FIXTOFIX_SUPPORTED_EN (IMG_UINT64_C(0X0000000000002000))
  260. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DUAL_8BIT_CONV_SUPPORTED_SHIFT (12U)
  261. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DUAL_8BIT_CONV_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFEFFF))
  262. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DUAL_8BIT_CONV_SUPPORTED_EN (IMG_UINT64_C(0X0000000000001000))
  263. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DATA_DECOMPRESSION_SUPPORTED_SHIFT (11U)
  264. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DATA_DECOMPRESSION_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF7FF))
  265. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DATA_DECOMPRESSION_SUPPORTED_EN (IMG_UINT64_C(0X0000000000000800))
  266. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DATA_COMPRESSION_SUPPORTED_SHIFT (10U)
  267. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DATA_COMPRESSION_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFBFF))
  268. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DATA_COMPRESSION_SUPPORTED_EN (IMG_UINT64_C(0X0000000000000400))
  269. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_ELEMENT_OPS_CALC_SUPPORTED_SHIFT (9U)
  270. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_ELEMENT_OPS_CALC_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFDFF))
  271. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_ELEMENT_OPS_CALC_SUPPORTED_EN (IMG_UINT64_C(0X0000000000000200))
  272. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_ELEMENT_OPS_FETCH_SUPPORTED_SHIFT (8U)
  273. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_ELEMENT_OPS_FETCH_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFEFF))
  274. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_ELEMENT_OPS_FETCH_SUPPORTED_EN (IMG_UINT64_C(0X0000000000000100))
  275. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_ELEMENT_OPS_SUPPORTED_SHIFT (7U)
  276. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_ELEMENT_OPS_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFF7F))
  277. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_ELEMENT_OPS_SUPPORTED_EN (IMG_UINT64_C(0X0000000000000080))
  278. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_POOL_AVG_SUPPORTED_SHIFT (6U)
  279. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_POOL_AVG_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFBF))
  280. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_POOL_AVG_SUPPORTED_EN (IMG_UINT64_C(0X0000000000000040))
  281. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_POOL_MAX_SUPPORTED_SHIFT (5U)
  282. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_POOL_MAX_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFDF))
  283. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_POOL_MAX_SUPPORTED_EN (IMG_UINT64_C(0X0000000000000020))
  284. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_NORM_ICN_SUPPORTED_SHIFT (4U)
  285. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_NORM_ICN_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFEF))
  286. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_NORM_ICN_SUPPORTED_EN (IMG_UINT64_C(0X0000000000000010))
  287. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_NORM_ACN_SUPPORTED_SHIFT (3U)
  288. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_NORM_ACN_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF7))
  289. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_NORM_ACN_SUPPORTED_EN (IMG_UINT64_C(0X0000000000000008))
  290. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_ACT_LUT_SUPPORTED_SHIFT (2U)
  291. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_ACT_LUT_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFB))
  292. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_ACT_LUT_SUPPORTED_EN (IMG_UINT64_C(0X0000000000000004))
  293. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DECONV_SUPPORTED_SHIFT (1U)
  294. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DECONV_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFD))
  295. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_DECONV_SUPPORTED_EN (IMG_UINT64_C(0X0000000000000002))
  296. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_CONV_SUPPORTED_SHIFT (0U)
  297. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_CONV_SUPPORTED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  298. #define VHA_CR_CNN_IP_CONFIG0_VHA_CNN_CONV_SUPPORTED_EN (IMG_UINT64_C(0X0000000000000001))
  299. /*
  300. Register VHA_CR_CNN_IP_CONFIG1
  301. */
  302. #define VHA_CR_CNN_IP_CONFIG1 (0x0070U)
  303. #define VHA_CR_CNN_IP_CONFIG1_MASKFULL (IMG_UINT64_C(0xFFFFFFFF3F0FFFFF))
  304. #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_ADDRESS_ALIGNMENT_BYTES_LOG2_SHIFT (60U)
  305. #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_ADDRESS_ALIGNMENT_BYTES_LOG2_CLRMSK (IMG_UINT64_C(0X0FFFFFFFFFFFFFFF))
  306. #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_MAX_FILTERS_PER_SET_MIN1_SHIFT (52U)
  307. #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_MAX_FILTERS_PER_SET_MIN1_CLRMSK (IMG_UINT64_C(0XF00FFFFFFFFFFFFF))
  308. #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_MAX_FILTERS_MIN1_SHIFT (39U)
  309. #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_MAX_FILTERS_MIN1_CLRMSK (IMG_UINT64_C(0XFFF0007FFFFFFFFF))
  310. #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_SCHEDULING_NUM_PRIORITY_MIN1_SHIFT (37U)
  311. #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_SCHEDULING_NUM_PRIORITY_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFF9FFFFFFFFF))
  312. #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_CONV_ENGINE_CALC_BLOCKS_MIN1_SHIFT (32U)
  313. #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_CONV_ENGINE_CALC_BLOCKS_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFE0FFFFFFFF))
  314. #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_WEIGHT_DATA_WIDTH_MIN1_SHIFT (24U)
  315. #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_WEIGHT_DATA_WIDTH_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFC0FFFFFF))
  316. #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_ACTIVATION_DATA_WIDTH_MIN1_SHIFT (16U)
  317. #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_ACTIVATION_DATA_WIDTH_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF0FFFF))
  318. #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_CONV_ENGINE_NUM_FILTERS_MIN1_SHIFT (12U)
  319. #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_CONV_ENGINE_NUM_FILTERS_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF0FFF))
  320. #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_CONV_ENGINE_NUM_COEFFS_MIN1_SHIFT (4U)
  321. #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_CONV_ENGINE_NUM_COEFFS_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF00F))
  322. #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_SCHEDULING_NUM_HOSTS_MIN1_SHIFT (0U)
  323. #define VHA_CR_CNN_IP_CONFIG1_VHA_CNN_SCHEDULING_NUM_HOSTS_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF0))
  324. /*
  325. Register VHA_CR_CNN_IP_CONFIG2
  326. */
  327. #define VHA_CR_CNN_IP_CONFIG2 (0x0078U)
  328. #define VHA_CR_CNN_IP_CONFIG2_MASKFULL (IMG_UINT64_C(0x00FFFFFFFFFFFFFF))
  329. #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_TENSOR_CONCAT_MIN1_SHIFT (51U)
  330. #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_TENSOR_CONCAT_MIN1_CLRMSK (IMG_UINT64_C(0XFF07FFFFFFFFFFFF))
  331. #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_TENSOR_SPLIT_MIN1_SHIFT (48U)
  332. #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_TENSOR_SPLIT_MIN1_CLRMSK (IMG_UINT64_C(0XFFF8FFFFFFFFFFFF))
  333. #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_SHARED_BUFFER_BANKS_MIN1_SHIFT (44U)
  334. #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_SHARED_BUFFER_BANKS_MIN1_CLRMSK (IMG_UINT64_C(0XFFFF0FFFFFFFFFFF))
  335. #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_MAX_FILTERS_WITH_BIAS_MIN1_SHIFT (34U)
  336. #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_MAX_FILTERS_WITH_BIAS_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFF003FFFFFFFF))
  337. #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_NORM_UNITS_MIN1_SHIFT (28U)
  338. #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_NORM_UNITS_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFC0FFFFFFF))
  339. #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_SHARED_BUFFER_SIZE_MIN1_SHIFT (20U)
  340. #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_SHARED_BUFFER_SIZE_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFF00FFFFF))
  341. #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_COEFF_BUFFER_SIZE_MIN1_SHIFT (4U)
  342. #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_COEFF_BUFFER_SIZE_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF0000F))
  343. #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_COEFF_BUFFER_BANKS_MIN1_SHIFT (0U)
  344. #define VHA_CR_CNN_IP_CONFIG2_VHA_CNN_COEFF_BUFFER_BANKS_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF0))
  345. /*
  346. Register VHA_CR_CNN_IP_CONFIG3
  347. */
  348. #define VHA_CR_CNN_IP_CONFIG3 (0x0080U)
  349. #define VHA_CR_CNN_IP_CONFIG3_MASKFULL (IMG_UINT64_C(0x000001FFFFFFFFFF))
  350. #define VHA_CR_CNN_IP_CONFIG3_VHA_CNN_MMM_PARALLELISM_L1_MIN1_SHIFT (38U)
  351. #define VHA_CR_CNN_IP_CONFIG3_VHA_CNN_MMM_PARALLELISM_L1_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFE3FFFFFFFFF))
  352. #define VHA_CR_CNN_IP_CONFIG3_VHA_CNN_MMM_PARALLELISM_L0_MIN1_SHIFT (34U)
  353. #define VHA_CR_CNN_IP_CONFIG3_VHA_CNN_MMM_PARALLELISM_L0_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFC3FFFFFFFF))
  354. #define VHA_CR_CNN_IP_CONFIG3_VHA_CNN_MMM_BUFFER_SIZE_MIN1_SHIFT (29U)
  355. #define VHA_CR_CNN_IP_CONFIG3_VHA_CNN_MMM_BUFFER_SIZE_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFC1FFFFFFF))
  356. #define VHA_CR_CNN_IP_CONFIG3_VHA_CNN_MMM_BUFFER_BANKS_MIN1_SHIFT (24U)
  357. #define VHA_CR_CNN_IP_CONFIG3_VHA_CNN_MMM_BUFFER_BANKS_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFE0FFFFFF))
  358. #define VHA_CR_CNN_IP_CONFIG3_VHA_CNN_ACT_LUT_SIZE_MIN1_SHIFT (16U)
  359. #define VHA_CR_CNN_IP_CONFIG3_VHA_CNN_ACT_LUT_SIZE_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF00FFFF))
  360. #define VHA_CR_CNN_IP_CONFIG3_VHA_CNN_INPUT_BUFFER_SIZE_MIN1_SHIFT (8U)
  361. #define VHA_CR_CNN_IP_CONFIG3_VHA_CNN_INPUT_BUFFER_SIZE_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF00FF))
  362. #define VHA_CR_CNN_IP_CONFIG3_VHA_CNN_INPUT_BUFFER_BANKS_MIN1_SHIFT (0U)
  363. #define VHA_CR_CNN_IP_CONFIG3_VHA_CNN_INPUT_BUFFER_BANKS_MIN1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFF00))
  364. /*
  365. Clock is gated and the module is inactive */
  366. #define VHA_CR_SYS_CLK_STATUS0_MODE_GATED (0x00000000U)
  367. /*
  368. Clock is running */
  369. #define VHA_CR_SYS_CLK_STATUS0_MODE_RUNNING (0x00000001U)
  370. /*
  371. Register VHA_CR_SYS_CLK_STATUS0
  372. */
  373. #define VHA_CR_SYS_CLK_STATUS0 (0x0088U)
  374. #define VHA_CR_SYS_CLK_STATUS0_MASKFULL (IMG_UINT64_C(0x0000000000000004))
  375. #define VHA_CR_SYS_CLK_STATUS0_SLC_SHIFT (2U)
  376. #define VHA_CR_SYS_CLK_STATUS0_SLC_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFB))
  377. #define VHA_CR_SYS_CLK_STATUS0_SLC_GATED (IMG_UINT64_C(0000000000000000))
  378. #define VHA_CR_SYS_CLK_STATUS0_SLC_RUNNING (IMG_UINT64_C(0x0000000000000004))
  379. /*
  380. Register VHA_CR_PERF_SLC0_READ
  381. */
  382. #define VHA_CR_PERF_SLC0_READ (0x0200U)
  383. #define VHA_CR_PERF_SLC0_READ_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  384. #define VHA_CR_PERF_SLC0_READ_COUNT_SHIFT (0U)
  385. #define VHA_CR_PERF_SLC0_READ_COUNT_CLRMSK (00000000U)
  386. /*
  387. Register VHA_CR_PERF_SLC0_WRITE
  388. */
  389. #define VHA_CR_PERF_SLC0_WRITE (0x0208U)
  390. #define VHA_CR_PERF_SLC0_WRITE_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  391. #define VHA_CR_PERF_SLC0_WRITE_COUNT_SHIFT (0U)
  392. #define VHA_CR_PERF_SLC0_WRITE_COUNT_CLRMSK (00000000U)
  393. /*
  394. Register VHA_CR_PERF_SLC0_WRITE_DATA_STALL
  395. */
  396. #define VHA_CR_PERF_SLC0_WRITE_DATA_STALL (0x0210U)
  397. #define VHA_CR_PERF_SLC0_WRITE_DATA_STALL_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  398. #define VHA_CR_PERF_SLC0_WRITE_DATA_STALL_COUNT_SHIFT (0U)
  399. #define VHA_CR_PERF_SLC0_WRITE_DATA_STALL_COUNT_CLRMSK (00000000U)
  400. /*
  401. Register VHA_CR_PERF_SLC0_READ_STALL
  402. */
  403. #define VHA_CR_PERF_SLC0_READ_STALL (0x0218U)
  404. #define VHA_CR_PERF_SLC0_READ_STALL_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  405. #define VHA_CR_PERF_SLC0_READ_STALL_COUNT_SHIFT (0U)
  406. #define VHA_CR_PERF_SLC0_READ_STALL_COUNT_CLRMSK (00000000U)
  407. /*
  408. Register VHA_CR_PERF_SLC0_WRITE_STALL
  409. */
  410. #define VHA_CR_PERF_SLC0_WRITE_STALL (0x0220U)
  411. #define VHA_CR_PERF_SLC0_WRITE_STALL_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  412. #define VHA_CR_PERF_SLC0_WRITE_STALL_COUNT_SHIFT (0U)
  413. #define VHA_CR_PERF_SLC0_WRITE_STALL_COUNT_CLRMSK (00000000U)
  414. /*
  415. Register VHA_CR_PERF_SLC0_READ_ID_STALL
  416. */
  417. #define VHA_CR_PERF_SLC0_READ_ID_STALL (0x0228U)
  418. #define VHA_CR_PERF_SLC0_READ_ID_STALL_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  419. #define VHA_CR_PERF_SLC0_READ_ID_STALL_COUNT_SHIFT (0U)
  420. #define VHA_CR_PERF_SLC0_READ_ID_STALL_COUNT_CLRMSK (00000000U)
  421. /*
  422. Register VHA_CR_PERF_SLC0_WRITE_ID_STALL
  423. */
  424. #define VHA_CR_PERF_SLC0_WRITE_ID_STALL (0x0230U)
  425. #define VHA_CR_PERF_SLC0_WRITE_ID_STALL_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  426. #define VHA_CR_PERF_SLC0_WRITE_ID_STALL_COUNT_SHIFT (0U)
  427. #define VHA_CR_PERF_SLC0_WRITE_ID_STALL_COUNT_CLRMSK (00000000U)
  428. /*
  429. Register VHA_CR_PERF_SLC0_RD_BURST_SIZE1
  430. */
  431. #define VHA_CR_PERF_SLC0_RD_BURST_SIZE1 (0x0238U)
  432. #define VHA_CR_PERF_SLC0_RD_BURST_SIZE1_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  433. #define VHA_CR_PERF_SLC0_RD_BURST_SIZE1_COUNT_SHIFT (0U)
  434. #define VHA_CR_PERF_SLC0_RD_BURST_SIZE1_COUNT_CLRMSK (00000000U)
  435. /*
  436. Register VHA_CR_PERF_SLC0_WR_BURST_SIZE1
  437. */
  438. #define VHA_CR_PERF_SLC0_WR_BURST_SIZE1 (0x0240U)
  439. #define VHA_CR_PERF_SLC0_WR_BURST_SIZE1_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  440. #define VHA_CR_PERF_SLC0_WR_BURST_SIZE1_COUNT_SHIFT (0U)
  441. #define VHA_CR_PERF_SLC0_WR_BURST_SIZE1_COUNT_CLRMSK (00000000U)
  442. /*
  443. Register VHA_CR_PERF_SLC0_RD_BURST_SIZE2
  444. */
  445. #define VHA_CR_PERF_SLC0_RD_BURST_SIZE2 (0x0248U)
  446. #define VHA_CR_PERF_SLC0_RD_BURST_SIZE2_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  447. #define VHA_CR_PERF_SLC0_RD_BURST_SIZE2_COUNT_SHIFT (0U)
  448. #define VHA_CR_PERF_SLC0_RD_BURST_SIZE2_COUNT_CLRMSK (00000000U)
  449. /*
  450. Register VHA_CR_PERF_SLC0_WR_BURST_SIZE2
  451. */
  452. #define VHA_CR_PERF_SLC0_WR_BURST_SIZE2 (0x0250U)
  453. #define VHA_CR_PERF_SLC0_WR_BURST_SIZE2_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  454. #define VHA_CR_PERF_SLC0_WR_BURST_SIZE2_COUNT_SHIFT (0U)
  455. #define VHA_CR_PERF_SLC0_WR_BURST_SIZE2_COUNT_CLRMSK (00000000U)
  456. /*
  457. Register VHA_CR_PERF_SLC0_RD_BURST_SIZE3
  458. */
  459. #define VHA_CR_PERF_SLC0_RD_BURST_SIZE3 (0x0258U)
  460. #define VHA_CR_PERF_SLC0_RD_BURST_SIZE3_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  461. #define VHA_CR_PERF_SLC0_RD_BURST_SIZE3_COUNT_SHIFT (0U)
  462. #define VHA_CR_PERF_SLC0_RD_BURST_SIZE3_COUNT_CLRMSK (00000000U)
  463. /*
  464. Register VHA_CR_PERF_SLC0_WR_BURST_SIZE3
  465. */
  466. #define VHA_CR_PERF_SLC0_WR_BURST_SIZE3 (0x0260U)
  467. #define VHA_CR_PERF_SLC0_WR_BURST_SIZE3_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  468. #define VHA_CR_PERF_SLC0_WR_BURST_SIZE3_COUNT_SHIFT (0U)
  469. #define VHA_CR_PERF_SLC0_WR_BURST_SIZE3_COUNT_CLRMSK (00000000U)
  470. /*
  471. Register VHA_CR_PERF_SLC0_RD_BURST_SIZE4
  472. */
  473. #define VHA_CR_PERF_SLC0_RD_BURST_SIZE4 (0x0268U)
  474. #define VHA_CR_PERF_SLC0_RD_BURST_SIZE4_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  475. #define VHA_CR_PERF_SLC0_RD_BURST_SIZE4_COUNT_SHIFT (0U)
  476. #define VHA_CR_PERF_SLC0_RD_BURST_SIZE4_COUNT_CLRMSK (00000000U)
  477. /*
  478. Register VHA_CR_PERF_SLC0_WR_BURST_SIZE4
  479. */
  480. #define VHA_CR_PERF_SLC0_WR_BURST_SIZE4 (0x0270U)
  481. #define VHA_CR_PERF_SLC0_WR_BURST_SIZE4_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  482. #define VHA_CR_PERF_SLC0_WR_BURST_SIZE4_COUNT_SHIFT (0U)
  483. #define VHA_CR_PERF_SLC0_WR_BURST_SIZE4_COUNT_CLRMSK (00000000U)
  484. /*
  485. Register VHA_CR_PERF_RESET_FULL
  486. */
  487. #define VHA_CR_PERF_RESET_FULL (0x0278U)
  488. #define VHA_CR_PERF_RESET_FULL_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  489. #define VHA_CR_PERF_RESET_FULL_RANGE_SHIFT (0U)
  490. #define VHA_CR_PERF_RESET_FULL_RANGE_CLRMSK (0XFFFFFFFEU)
  491. #define VHA_CR_PERF_RESET_FULL_RANGE_EN (0X00000001U)
  492. /*
  493. Register VHA_CR_PERF_ENABLE_FULL
  494. */
  495. #define VHA_CR_PERF_ENABLE_FULL (0x0280U)
  496. #define VHA_CR_PERF_ENABLE_FULL_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  497. #define VHA_CR_PERF_ENABLE_FULL_RANGE_SHIFT (0U)
  498. #define VHA_CR_PERF_ENABLE_FULL_RANGE_CLRMSK (0XFFFFFFFEU)
  499. #define VHA_CR_PERF_ENABLE_FULL_RANGE_EN (0X00000001U)
  500. /*
  501. Register VHA_CR_MMU_STATUS
  502. */
  503. #define VHA_CR_MMU_STATUS (0x0288U)
  504. #define VHA_CR_MMU_STATUS_MASKFULL (IMG_UINT64_C(0x000001FFFFFFFFFF))
  505. #define VHA_CR_MMU_STATUS_MMU_STALLED_SHIFT (40U)
  506. #define VHA_CR_MMU_STATUS_MMU_STALLED_CLRMSK (IMG_UINT64_C(0XFFFFFEFFFFFFFFFF))
  507. #define VHA_CR_MMU_STATUS_MMU_STALLED_EN (IMG_UINT64_C(0X0000010000000000))
  508. #define VHA_CR_MMU_STATUS_PM_WRITES_SHIFT (38U)
  509. #define VHA_CR_MMU_STATUS_PM_WRITES_CLRMSK (IMG_UINT64_C(0XFFFFFF3FFFFFFFFF))
  510. #define VHA_CR_MMU_STATUS_PM_READS_SHIFT (36U)
  511. #define VHA_CR_MMU_STATUS_PM_READS_CLRMSK (IMG_UINT64_C(0XFFFFFFCFFFFFFFFF))
  512. #define VHA_CR_MMU_STATUS_PC_READS_SHIFT (24U)
  513. #define VHA_CR_MMU_STATUS_PC_READS_CLRMSK (IMG_UINT64_C(0XFFFFFFF000FFFFFF))
  514. #define VHA_CR_MMU_STATUS_PD_READS_SHIFT (12U)
  515. #define VHA_CR_MMU_STATUS_PD_READS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF000FFF))
  516. #define VHA_CR_MMU_STATUS_PT_READS_SHIFT (0U)
  517. #define VHA_CR_MMU_STATUS_PT_READS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF000))
  518. /*
  519. Register VHA_CR_SLC_STATUS1
  520. */
  521. #define VHA_CR_SLC_STATUS1 (0x0290U)
  522. #define VHA_CR_SLC_STATUS1_MASKFULL (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
  523. #define VHA_CR_SLC_STATUS1_XBAR_CFI_TIMEOUTS_SHIFT (48U)
  524. #define VHA_CR_SLC_STATUS1_XBAR_CFI_TIMEOUTS_CLRMSK (IMG_UINT64_C(0X0000FFFFFFFFFFFF))
  525. #define VHA_CR_SLC_STATUS1_BUS1_OUTSTANDING_WRITES_SHIFT (36U)
  526. #define VHA_CR_SLC_STATUS1_BUS1_OUTSTANDING_WRITES_CLRMSK (IMG_UINT64_C(0XFFFF000FFFFFFFFF))
  527. #define VHA_CR_SLC_STATUS1_BUS0_OUTSTANDING_WRITES_SHIFT (24U)
  528. #define VHA_CR_SLC_STATUS1_BUS0_OUTSTANDING_WRITES_CLRMSK (IMG_UINT64_C(0XFFFFFFF000FFFFFF))
  529. #define VHA_CR_SLC_STATUS1_BUS1_OUTSTANDING_READS_SHIFT (12U)
  530. #define VHA_CR_SLC_STATUS1_BUS1_OUTSTANDING_READS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF000FFF))
  531. #define VHA_CR_SLC_STATUS1_BUS0_OUTSTANDING_READS_SHIFT (0U)
  532. #define VHA_CR_SLC_STATUS1_BUS0_OUTSTANDING_READS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF000))
  533. /*
  534. Register VHA_CR_SLC_STATUS2
  535. */
  536. #define VHA_CR_SLC_STATUS2 (0x0298U)
  537. #define VHA_CR_SLC_STATUS2_MASKFULL (IMG_UINT64_C(0x0000FFFFFFFFFFFF))
  538. #define VHA_CR_SLC_STATUS2_BUS3_OUTSTANDING_WRITES_SHIFT (36U)
  539. #define VHA_CR_SLC_STATUS2_BUS3_OUTSTANDING_WRITES_CLRMSK (IMG_UINT64_C(0XFFFF000FFFFFFFFF))
  540. #define VHA_CR_SLC_STATUS2_BUS2_OUTSTANDING_WRITES_SHIFT (24U)
  541. #define VHA_CR_SLC_STATUS2_BUS2_OUTSTANDING_WRITES_CLRMSK (IMG_UINT64_C(0XFFFFFFF000FFFFFF))
  542. #define VHA_CR_SLC_STATUS2_BUS3_OUTSTANDING_READS_SHIFT (12U)
  543. #define VHA_CR_SLC_STATUS2_BUS3_OUTSTANDING_READS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF000FFF))
  544. #define VHA_CR_SLC_STATUS2_BUS2_OUTSTANDING_READS_SHIFT (0U)
  545. #define VHA_CR_SLC_STATUS2_BUS2_OUTSTANDING_READS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF000))
  546. /*
  547. Register VHA_CR_SLC_IDLE
  548. */
  549. #define VHA_CR_SLC_IDLE (0x02A0U)
  550. #define VHA_CR_SLC_IDLE_MASKFULL (IMG_UINT64_C(0x000000000000FFFF))
  551. #define VHA_CR_SLC_IDLE_ACE_CONVERTERS_SHIFT (12U)
  552. #define VHA_CR_SLC_IDLE_ACE_CONVERTERS_CLRMSK (0XFFFF0FFFU)
  553. #define VHA_CR_SLC_IDLE_CACHE_BANKS_SHIFT (4U)
  554. #define VHA_CR_SLC_IDLE_CACHE_BANKS_CLRMSK (0XFFFFF00FU)
  555. #define VHA_CR_SLC_IDLE_MMU_SHIFT (3U)
  556. #define VHA_CR_SLC_IDLE_MMU_CLRMSK (0XFFFFFFF7U)
  557. #define VHA_CR_SLC_IDLE_MMU_EN (0X00000008U)
  558. #define VHA_CR_SLC_IDLE_CCM_SHIFT (2U)
  559. #define VHA_CR_SLC_IDLE_CCM_CLRMSK (0XFFFFFFFBU)
  560. #define VHA_CR_SLC_IDLE_CCM_EN (0X00000004U)
  561. #define VHA_CR_SLC_IDLE_RDI_SHIFT (1U)
  562. #define VHA_CR_SLC_IDLE_RDI_CLRMSK (0XFFFFFFFDU)
  563. #define VHA_CR_SLC_IDLE_RDI_EN (0X00000002U)
  564. #define VHA_CR_SLC_IDLE_XBAR_SHIFT (0U)
  565. #define VHA_CR_SLC_IDLE_XBAR_CLRMSK (0XFFFFFFFEU)
  566. #define VHA_CR_SLC_IDLE_XBAR_EN (0X00000001U)
  567. /*
  568. Register VHA_CR_SLC_STATUS3
  569. */
  570. #define VHA_CR_SLC_STATUS3 (0x02A8U)
  571. #define VHA_CR_SLC_STATUS3_MASKFULL (IMG_UINT64_C(0x0FFFFFFFFFFFFFFF))
  572. #define VHA_CR_SLC_STATUS3_MAX_CRITICAL_QOS_READ_LATENCY_SHIFT (50U)
  573. #define VHA_CR_SLC_STATUS3_MAX_CRITICAL_QOS_READ_LATENCY_CLRMSK (IMG_UINT64_C(0XF003FFFFFFFFFFFF))
  574. #define VHA_CR_SLC_STATUS3_MAX_LOW_QOS_READ_LATENCY_SHIFT (40U)
  575. #define VHA_CR_SLC_STATUS3_MAX_LOW_QOS_READ_LATENCY_CLRMSK (IMG_UINT64_C(0XFFFC00FFFFFFFFFF))
  576. #define VHA_CR_SLC_STATUS3_AVG_CRITICAL_QOS_READ_LATENCY_SHIFT (30U)
  577. #define VHA_CR_SLC_STATUS3_AVG_CRITICAL_QOS_READ_LATENCY_CLRMSK (IMG_UINT64_C(0XFFFFFF003FFFFFFF))
  578. #define VHA_CR_SLC_STATUS3_AVG_LOW_QOS_READ_LATENCY_SHIFT (20U)
  579. #define VHA_CR_SLC_STATUS3_AVG_LOW_QOS_READ_LATENCY_CLRMSK (IMG_UINT64_C(0XFFFFFFFFC00FFFFF))
  580. #define VHA_CR_SLC_STATUS3_MIN_CRITICAL_QOS_READ_LATENCY_SHIFT (10U)
  581. #define VHA_CR_SLC_STATUS3_MIN_CRITICAL_QOS_READ_LATENCY_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF003FF))
  582. #define VHA_CR_SLC_STATUS3_MIN_LOW_QOS_READ_LATENCY_SHIFT (0U)
  583. #define VHA_CR_SLC_STATUS3_MIN_LOW_QOS_READ_LATENCY_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFC00))
  584. /*
  585. Register VHA_CR_SLC_FAULT_STOP_STATUS
  586. */
  587. #define VHA_CR_SLC_FAULT_STOP_STATUS (0x02B0U)
  588. #define VHA_CR_SLC_FAULT_STOP_STATUS_MASKFULL (IMG_UINT64_C(0x000000000001FFFF))
  589. #define VHA_CR_SLC_FAULT_STOP_STATUS_BIF_SHIFT (0U)
  590. #define VHA_CR_SLC_FAULT_STOP_STATUS_BIF_CLRMSK (0XFFFE0000U)
  591. /*
  592. Register VHA_CR_SLC_STATUS_DEBUG
  593. */
  594. #define VHA_CR_SLC_STATUS_DEBUG (0x02B8U)
  595. #define VHA_CR_SLC_STATUS_DEBUG_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  596. #define VHA_CR_SLC_STATUS_DEBUG_ERR_COH_REQ_SHIFT (16U)
  597. #define VHA_CR_SLC_STATUS_DEBUG_ERR_COH_REQ_CLRMSK (0X0000FFFFU)
  598. #define VHA_CR_SLC_STATUS_DEBUG_ERR_ADDR_ALIAS_SHIFT (0U)
  599. #define VHA_CR_SLC_STATUS_DEBUG_ERR_ADDR_ALIAS_CLRMSK (0XFFFF0000U)
  600. /*
  601. Register VHA_CR_BIF_OUTSTANDING_READ
  602. */
  603. #define VHA_CR_BIF_OUTSTANDING_READ (0x02C0U)
  604. #define VHA_CR_BIF_OUTSTANDING_READ_MASKFULL (IMG_UINT64_C(0x000000000000FFFF))
  605. #define VHA_CR_BIF_OUTSTANDING_READ_COUNTER_SHIFT (0U)
  606. #define VHA_CR_BIF_OUTSTANDING_READ_COUNTER_CLRMSK (0XFFFF0000U)
  607. /*
  608. Register VHA_CR_BIF_PAGE_FAULT_STALL
  609. */
  610. #define VHA_CR_BIF_PAGE_FAULT_STALL (0x02C8U)
  611. #define VHA_CR_BIF_PAGE_FAULT_STALL_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  612. #define VHA_CR_BIF_PAGE_FAULT_STALL_STATUS_SHIFT (0U)
  613. #define VHA_CR_BIF_PAGE_FAULT_STALL_STATUS_CLRMSK (0XFFFFFFFEU)
  614. #define VHA_CR_BIF_PAGE_FAULT_STALL_STATUS_EN (0X00000001U)
  615. /*
  616. Register VHA_CR_PERF_SLC
  617. */
  618. #define VHA_CR_PERF_SLC (0x02D0U)
  619. #define VHA_CR_PERF_SLC_MASKFULL (IMG_UINT64_C(0x000000000FEFFEFF))
  620. #define VHA_CR_PERF_SLC_EWO_REQ_RD_WORD_COUNTER_RESET_SHIFT (27U)
  621. #define VHA_CR_PERF_SLC_EWO_REQ_RD_WORD_COUNTER_RESET_CLRMSK (0XF7FFFFFFU)
  622. #define VHA_CR_PERF_SLC_EWO_REQ_RD_WORD_COUNTER_RESET_EN (0X08000000U)
  623. #define VHA_CR_PERF_SLC_EWO_REQ_RD_COUNTER_RESET_SHIFT (26U)
  624. #define VHA_CR_PERF_SLC_EWO_REQ_RD_COUNTER_RESET_CLRMSK (0XFBFFFFFFU)
  625. #define VHA_CR_PERF_SLC_EWO_REQ_RD_COUNTER_RESET_EN (0X04000000U)
  626. #define VHA_CR_PERF_SLC_MMU_REQ_RD_WORD_COUNTER_RESET_SHIFT (25U)
  627. #define VHA_CR_PERF_SLC_MMU_REQ_RD_WORD_COUNTER_RESET_CLRMSK (0XFDFFFFFFU)
  628. #define VHA_CR_PERF_SLC_MMU_REQ_RD_WORD_COUNTER_RESET_EN (0X02000000U)
  629. #define VHA_CR_PERF_SLC_MMU_REQ_RD_COUNTER_RESET_SHIFT (24U)
  630. #define VHA_CR_PERF_SLC_MMU_REQ_RD_COUNTER_RESET_CLRMSK (0XFEFFFFFFU)
  631. #define VHA_CR_PERF_SLC_MMU_REQ_RD_COUNTER_RESET_EN (0X01000000U)
  632. #define VHA_CR_PERF_SLC_OPK_REQ_WR_WORD_COUNTER_RESET_SHIFT (23U)
  633. #define VHA_CR_PERF_SLC_OPK_REQ_WR_WORD_COUNTER_RESET_CLRMSK (0XFF7FFFFFU)
  634. #define VHA_CR_PERF_SLC_OPK_REQ_WR_WORD_COUNTER_RESET_EN (0X00800000U)
  635. #define VHA_CR_PERF_SLC_ABUF_REQ_RD_WORD_COUNTER_RESET_SHIFT (22U)
  636. #define VHA_CR_PERF_SLC_ABUF_REQ_RD_WORD_COUNTER_RESET_CLRMSK (0XFFBFFFFFU)
  637. #define VHA_CR_PERF_SLC_ABUF_REQ_RD_WORD_COUNTER_RESET_EN (0X00400000U)
  638. #define VHA_CR_PERF_SLC_CBUF_REQ_RD_WORD_COUNTER_RESET_SHIFT (21U)
  639. #define VHA_CR_PERF_SLC_CBUF_REQ_RD_WORD_COUNTER_RESET_CLRMSK (0XFFDFFFFFU)
  640. #define VHA_CR_PERF_SLC_CBUF_REQ_RD_WORD_COUNTER_RESET_EN (0X00200000U)
  641. #define VHA_CR_PERF_SLC_MMM_REQ_WR_WORD_COUNTER_RESET_SHIFT (19U)
  642. #define VHA_CR_PERF_SLC_MMM_REQ_WR_WORD_COUNTER_RESET_CLRMSK (0XFFF7FFFFU)
  643. #define VHA_CR_PERF_SLC_MMM_REQ_WR_WORD_COUNTER_RESET_EN (0X00080000U)
  644. #define VHA_CR_PERF_SLC_MMM_REQ_RD_WORD_COUNTER_RESET_SHIFT (18U)
  645. #define VHA_CR_PERF_SLC_MMM_REQ_RD_WORD_COUNTER_RESET_CLRMSK (0XFFFBFFFFU)
  646. #define VHA_CR_PERF_SLC_MMM_REQ_RD_WORD_COUNTER_RESET_EN (0X00040000U)
  647. #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_WORD_COUNTER_RESET_SHIFT (17U)
  648. #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_WORD_COUNTER_RESET_CLRMSK (0XFFFDFFFFU)
  649. #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_WORD_COUNTER_RESET_EN (0X00020000U)
  650. #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_WORD_COUNTER_RESET_SHIFT (16U)
  651. #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_WORD_COUNTER_RESET_CLRMSK (0XFFFEFFFFU)
  652. #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_WORD_COUNTER_RESET_EN (0X00010000U)
  653. #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_WORD_COUNTER_RESET_SHIFT (15U)
  654. #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_WORD_COUNTER_RESET_CLRMSK (0XFFFF7FFFU)
  655. #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_WORD_COUNTER_RESET_EN (0X00008000U)
  656. #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_WORD_COUNTER_RESET_SHIFT (14U)
  657. #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_WORD_COUNTER_RESET_CLRMSK (0XFFFFBFFFU)
  658. #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_WORD_COUNTER_RESET_EN (0X00004000U)
  659. #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_WORD_COUNTER_RESET_SHIFT (13U)
  660. #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_WORD_COUNTER_RESET_CLRMSK (0XFFFFDFFFU)
  661. #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_WORD_COUNTER_RESET_EN (0X00002000U)
  662. #define VHA_CR_PERF_SLC_CMD_REQ_RD_WORD_COUNTER_RESET_SHIFT (12U)
  663. #define VHA_CR_PERF_SLC_CMD_REQ_RD_WORD_COUNTER_RESET_CLRMSK (0XFFFFEFFFU)
  664. #define VHA_CR_PERF_SLC_CMD_REQ_RD_WORD_COUNTER_RESET_EN (0X00001000U)
  665. #define VHA_CR_PERF_SLC_OPK_REQ_WR_COUNTER_RESET_SHIFT (11U)
  666. #define VHA_CR_PERF_SLC_OPK_REQ_WR_COUNTER_RESET_CLRMSK (0XFFFFF7FFU)
  667. #define VHA_CR_PERF_SLC_OPK_REQ_WR_COUNTER_RESET_EN (0X00000800U)
  668. #define VHA_CR_PERF_SLC_ABUF_REQ_RD_COUNTER_RESET_SHIFT (10U)
  669. #define VHA_CR_PERF_SLC_ABUF_REQ_RD_COUNTER_RESET_CLRMSK (0XFFFFFBFFU)
  670. #define VHA_CR_PERF_SLC_ABUF_REQ_RD_COUNTER_RESET_EN (0X00000400U)
  671. #define VHA_CR_PERF_SLC_CBUF_REQ_RD_COUNTER_RESET_SHIFT (9U)
  672. #define VHA_CR_PERF_SLC_CBUF_REQ_RD_COUNTER_RESET_CLRMSK (0XFFFFFDFFU)
  673. #define VHA_CR_PERF_SLC_CBUF_REQ_RD_COUNTER_RESET_EN (0X00000200U)
  674. #define VHA_CR_PERF_SLC_MMM_REQ_WR_COUNTER_RESET_SHIFT (7U)
  675. #define VHA_CR_PERF_SLC_MMM_REQ_WR_COUNTER_RESET_CLRMSK (0XFFFFFF7FU)
  676. #define VHA_CR_PERF_SLC_MMM_REQ_WR_COUNTER_RESET_EN (0X00000080U)
  677. #define VHA_CR_PERF_SLC_MMM_REQ_RD_COUNTER_RESET_SHIFT (6U)
  678. #define VHA_CR_PERF_SLC_MMM_REQ_RD_COUNTER_RESET_CLRMSK (0XFFFFFFBFU)
  679. #define VHA_CR_PERF_SLC_MMM_REQ_RD_COUNTER_RESET_EN (0X00000040U)
  680. #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_COUNTER_RESET_SHIFT (5U)
  681. #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_COUNTER_RESET_CLRMSK (0XFFFFFFDFU)
  682. #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_COUNTER_RESET_EN (0X00000020U)
  683. #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_COUNTER_RESET_SHIFT (4U)
  684. #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_COUNTER_RESET_CLRMSK (0XFFFFFFEFU)
  685. #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_COUNTER_RESET_EN (0X00000010U)
  686. #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_COUNTER_RESET_SHIFT (3U)
  687. #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_COUNTER_RESET_CLRMSK (0XFFFFFFF7U)
  688. #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_COUNTER_RESET_EN (0X00000008U)
  689. #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_COUNTER_RESET_SHIFT (2U)
  690. #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_COUNTER_RESET_CLRMSK (0XFFFFFFFBU)
  691. #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_COUNTER_RESET_EN (0X00000004U)
  692. #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_COUNTER_RESET_SHIFT (1U)
  693. #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_COUNTER_RESET_CLRMSK (0XFFFFFFFDU)
  694. #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_COUNTER_RESET_EN (0X00000002U)
  695. #define VHA_CR_PERF_SLC_CMD_REQ_RD_COUNTER_RESET_SHIFT (0U)
  696. #define VHA_CR_PERF_SLC_CMD_REQ_RD_COUNTER_RESET_CLRMSK (0XFFFFFFFEU)
  697. #define VHA_CR_PERF_SLC_CMD_REQ_RD_COUNTER_RESET_EN (0X00000001U)
  698. /*
  699. Register VHA_CR_PERF_SLC_REQ_COUNT
  700. */
  701. #define VHA_CR_PERF_SLC_REQ_COUNT (0x02D8U)
  702. #define VHA_CR_PERF_SLC_REQ_COUNT_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  703. #define VHA_CR_PERF_SLC_REQ_COUNT_ENABLE_SHIFT (0U)
  704. #define VHA_CR_PERF_SLC_REQ_COUNT_ENABLE_CLRMSK (0XFFFFFFFEU)
  705. #define VHA_CR_PERF_SLC_REQ_COUNT_ENABLE_EN (0X00000001U)
  706. /*
  707. Register VHA_CR_PERF_SLC_CMD_REQ_RD
  708. */
  709. #define VHA_CR_PERF_SLC_CMD_REQ_RD (0x02E0U)
  710. #define VHA_CR_PERF_SLC_CMD_REQ_RD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  711. #define VHA_CR_PERF_SLC_CMD_REQ_RD_COUNTER_SHIFT (0U)
  712. #define VHA_CR_PERF_SLC_CMD_REQ_RD_COUNTER_CLRMSK (00000000U)
  713. /*
  714. Register VHA_CR_PERF_SLC_CMD_BCK_REQ_WR
  715. */
  716. #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR (0x02E8U)
  717. #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  718. #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_COUNTER_SHIFT (0U)
  719. #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_COUNTER_CLRMSK (00000000U)
  720. /*
  721. Register VHA_CR_PERF_SLC_CMD_CRC_REQ_WR
  722. */
  723. #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR (0x02F0U)
  724. #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  725. #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_COUNTER_SHIFT (0U)
  726. #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_COUNTER_CLRMSK (00000000U)
  727. /*
  728. Register VHA_CR_PERF_SLC_CMD_DBG_REQ_WR
  729. */
  730. #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR (0x02F8U)
  731. #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  732. #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_COUNTER_SHIFT (0U)
  733. #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_COUNTER_CLRMSK (00000000U)
  734. /*
  735. Register VHA_CR_PERF_SLC_CMD_REQ_FENCE
  736. */
  737. #define VHA_CR_PERF_SLC_CMD_REQ_FENCE (0x0300U)
  738. #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  739. #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_COUNTER_SHIFT (0U)
  740. #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_COUNTER_CLRMSK (00000000U)
  741. /*
  742. Register VHA_CR_PERF_SLC_IBUF_REQ0_RD
  743. */
  744. #define VHA_CR_PERF_SLC_IBUF_REQ0_RD (0x0308U)
  745. #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  746. #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_COUNTER_SHIFT (0U)
  747. #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_COUNTER_CLRMSK (00000000U)
  748. /*
  749. Register VHA_CR_PERF_SLC_MMM_REQ_RD
  750. */
  751. #define VHA_CR_PERF_SLC_MMM_REQ_RD (0x0310U)
  752. #define VHA_CR_PERF_SLC_MMM_REQ_RD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  753. #define VHA_CR_PERF_SLC_MMM_REQ_RD_COUNTER_SHIFT (0U)
  754. #define VHA_CR_PERF_SLC_MMM_REQ_RD_COUNTER_CLRMSK (00000000U)
  755. /*
  756. Register VHA_CR_PERF_SLC_MMM_REQ_WR
  757. */
  758. #define VHA_CR_PERF_SLC_MMM_REQ_WR (0x0318U)
  759. #define VHA_CR_PERF_SLC_MMM_REQ_WR_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  760. #define VHA_CR_PERF_SLC_MMM_REQ_WR_COUNTER_SHIFT (0U)
  761. #define VHA_CR_PERF_SLC_MMM_REQ_WR_COUNTER_CLRMSK (00000000U)
  762. /*
  763. Register VHA_CR_PERF_SLC_CBUF_REQ_RD
  764. */
  765. #define VHA_CR_PERF_SLC_CBUF_REQ_RD (0x0328U)
  766. #define VHA_CR_PERF_SLC_CBUF_REQ_RD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  767. #define VHA_CR_PERF_SLC_CBUF_REQ_RD_COUNTER_SHIFT (0U)
  768. #define VHA_CR_PERF_SLC_CBUF_REQ_RD_COUNTER_CLRMSK (00000000U)
  769. /*
  770. Register VHA_CR_PERF_SLC_ABUF_REQ_RD
  771. */
  772. #define VHA_CR_PERF_SLC_ABUF_REQ_RD (0x0330U)
  773. #define VHA_CR_PERF_SLC_ABUF_REQ_RD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  774. #define VHA_CR_PERF_SLC_ABUF_REQ_RD_COUNTER_SHIFT (0U)
  775. #define VHA_CR_PERF_SLC_ABUF_REQ_RD_COUNTER_CLRMSK (00000000U)
  776. /*
  777. Register VHA_CR_PERF_SLC_OPK_REQ_WR
  778. */
  779. #define VHA_CR_PERF_SLC_OPK_REQ_WR (0x0338U)
  780. #define VHA_CR_PERF_SLC_OPK_REQ_WR_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  781. #define VHA_CR_PERF_SLC_OPK_REQ_WR_COUNTER_SHIFT (0U)
  782. #define VHA_CR_PERF_SLC_OPK_REQ_WR_COUNTER_CLRMSK (00000000U)
  783. /*
  784. Register VHA_CR_PERF_SLC_CMD_REQ_RD_WORD
  785. */
  786. #define VHA_CR_PERF_SLC_CMD_REQ_RD_WORD (0x0340U)
  787. #define VHA_CR_PERF_SLC_CMD_REQ_RD_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  788. #define VHA_CR_PERF_SLC_CMD_REQ_RD_WORD_COUNTER_SHIFT (0U)
  789. #define VHA_CR_PERF_SLC_CMD_REQ_RD_WORD_COUNTER_CLRMSK (00000000U)
  790. /*
  791. Register VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_WORD
  792. */
  793. #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_WORD (0x0348U)
  794. #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  795. #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_WORD_COUNTER_SHIFT (0U)
  796. #define VHA_CR_PERF_SLC_CMD_BCK_REQ_WR_WORD_COUNTER_CLRMSK (00000000U)
  797. /*
  798. Register VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_WORD
  799. */
  800. #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_WORD (0x0350U)
  801. #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  802. #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_WORD_COUNTER_SHIFT (0U)
  803. #define VHA_CR_PERF_SLC_CMD_CRC_REQ_WR_WORD_COUNTER_CLRMSK (00000000U)
  804. /*
  805. Register VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_WORD
  806. */
  807. #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_WORD (0x0358U)
  808. #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  809. #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_WORD_COUNTER_SHIFT (0U)
  810. #define VHA_CR_PERF_SLC_CMD_DBG_REQ_WR_WORD_COUNTER_CLRMSK (00000000U)
  811. /*
  812. Register VHA_CR_PERF_SLC_CMD_REQ_FENCE_WORD
  813. */
  814. #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_WORD (0x0360U)
  815. #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  816. #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_WORD_COUNTER_SHIFT (0U)
  817. #define VHA_CR_PERF_SLC_CMD_REQ_FENCE_WORD_COUNTER_CLRMSK (00000000U)
  818. /*
  819. Register VHA_CR_PERF_SLC_IBUF_REQ0_RD_WORD
  820. */
  821. #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_WORD (0x0368U)
  822. #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  823. #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_WORD_COUNTER_SHIFT (0U)
  824. #define VHA_CR_PERF_SLC_IBUF_REQ0_RD_WORD_COUNTER_CLRMSK (00000000U)
  825. /*
  826. Register VHA_CR_PERF_SLC_MMM_REQ_RD_WORD
  827. */
  828. #define VHA_CR_PERF_SLC_MMM_REQ_RD_WORD (0x0370U)
  829. #define VHA_CR_PERF_SLC_MMM_REQ_RD_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  830. #define VHA_CR_PERF_SLC_MMM_REQ_RD_WORD_COUNTER_SHIFT (0U)
  831. #define VHA_CR_PERF_SLC_MMM_REQ_RD_WORD_COUNTER_CLRMSK (00000000U)
  832. /*
  833. Register VHA_CR_PERF_SLC_MMM_REQ_WR_WORD
  834. */
  835. #define VHA_CR_PERF_SLC_MMM_REQ_WR_WORD (0x0378U)
  836. #define VHA_CR_PERF_SLC_MMM_REQ_WR_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  837. #define VHA_CR_PERF_SLC_MMM_REQ_WR_WORD_COUNTER_SHIFT (0U)
  838. #define VHA_CR_PERF_SLC_MMM_REQ_WR_WORD_COUNTER_CLRMSK (00000000U)
  839. /*
  840. Register VHA_CR_PERF_SLC_CBUF_REQ_RD_WORD
  841. */
  842. #define VHA_CR_PERF_SLC_CBUF_REQ_RD_WORD (0x0388U)
  843. #define VHA_CR_PERF_SLC_CBUF_REQ_RD_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  844. #define VHA_CR_PERF_SLC_CBUF_REQ_RD_WORD_COUNTER_SHIFT (0U)
  845. #define VHA_CR_PERF_SLC_CBUF_REQ_RD_WORD_COUNTER_CLRMSK (00000000U)
  846. /*
  847. Register VHA_CR_PERF_SLC_ABUF_REQ_RD_WORD
  848. */
  849. #define VHA_CR_PERF_SLC_ABUF_REQ_RD_WORD (0x0390U)
  850. #define VHA_CR_PERF_SLC_ABUF_REQ_RD_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  851. #define VHA_CR_PERF_SLC_ABUF_REQ_RD_WORD_COUNTER_SHIFT (0U)
  852. #define VHA_CR_PERF_SLC_ABUF_REQ_RD_WORD_COUNTER_CLRMSK (00000000U)
  853. /*
  854. Register VHA_CR_PERF_SLC_OPK_REQ_WR_WORD
  855. */
  856. #define VHA_CR_PERF_SLC_OPK_REQ_WR_WORD (0x0398U)
  857. #define VHA_CR_PERF_SLC_OPK_REQ_WR_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  858. #define VHA_CR_PERF_SLC_OPK_REQ_WR_WORD_COUNTER_SHIFT (0U)
  859. #define VHA_CR_PERF_SLC_OPK_REQ_WR_WORD_COUNTER_CLRMSK (00000000U)
  860. /*
  861. Register VHA_CR_PERF_SLC_MMU_REQ_RD
  862. */
  863. #define VHA_CR_PERF_SLC_MMU_REQ_RD (0x03A0U)
  864. #define VHA_CR_PERF_SLC_MMU_REQ_RD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  865. #define VHA_CR_PERF_SLC_MMU_REQ_RD_COUNTER_SHIFT (0U)
  866. #define VHA_CR_PERF_SLC_MMU_REQ_RD_COUNTER_CLRMSK (00000000U)
  867. /*
  868. Register VHA_CR_PERF_SLC_MMU_REQ_RD_WORD
  869. */
  870. #define VHA_CR_PERF_SLC_MMU_REQ_RD_WORD (0x03A8U)
  871. #define VHA_CR_PERF_SLC_MMU_REQ_RD_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  872. #define VHA_CR_PERF_SLC_MMU_REQ_RD_WORD_COUNTER_SHIFT (0U)
  873. #define VHA_CR_PERF_SLC_MMU_REQ_RD_WORD_COUNTER_CLRMSK (00000000U)
  874. /*
  875. Register VHA_CR_PERF_SLC_EWO_REQ_RD
  876. */
  877. #define VHA_CR_PERF_SLC_EWO_REQ_RD (0x03B0U)
  878. #define VHA_CR_PERF_SLC_EWO_REQ_RD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  879. #define VHA_CR_PERF_SLC_EWO_REQ_RD_COUNTER_SHIFT (0U)
  880. #define VHA_CR_PERF_SLC_EWO_REQ_RD_COUNTER_CLRMSK (00000000U)
  881. /*
  882. Register VHA_CR_PERF_SLC_EWO_REQ_RD_WORD
  883. */
  884. #define VHA_CR_PERF_SLC_EWO_REQ_RD_WORD (0x03B8U)
  885. #define VHA_CR_PERF_SLC_EWO_REQ_RD_WORD_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  886. #define VHA_CR_PERF_SLC_EWO_REQ_RD_WORD_COUNTER_SHIFT (0U)
  887. #define VHA_CR_PERF_SLC_EWO_REQ_RD_WORD_COUNTER_CLRMSK (00000000U)
  888. /*
  889. Register VHA_CR_BIF_RTN_FIFO_WORD_COUNT
  890. */
  891. #define VHA_CR_BIF_RTN_FIFO_WORD_COUNT (0x03C0U)
  892. #define VHA_CR_BIF_RTN_FIFO_WORD_COUNT_MASKFULL (IMG_UINT64_C(0x00000000000001FF))
  893. #define VHA_CR_BIF_RTN_FIFO_WORD_COUNT_COUNTER_SHIFT (0U)
  894. #define VHA_CR_BIF_RTN_FIFO_WORD_COUNT_COUNTER_CLRMSK (0XFFFFFE00U)
  895. #define VHA_CR_CLK_CTRL0_MODE_MASK (0x00000003U)
  896. /*
  897. The domain clock is forced off */
  898. #define VHA_CR_CLK_CTRL0_MODE_OFF (0x00000000U)
  899. /*
  900. The domain clock is forced on */
  901. #define VHA_CR_CLK_CTRL0_MODE_ON (0x00000001U)
  902. /*
  903. Automatic clock gating is active, the domain clock is only on whilst data is being processed */
  904. #define VHA_CR_CLK_CTRL0_MODE_AUTO (0x00000002U)
  905. /*
  906. Register VHA_CR_CLK_CTRL0
  907. */
  908. #define VHA_CR_CLK_CTRL0 (0x2000U)
  909. #define VHA_CR_CLK_CTRL0_MASKFULL (IMG_UINT64_C(0xF3FFFFFF3F000330))
  910. #define VHA_CR_CLK_CTRL0_CNN_CORE_XBAR_SHIFT (62U)
  911. #define VHA_CR_CLK_CTRL0_CNN_CORE_XBAR_CLRMSK (IMG_UINT64_C(0X3FFFFFFFFFFFFFFF))
  912. #define VHA_CR_CLK_CTRL0_CNN_CORE_XBAR_OFF (IMG_UINT64_C(0000000000000000))
  913. #define VHA_CR_CLK_CTRL0_CNN_CORE_XBAR_ON (IMG_UINT64_C(0x4000000000000000))
  914. #define VHA_CR_CLK_CTRL0_CNN_CORE_XBAR_AUTO (IMG_UINT64_C(0x8000000000000000))
  915. #define VHA_CR_CLK_CTRL0_CNN_MMM_SHIFT (60U)
  916. #define VHA_CR_CLK_CTRL0_CNN_MMM_CLRMSK (IMG_UINT64_C(0XCFFFFFFFFFFFFFFF))
  917. #define VHA_CR_CLK_CTRL0_CNN_MMM_OFF (IMG_UINT64_C(0000000000000000))
  918. #define VHA_CR_CLK_CTRL0_CNN_MMM_ON (IMG_UINT64_C(0x1000000000000000))
  919. #define VHA_CR_CLK_CTRL0_CNN_MMM_AUTO (IMG_UINT64_C(0x2000000000000000))
  920. #define VHA_CR_CLK_CTRL0_CNN_EWO_SHIFT (56U)
  921. #define VHA_CR_CLK_CTRL0_CNN_EWO_CLRMSK (IMG_UINT64_C(0XFCFFFFFFFFFFFFFF))
  922. #define VHA_CR_CLK_CTRL0_CNN_EWO_OFF (IMG_UINT64_C(0000000000000000))
  923. #define VHA_CR_CLK_CTRL0_CNN_EWO_ON (IMG_UINT64_C(0x0100000000000000))
  924. #define VHA_CR_CLK_CTRL0_CNN_EWO_AUTO (IMG_UINT64_C(0x0200000000000000))
  925. #define VHA_CR_CLK_CTRL0_CNN_PACK_SHIFT (54U)
  926. #define VHA_CR_CLK_CTRL0_CNN_PACK_CLRMSK (IMG_UINT64_C(0XFF3FFFFFFFFFFFFF))
  927. #define VHA_CR_CLK_CTRL0_CNN_PACK_OFF (IMG_UINT64_C(0000000000000000))
  928. #define VHA_CR_CLK_CTRL0_CNN_PACK_ON (IMG_UINT64_C(0x0040000000000000))
  929. #define VHA_CR_CLK_CTRL0_CNN_PACK_AUTO (IMG_UINT64_C(0x0080000000000000))
  930. #define VHA_CR_CLK_CTRL0_CNN_OIN_SHIFT (52U)
  931. #define VHA_CR_CLK_CTRL0_CNN_OIN_CLRMSK (IMG_UINT64_C(0XFFCFFFFFFFFFFFFF))
  932. #define VHA_CR_CLK_CTRL0_CNN_OIN_OFF (IMG_UINT64_C(0000000000000000))
  933. #define VHA_CR_CLK_CTRL0_CNN_OIN_ON (IMG_UINT64_C(0x0010000000000000))
  934. #define VHA_CR_CLK_CTRL0_CNN_OIN_AUTO (IMG_UINT64_C(0x0020000000000000))
  935. #define VHA_CR_CLK_CTRL0_CNN_POOL_SHIFT (50U)
  936. #define VHA_CR_CLK_CTRL0_CNN_POOL_CLRMSK (IMG_UINT64_C(0XFFF3FFFFFFFFFFFF))
  937. #define VHA_CR_CLK_CTRL0_CNN_POOL_OFF (IMG_UINT64_C(0000000000000000))
  938. #define VHA_CR_CLK_CTRL0_CNN_POOL_ON (IMG_UINT64_C(0x0004000000000000))
  939. #define VHA_CR_CLK_CTRL0_CNN_POOL_AUTO (IMG_UINT64_C(0x0008000000000000))
  940. #define VHA_CR_CLK_CTRL0_CNN_SB_SHIFT (48U)
  941. #define VHA_CR_CLK_CTRL0_CNN_SB_CLRMSK (IMG_UINT64_C(0XFFFCFFFFFFFFFFFF))
  942. #define VHA_CR_CLK_CTRL0_CNN_SB_OFF (IMG_UINT64_C(0000000000000000))
  943. #define VHA_CR_CLK_CTRL0_CNN_SB_ON (IMG_UINT64_C(0x0001000000000000))
  944. #define VHA_CR_CLK_CTRL0_CNN_SB_AUTO (IMG_UINT64_C(0x0002000000000000))
  945. #define VHA_CR_CLK_CTRL0_CNN_XBAR_SHIFT (46U)
  946. #define VHA_CR_CLK_CTRL0_CNN_XBAR_CLRMSK (IMG_UINT64_C(0XFFFF3FFFFFFFFFFF))
  947. #define VHA_CR_CLK_CTRL0_CNN_XBAR_OFF (IMG_UINT64_C(0000000000000000))
  948. #define VHA_CR_CLK_CTRL0_CNN_XBAR_ON (IMG_UINT64_C(0x0000400000000000))
  949. #define VHA_CR_CLK_CTRL0_CNN_XBAR_AUTO (IMG_UINT64_C(0x0000800000000000))
  950. #define VHA_CR_CLK_CTRL0_CNN_NORM_SHIFT (44U)
  951. #define VHA_CR_CLK_CTRL0_CNN_NORM_CLRMSK (IMG_UINT64_C(0XFFFFCFFFFFFFFFFF))
  952. #define VHA_CR_CLK_CTRL0_CNN_NORM_OFF (IMG_UINT64_C(0000000000000000))
  953. #define VHA_CR_CLK_CTRL0_CNN_NORM_ON (IMG_UINT64_C(0x0000100000000000))
  954. #define VHA_CR_CLK_CTRL0_CNN_NORM_AUTO (IMG_UINT64_C(0x0000200000000000))
  955. #define VHA_CR_CLK_CTRL0_CNN_ACT_SHIFT (42U)
  956. #define VHA_CR_CLK_CTRL0_CNN_ACT_CLRMSK (IMG_UINT64_C(0XFFFFF3FFFFFFFFFF))
  957. #define VHA_CR_CLK_CTRL0_CNN_ACT_OFF (IMG_UINT64_C(0000000000000000))
  958. #define VHA_CR_CLK_CTRL0_CNN_ACT_ON (IMG_UINT64_C(0x0000040000000000))
  959. #define VHA_CR_CLK_CTRL0_CNN_ACT_AUTO (IMG_UINT64_C(0x0000080000000000))
  960. #define VHA_CR_CLK_CTRL0_CNN_ACCUM_SHIFT (40U)
  961. #define VHA_CR_CLK_CTRL0_CNN_ACCUM_CLRMSK (IMG_UINT64_C(0XFFFFFCFFFFFFFFFF))
  962. #define VHA_CR_CLK_CTRL0_CNN_ACCUM_OFF (IMG_UINT64_C(0000000000000000))
  963. #define VHA_CR_CLK_CTRL0_CNN_ACCUM_ON (IMG_UINT64_C(0x0000010000000000))
  964. #define VHA_CR_CLK_CTRL0_CNN_ACCUM_AUTO (IMG_UINT64_C(0x0000020000000000))
  965. #define VHA_CR_CLK_CTRL0_CNN_CNV_SHIFT (38U)
  966. #define VHA_CR_CLK_CTRL0_CNN_CNV_CLRMSK (IMG_UINT64_C(0XFFFFFF3FFFFFFFFF))
  967. #define VHA_CR_CLK_CTRL0_CNN_CNV_OFF (IMG_UINT64_C(0000000000000000))
  968. #define VHA_CR_CLK_CTRL0_CNN_CNV_ON (IMG_UINT64_C(0x0000004000000000))
  969. #define VHA_CR_CLK_CTRL0_CNN_CNV_AUTO (IMG_UINT64_C(0x0000008000000000))
  970. #define VHA_CR_CLK_CTRL0_CNN_CBUF_SHIFT (36U)
  971. #define VHA_CR_CLK_CTRL0_CNN_CBUF_CLRMSK (IMG_UINT64_C(0XFFFFFFCFFFFFFFFF))
  972. #define VHA_CR_CLK_CTRL0_CNN_CBUF_OFF (IMG_UINT64_C(0000000000000000))
  973. #define VHA_CR_CLK_CTRL0_CNN_CBUF_ON (IMG_UINT64_C(0x0000001000000000))
  974. #define VHA_CR_CLK_CTRL0_CNN_CBUF_AUTO (IMG_UINT64_C(0x0000002000000000))
  975. #define VHA_CR_CLK_CTRL0_CNN_IBUF_SHIFT (34U)
  976. #define VHA_CR_CLK_CTRL0_CNN_IBUF_CLRMSK (IMG_UINT64_C(0XFFFFFFF3FFFFFFFF))
  977. #define VHA_CR_CLK_CTRL0_CNN_IBUF_OFF (IMG_UINT64_C(0000000000000000))
  978. #define VHA_CR_CLK_CTRL0_CNN_IBUF_ON (IMG_UINT64_C(0x0000000400000000))
  979. #define VHA_CR_CLK_CTRL0_CNN_IBUF_AUTO (IMG_UINT64_C(0x0000000800000000))
  980. #define VHA_CR_CLK_CTRL0_CNN_CMD_SHIFT (32U)
  981. #define VHA_CR_CLK_CTRL0_CNN_CMD_CLRMSK (IMG_UINT64_C(0XFFFFFFFCFFFFFFFF))
  982. #define VHA_CR_CLK_CTRL0_CNN_CMD_OFF (IMG_UINT64_C(0000000000000000))
  983. #define VHA_CR_CLK_CTRL0_CNN_CMD_ON (IMG_UINT64_C(0x0000000100000000))
  984. #define VHA_CR_CLK_CTRL0_CNN_CMD_AUTO (IMG_UINT64_C(0x0000000200000000))
  985. #define VHA_CR_CLK_CTRL0_CNN_SHIFT (28U)
  986. #define VHA_CR_CLK_CTRL0_CNN_CLRMSK (IMG_UINT64_C(0XFFFFFFFFCFFFFFFF))
  987. #define VHA_CR_CLK_CTRL0_CNN_OFF (IMG_UINT64_C(0000000000000000))
  988. #define VHA_CR_CLK_CTRL0_CNN_ON (IMG_UINT64_C(0x0000000010000000))
  989. #define VHA_CR_CLK_CTRL0_CNN_AUTO (IMG_UINT64_C(0x0000000020000000))
  990. #define VHA_CR_CLK_CTRL0_CNN_TRS_A_SHIFT (26U)
  991. #define VHA_CR_CLK_CTRL0_CNN_TRS_A_CLRMSK (IMG_UINT64_C(0XFFFFFFFFF3FFFFFF))
  992. #define VHA_CR_CLK_CTRL0_CNN_TRS_A_OFF (IMG_UINT64_C(0000000000000000))
  993. #define VHA_CR_CLK_CTRL0_CNN_TRS_A_ON (IMG_UINT64_C(0x0000000004000000))
  994. #define VHA_CR_CLK_CTRL0_CNN_TRS_A_AUTO (IMG_UINT64_C(0x0000000008000000))
  995. #define VHA_CR_CLK_CTRL0_CNN_TRS_B_SHIFT (24U)
  996. #define VHA_CR_CLK_CTRL0_CNN_TRS_B_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFCFFFFFF))
  997. #define VHA_CR_CLK_CTRL0_CNN_TRS_B_OFF (IMG_UINT64_C(0000000000000000))
  998. #define VHA_CR_CLK_CTRL0_CNN_TRS_B_ON (IMG_UINT64_C(0x0000000001000000))
  999. #define VHA_CR_CLK_CTRL0_CNN_TRS_B_AUTO (IMG_UINT64_C(0x0000000002000000))
  1000. #define VHA_CR_CLK_CTRL0_SLC_SHIFT (8U)
  1001. #define VHA_CR_CLK_CTRL0_SLC_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFCFF))
  1002. #define VHA_CR_CLK_CTRL0_SLC_OFF (IMG_UINT64_C(0000000000000000))
  1003. #define VHA_CR_CLK_CTRL0_SLC_ON (IMG_UINT64_C(0x0000000000000100))
  1004. #define VHA_CR_CLK_CTRL0_SLC_AUTO (IMG_UINT64_C(0x0000000000000200))
  1005. #define VHA_CR_CLK_CTRL0_BIF_SHIFT (4U)
  1006. #define VHA_CR_CLK_CTRL0_BIF_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFCF))
  1007. #define VHA_CR_CLK_CTRL0_BIF_OFF (IMG_UINT64_C(0000000000000000))
  1008. #define VHA_CR_CLK_CTRL0_BIF_ON (IMG_UINT64_C(0x0000000000000010))
  1009. #define VHA_CR_CLK_CTRL0_BIF_AUTO (IMG_UINT64_C(0x0000000000000020))
  1010. /*
  1011. Register VHA_CR_VHA_AXI_RESET_CTRL
  1012. */
  1013. #define VHA_CR_VHA_AXI_RESET_CTRL (0x2008U)
  1014. #define VHA_CR_VHA_AXI_RESET_CTRL_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  1015. #define VHA_CR_VHA_AXI_RESET_CTRL_SOFT_RESET_CYCLES_SHIFT (0U)
  1016. #define VHA_CR_VHA_AXI_RESET_CTRL_SOFT_RESET_CYCLES_CLRMSK (00000000U)
  1017. /*
  1018. Register VHA_CR_RESET_CTRL
  1019. */
  1020. #define VHA_CR_RESET_CTRL (0x2010U)
  1021. #define VHA_CR_RESET_CTRL_MASKFULL (IMG_UINT64_C(0x00000000C0000107))
  1022. #define VHA_CR_RESET_CTRL_VHA_SYS_SOFT_RESET_SHIFT (31U)
  1023. #define VHA_CR_RESET_CTRL_VHA_SYS_SOFT_RESET_CLRMSK (0X7FFFFFFFU)
  1024. #define VHA_CR_RESET_CTRL_VHA_SYS_SOFT_RESET_EN (0X80000000U)
  1025. #define VHA_CR_RESET_CTRL_VHA_AXI_SOFT_RESET_SHIFT (30U)
  1026. #define VHA_CR_RESET_CTRL_VHA_AXI_SOFT_RESET_CLRMSK (0XBFFFFFFFU)
  1027. #define VHA_CR_RESET_CTRL_VHA_AXI_SOFT_RESET_EN (0X40000000U)
  1028. #define VHA_CR_RESET_CTRL_VHA_CNN0_SOFT_RESET_SHIFT (8U)
  1029. #define VHA_CR_RESET_CTRL_VHA_CNN0_SOFT_RESET_CLRMSK (0XFFFFFEFFU)
  1030. #define VHA_CR_RESET_CTRL_VHA_CNN0_SOFT_RESET_EN (0X00000100U)
  1031. #define VHA_CR_RESET_CTRL_VHA_SLC_SOFT_RESET_SHIFT (2U)
  1032. #define VHA_CR_RESET_CTRL_VHA_SLC_SOFT_RESET_CLRMSK (0XFFFFFFFBU)
  1033. #define VHA_CR_RESET_CTRL_VHA_SLC_SOFT_RESET_EN (0X00000004U)
  1034. #define VHA_CR_RESET_CTRL_VHA_BIF_SOFT_RESET_SHIFT (1U)
  1035. #define VHA_CR_RESET_CTRL_VHA_BIF_SOFT_RESET_CLRMSK (0XFFFFFFFDU)
  1036. #define VHA_CR_RESET_CTRL_VHA_BIF_SOFT_RESET_EN (0X00000002U)
  1037. #define VHA_CR_RESET_CTRL_VHA_SOFT_RESET_SHIFT (0U)
  1038. #define VHA_CR_RESET_CTRL_VHA_SOFT_RESET_CLRMSK (0XFFFFFFFEU)
  1039. #define VHA_CR_RESET_CTRL_VHA_SOFT_RESET_EN (0X00000001U)
  1040. /*
  1041. Register VHA_CR_CNN_CMD_MH_CONTROL
  1042. */
  1043. #define VHA_CR_CNN_CMD_MH_CONTROL (0x2018U)
  1044. #define VHA_CR_CNN_CMD_MH_CONTROL_MASKFULL (IMG_UINT64_C(0x0000000000000034))
  1045. #define VHA_CR_CNN_CMD_MH_CONTROL_MAX_BURST_LENGTH_SHIFT (4U)
  1046. #define VHA_CR_CNN_CMD_MH_CONTROL_MAX_BURST_LENGTH_CLRMSK (0XFFFFFFCFU)
  1047. #define VHA_CR_CNN_CMD_MH_CONTROL_SLC_CACHE_POLICY_SHIFT (2U)
  1048. #define VHA_CR_CNN_CMD_MH_CONTROL_SLC_CACHE_POLICY_CLRMSK (0XFFFFFFFBU)
  1049. #define VHA_CR_CNN_CMD_MH_CONTROL_SLC_CACHE_POLICY_EN (0X00000004U)
  1050. /*
  1051. Register VHA_CR_CNN_IBUF_MH_CONTROL
  1052. */
  1053. #define VHA_CR_CNN_IBUF_MH_CONTROL (0x2020U)
  1054. #define VHA_CR_CNN_IBUF_MH_CONTROL_MASKFULL (IMG_UINT64_C(0x0000000000000018))
  1055. #define VHA_CR_CNN_IBUF_MH_CONTROL_MAX_BURST_LENGTH_SHIFT (3U)
  1056. #define VHA_CR_CNN_IBUF_MH_CONTROL_MAX_BURST_LENGTH_CLRMSK (0XFFFFFFE7U)
  1057. /*
  1058. Register VHA_CR_CNN_CBUF_MH_CONTROL
  1059. */
  1060. #define VHA_CR_CNN_CBUF_MH_CONTROL (0x2028U)
  1061. #define VHA_CR_CNN_CBUF_MH_CONTROL_MASKFULL (IMG_UINT64_C(0x0000000000000018))
  1062. #define VHA_CR_CNN_CBUF_MH_CONTROL_MAX_BURST_LENGTH_SHIFT (3U)
  1063. #define VHA_CR_CNN_CBUF_MH_CONTROL_MAX_BURST_LENGTH_CLRMSK (0XFFFFFFE7U)
  1064. /*
  1065. Register VHA_CR_CNN_ABUF_MH_CONTROL
  1066. */
  1067. #define VHA_CR_CNN_ABUF_MH_CONTROL (0x2030U)
  1068. #define VHA_CR_CNN_ABUF_MH_CONTROL_MASKFULL (IMG_UINT64_C(0x0000000000000018))
  1069. #define VHA_CR_CNN_ABUF_MH_CONTROL_MAX_BURST_LENGTH_SHIFT (3U)
  1070. #define VHA_CR_CNN_ABUF_MH_CONTROL_MAX_BURST_LENGTH_CLRMSK (0XFFFFFFE7U)
  1071. /*
  1072. Register VHA_CR_CNN_OUTPACK_MH_CONTROL
  1073. */
  1074. #define VHA_CR_CNN_OUTPACK_MH_CONTROL (0x2038U)
  1075. #define VHA_CR_CNN_OUTPACK_MH_CONTROL_MASKFULL (IMG_UINT64_C(0x0000000000000018))
  1076. #define VHA_CR_CNN_OUTPACK_MH_CONTROL_MAX_BURST_LENGTH_SHIFT (3U)
  1077. #define VHA_CR_CNN_OUTPACK_MH_CONTROL_MAX_BURST_LENGTH_CLRMSK (0XFFFFFFE7U)
  1078. /*
  1079. Register VHA_CR_CNN_ELEMENTOPS_MH_CONTROL
  1080. */
  1081. #define VHA_CR_CNN_ELEMENTOPS_MH_CONTROL (0x2040U)
  1082. #define VHA_CR_CNN_ELEMENTOPS_MH_CONTROL_MASKFULL (IMG_UINT64_C(0x0000000000000018))
  1083. #define VHA_CR_CNN_ELEMENTOPS_MH_CONTROL_MAX_BURST_LENGTH_SHIFT (3U)
  1084. #define VHA_CR_CNN_ELEMENTOPS_MH_CONTROL_MAX_BURST_LENGTH_CLRMSK (0XFFFFFFE7U)
  1085. /*
  1086. Register VHA_CR_CNN_MMM_MH_CONTROL
  1087. */
  1088. #define VHA_CR_CNN_MMM_MH_CONTROL (0x2048U)
  1089. #define VHA_CR_CNN_MMM_MH_CONTROL_MASKFULL (IMG_UINT64_C(0x0000000000000018))
  1090. #define VHA_CR_CNN_MMM_MH_CONTROL_MAX_BURST_LENGTH_SHIFT (3U)
  1091. #define VHA_CR_CNN_MMM_MH_CONTROL_MAX_BURST_LENGTH_CLRMSK (0XFFFFFFE7U)
  1092. /*
  1093. Register VHA_CR_CNN_TRS_A_MH_CONTROL
  1094. */
  1095. #define VHA_CR_CNN_TRS_A_MH_CONTROL (0x2050U)
  1096. #define VHA_CR_CNN_TRS_A_MH_CONTROL_MASKFULL (IMG_UINT64_C(0x0000000000000018))
  1097. #define VHA_CR_CNN_TRS_A_MH_CONTROL_MAX_BURST_LENGTH_SHIFT (3U)
  1098. #define VHA_CR_CNN_TRS_A_MH_CONTROL_MAX_BURST_LENGTH_CLRMSK (0XFFFFFFE7U)
  1099. /*
  1100. Register VHA_CR_CNN_TRS_B_MH_CONTROL
  1101. */
  1102. #define VHA_CR_CNN_TRS_B_MH_CONTROL (0x2058U)
  1103. #define VHA_CR_CNN_TRS_B_MH_CONTROL_MASKFULL (IMG_UINT64_C(0x0000000000000018))
  1104. #define VHA_CR_CNN_TRS_B_MH_CONTROL_MAX_BURST_LENGTH_SHIFT (3U)
  1105. #define VHA_CR_CNN_TRS_B_MH_CONTROL_MAX_BURST_LENGTH_CLRMSK (0XFFFFFFE7U)
  1106. /*
  1107. Register VHA_CR_CNN_DWPE_MH_CONTROL
  1108. */
  1109. #define VHA_CR_CNN_DWPE_MH_CONTROL (0x2060U)
  1110. #define VHA_CR_CNN_DWPE_MH_CONTROL_MASKFULL (IMG_UINT64_C(0x0000000000000018))
  1111. #define VHA_CR_CNN_DWPE_MH_CONTROL_MAX_BURST_LENGTH_SHIFT (3U)
  1112. #define VHA_CR_CNN_DWPE_MH_CONTROL_MAX_BURST_LENGTH_CLRMSK (0XFFFFFFE7U)
  1113. /*
  1114. Register VHA_CR_FUSA_CONTROL
  1115. */
  1116. #define VHA_CR_FUSA_CONTROL (0x2090U)
  1117. #define VHA_CR_FUSA_CONTROL_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  1118. #define VHA_CR_FUSA_CONTROL_ECC_INIT_KICK_SHIFT (0U)
  1119. #define VHA_CR_FUSA_CONTROL_ECC_INIT_KICK_CLRMSK (0XFFFFFFFEU)
  1120. #define VHA_CR_FUSA_CONTROL_ECC_INIT_KICK_EN (0X00000001U)
  1121. /*
  1122. Register VHA_CR_PM_VFP_TRAN_EN
  1123. */
  1124. #define VHA_CR_PM_VFP_TRAN_EN (0x2100U)
  1125. #define VHA_CR_PM_VFP_TRAN_EN_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  1126. #define VHA_CR_PM_VFP_TRAN_EN_OP_SHIFT (0U)
  1127. #define VHA_CR_PM_VFP_TRAN_EN_OP_CLRMSK (0XFFFFFFFEU)
  1128. #define VHA_CR_PM_VFP_TRAN_EN_OP_EN (0X00000001U)
  1129. /*
  1130. Register VHA_CR_CNN_MEM_WDT_COMPAREMATCH
  1131. */
  1132. #define VHA_CR_CNN_MEM_WDT_COMPAREMATCH (0x2118U)
  1133. #define VHA_CR_CNN_MEM_WDT_COMPAREMATCH_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  1134. #define VHA_CR_CNN_MEM_WDT_COMPAREMATCH_REG_SHIFT (0U)
  1135. #define VHA_CR_CNN_MEM_WDT_COMPAREMATCH_REG_CLRMSK (00000000U)
  1136. #define VHA_CR_CNN_MEM_WDT_CTRL_CNN_MEM_WDT_CTRL_MASK (0x00000003U)
  1137. /*
  1138. WDT is Disabled */
  1139. #define VHA_CR_CNN_MEM_WDT_CTRL_CNN_MEM_WDT_CTRL_NONE (0x00000000U)
  1140. /*
  1141. WDT is Cleared when CMD Parser starts a pass or CMD parser is kicked*/
  1142. #define VHA_CR_CNN_MEM_WDT_CTRL_CNN_MEM_WDT_CTRL_KICK_PASS (0x00000001U)
  1143. /*
  1144. WDT is Cleared when CMD Parser is kicked */
  1145. #define VHA_CR_CNN_MEM_WDT_CTRL_CNN_MEM_WDT_CTRL_KICK (0x00000002U)
  1146. /*
  1147. Register VHA_CR_CNN_MEM_WDT_CTRL
  1148. */
  1149. #define VHA_CR_CNN_MEM_WDT_CTRL (0x2120U)
  1150. #define VHA_CR_CNN_MEM_WDT_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000000003))
  1151. #define VHA_CR_CNN_MEM_WDT_CTRL_MODE_SHIFT (0U)
  1152. #define VHA_CR_CNN_MEM_WDT_CTRL_MODE_CLRMSK (0XFFFFFFFCU)
  1153. #define VHA_CR_CNN_MEM_WDT_CTRL_MODE_NONE (00000000U)
  1154. #define VHA_CR_CNN_MEM_WDT_CTRL_MODE_KICK_PASS (0X00000001U)
  1155. #define VHA_CR_CNN_MEM_WDT_CTRL_MODE_KICK (0X00000002U)
  1156. #define VHA_CR_CNN_HL_WDT_CTRL_CNN_HL_WDT_CTRL_MASK (0x00000003U)
  1157. /*
  1158. WDT is Cleared when CMD Parser starts a pass or CMD parser is kicked*/
  1159. #define VHA_CR_CNN_HL_WDT_CTRL_CNN_HL_WDT_CTRL_KICK_PASS (0x00000001U)
  1160. /*
  1161. WDT is Cleared when CMD Parser starts a layer group or CMD parser is kicked*/
  1162. #define VHA_CR_CNN_HL_WDT_CTRL_CNN_HL_WDT_CTRL_KICK_LAYER (0x00000002U)
  1163. /*
  1164. Register VHA_CR_CNN_HL_WDT_CTRL
  1165. */
  1166. #define VHA_CR_CNN_HL_WDT_CTRL (0x2128U)
  1167. #define VHA_CR_CNN_HL_WDT_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000000003))
  1168. #define VHA_CR_CNN_HL_WDT_CTRL_MODE_SHIFT (0U)
  1169. #define VHA_CR_CNN_HL_WDT_CTRL_MODE_CLRMSK (0XFFFFFFFCU)
  1170. #define VHA_CR_CNN_HL_WDT_CTRL_MODE_KICK_PASS (0X00000001U)
  1171. #define VHA_CR_CNN_HL_WDT_CTRL_MODE_KICK_LAYER (0X00000002U)
  1172. /*
  1173. Register VHA_CR_CNN_HL_WDT_COMPAREMATCH
  1174. */
  1175. #define VHA_CR_CNN_HL_WDT_COMPAREMATCH (0x2130U)
  1176. #define VHA_CR_CNN_HL_WDT_COMPAREMATCH_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  1177. #define VHA_CR_CNN_HL_WDT_COMPAREMATCH_REG_SHIFT (0U)
  1178. #define VHA_CR_CNN_HL_WDT_COMPAREMATCH_REG_CLRMSK (00000000U)
  1179. /*
  1180. Register VHA_CR_IDLE_HYSTERESIS_COUNT
  1181. */
  1182. #define VHA_CR_IDLE_HYSTERESIS_COUNT (0x2140U)
  1183. #define VHA_CR_IDLE_HYSTERESIS_COUNT_MASKFULL (IMG_UINT64_C(0x0000001F00001F1F))
  1184. #define VHA_CR_IDLE_HYSTERESIS_COUNT_VHA_SYS_SHIFT (32U)
  1185. #define VHA_CR_IDLE_HYSTERESIS_COUNT_VHA_SYS_CLRMSK (IMG_UINT64_C(0XFFFFFFE0FFFFFFFF))
  1186. #define VHA_CR_IDLE_HYSTERESIS_COUNT_CNN_TOP_SHIFT (8U)
  1187. #define VHA_CR_IDLE_HYSTERESIS_COUNT_CNN_TOP_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFE0FF))
  1188. #define VHA_CR_IDLE_HYSTERESIS_COUNT_VHA_CTRL_SHIFT (0U)
  1189. #define VHA_CR_IDLE_HYSTERESIS_COUNT_VHA_CTRL_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFE0))
  1190. /*
  1191. Register VHA_CR_SOCIF_WAKEUP_ENABLE
  1192. */
  1193. #define VHA_CR_SOCIF_WAKEUP_ENABLE (0x2148U)
  1194. #define VHA_CR_SOCIF_WAKEUP_ENABLE_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  1195. #define VHA_CR_SOCIF_WAKEUP_ENABLE_ALWAYS_SHIFT (0U)
  1196. #define VHA_CR_SOCIF_WAKEUP_ENABLE_ALWAYS_CLRMSK (0XFFFFFFFEU)
  1197. #define VHA_CR_SOCIF_WAKEUP_ENABLE_ALWAYS_EN (0X00000001U)
  1198. /*
  1199. Register VHA_CR_RESET_CLK_CTRL
  1200. */
  1201. #define VHA_CR_RESET_CLK_CTRL (0x2150U)
  1202. #define VHA_CR_RESET_CLK_CTRL_MASKFULL (IMG_UINT64_C(0x00000000000003FF))
  1203. #define VHA_CR_RESET_CLK_CTRL_VHA_SYS_SHIFT (8U)
  1204. #define VHA_CR_RESET_CLK_CTRL_VHA_SYS_CLRMSK (0XFFFFFCFFU)
  1205. #define VHA_CR_RESET_CLK_CTRL_CNN_FE_SHIFT (6U)
  1206. #define VHA_CR_RESET_CLK_CTRL_CNN_FE_CLRMSK (0XFFFFFF3FU)
  1207. #define VHA_CR_RESET_CLK_CTRL_CNN_BE_SHIFT (4U)
  1208. #define VHA_CR_RESET_CLK_CTRL_CNN_BE_CLRMSK (0XFFFFFFCFU)
  1209. #define VHA_CR_RESET_CLK_CTRL_CNN_TOP_SHIFT (2U)
  1210. #define VHA_CR_RESET_CLK_CTRL_CNN_TOP_CLRMSK (0XFFFFFFF3U)
  1211. #define VHA_CR_RESET_CLK_CTRL_VHA_CTRL_SHIFT (0U)
  1212. #define VHA_CR_RESET_CLK_CTRL_VHA_CTRL_CLRMSK (0XFFFFFFFCU)
  1213. #define VHA_CR_SYS_CLK_CTRL0_MODE_MASK (0x00000003U)
  1214. /*
  1215. The domain clock is forced off */
  1216. #define VHA_CR_SYS_CLK_CTRL0_MODE_OFF (0x00000000U)
  1217. /*
  1218. The domain clock is forced on */
  1219. #define VHA_CR_SYS_CLK_CTRL0_MODE_ON (0x00000001U)
  1220. /*
  1221. Automatic clock gating is active, the domain clock is only on whilst data is being processed */
  1222. #define VHA_CR_SYS_CLK_CTRL0_MODE_AUTO (0x00000002U)
  1223. /*
  1224. Register VHA_CR_SYS_CLK_CTRL0
  1225. */
  1226. #define VHA_CR_SYS_CLK_CTRL0 (0x2158U)
  1227. #define VHA_CR_SYS_CLK_CTRL0_MASKFULL (IMG_UINT64_C(0x0000000000000030))
  1228. #define VHA_CR_SYS_CLK_CTRL0_SLC_SHIFT (4U)
  1229. #define VHA_CR_SYS_CLK_CTRL0_SLC_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFCF))
  1230. #define VHA_CR_SYS_CLK_CTRL0_SLC_OFF (IMG_UINT64_C(0000000000000000))
  1231. #define VHA_CR_SYS_CLK_CTRL0_SLC_ON (IMG_UINT64_C(0x0000000000000010))
  1232. #define VHA_CR_SYS_CLK_CTRL0_SLC_AUTO (IMG_UINT64_C(0x0000000000000020))
  1233. /*
  1234. Register VHA_CR_AXI_EXACCESS
  1235. */
  1236. #define VHA_CR_AXI_EXACCESS (0x2168U)
  1237. #define VHA_CR_AXI_EXACCESS_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  1238. #define VHA_CR_AXI_EXACCESS_SOCIF_ENABLE_SHIFT (0U)
  1239. #define VHA_CR_AXI_EXACCESS_SOCIF_ENABLE_CLRMSK (0XFFFFFFFEU)
  1240. #define VHA_CR_AXI_EXACCESS_SOCIF_ENABLE_EN (0X00000001U)
  1241. /*
  1242. Register VHA_CR_REGBANK_REQUEST_INVALID
  1243. */
  1244. #define VHA_CR_REGBANK_REQUEST_INVALID (0x2170U)
  1245. #define VHA_CR_REGBANK_REQUEST_INVALID_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  1246. #define VHA_CR_REGBANK_REQUEST_INVALID_FLAG_SHIFT (0U)
  1247. #define VHA_CR_REGBANK_REQUEST_INVALID_FLAG_CLRMSK (0XFFFFFFFEU)
  1248. #define VHA_CR_REGBANK_REQUEST_INVALID_FLAG_EN (0X00000001U)
  1249. /*
  1250. Register VHA_CR_CNN_CMD_PRIORITY_LIMITS_LEGACY
  1251. */
  1252. #define VHA_CR_CNN_CMD_PRIORITY_LIMITS_LEGACY (0x2180U)
  1253. #define VHA_CR_CNN_CMD_PRIORITY_LIMITS_LEGACY_MASKFULL (IMG_UINT64_C(0x000000000000019B))
  1254. #define VHA_CR_CNN_CMD_PRIORITY_LIMITS_LEGACY_OS2_LIMIT_SHIFT (7U)
  1255. #define VHA_CR_CNN_CMD_PRIORITY_LIMITS_LEGACY_OS2_LIMIT_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFE7F))
  1256. #define VHA_CR_CNN_CMD_PRIORITY_LIMITS_LEGACY_OS1_LIMIT_SHIFT (3U)
  1257. #define VHA_CR_CNN_CMD_PRIORITY_LIMITS_LEGACY_OS1_LIMIT_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFE7))
  1258. #define VHA_CR_CNN_CMD_PRIORITY_LIMITS_LEGACY_OS0_LIMIT_SHIFT (0U)
  1259. #define VHA_CR_CNN_CMD_PRIORITY_LIMITS_LEGACY_OS0_LIMIT_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFC))
  1260. /*
  1261. Register VHA_CR_VHA_CNN_CMD_SECURITY_CONTROL
  1262. */
  1263. #define VHA_CR_VHA_CNN_CMD_SECURITY_CONTROL (0x2188U)
  1264. #define VHA_CR_VHA_CNN_CMD_SECURITY_CONTROL_MASKFULL (IMG_UINT64_C(0x0000000000000007))
  1265. #define VHA_CR_VHA_CNN_CMD_SECURITY_CONTROL_FORCE_DISABLE_CRC_SHIFT (2U)
  1266. #define VHA_CR_VHA_CNN_CMD_SECURITY_CONTROL_FORCE_DISABLE_CRC_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFB))
  1267. #define VHA_CR_VHA_CNN_CMD_SECURITY_CONTROL_FORCE_DISABLE_CRC_EN (IMG_UINT64_C(0X0000000000000004))
  1268. #define VHA_CR_VHA_CNN_CMD_SECURITY_CONTROL_RAM_SCRUB_ON_SWITCH_SHIFT (1U)
  1269. #define VHA_CR_VHA_CNN_CMD_SECURITY_CONTROL_RAM_SCRUB_ON_SWITCH_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFD))
  1270. #define VHA_CR_VHA_CNN_CMD_SECURITY_CONTROL_RAM_SCRUB_ON_SWITCH_EN (IMG_UINT64_C(0X0000000000000002))
  1271. #define VHA_CR_VHA_CNN_CMD_SECURITY_CONTROL_FORCE_RAM_SCRUB_SHIFT (0U)
  1272. #define VHA_CR_VHA_CNN_CMD_SECURITY_CONTROL_FORCE_RAM_SCRUB_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  1273. #define VHA_CR_VHA_CNN_CMD_SECURITY_CONTROL_FORCE_RAM_SCRUB_EN (IMG_UINT64_C(0X0000000000000001))
  1274. /*
  1275. Register VHA_CR_CNN_ARB_STALL_RATIO
  1276. */
  1277. #define VHA_CR_CNN_ARB_STALL_RATIO (0x2200U)
  1278. #define VHA_CR_CNN_ARB_STALL_RATIO_MASKFULL (IMG_UINT64_C(0x0000000FFFFFFFFF))
  1279. #define VHA_CR_CNN_ARB_STALL_RATIO_OUTPUT_SHIFT (32U)
  1280. #define VHA_CR_CNN_ARB_STALL_RATIO_OUTPUT_CLRMSK (IMG_UINT64_C(0XFFFFFFF0FFFFFFFF))
  1281. #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_8_SHIFT (28U)
  1282. #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_8_CLRMSK (IMG_UINT64_C(0XFFFFFFFF0FFFFFFF))
  1283. #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_7_SHIFT (24U)
  1284. #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_7_CLRMSK (IMG_UINT64_C(0XFFFFFFFFF0FFFFFF))
  1285. #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_6_SHIFT (20U)
  1286. #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_6_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF0FFFFF))
  1287. #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_5_SHIFT (16U)
  1288. #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_5_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF0FFFF))
  1289. #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_4_SHIFT (12U)
  1290. #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_4_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF0FFF))
  1291. #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_3_SHIFT (8U)
  1292. #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_3_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF0FF))
  1293. #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_2_SHIFT (4U)
  1294. #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_2_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFF0F))
  1295. #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_1_SHIFT (0U)
  1296. #define VHA_CR_CNN_ARB_STALL_RATIO_REQUESTER_1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF0))
  1297. /*
  1298. Register VHA_CR_CNN_DATAPATH_STALL_RATIO_0
  1299. */
  1300. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0 (0x2208U)
  1301. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_MASKFULL (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
  1302. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_CORE_XBAR_ACT_SHIFT (60U)
  1303. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_CORE_XBAR_ACT_CLRMSK (IMG_UINT64_C(0X0FFFFFFFFFFFFFFF))
  1304. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_ACT_CORE_XBAR_SHIFT (56U)
  1305. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_ACT_CORE_XBAR_CLRMSK (IMG_UINT64_C(0XF0FFFFFFFFFFFFFF))
  1306. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_EWO_CORE_XBAR_SHIFT (52U)
  1307. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_EWO_CORE_XBAR_CLRMSK (IMG_UINT64_C(0XFF0FFFFFFFFFFFFF))
  1308. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_TENSORB_CORE_XBAR_SHIFT (48U)
  1309. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_TENSORB_CORE_XBAR_CLRMSK (IMG_UINT64_C(0XFFF0FFFFFFFFFFFF))
  1310. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_CORE_XBAR_EWO_SHIFT (44U)
  1311. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_CORE_XBAR_EWO_CLRMSK (IMG_UINT64_C(0XFFFF0FFFFFFFFFFF))
  1312. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_CORE_XBAR_TENSORB_SHIFT (40U)
  1313. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_CORE_XBAR_TENSORB_CLRMSK (IMG_UINT64_C(0XFFFFF0FFFFFFFFFF))
  1314. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_CORE_XBAR_NORM_SHIFT (36U)
  1315. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_CORE_XBAR_NORM_CLRMSK (IMG_UINT64_C(0XFFFFFF0FFFFFFFFF))
  1316. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_NORM_POOL_SHIFT (32U)
  1317. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_NORM_POOL_CLRMSK (IMG_UINT64_C(0XFFFFFFF0FFFFFFFF))
  1318. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_CNV_ABUF_SHIFT (28U)
  1319. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_CNV_ABUF_CLRMSK (IMG_UINT64_C(0XFFFFFFFF0FFFFFFF))
  1320. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_IBUF_CNV_SHIFT (24U)
  1321. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_IBUF_CNV_CLRMSK (IMG_UINT64_C(0XFFFFFFFFF0FFFFFF))
  1322. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_ABUF_CORE_XBAR_SHIFT (20U)
  1323. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_ABUF_CORE_XBAR_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF0FFFFF))
  1324. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_CORE_XBAR_IBUF_SHIFT (16U)
  1325. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_CORE_XBAR_IBUF_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF0FFFF))
  1326. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_IBUF_CORE_XBAR_SHIFT (12U)
  1327. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_IBUF_CORE_XBAR_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF0FFF))
  1328. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_CBUF_CNV_SHIFT (8U)
  1329. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_CBUF_CNV_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF0FF))
  1330. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_ABUF_OUTPACK_SHIFT (4U)
  1331. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_ABUF_OUTPACK_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFF0F))
  1332. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_CBUF_ABUF_SHIFT (0U)
  1333. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_0_CBUF_ABUF_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF0))
  1334. /*
  1335. Register VHA_CR_CNN_DATAPATH_STALL_RATIO_1
  1336. */
  1337. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_1 (0x2210U)
  1338. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_1_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  1339. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_1_NORM_POOL_BYPASS_SHIFT (36U)
  1340. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_1_NORM_POOL_BYPASS_CLRMSK (IMG_UINT64_C(0XFFFFFF0FFFFFFFFF))
  1341. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_1_TRS_B_XBAR_SHIFT (32U)
  1342. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_1_TRS_B_XBAR_CLRMSK (IMG_UINT64_C(0XFFFFFFF0FFFFFFFF))
  1343. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_1_XBAR_TRS_B_SHIFT (28U)
  1344. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_1_XBAR_TRS_B_CLRMSK (IMG_UINT64_C(0XFFFFFFFF0FFFFFFF))
  1345. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_1_TRS_A_XBAR_SHIFT (24U)
  1346. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_1_TRS_A_XBAR_CLRMSK (IMG_UINT64_C(0XFFFFFFFFF0FFFFFF))
  1347. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_1_XBAR_TRS_A_SHIFT (20U)
  1348. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_1_XBAR_TRS_A_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF0FFFFF))
  1349. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_1_OIN_OPK_SHIFT (16U)
  1350. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_1_OIN_OPK_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF0FFFF))
  1351. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_1_CORE_XBAR_OIN_SHIFT (12U)
  1352. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_1_CORE_XBAR_OIN_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF0FFF))
  1353. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_1_POOL_CORE_XBAR_SHIFT (8U)
  1354. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_1_POOL_CORE_XBAR_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF0FF))
  1355. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_1_POOL_SB_SHIFT (4U)
  1356. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_1_POOL_SB_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFF0F))
  1357. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_1_OIN_SB_SHIFT (0U)
  1358. #define VHA_CR_CNN_DATAPATH_STALL_RATIO_1_OIN_SB_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF0))
  1359. /*
  1360. Register VHA_CR_CNN_ARB_CTRL
  1361. */
  1362. #define VHA_CR_CNN_ARB_CTRL (0x2218U)
  1363. #define VHA_CR_CNN_ARB_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000000307))
  1364. #define VHA_CR_CNN_ARB_CTRL_ENABLE_PASS_PRIORITY_SHIFT (9U)
  1365. #define VHA_CR_CNN_ARB_CTRL_ENABLE_PASS_PRIORITY_CLRMSK (0XFFFFFDFFU)
  1366. #define VHA_CR_CNN_ARB_CTRL_ENABLE_PASS_PRIORITY_EN (0X00000200U)
  1367. #define VHA_CR_CNN_ARB_CTRL_MMM_PRIORITY_SEL_SHIFT (8U)
  1368. #define VHA_CR_CNN_ARB_CTRL_MMM_PRIORITY_SEL_CLRMSK (0XFFFFFEFFU)
  1369. #define VHA_CR_CNN_ARB_CTRL_MMM_PRIORITY_SEL_EN (0X00000100U)
  1370. #define VHA_CR_CNN_ARB_CTRL_MAX_PAGE_COUNT_MIN1_SHIFT (0U)
  1371. #define VHA_CR_CNN_ARB_CTRL_MAX_PAGE_COUNT_MIN1_CLRMSK (0XFFFFFFF8U)
  1372. /*
  1373. Register VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0
  1374. */
  1375. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0 (0xE008U)
  1376. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0_MASKFULL (IMG_UINT64_C(0x0FFFFFFFFFFFF001))
  1377. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0_INIT_PAGE_SHIFT (40U)
  1378. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0_INIT_PAGE_CLRMSK (IMG_UINT64_C(0XF00000FFFFFFFFFF))
  1379. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0_ADDR_SHIFT (12U)
  1380. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000FFF))
  1381. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0_VALID_SHIFT (0U)
  1382. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0_VALID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  1383. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0_VALID_EN (IMG_UINT64_C(0X0000000000000001))
  1384. /*
  1385. Register VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE1
  1386. */
  1387. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE1 (0xE010U)
  1388. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE1_MASKFULL (IMG_UINT64_C(0x00000003FFFFC001))
  1389. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE1_INIT_PAGE_SHIFT (14U)
  1390. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE1_INIT_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1391. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE1_VALID_SHIFT (0U)
  1392. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE1_VALID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  1393. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE1_VALID_EN (IMG_UINT64_C(0X0000000000000001))
  1394. /*
  1395. Register VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE2
  1396. */
  1397. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE2 (0xE018U)
  1398. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE2_MASKFULL (IMG_UINT64_C(0x00000003FFFFC001))
  1399. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE2_INIT_PAGE_SHIFT (14U)
  1400. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE2_INIT_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1401. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE2_VALID_SHIFT (0U)
  1402. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE2_VALID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  1403. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE2_VALID_EN (IMG_UINT64_C(0X0000000000000001))
  1404. /*
  1405. Register VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE3
  1406. */
  1407. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE3 (0xE020U)
  1408. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE3_MASKFULL (IMG_UINT64_C(0x00000003FFFFC001))
  1409. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE3_INIT_PAGE_SHIFT (14U)
  1410. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE3_INIT_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1411. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE3_VALID_SHIFT (0U)
  1412. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE3_VALID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  1413. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE3_VALID_EN (IMG_UINT64_C(0X0000000000000001))
  1414. /*
  1415. Register VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0
  1416. */
  1417. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0 (0xE028U)
  1418. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0_MASKFULL (IMG_UINT64_C(0x0FFFFFFFFFFFF001))
  1419. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0_INIT_PAGE_SHIFT (40U)
  1420. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0_INIT_PAGE_CLRMSK (IMG_UINT64_C(0XF00000FFFFFFFFFF))
  1421. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0_ADDR_SHIFT (12U)
  1422. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000FFF))
  1423. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0_VALID_SHIFT (0U)
  1424. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0_VALID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  1425. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0_VALID_EN (IMG_UINT64_C(0X0000000000000001))
  1426. /*
  1427. Register VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE1
  1428. */
  1429. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE1 (0xE030U)
  1430. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE1_MASKFULL (IMG_UINT64_C(0x00000003FFFFC001))
  1431. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE1_INIT_PAGE_SHIFT (14U)
  1432. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE1_INIT_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1433. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE1_VALID_SHIFT (0U)
  1434. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE1_VALID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  1435. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE1_VALID_EN (IMG_UINT64_C(0X0000000000000001))
  1436. /*
  1437. Register VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE2
  1438. */
  1439. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE2 (0xE038U)
  1440. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE2_MASKFULL (IMG_UINT64_C(0x00000003FFFFC001))
  1441. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE2_INIT_PAGE_SHIFT (14U)
  1442. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE2_INIT_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1443. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE2_VALID_SHIFT (0U)
  1444. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE2_VALID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  1445. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE2_VALID_EN (IMG_UINT64_C(0X0000000000000001))
  1446. /*
  1447. Register VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE3
  1448. */
  1449. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE3 (0xE040U)
  1450. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE3_MASKFULL (IMG_UINT64_C(0x00000003FFFFC001))
  1451. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE3_INIT_PAGE_SHIFT (14U)
  1452. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE3_INIT_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1453. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE3_VALID_SHIFT (0U)
  1454. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE3_VALID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  1455. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE3_VALID_EN (IMG_UINT64_C(0X0000000000000001))
  1456. /*
  1457. Register VHA_CR_MMU_PM_CAT_BASE_ALIST0
  1458. */
  1459. #define VHA_CR_MMU_PM_CAT_BASE_ALIST0 (0xE048U)
  1460. #define VHA_CR_MMU_PM_CAT_BASE_ALIST0_MASKFULL (IMG_UINT64_C(0x0FFFFFFFFFFFF001))
  1461. #define VHA_CR_MMU_PM_CAT_BASE_ALIST0_INIT_PAGE_SHIFT (40U)
  1462. #define VHA_CR_MMU_PM_CAT_BASE_ALIST0_INIT_PAGE_CLRMSK (IMG_UINT64_C(0XF00000FFFFFFFFFF))
  1463. #define VHA_CR_MMU_PM_CAT_BASE_ALIST0_ADDR_SHIFT (12U)
  1464. #define VHA_CR_MMU_PM_CAT_BASE_ALIST0_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000FFF))
  1465. #define VHA_CR_MMU_PM_CAT_BASE_ALIST0_VALID_SHIFT (0U)
  1466. #define VHA_CR_MMU_PM_CAT_BASE_ALIST0_VALID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  1467. #define VHA_CR_MMU_PM_CAT_BASE_ALIST0_VALID_EN (IMG_UINT64_C(0X0000000000000001))
  1468. /*
  1469. Register VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0
  1470. */
  1471. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0 (0xE050U)
  1472. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0_MASKFULL (IMG_UINT64_C(0x0FFFFFFFFFFFF001))
  1473. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0_INIT_PAGE_SHIFT (40U)
  1474. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0_INIT_PAGE_CLRMSK (IMG_UINT64_C(0XF00000FFFFFFFFFF))
  1475. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0_ADDR_SHIFT (12U)
  1476. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000FFF))
  1477. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0_VALID_SHIFT (0U)
  1478. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0_VALID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  1479. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0_VALID_EN (IMG_UINT64_C(0X0000000000000001))
  1480. /*
  1481. Register VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE1
  1482. */
  1483. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE1 (0xE058U)
  1484. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE1_MASKFULL (IMG_UINT64_C(0x00000003FFFFC001))
  1485. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE1_INIT_PAGE_SHIFT (14U)
  1486. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE1_INIT_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1487. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE1_VALID_SHIFT (0U)
  1488. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE1_VALID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  1489. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE1_VALID_EN (IMG_UINT64_C(0X0000000000000001))
  1490. /*
  1491. Register VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE2
  1492. */
  1493. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE2 (0xE060U)
  1494. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE2_MASKFULL (IMG_UINT64_C(0x00000003FFFFC001))
  1495. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE2_INIT_PAGE_SHIFT (14U)
  1496. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE2_INIT_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1497. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE2_VALID_SHIFT (0U)
  1498. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE2_VALID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  1499. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE2_VALID_EN (IMG_UINT64_C(0X0000000000000001))
  1500. /*
  1501. Register VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE3
  1502. */
  1503. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE3 (0xE068U)
  1504. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE3_MASKFULL (IMG_UINT64_C(0x00000003FFFFC001))
  1505. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE3_INIT_PAGE_SHIFT (14U)
  1506. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE3_INIT_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1507. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE3_VALID_SHIFT (0U)
  1508. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE3_VALID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  1509. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE3_VALID_EN (IMG_UINT64_C(0X0000000000000001))
  1510. /*
  1511. Register VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0
  1512. */
  1513. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0 (0xE070U)
  1514. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0_MASKFULL (IMG_UINT64_C(0x0FFFFFFFFFFFF001))
  1515. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0_INIT_PAGE_SHIFT (40U)
  1516. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0_INIT_PAGE_CLRMSK (IMG_UINT64_C(0XF00000FFFFFFFFFF))
  1517. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0_ADDR_SHIFT (12U)
  1518. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000FFF))
  1519. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0_VALID_SHIFT (0U)
  1520. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0_VALID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  1521. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0_VALID_EN (IMG_UINT64_C(0X0000000000000001))
  1522. /*
  1523. Register VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE1
  1524. */
  1525. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE1 (0xE078U)
  1526. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE1_MASKFULL (IMG_UINT64_C(0x00000003FFFFC001))
  1527. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE1_INIT_PAGE_SHIFT (14U)
  1528. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE1_INIT_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1529. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE1_VALID_SHIFT (0U)
  1530. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE1_VALID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  1531. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE1_VALID_EN (IMG_UINT64_C(0X0000000000000001))
  1532. /*
  1533. Register VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE2
  1534. */
  1535. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE2 (0xE080U)
  1536. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE2_MASKFULL (IMG_UINT64_C(0x00000003FFFFC001))
  1537. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE2_INIT_PAGE_SHIFT (14U)
  1538. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE2_INIT_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1539. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE2_VALID_SHIFT (0U)
  1540. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE2_VALID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  1541. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE2_VALID_EN (IMG_UINT64_C(0X0000000000000001))
  1542. /*
  1543. Register VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE3
  1544. */
  1545. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE3 (0xE088U)
  1546. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE3_MASKFULL (IMG_UINT64_C(0x00000003FFFFC001))
  1547. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE3_INIT_PAGE_SHIFT (14U)
  1548. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE3_INIT_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1549. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE3_VALID_SHIFT (0U)
  1550. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE3_VALID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  1551. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE3_VALID_EN (IMG_UINT64_C(0X0000000000000001))
  1552. /*
  1553. Register VHA_CR_MMU_PM_CAT_BASE_ALIST1
  1554. */
  1555. #define VHA_CR_MMU_PM_CAT_BASE_ALIST1 (0xE090U)
  1556. #define VHA_CR_MMU_PM_CAT_BASE_ALIST1_MASKFULL (IMG_UINT64_C(0x0FFFFFFFFFFFF001))
  1557. #define VHA_CR_MMU_PM_CAT_BASE_ALIST1_INIT_PAGE_SHIFT (40U)
  1558. #define VHA_CR_MMU_PM_CAT_BASE_ALIST1_INIT_PAGE_CLRMSK (IMG_UINT64_C(0XF00000FFFFFFFFFF))
  1559. #define VHA_CR_MMU_PM_CAT_BASE_ALIST1_ADDR_SHIFT (12U)
  1560. #define VHA_CR_MMU_PM_CAT_BASE_ALIST1_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000FFF))
  1561. #define VHA_CR_MMU_PM_CAT_BASE_ALIST1_VALID_SHIFT (0U)
  1562. #define VHA_CR_MMU_PM_CAT_BASE_ALIST1_VALID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  1563. #define VHA_CR_MMU_PM_CAT_BASE_ALIST1_VALID_EN (IMG_UINT64_C(0X0000000000000001))
  1564. /*
  1565. Register VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0_LAST
  1566. */
  1567. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0_LAST (0xE098U)
  1568. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0_LAST_MASKFULL (IMG_UINT64_C(0x00000003FFFFC000))
  1569. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0_LAST_PAGE_SHIFT (14U)
  1570. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0_LAST_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1571. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0_LAST_PAGE_ALIGNSHIFT (14U)
  1572. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE0_LAST_PAGE_ALIGNSIZE (16384U)
  1573. /*
  1574. Register VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE1_LAST
  1575. */
  1576. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE1_LAST (0xE0A0U)
  1577. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE1_LAST_MASKFULL (IMG_UINT64_C(0x00000003FFFFC000))
  1578. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE1_LAST_PAGE_SHIFT (14U)
  1579. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE1_LAST_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1580. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE1_LAST_PAGE_ALIGNSHIFT (14U)
  1581. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE1_LAST_PAGE_ALIGNSIZE (16384U)
  1582. /*
  1583. Register VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE2_LAST
  1584. */
  1585. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE2_LAST (0xE0A8U)
  1586. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE2_LAST_MASKFULL (IMG_UINT64_C(0x00000003FFFFC000))
  1587. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE2_LAST_PAGE_SHIFT (14U)
  1588. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE2_LAST_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1589. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE2_LAST_PAGE_ALIGNSHIFT (14U)
  1590. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE2_LAST_PAGE_ALIGNSIZE (16384U)
  1591. /*
  1592. Register VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE3_LAST
  1593. */
  1594. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE3_LAST (0xE0B0U)
  1595. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE3_LAST_MASKFULL (IMG_UINT64_C(0x00000003FFFFC000))
  1596. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE3_LAST_PAGE_SHIFT (14U)
  1597. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE3_LAST_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1598. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE3_LAST_PAGE_ALIGNSHIFT (14U)
  1599. #define VHA_CR_MMU_PM_CAT_BASE_VCE0_PIPE3_LAST_PAGE_ALIGNSIZE (16384U)
  1600. /*
  1601. Register VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0_LAST
  1602. */
  1603. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0_LAST (0xE0B8U)
  1604. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0_LAST_MASKFULL (IMG_UINT64_C(0x00000003FFFFC000))
  1605. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0_LAST_PAGE_SHIFT (14U)
  1606. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0_LAST_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1607. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0_LAST_PAGE_ALIGNSHIFT (14U)
  1608. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE0_LAST_PAGE_ALIGNSIZE (16384U)
  1609. /*
  1610. Register VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE1_LAST
  1611. */
  1612. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE1_LAST (0xE0C0U)
  1613. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE1_LAST_MASKFULL (IMG_UINT64_C(0x00000003FFFFC000))
  1614. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE1_LAST_PAGE_SHIFT (14U)
  1615. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE1_LAST_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1616. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE1_LAST_PAGE_ALIGNSHIFT (14U)
  1617. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE1_LAST_PAGE_ALIGNSIZE (16384U)
  1618. /*
  1619. Register VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE2_LAST
  1620. */
  1621. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE2_LAST (0xE0C8U)
  1622. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE2_LAST_MASKFULL (IMG_UINT64_C(0x00000003FFFFC000))
  1623. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE2_LAST_PAGE_SHIFT (14U)
  1624. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE2_LAST_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1625. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE2_LAST_PAGE_ALIGNSHIFT (14U)
  1626. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE2_LAST_PAGE_ALIGNSIZE (16384U)
  1627. /*
  1628. Register VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE3_LAST
  1629. */
  1630. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE3_LAST (0xE0D0U)
  1631. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE3_LAST_MASKFULL (IMG_UINT64_C(0x00000003FFFFC000))
  1632. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE3_LAST_PAGE_SHIFT (14U)
  1633. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE3_LAST_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1634. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE3_LAST_PAGE_ALIGNSHIFT (14U)
  1635. #define VHA_CR_MMU_PM_CAT_BASE_TE0_PIPE3_LAST_PAGE_ALIGNSIZE (16384U)
  1636. /*
  1637. Register VHA_CR_MMU_PM_CAT_BASE_ALIST0_LAST
  1638. */
  1639. #define VHA_CR_MMU_PM_CAT_BASE_ALIST0_LAST (0xE0D8U)
  1640. #define VHA_CR_MMU_PM_CAT_BASE_ALIST0_LAST_MASKFULL (IMG_UINT64_C(0x00000003FFFFC000))
  1641. #define VHA_CR_MMU_PM_CAT_BASE_ALIST0_LAST_PAGE_SHIFT (14U)
  1642. #define VHA_CR_MMU_PM_CAT_BASE_ALIST0_LAST_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1643. #define VHA_CR_MMU_PM_CAT_BASE_ALIST0_LAST_PAGE_ALIGNSHIFT (14U)
  1644. #define VHA_CR_MMU_PM_CAT_BASE_ALIST0_LAST_PAGE_ALIGNSIZE (16384U)
  1645. /*
  1646. Register VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0_LAST
  1647. */
  1648. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0_LAST (0xE0E0U)
  1649. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0_LAST_MASKFULL (IMG_UINT64_C(0x00000003FFFFC000))
  1650. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0_LAST_PAGE_SHIFT (14U)
  1651. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0_LAST_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1652. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0_LAST_PAGE_ALIGNSHIFT (14U)
  1653. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE0_LAST_PAGE_ALIGNSIZE (16384U)
  1654. /*
  1655. Register VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE1_LAST
  1656. */
  1657. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE1_LAST (0xE0E8U)
  1658. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE1_LAST_MASKFULL (IMG_UINT64_C(0x00000003FFFFC000))
  1659. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE1_LAST_PAGE_SHIFT (14U)
  1660. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE1_LAST_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1661. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE1_LAST_PAGE_ALIGNSHIFT (14U)
  1662. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE1_LAST_PAGE_ALIGNSIZE (16384U)
  1663. /*
  1664. Register VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE2_LAST
  1665. */
  1666. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE2_LAST (0xE0F0U)
  1667. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE2_LAST_MASKFULL (IMG_UINT64_C(0x00000003FFFFC000))
  1668. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE2_LAST_PAGE_SHIFT (14U)
  1669. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE2_LAST_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1670. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE2_LAST_PAGE_ALIGNSHIFT (14U)
  1671. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE2_LAST_PAGE_ALIGNSIZE (16384U)
  1672. /*
  1673. Register VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE3_LAST
  1674. */
  1675. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE3_LAST (0xE0F8U)
  1676. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE3_LAST_MASKFULL (IMG_UINT64_C(0x00000003FFFFC000))
  1677. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE3_LAST_PAGE_SHIFT (14U)
  1678. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE3_LAST_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1679. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE3_LAST_PAGE_ALIGNSHIFT (14U)
  1680. #define VHA_CR_MMU_PM_CAT_BASE_VCE1_PIPE3_LAST_PAGE_ALIGNSIZE (16384U)
  1681. /*
  1682. Register VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0_LAST
  1683. */
  1684. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0_LAST (0xE100U)
  1685. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0_LAST_MASKFULL (IMG_UINT64_C(0x00000003FFFFC000))
  1686. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0_LAST_PAGE_SHIFT (14U)
  1687. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0_LAST_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1688. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0_LAST_PAGE_ALIGNSHIFT (14U)
  1689. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE0_LAST_PAGE_ALIGNSIZE (16384U)
  1690. /*
  1691. Register VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE1_LAST
  1692. */
  1693. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE1_LAST (0xE108U)
  1694. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE1_LAST_MASKFULL (IMG_UINT64_C(0x00000003FFFFC000))
  1695. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE1_LAST_PAGE_SHIFT (14U)
  1696. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE1_LAST_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1697. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE1_LAST_PAGE_ALIGNSHIFT (14U)
  1698. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE1_LAST_PAGE_ALIGNSIZE (16384U)
  1699. /*
  1700. Register VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE2_LAST
  1701. */
  1702. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE2_LAST (0xE110U)
  1703. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE2_LAST_MASKFULL (IMG_UINT64_C(0x00000003FFFFC000))
  1704. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE2_LAST_PAGE_SHIFT (14U)
  1705. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE2_LAST_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1706. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE2_LAST_PAGE_ALIGNSHIFT (14U)
  1707. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE2_LAST_PAGE_ALIGNSIZE (16384U)
  1708. /*
  1709. Register VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE3_LAST
  1710. */
  1711. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE3_LAST (0xE118U)
  1712. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE3_LAST_MASKFULL (IMG_UINT64_C(0x00000003FFFFC000))
  1713. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE3_LAST_PAGE_SHIFT (14U)
  1714. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE3_LAST_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1715. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE3_LAST_PAGE_ALIGNSHIFT (14U)
  1716. #define VHA_CR_MMU_PM_CAT_BASE_TE1_PIPE3_LAST_PAGE_ALIGNSIZE (16384U)
  1717. /*
  1718. Register VHA_CR_MMU_PM_CAT_BASE_ALIST1_LAST
  1719. */
  1720. #define VHA_CR_MMU_PM_CAT_BASE_ALIST1_LAST (0xE120U)
  1721. #define VHA_CR_MMU_PM_CAT_BASE_ALIST1_LAST_MASKFULL (IMG_UINT64_C(0x00000003FFFFC000))
  1722. #define VHA_CR_MMU_PM_CAT_BASE_ALIST1_LAST_PAGE_SHIFT (14U)
  1723. #define VHA_CR_MMU_PM_CAT_BASE_ALIST1_LAST_PAGE_CLRMSK (IMG_UINT64_C(0XFFFFFFFC00003FFF))
  1724. #define VHA_CR_MMU_PM_CAT_BASE_ALIST1_LAST_PAGE_ALIGNSHIFT (14U)
  1725. #define VHA_CR_MMU_PM_CAT_BASE_ALIST1_LAST_PAGE_ALIGNSIZE (16384U)
  1726. /*
  1727. Register VHA_CR_MMU_FAULT_STATUS_META
  1728. */
  1729. #define VHA_CR_MMU_FAULT_STATUS_META (0xE160U)
  1730. #define VHA_CR_MMU_FAULT_STATUS_META_MASKFULL (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
  1731. #define VHA_CR_MMU_FAULT_STATUS_META_LEVEL_SHIFT (62U)
  1732. #define VHA_CR_MMU_FAULT_STATUS_META_LEVEL_CLRMSK (IMG_UINT64_C(0X3FFFFFFFFFFFFFFF))
  1733. #define VHA_CR_MMU_FAULT_STATUS_META_REQ_ID_SHIFT (56U)
  1734. #define VHA_CR_MMU_FAULT_STATUS_META_REQ_ID_CLRMSK (IMG_UINT64_C(0XC0FFFFFFFFFFFFFF))
  1735. #define VHA_CR_MMU_FAULT_STATUS_META_CONTEXT_SHIFT (48U)
  1736. #define VHA_CR_MMU_FAULT_STATUS_META_CONTEXT_CLRMSK (IMG_UINT64_C(0XFF00FFFFFFFFFFFF))
  1737. #define VHA_CR_MMU_FAULT_STATUS_META_ADDRESS_SHIFT (4U)
  1738. #define VHA_CR_MMU_FAULT_STATUS_META_ADDRESS_CLRMSK (IMG_UINT64_C(0XFFFF00000000000F))
  1739. #define VHA_CR_MMU_FAULT_STATUS_META_RNW_SHIFT (3U)
  1740. #define VHA_CR_MMU_FAULT_STATUS_META_RNW_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF7))
  1741. #define VHA_CR_MMU_FAULT_STATUS_META_RNW_EN (IMG_UINT64_C(0X0000000000000008))
  1742. #define VHA_CR_MMU_FAULT_STATUS_META_TYPE_SHIFT (1U)
  1743. #define VHA_CR_MMU_FAULT_STATUS_META_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF9))
  1744. #define VHA_CR_MMU_FAULT_STATUS_META_FAULT_SHIFT (0U)
  1745. #define VHA_CR_MMU_FAULT_STATUS_META_FAULT_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  1746. #define VHA_CR_MMU_FAULT_STATUS_META_FAULT_EN (IMG_UINT64_C(0X0000000000000001))
  1747. /*
  1748. Register VHA_CR_MMU_FAULT_STATUS2_META
  1749. */
  1750. #define VHA_CR_MMU_FAULT_STATUS2_META (0xE198U)
  1751. #define VHA_CR_MMU_FAULT_STATUS2_META_MASKFULL (IMG_UINT64_C(0x0000000000003FFF))
  1752. #define VHA_CR_MMU_FAULT_STATUS2_META_WRITEBACK_SHIFT (13U)
  1753. #define VHA_CR_MMU_FAULT_STATUS2_META_WRITEBACK_CLRMSK (0XFFFFDFFFU)
  1754. #define VHA_CR_MMU_FAULT_STATUS2_META_WRITEBACK_EN (0X00002000U)
  1755. #define VHA_CR_MMU_FAULT_STATUS2_META_CLEANUNIQUE_SHIFT (12U)
  1756. #define VHA_CR_MMU_FAULT_STATUS2_META_CLEANUNIQUE_CLRMSK (0XFFFFEFFFU)
  1757. #define VHA_CR_MMU_FAULT_STATUS2_META_CLEANUNIQUE_EN (0X00001000U)
  1758. #define VHA_CR_MMU_FAULT_STATUS2_META_BANK_SHIFT (8U)
  1759. #define VHA_CR_MMU_FAULT_STATUS2_META_BANK_CLRMSK (0XFFFFF0FFU)
  1760. #define VHA_CR_MMU_FAULT_STATUS2_META_TLB_ENTRY_SHIFT (0U)
  1761. #define VHA_CR_MMU_FAULT_STATUS2_META_TLB_ENTRY_CLRMSK (0XFFFFFF00U)
  1762. /*
  1763. Register VHA_CR_MMU_FAULT_STATUS_PM
  1764. */
  1765. #define VHA_CR_MMU_FAULT_STATUS_PM (0xE130U)
  1766. #define VHA_CR_MMU_FAULT_STATUS_PM_MASKFULL (IMG_UINT64_C(0x0000000007FFFFFF))
  1767. #define VHA_CR_MMU_FAULT_STATUS_PM_DM_SHIFT (24U)
  1768. #define VHA_CR_MMU_FAULT_STATUS_PM_DM_CLRMSK (IMG_UINT64_C(0XFFFFFFFFF8FFFFFF))
  1769. #define VHA_CR_MMU_FAULT_STATUS_PM_RNW_SHIFT (23U)
  1770. #define VHA_CR_MMU_FAULT_STATUS_PM_RNW_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF7FFFFF))
  1771. #define VHA_CR_MMU_FAULT_STATUS_PM_RNW_EN (IMG_UINT64_C(0X0000000000800000))
  1772. #define VHA_CR_MMU_FAULT_STATUS_PM_ADDRESS_SHIFT (3U)
  1773. #define VHA_CR_MMU_FAULT_STATUS_PM_ADDRESS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF800007))
  1774. #define VHA_CR_MMU_FAULT_STATUS_PM_LEVEL_SHIFT (1U)
  1775. #define VHA_CR_MMU_FAULT_STATUS_PM_LEVEL_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF9))
  1776. #define VHA_CR_MMU_FAULT_STATUS_PM_FAULT_SHIFT (0U)
  1777. #define VHA_CR_MMU_FAULT_STATUS_PM_FAULT_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  1778. #define VHA_CR_MMU_FAULT_STATUS_PM_FAULT_EN (IMG_UINT64_C(0X0000000000000001))
  1779. /*
  1780. Register VHA_CR_MMU_ABORT_PM_CTRL
  1781. */
  1782. #define VHA_CR_MMU_ABORT_PM_CTRL (0xE188U)
  1783. #define VHA_CR_MMU_ABORT_PM_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  1784. #define VHA_CR_MMU_ABORT_PM_CTRL_ENABLE_SHIFT (0U)
  1785. #define VHA_CR_MMU_ABORT_PM_CTRL_ENABLE_CLRMSK (0XFFFFFFFEU)
  1786. #define VHA_CR_MMU_ABORT_PM_CTRL_ENABLE_EN (0X00000001U)
  1787. /*
  1788. Register VHA_CR_MMU_ABORT_PM_STATUS
  1789. */
  1790. #define VHA_CR_MMU_ABORT_PM_STATUS (0xE190U)
  1791. #define VHA_CR_MMU_ABORT_PM_STATUS_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  1792. #define VHA_CR_MMU_ABORT_PM_STATUS_ABORT_SHIFT (0U)
  1793. #define VHA_CR_MMU_ABORT_PM_STATUS_ABORT_CLRMSK (0XFFFFFFFEU)
  1794. #define VHA_CR_MMU_ABORT_PM_STATUS_ABORT_EN (0X00000001U)
  1795. /*
  1796. Register VHA_CR_MMU_HOST_IRQ_ENABLE
  1797. */
  1798. #define VHA_CR_MMU_HOST_IRQ_ENABLE (0xE1A0U)
  1799. #define VHA_CR_MMU_HOST_IRQ_ENABLE_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  1800. #define VHA_CR_MMU_HOST_IRQ_ENABLE_FAULT_PM_SHIFT (0U)
  1801. #define VHA_CR_MMU_HOST_IRQ_ENABLE_FAULT_PM_CLRMSK (0XFFFFFFFEU)
  1802. #define VHA_CR_MMU_HOST_IRQ_ENABLE_FAULT_PM_EN (0X00000001U)
  1803. /*
  1804. Register VHA_CR_MMU_PAGE_SIZE_RANGE_ONE
  1805. */
  1806. #define VHA_CR_MMU_PAGE_SIZE_RANGE_ONE (0xE350U)
  1807. #define VHA_CR_MMU_PAGE_SIZE_RANGE_ONE_MASKFULL (IMG_UINT64_C(0x000001FFFFFFFFFF))
  1808. #define VHA_CR_MMU_PAGE_SIZE_RANGE_ONE_PAGE_SIZE_SHIFT (38U)
  1809. #define VHA_CR_MMU_PAGE_SIZE_RANGE_ONE_PAGE_SIZE_CLRMSK (IMG_UINT64_C(0XFFFFFE3FFFFFFFFF))
  1810. #define VHA_CR_MMU_PAGE_SIZE_RANGE_ONE_END_ADDR_SHIFT (19U)
  1811. #define VHA_CR_MMU_PAGE_SIZE_RANGE_ONE_END_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFFC00007FFFF))
  1812. #define VHA_CR_MMU_PAGE_SIZE_RANGE_ONE_END_ADDR_ALIGNSHIFT (21U)
  1813. #define VHA_CR_MMU_PAGE_SIZE_RANGE_ONE_END_ADDR_ALIGNSIZE (2097152U)
  1814. #define VHA_CR_MMU_PAGE_SIZE_RANGE_ONE_BASE_ADDR_SHIFT (0U)
  1815. #define VHA_CR_MMU_PAGE_SIZE_RANGE_ONE_BASE_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF80000))
  1816. #define VHA_CR_MMU_PAGE_SIZE_RANGE_ONE_BASE_ADDR_ALIGNSHIFT (21U)
  1817. #define VHA_CR_MMU_PAGE_SIZE_RANGE_ONE_BASE_ADDR_ALIGNSIZE (2097152U)
  1818. /*
  1819. Register VHA_CR_MMU_PAGE_SIZE_RANGE_TWO
  1820. */
  1821. #define VHA_CR_MMU_PAGE_SIZE_RANGE_TWO (0xE358U)
  1822. #define VHA_CR_MMU_PAGE_SIZE_RANGE_TWO_MASKFULL (IMG_UINT64_C(0x000001FFFFFFFFFF))
  1823. #define VHA_CR_MMU_PAGE_SIZE_RANGE_TWO_PAGE_SIZE_SHIFT (38U)
  1824. #define VHA_CR_MMU_PAGE_SIZE_RANGE_TWO_PAGE_SIZE_CLRMSK (IMG_UINT64_C(0XFFFFFE3FFFFFFFFF))
  1825. #define VHA_CR_MMU_PAGE_SIZE_RANGE_TWO_END_ADDR_SHIFT (19U)
  1826. #define VHA_CR_MMU_PAGE_SIZE_RANGE_TWO_END_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFFC00007FFFF))
  1827. #define VHA_CR_MMU_PAGE_SIZE_RANGE_TWO_END_ADDR_ALIGNSHIFT (21U)
  1828. #define VHA_CR_MMU_PAGE_SIZE_RANGE_TWO_END_ADDR_ALIGNSIZE (2097152U)
  1829. #define VHA_CR_MMU_PAGE_SIZE_RANGE_TWO_BASE_ADDR_SHIFT (0U)
  1830. #define VHA_CR_MMU_PAGE_SIZE_RANGE_TWO_BASE_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF80000))
  1831. #define VHA_CR_MMU_PAGE_SIZE_RANGE_TWO_BASE_ADDR_ALIGNSHIFT (21U)
  1832. #define VHA_CR_MMU_PAGE_SIZE_RANGE_TWO_BASE_ADDR_ALIGNSIZE (2097152U)
  1833. /*
  1834. Register VHA_CR_MMU_PAGE_SIZE_RANGE_THREE
  1835. */
  1836. #define VHA_CR_MMU_PAGE_SIZE_RANGE_THREE (0xE360U)
  1837. #define VHA_CR_MMU_PAGE_SIZE_RANGE_THREE_MASKFULL (IMG_UINT64_C(0x000001FFFFFFFFFF))
  1838. #define VHA_CR_MMU_PAGE_SIZE_RANGE_THREE_PAGE_SIZE_SHIFT (38U)
  1839. #define VHA_CR_MMU_PAGE_SIZE_RANGE_THREE_PAGE_SIZE_CLRMSK (IMG_UINT64_C(0XFFFFFE3FFFFFFFFF))
  1840. #define VHA_CR_MMU_PAGE_SIZE_RANGE_THREE_END_ADDR_SHIFT (19U)
  1841. #define VHA_CR_MMU_PAGE_SIZE_RANGE_THREE_END_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFFC00007FFFF))
  1842. #define VHA_CR_MMU_PAGE_SIZE_RANGE_THREE_END_ADDR_ALIGNSHIFT (21U)
  1843. #define VHA_CR_MMU_PAGE_SIZE_RANGE_THREE_END_ADDR_ALIGNSIZE (2097152U)
  1844. #define VHA_CR_MMU_PAGE_SIZE_RANGE_THREE_BASE_ADDR_SHIFT (0U)
  1845. #define VHA_CR_MMU_PAGE_SIZE_RANGE_THREE_BASE_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF80000))
  1846. #define VHA_CR_MMU_PAGE_SIZE_RANGE_THREE_BASE_ADDR_ALIGNSHIFT (21U)
  1847. #define VHA_CR_MMU_PAGE_SIZE_RANGE_THREE_BASE_ADDR_ALIGNSIZE (2097152U)
  1848. /*
  1849. Register VHA_CR_MMU_PAGE_SIZE_RANGE_FOUR
  1850. */
  1851. #define VHA_CR_MMU_PAGE_SIZE_RANGE_FOUR (0xE368U)
  1852. #define VHA_CR_MMU_PAGE_SIZE_RANGE_FOUR_MASKFULL (IMG_UINT64_C(0x000001FFFFFFFFFF))
  1853. #define VHA_CR_MMU_PAGE_SIZE_RANGE_FOUR_PAGE_SIZE_SHIFT (38U)
  1854. #define VHA_CR_MMU_PAGE_SIZE_RANGE_FOUR_PAGE_SIZE_CLRMSK (IMG_UINT64_C(0XFFFFFE3FFFFFFFFF))
  1855. #define VHA_CR_MMU_PAGE_SIZE_RANGE_FOUR_END_ADDR_SHIFT (19U)
  1856. #define VHA_CR_MMU_PAGE_SIZE_RANGE_FOUR_END_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFFC00007FFFF))
  1857. #define VHA_CR_MMU_PAGE_SIZE_RANGE_FOUR_END_ADDR_ALIGNSHIFT (21U)
  1858. #define VHA_CR_MMU_PAGE_SIZE_RANGE_FOUR_END_ADDR_ALIGNSIZE (2097152U)
  1859. #define VHA_CR_MMU_PAGE_SIZE_RANGE_FOUR_BASE_ADDR_SHIFT (0U)
  1860. #define VHA_CR_MMU_PAGE_SIZE_RANGE_FOUR_BASE_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF80000))
  1861. #define VHA_CR_MMU_PAGE_SIZE_RANGE_FOUR_BASE_ADDR_ALIGNSHIFT (21U)
  1862. #define VHA_CR_MMU_PAGE_SIZE_RANGE_FOUR_BASE_ADDR_ALIGNSIZE (2097152U)
  1863. #define VHA_CR_SLC_CTRL_ENUM_HASH_MODE_MASK (0x00000003U)
  1864. /*
  1865. Reserved value */
  1866. #define VHA_CR_SLC_CTRL_ENUM_HASH_MODE_RESERVED (0x00000000U)
  1867. /*
  1868. Addresses interleaved between Cache Bank using a combined Set & Bank hash of the upper address bits */
  1869. #define VHA_CR_SLC_CTRL_ENUM_HASH_MODE_PVR_V3_HASHING (0x00000001U)
  1870. /*
  1871. Addresses are interleaved between Cache Banks on a Cacheline boundary */
  1872. #define VHA_CR_SLC_CTRL_ENUM_HASH_MODE_LINEAR (0x00000002U)
  1873. /*
  1874. Addresses interleaved between Cache Banks using an XOR hash of the address bits below the 4KB page granularity */
  1875. #define VHA_CR_SLC_CTRL_ENUM_HASH_MODE_IN_PAGE_HASH (0x00000003U)
  1876. /*
  1877. Register VHA_CR_SLC_CTRL
  1878. */
  1879. #define VHA_CR_SLC_CTRL (0xE200U)
  1880. #define VHA_CR_SLC_CTRL_MASKFULL (IMG_UINT64_C(0x000000000001FFF3))
  1881. #define VHA_CR_SLC_CTRL_ISCHED_CREDIT_THRESHOLD_SHIFT (13U)
  1882. #define VHA_CR_SLC_CTRL_ISCHED_CREDIT_THRESHOLD_CLRMSK (0XFFFE1FFFU)
  1883. #define VHA_CR_SLC_CTRL_CFI_TIMEOUT_ENABLE_SHIFT (12U)
  1884. #define VHA_CR_SLC_CTRL_CFI_TIMEOUT_ENABLE_CLRMSK (0XFFFFEFFFU)
  1885. #define VHA_CR_SLC_CTRL_CFI_TIMEOUT_ENABLE_EN (0X00001000U)
  1886. #define VHA_CR_SLC_CTRL_CFI_TIMEOUT_CYCLES_SHIFT (8U)
  1887. #define VHA_CR_SLC_CTRL_CFI_TIMEOUT_CYCLES_CLRMSK (0XFFFFF0FFU)
  1888. #define VHA_CR_SLC_CTRL_PERSISTENCE_DECAY_ENABLE_SHIFT (7U)
  1889. #define VHA_CR_SLC_CTRL_PERSISTENCE_DECAY_ENABLE_CLRMSK (0XFFFFFF7FU)
  1890. #define VHA_CR_SLC_CTRL_PERSISTENCE_DECAY_ENABLE_EN (0X00000080U)
  1891. #define VHA_CR_SLC_CTRL_MAX_FENCES_SHIFT (4U)
  1892. #define VHA_CR_SLC_CTRL_MAX_FENCES_CLRMSK (0XFFFFFF8FU)
  1893. #define VHA_CR_SLC_CTRL_HASH_MODE_SHIFT (0U)
  1894. #define VHA_CR_SLC_CTRL_HASH_MODE_CLRMSK (0XFFFFFFFCU)
  1895. #define VHA_CR_SLC_CTRL_HASH_MODE_RESERVED (00000000U)
  1896. #define VHA_CR_SLC_CTRL_HASH_MODE_PVR_V3_HASHING (0X00000001U)
  1897. #define VHA_CR_SLC_CTRL_HASH_MODE_LINEAR (0X00000002U)
  1898. #define VHA_CR_SLC_CTRL_HASH_MODE_IN_PAGE_HASH (0X00000003U)
  1899. /*
  1900. Register VHA_CR_SLC_FAULT_STOP_CTRL
  1901. */
  1902. #define VHA_CR_SLC_FAULT_STOP_CTRL (0xE248U)
  1903. #define VHA_CR_SLC_FAULT_STOP_CTRL_MASKFULL (IMG_UINT64_C(0x000000000003FFFF))
  1904. #define VHA_CR_SLC_FAULT_STOP_CTRL_ALL_SHIFT (17U)
  1905. #define VHA_CR_SLC_FAULT_STOP_CTRL_ALL_CLRMSK (0XFFFDFFFFU)
  1906. #define VHA_CR_SLC_FAULT_STOP_CTRL_ALL_EN (0X00020000U)
  1907. #define VHA_CR_SLC_FAULT_STOP_CTRL_ENABLE_SHIFT (0U)
  1908. #define VHA_CR_SLC_FAULT_STOP_CTRL_ENABLE_CLRMSK (0XFFFE0000U)
  1909. /*
  1910. Register VHA_CR_MMU_OSID_CTXT_MAPPING0
  1911. */
  1912. #define VHA_CR_MMU_OSID_CTXT_MAPPING0 (0xE280U)
  1913. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_MASKFULL (IMG_UINT64_C(0x7777777777777777))
  1914. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_15_SHIFT (60U)
  1915. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_15_CLRMSK (IMG_UINT64_C(0X8FFFFFFFFFFFFFFF))
  1916. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_14_SHIFT (56U)
  1917. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_14_CLRMSK (IMG_UINT64_C(0XF8FFFFFFFFFFFFFF))
  1918. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_13_SHIFT (52U)
  1919. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_13_CLRMSK (IMG_UINT64_C(0XFF8FFFFFFFFFFFFF))
  1920. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_12_SHIFT (48U)
  1921. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_12_CLRMSK (IMG_UINT64_C(0XFFF8FFFFFFFFFFFF))
  1922. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_11_SHIFT (44U)
  1923. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_11_CLRMSK (IMG_UINT64_C(0XFFFF8FFFFFFFFFFF))
  1924. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_10_SHIFT (40U)
  1925. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_10_CLRMSK (IMG_UINT64_C(0XFFFFF8FFFFFFFFFF))
  1926. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_9_SHIFT (36U)
  1927. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_9_CLRMSK (IMG_UINT64_C(0XFFFFFF8FFFFFFFFF))
  1928. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_8_SHIFT (32U)
  1929. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_8_CLRMSK (IMG_UINT64_C(0XFFFFFFF8FFFFFFFF))
  1930. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_7_SHIFT (28U)
  1931. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_7_CLRMSK (IMG_UINT64_C(0XFFFFFFFF8FFFFFFF))
  1932. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_6_SHIFT (24U)
  1933. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_6_CLRMSK (IMG_UINT64_C(0XFFFFFFFFF8FFFFFF))
  1934. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_5_SHIFT (20U)
  1935. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_5_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF8FFFFF))
  1936. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_4_SHIFT (16U)
  1937. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_4_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF8FFFF))
  1938. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_3_SHIFT (12U)
  1939. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_3_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF8FFF))
  1940. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_2_SHIFT (8U)
  1941. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_2_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF8FF))
  1942. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_1_SHIFT (4U)
  1943. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFF8F))
  1944. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_0_SHIFT (0U)
  1945. #define VHA_CR_MMU_OSID_CTXT_MAPPING0_OSID_0_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF8))
  1946. /*
  1947. Register VHA_CR_MMU_OSID_CTXT_MAPPING1
  1948. */
  1949. #define VHA_CR_MMU_OSID_CTXT_MAPPING1 (0xE288U)
  1950. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_MASKFULL (IMG_UINT64_C(0x7777777777777777))
  1951. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_31_SHIFT (60U)
  1952. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_31_CLRMSK (IMG_UINT64_C(0X8FFFFFFFFFFFFFFF))
  1953. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_30_SHIFT (56U)
  1954. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_30_CLRMSK (IMG_UINT64_C(0XF8FFFFFFFFFFFFFF))
  1955. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_29_SHIFT (52U)
  1956. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_29_CLRMSK (IMG_UINT64_C(0XFF8FFFFFFFFFFFFF))
  1957. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_28_SHIFT (48U)
  1958. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_28_CLRMSK (IMG_UINT64_C(0XFFF8FFFFFFFFFFFF))
  1959. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_27_SHIFT (44U)
  1960. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_27_CLRMSK (IMG_UINT64_C(0XFFFF8FFFFFFFFFFF))
  1961. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_26_SHIFT (40U)
  1962. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_26_CLRMSK (IMG_UINT64_C(0XFFFFF8FFFFFFFFFF))
  1963. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_25_SHIFT (36U)
  1964. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_25_CLRMSK (IMG_UINT64_C(0XFFFFFF8FFFFFFFFF))
  1965. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_24_SHIFT (32U)
  1966. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_24_CLRMSK (IMG_UINT64_C(0XFFFFFFF8FFFFFFFF))
  1967. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_23_SHIFT (28U)
  1968. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_23_CLRMSK (IMG_UINT64_C(0XFFFFFFFF8FFFFFFF))
  1969. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_22_SHIFT (24U)
  1970. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_22_CLRMSK (IMG_UINT64_C(0XFFFFFFFFF8FFFFFF))
  1971. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_21_SHIFT (20U)
  1972. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_21_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF8FFFFF))
  1973. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_20_SHIFT (16U)
  1974. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_20_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF8FFFF))
  1975. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_19_SHIFT (12U)
  1976. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_19_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF8FFF))
  1977. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_18_SHIFT (8U)
  1978. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_18_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF8FF))
  1979. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_17_SHIFT (4U)
  1980. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_17_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFF8F))
  1981. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_16_SHIFT (0U)
  1982. #define VHA_CR_MMU_OSID_CTXT_MAPPING1_OSID_16_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF8))
  1983. /*
  1984. Register VHA_CR_ACE_QOS_CTRL
  1985. */
  1986. #define VHA_CR_ACE_QOS_CTRL (0xE310U)
  1987. #define VHA_CR_ACE_QOS_CTRL_MASKFULL (IMG_UINT64_C(0x000000000000FFFF))
  1988. #define VHA_CR_ACE_QOS_CTRL_CRITICAL_SHIFT (12U)
  1989. #define VHA_CR_ACE_QOS_CTRL_CRITICAL_CLRMSK (0XFFFF0FFFU)
  1990. #define VHA_CR_ACE_QOS_CTRL_HIGH_SHIFT (8U)
  1991. #define VHA_CR_ACE_QOS_CTRL_HIGH_CLRMSK (0XFFFFF0FFU)
  1992. #define VHA_CR_ACE_QOS_CTRL_MEDIUM_SHIFT (4U)
  1993. #define VHA_CR_ACE_QOS_CTRL_MEDIUM_CLRMSK (0XFFFFFF0FU)
  1994. #define VHA_CR_ACE_QOS_CTRL_LOW_SHIFT (0U)
  1995. #define VHA_CR_ACE_QOS_CTRL_LOW_CLRMSK (0XFFFFFFF0U)
  1996. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_ENUM_PRIORITIES_MASK (0x00000003U)
  1997. /*
  1998. Low */
  1999. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_ENUM_PRIORITIES_LOW (0x00000000U)
  2000. /*
  2001. Medium */
  2002. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_ENUM_PRIORITIES_MEDIUM (0x00000001U)
  2003. /*
  2004. High */
  2005. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_ENUM_PRIORITIES_HIGH (0x00000002U)
  2006. /*
  2007. Critical */
  2008. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_ENUM_PRIORITIES_CRITICAL (0x00000003U)
  2009. /*
  2010. Register VHA_CR_ACE_PRIORITY_MAPPING_CTRL
  2011. */
  2012. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL (0xE318U)
  2013. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MASKFULL (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
  2014. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMU_SHIFT (62U)
  2015. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMU_CLRMSK (IMG_UINT64_C(0X3FFFFFFFFFFFFFFF))
  2016. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMU_LOW (IMG_UINT64_C(0000000000000000))
  2017. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMU_MEDIUM (IMG_UINT64_C(0x4000000000000000))
  2018. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMU_HIGH (IMG_UINT64_C(0x8000000000000000))
  2019. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMU_CRITICAL (IMG_UINT64_C(0xc000000000000000))
  2020. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_RESERVED_SHIFT (32U)
  2021. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_RESERVED_CLRMSK (IMG_UINT64_C(0XC0000000FFFFFFFF))
  2022. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TRS_B_SHIFT (30U)
  2023. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TRS_B_CLRMSK (IMG_UINT64_C(0XFFFFFFFF3FFFFFFF))
  2024. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TRS_B_LOW (IMG_UINT64_C(0000000000000000))
  2025. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TRS_B_MEDIUM (IMG_UINT64_C(0x0000000040000000))
  2026. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TRS_B_HIGH (IMG_UINT64_C(0x0000000080000000))
  2027. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TRS_B_CRITICAL (IMG_UINT64_C(0x00000000c0000000))
  2028. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TRS_A_SHIFT (28U)
  2029. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TRS_A_CLRMSK (IMG_UINT64_C(0XFFFFFFFFCFFFFFFF))
  2030. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TRS_A_LOW (IMG_UINT64_C(0000000000000000))
  2031. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TRS_A_MEDIUM (IMG_UINT64_C(0x0000000010000000))
  2032. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TRS_A_HIGH (IMG_UINT64_C(0x0000000020000000))
  2033. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_TRS_A_CRITICAL (IMG_UINT64_C(0x0000000030000000))
  2034. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_POOL_SHIFT (26U)
  2035. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_POOL_CLRMSK (IMG_UINT64_C(0XFFFFFFFFF3FFFFFF))
  2036. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_POOL_LOW (IMG_UINT64_C(0000000000000000))
  2037. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_POOL_MEDIUM (IMG_UINT64_C(0x0000000004000000))
  2038. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_POOL_HIGH (IMG_UINT64_C(0x0000000008000000))
  2039. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_POOL_CRITICAL (IMG_UINT64_C(0x000000000c000000))
  2040. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMM_WR_SHIFT (24U)
  2041. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMM_WR_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFCFFFFFF))
  2042. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMM_WR_LOW (IMG_UINT64_C(0000000000000000))
  2043. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMM_WR_MEDIUM (IMG_UINT64_C(0x0000000001000000))
  2044. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMM_WR_HIGH (IMG_UINT64_C(0x0000000002000000))
  2045. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMM_WR_CRITICAL (IMG_UINT64_C(0x0000000003000000))
  2046. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMM_RD_SHIFT (22U)
  2047. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMM_RD_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF3FFFFF))
  2048. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMM_RD_LOW (IMG_UINT64_C(0000000000000000))
  2049. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMM_RD_MEDIUM (IMG_UINT64_C(0x0000000000400000))
  2050. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMM_RD_HIGH (IMG_UINT64_C(0x0000000000800000))
  2051. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_MMM_RD_CRITICAL (IMG_UINT64_C(0x0000000000c00000))
  2052. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_EWO_PSF_SHIFT (20U)
  2053. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_EWO_PSF_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFCFFFFF))
  2054. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_EWO_PSF_LOW (IMG_UINT64_C(0000000000000000))
  2055. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_EWO_PSF_MEDIUM (IMG_UINT64_C(0x0000000000100000))
  2056. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_EWO_PSF_HIGH (IMG_UINT64_C(0x0000000000200000))
  2057. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_EWO_PSF_CRITICAL (IMG_UINT64_C(0x0000000000300000))
  2058. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_EWO_SHIFT (18U)
  2059. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_EWO_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF3FFFF))
  2060. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_EWO_LOW (IMG_UINT64_C(0000000000000000))
  2061. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_EWO_MEDIUM (IMG_UINT64_C(0x0000000000040000))
  2062. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_EWO_HIGH (IMG_UINT64_C(0x0000000000080000))
  2063. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_EWO_CRITICAL (IMG_UINT64_C(0x00000000000c0000))
  2064. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_OUTPACK_SHIFT (16U)
  2065. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_OUTPACK_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFCFFFF))
  2066. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_OUTPACK_LOW (IMG_UINT64_C(0000000000000000))
  2067. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_OUTPACK_MEDIUM (IMG_UINT64_C(0x0000000000010000))
  2068. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_OUTPACK_HIGH (IMG_UINT64_C(0x0000000000020000))
  2069. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_OUTPACK_CRITICAL (IMG_UINT64_C(0x0000000000030000))
  2070. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_ABUF_SHIFT (14U)
  2071. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_ABUF_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF3FFF))
  2072. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_ABUF_LOW (IMG_UINT64_C(0000000000000000))
  2073. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_ABUF_MEDIUM (IMG_UINT64_C(0x0000000000004000))
  2074. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_ABUF_HIGH (IMG_UINT64_C(0x0000000000008000))
  2075. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_ABUF_CRITICAL (IMG_UINT64_C(0x000000000000c000))
  2076. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CBUF_SHIFT (12U)
  2077. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CBUF_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFCFFF))
  2078. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CBUF_LOW (IMG_UINT64_C(0000000000000000))
  2079. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CBUF_MEDIUM (IMG_UINT64_C(0x0000000000001000))
  2080. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CBUF_HIGH (IMG_UINT64_C(0x0000000000002000))
  2081. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CBUF_CRITICAL (IMG_UINT64_C(0x0000000000003000))
  2082. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_IBUF_0_SHIFT (10U)
  2083. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_IBUF_0_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF3FF))
  2084. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_IBUF_0_LOW (IMG_UINT64_C(0000000000000000))
  2085. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_IBUF_0_MEDIUM (IMG_UINT64_C(0x0000000000000400))
  2086. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_IBUF_0_HIGH (IMG_UINT64_C(0x0000000000000800))
  2087. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_IBUF_0_CRITICAL (IMG_UINT64_C(0x0000000000000c00))
  2088. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_4_SHIFT (8U)
  2089. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_4_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFCFF))
  2090. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_4_LOW (IMG_UINT64_C(0000000000000000))
  2091. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_4_MEDIUM (IMG_UINT64_C(0x0000000000000100))
  2092. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_4_HIGH (IMG_UINT64_C(0x0000000000000200))
  2093. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_4_CRITICAL (IMG_UINT64_C(0x0000000000000300))
  2094. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_3_SHIFT (6U)
  2095. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_3_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFF3F))
  2096. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_3_LOW (IMG_UINT64_C(0000000000000000))
  2097. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_3_MEDIUM (IMG_UINT64_C(0x0000000000000040))
  2098. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_3_HIGH (IMG_UINT64_C(0x0000000000000080))
  2099. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_3_CRITICAL (IMG_UINT64_C(0x00000000000000c0))
  2100. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_2_SHIFT (4U)
  2101. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_2_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFCF))
  2102. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_2_LOW (IMG_UINT64_C(0000000000000000))
  2103. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_2_MEDIUM (IMG_UINT64_C(0x0000000000000010))
  2104. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_2_HIGH (IMG_UINT64_C(0x0000000000000020))
  2105. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_2_CRITICAL (IMG_UINT64_C(0x0000000000000030))
  2106. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_1_SHIFT (2U)
  2107. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF3))
  2108. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_1_LOW (IMG_UINT64_C(0000000000000000))
  2109. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_1_MEDIUM (IMG_UINT64_C(0x0000000000000004))
  2110. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_1_HIGH (IMG_UINT64_C(0x0000000000000008))
  2111. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_1_CRITICAL (IMG_UINT64_C(0x000000000000000c))
  2112. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_0_SHIFT (0U)
  2113. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_0_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFC))
  2114. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_0_LOW (IMG_UINT64_C(0000000000000000))
  2115. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_0_MEDIUM (IMG_UINT64_C(0x0000000000000001))
  2116. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_0_HIGH (IMG_UINT64_C(0x0000000000000002))
  2117. #define VHA_CR_ACE_PRIORITY_MAPPING_CTRL_CMD_0_CRITICAL (IMG_UINT64_C(0x0000000000000003))
  2118. #define VHA_CR_ACE_CTRL_ENUM_WR_CACHEABLE_MASK (0x0000000FU)
  2119. /*
  2120. Device Non-bufferable */
  2121. #define VHA_CR_ACE_CTRL_ENUM_WR_CACHEABLE_DEVICE_NON_BUFFERABLE (0x00000000U)
  2122. /*
  2123. Device Bufferable */
  2124. #define VHA_CR_ACE_CTRL_ENUM_WR_CACHEABLE_DEVICE_BUFFERABLE (0x00000001U)
  2125. /*
  2126. Normal Non-cacheable Non-bufferable */
  2127. #define VHA_CR_ACE_CTRL_ENUM_WR_CACHEABLE_NORMAL_NC_NON_BUFFERABLE (0x00000002U)
  2128. /*
  2129. Normal Non-cacheable Bufferable */
  2130. #define VHA_CR_ACE_CTRL_ENUM_WR_CACHEABLE_NORMAL_NC_BUFFERABLE (0x00000003U)
  2131. /*
  2132. Write-through No-allocate */
  2133. #define VHA_CR_ACE_CTRL_ENUM_WR_CACHEABLE_WRITE_THROUGH_NO_ALLOCATE (0x00000006U)
  2134. /*
  2135. Write-through Write-allocate */
  2136. #define VHA_CR_ACE_CTRL_ENUM_WR_CACHEABLE_WRITE_THROUGH_WRITE_ALLOCATE (0x0000000eU)
  2137. /*
  2138. Write-back No-allocate */
  2139. #define VHA_CR_ACE_CTRL_ENUM_WR_CACHEABLE_WRITE_BACK_NO_ALLOCATE (0x00000007U)
  2140. /*
  2141. Write-back Write-allocate */
  2142. #define VHA_CR_ACE_CTRL_ENUM_WR_CACHEABLE_WRITE_BACK_WRITE_ALLOCATE (0x0000000fU)
  2143. #define VHA_CR_ACE_CTRL_ENUM_RD_CACHEABLE_MASK (0x0000000FU)
  2144. /*
  2145. Device Non-bufferable */
  2146. #define VHA_CR_ACE_CTRL_ENUM_RD_CACHEABLE_DEVICE_NON_BUFFERABLE (0x00000000U)
  2147. /*
  2148. Device Bufferable */
  2149. #define VHA_CR_ACE_CTRL_ENUM_RD_CACHEABLE_DEVICE_BUFFERABLE (0x00000001U)
  2150. /*
  2151. Normal Non-cacheable Non-bufferable */
  2152. #define VHA_CR_ACE_CTRL_ENUM_RD_CACHEABLE_NORMAL_NC_NON_BUFFERABLE (0x00000002U)
  2153. /*
  2154. Normal Non-cacheable Bufferable */
  2155. #define VHA_CR_ACE_CTRL_ENUM_RD_CACHEABLE_NORMAL_NC_BUFFERABLE (0x00000003U)
  2156. /*
  2157. Write-through No-allocate */
  2158. #define VHA_CR_ACE_CTRL_ENUM_RD_CACHEABLE_WRITE_THROUGH_NO_ALLOCATE (0x0000000aU)
  2159. /*
  2160. Write-through Read-allocate */
  2161. #define VHA_CR_ACE_CTRL_ENUM_RD_CACHEABLE_WRITE_THROUGH_READ_ALLOCATE (0x0000000eU)
  2162. /*
  2163. Write-back No-allocate */
  2164. #define VHA_CR_ACE_CTRL_ENUM_RD_CACHEABLE_WRITE_BACK_NO_ALLOCATE (0x0000000bU)
  2165. /*
  2166. Write-back Read-allocate */
  2167. #define VHA_CR_ACE_CTRL_ENUM_RD_CACHEABLE_WRITE_BACK_READ_ALLOCATE (0x0000000fU)
  2168. /*
  2169. Non-Shareable */
  2170. #define VHA_CR_ACE_CTRL_ENUM_NCOH_DOMAIN_NON_SHAREABLE (0x00000000U)
  2171. /*
  2172. System */
  2173. #define VHA_CR_ACE_CTRL_ENUM_NCOH_DOMAIN_SYSTEM (0x00000001U)
  2174. /*
  2175. Inner-Shareable */
  2176. #define VHA_CR_ACE_CTRL_ENUM_COH_DOMAIN_INNER_SHAREABLE (0x00000000U)
  2177. /*
  2178. Outer-Shareable */
  2179. #define VHA_CR_ACE_CTRL_ENUM_COH_DOMAIN_OUTER_SHAREABLE (0x00000001U)
  2180. /*
  2181. Register VHA_CR_ACE_CTRL
  2182. */
  2183. #define VHA_CR_ACE_CTRL (0xE320U)
  2184. #define VHA_CR_ACE_CTRL_MASKFULL (IMG_UINT64_C(0x00000000007FCFFF))
  2185. #define VHA_CR_ACE_CTRL_CLB_AXQOS_SHIFT (19U)
  2186. #define VHA_CR_ACE_CTRL_CLB_AXQOS_CLRMSK (0XFF87FFFFU)
  2187. #define VHA_CR_ACE_CTRL_PM_MMU_AXCACHE_SHIFT (15U)
  2188. #define VHA_CR_ACE_CTRL_PM_MMU_AXCACHE_CLRMSK (0XFFF87FFFU)
  2189. #define VHA_CR_ACE_CTRL_ENABLE_NONSECURE_PROT_MATCH_SHIFT (14U)
  2190. #define VHA_CR_ACE_CTRL_ENABLE_NONSECURE_PROT_MATCH_CLRMSK (0XFFFFBFFFU)
  2191. #define VHA_CR_ACE_CTRL_ENABLE_NONSECURE_PROT_MATCH_EN (0X00004000U)
  2192. #define VHA_CR_ACE_CTRL_MMU_AWCACHE_SHIFT (8U)
  2193. #define VHA_CR_ACE_CTRL_MMU_AWCACHE_CLRMSK (0XFFFFF0FFU)
  2194. #define VHA_CR_ACE_CTRL_MMU_AWCACHE_DEVICE_NON_BUFFERABLE (00000000U)
  2195. #define VHA_CR_ACE_CTRL_MMU_AWCACHE_DEVICE_BUFFERABLE (0X00000100U)
  2196. #define VHA_CR_ACE_CTRL_MMU_AWCACHE_NORMAL_NC_NON_BUFFERABLE (0X00000200U)
  2197. #define VHA_CR_ACE_CTRL_MMU_AWCACHE_NORMAL_NC_BUFFERABLE (0X00000300U)
  2198. #define VHA_CR_ACE_CTRL_MMU_AWCACHE_WRITE_THROUGH_NO_ALLOCATE (0X00000600U)
  2199. #define VHA_CR_ACE_CTRL_MMU_AWCACHE_WRITE_THROUGH_WRITE_ALLOCATE (0X00000E00U)
  2200. #define VHA_CR_ACE_CTRL_MMU_AWCACHE_WRITE_BACK_NO_ALLOCATE (0X00000700U)
  2201. #define VHA_CR_ACE_CTRL_MMU_AWCACHE_WRITE_BACK_WRITE_ALLOCATE (0X00000F00U)
  2202. #define VHA_CR_ACE_CTRL_MMU_ARCACHE_SHIFT (4U)
  2203. #define VHA_CR_ACE_CTRL_MMU_ARCACHE_CLRMSK (0XFFFFFF0FU)
  2204. #define VHA_CR_ACE_CTRL_MMU_ARCACHE_DEVICE_NON_BUFFERABLE (00000000U)
  2205. #define VHA_CR_ACE_CTRL_MMU_ARCACHE_DEVICE_BUFFERABLE (0X00000010U)
  2206. #define VHA_CR_ACE_CTRL_MMU_ARCACHE_NORMAL_NC_NON_BUFFERABLE (0X00000020U)
  2207. #define VHA_CR_ACE_CTRL_MMU_ARCACHE_NORMAL_NC_BUFFERABLE (0X00000030U)
  2208. #define VHA_CR_ACE_CTRL_MMU_ARCACHE_WRITE_THROUGH_NO_ALLOCATE (0X000000A0U)
  2209. #define VHA_CR_ACE_CTRL_MMU_ARCACHE_WRITE_THROUGH_READ_ALLOCATE (0X000000E0U)
  2210. #define VHA_CR_ACE_CTRL_MMU_ARCACHE_WRITE_BACK_NO_ALLOCATE (0X000000B0U)
  2211. #define VHA_CR_ACE_CTRL_MMU_ARCACHE_WRITE_BACK_READ_ALLOCATE (0X000000F0U)
  2212. #define VHA_CR_ACE_CTRL_MMU_DOMAIN_SHIFT (2U)
  2213. #define VHA_CR_ACE_CTRL_MMU_DOMAIN_CLRMSK (0XFFFFFFF3U)
  2214. #define VHA_CR_ACE_CTRL_COH_DOMAIN_SHIFT (1U)
  2215. #define VHA_CR_ACE_CTRL_COH_DOMAIN_CLRMSK (0XFFFFFFFDU)
  2216. #define VHA_CR_ACE_CTRL_COH_DOMAIN_INNER_SHAREABLE (00000000U)
  2217. #define VHA_CR_ACE_CTRL_COH_DOMAIN_OUTER_SHAREABLE (0X00000002U)
  2218. #define VHA_CR_ACE_CTRL_NON_COH_DOMAIN_SHIFT (0U)
  2219. #define VHA_CR_ACE_CTRL_NON_COH_DOMAIN_CLRMSK (0XFFFFFFFEU)
  2220. #define VHA_CR_ACE_CTRL_NON_COH_DOMAIN_NON_SHAREABLE (00000000U)
  2221. #define VHA_CR_ACE_CTRL_NON_COH_DOMAIN_SYSTEM (0X00000001U)
  2222. /*
  2223. Register VHA_CR_ACE_STATUS
  2224. */
  2225. #define VHA_CR_ACE_STATUS (0xE330U)
  2226. #define VHA_CR_ACE_STATUS_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  2227. #define VHA_CR_ACE_STATUS_WR_BUS3_ERROR_SHIFT (28U)
  2228. #define VHA_CR_ACE_STATUS_WR_BUS3_ERROR_CLRMSK (0X0FFFFFFFU)
  2229. #define VHA_CR_ACE_STATUS_RD_BUS3_ERROR_SHIFT (24U)
  2230. #define VHA_CR_ACE_STATUS_RD_BUS3_ERROR_CLRMSK (0XF0FFFFFFU)
  2231. #define VHA_CR_ACE_STATUS_WR_BUS2_ERROR_SHIFT (20U)
  2232. #define VHA_CR_ACE_STATUS_WR_BUS2_ERROR_CLRMSK (0XFF0FFFFFU)
  2233. #define VHA_CR_ACE_STATUS_RD_BUS2_ERROR_SHIFT (16U)
  2234. #define VHA_CR_ACE_STATUS_RD_BUS2_ERROR_CLRMSK (0XFFF0FFFFU)
  2235. #define VHA_CR_ACE_STATUS_WR_BUS1_ERROR_SHIFT (12U)
  2236. #define VHA_CR_ACE_STATUS_WR_BUS1_ERROR_CLRMSK (0XFFFF0FFFU)
  2237. #define VHA_CR_ACE_STATUS_RD_BUS1_ERROR_SHIFT (8U)
  2238. #define VHA_CR_ACE_STATUS_RD_BUS1_ERROR_CLRMSK (0XFFFFF0FFU)
  2239. #define VHA_CR_ACE_STATUS_WR_BUS0_ERROR_SHIFT (4U)
  2240. #define VHA_CR_ACE_STATUS_WR_BUS0_ERROR_CLRMSK (0XFFFFFF0FU)
  2241. #define VHA_CR_ACE_STATUS_RD_BUS0_ERROR_SHIFT (0U)
  2242. #define VHA_CR_ACE_STATUS_RD_BUS0_ERROR_CLRMSK (0XFFFFFFF0U)
  2243. #define VHA_CR_SOC_AXI_ENUM_COH_MASK (0x00000003U)
  2244. /*
  2245. The SoC does not support any form of Coherency*/
  2246. #define VHA_CR_SOC_AXI_ENUM_COH_NO_COHERENCY (0x00000000U)
  2247. /*
  2248. The SoC supports ACE-Lite or I/O Coherency*/
  2249. #define VHA_CR_SOC_AXI_ENUM_COH_ACE_LITE_COHERENCY (0x00000001U)
  2250. /*
  2251. The SoC supports full ACE or 2-Way Coherency*/
  2252. #define VHA_CR_SOC_AXI_ENUM_COH_FULL_ACE_COHERENCY (0x00000002U)
  2253. /*
  2254. Register VHA_CR_SOC_AXI
  2255. */
  2256. #define VHA_CR_SOC_AXI (0xE338U)
  2257. #define VHA_CR_SOC_AXI_MASKFULL (IMG_UINT64_C(0x000000000000000F))
  2258. #define VHA_CR_SOC_AXI_NON_COHERENT_128_BYTE_BURST_SUPPORT_SHIFT (3U)
  2259. #define VHA_CR_SOC_AXI_NON_COHERENT_128_BYTE_BURST_SUPPORT_CLRMSK (0XFFFFFFF7U)
  2260. #define VHA_CR_SOC_AXI_NON_COHERENT_128_BYTE_BURST_SUPPORT_EN (0X00000008U)
  2261. #define VHA_CR_SOC_AXI_COHERENT_128_BYTE_BURST_SUPPORT_SHIFT (2U)
  2262. #define VHA_CR_SOC_AXI_COHERENT_128_BYTE_BURST_SUPPORT_CLRMSK (0XFFFFFFFBU)
  2263. #define VHA_CR_SOC_AXI_COHERENT_128_BYTE_BURST_SUPPORT_EN (0X00000004U)
  2264. #define VHA_CR_SOC_AXI_COHERENCY_SUPPORT_SHIFT (0U)
  2265. #define VHA_CR_SOC_AXI_COHERENCY_SUPPORT_CLRMSK (0XFFFFFFFCU)
  2266. #define VHA_CR_SOC_AXI_COHERENCY_SUPPORT_NO_COHERENCY (00000000U)
  2267. #define VHA_CR_SOC_AXI_COHERENCY_SUPPORT_ACE_LITE_COHERENCY (0X00000001U)
  2268. #define VHA_CR_SOC_AXI_COHERENCY_SUPPORT_FULL_ACE_COHERENCY (0X00000002U)
  2269. #define VHA_CR_L1_GLB_CTRL_ENUM_HASH_MODE_MASK (0x00000003U)
  2270. /*
  2271. Addresses interleaved between Cache Banks using a weaved XOR hash of address bits */
  2272. #define VHA_CR_L1_GLB_CTRL_ENUM_HASH_MODE_WEAVED_HASH (0x00000000U)
  2273. /*
  2274. Addresses interleaved between Cache Bank using a combined Set & Bank hash of the upper address bits */
  2275. #define VHA_CR_L1_GLB_CTRL_ENUM_HASH_MODE_PVR_V3_HASHING (0x00000001U)
  2276. /*
  2277. Register VHA_CR_L1_GLB_CTRL
  2278. */
  2279. #define VHA_CR_L1_GLB_CTRL (0xE400U)
  2280. #define VHA_CR_L1_GLB_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000000003))
  2281. #define VHA_CR_L1_GLB_CTRL_HASH_MODE_SHIFT (0U)
  2282. #define VHA_CR_L1_GLB_CTRL_HASH_MODE_CLRMSK (0XFFFFFFFCU)
  2283. #define VHA_CR_L1_GLB_CTRL_HASH_MODE_WEAVED_HASH (00000000U)
  2284. #define VHA_CR_L1_GLB_CTRL_HASH_MODE_PVR_V3_HASHING (0X00000001U)
  2285. /*
  2286. Register VHA_CR_CONTEXT_MAPPING2
  2287. */
  2288. #define VHA_CR_CONTEXT_MAPPING2 (0xF088U)
  2289. #define VHA_CR_CONTEXT_MAPPING2_MASKFULL (IMG_UINT64_C(0x0000000000FFFFFF))
  2290. #define VHA_CR_CONTEXT_MAPPING2_ALIST0_SHIFT (16U)
  2291. #define VHA_CR_CONTEXT_MAPPING2_ALIST0_CLRMSK (0XFF00FFFFU)
  2292. #define VHA_CR_CONTEXT_MAPPING2_TE0_SHIFT (8U)
  2293. #define VHA_CR_CONTEXT_MAPPING2_TE0_CLRMSK (0XFFFF00FFU)
  2294. #define VHA_CR_CONTEXT_MAPPING2_VCE0_SHIFT (0U)
  2295. #define VHA_CR_CONTEXT_MAPPING2_VCE0_CLRMSK (0XFFFFFF00U)
  2296. /*
  2297. Register VHA_CR_CONTEXT_MAPPING3
  2298. */
  2299. #define VHA_CR_CONTEXT_MAPPING3 (0xF090U)
  2300. #define VHA_CR_CONTEXT_MAPPING3_MASKFULL (IMG_UINT64_C(0x0000000000FFFFFF))
  2301. #define VHA_CR_CONTEXT_MAPPING3_ALIST1_SHIFT (16U)
  2302. #define VHA_CR_CONTEXT_MAPPING3_ALIST1_CLRMSK (0XFF00FFFFU)
  2303. #define VHA_CR_CONTEXT_MAPPING3_TE1_SHIFT (8U)
  2304. #define VHA_CR_CONTEXT_MAPPING3_TE1_CLRMSK (0XFFFF00FFU)
  2305. #define VHA_CR_CONTEXT_MAPPING3_VCE1_SHIFT (0U)
  2306. #define VHA_CR_CONTEXT_MAPPING3_VCE1_CLRMSK (0XFFFFFF00U)
  2307. /*
  2308. Register VHA_CR_SLC_FIX
  2309. */
  2310. #define VHA_CR_SLC_FIX (0xF0D8U)
  2311. #define VHA_CR_SLC_FIX_MASKFULL (IMG_UINT64_C(0x000000000000FFFF))
  2312. #define VHA_CR_SLC_FIX_DISABLE_SHIFT (0U)
  2313. #define VHA_CR_SLC_FIX_DISABLE_CLRMSK (0XFFFF0000U)
  2314. /*
  2315. Register VHA_CR_PWR_MAN_HYSTERESIS
  2316. */
  2317. #define VHA_CR_PWR_MAN_HYSTERESIS (0xF100U)
  2318. #define VHA_CR_PWR_MAN_HYSTERESIS_MASKFULL (IMG_UINT64_C(0x000000000000001F))
  2319. #define VHA_CR_PWR_MAN_HYSTERESIS_VALUE_SHIFT (0U)
  2320. #define VHA_CR_PWR_MAN_HYSTERESIS_VALUE_CLRMSK (0XFFFFFFE0U)
  2321. #define VHA_CR_CNN_MASK_CTRL_MASK (0x00000003U)
  2322. /*
  2323. No Masks Applied */
  2324. #define VHA_CR_CNN_MASK_CTRL_NO_MASK (0x00000000U)
  2325. /*
  2326. Mask port with mask_level < 1 */
  2327. #define VHA_CR_CNN_MASK_CTRL_MASK_L1 (0x00000001U)
  2328. /*
  2329. Mask port with mask_level < 2 */
  2330. #define VHA_CR_CNN_MASK_CTRL_MASK_L2 (0x00000002U)
  2331. /*
  2332. Mask port with mask_level < 3 */
  2333. #define VHA_CR_CNN_MASK_CTRL_MASK_L3 (0x00000003U)
  2334. #define VHA_CR_CNN_DEBUG_CTRL_MASK (0x00000003U)
  2335. /*
  2336. Debug is switched off */
  2337. #define VHA_CR_CNN_DEBUG_CTRL_DISABLE (0x00000000U)
  2338. /*
  2339. Debug is output at the end of each stream */
  2340. #define VHA_CR_CNN_DEBUG_CTRL_STREAM (0x00000001U)
  2341. /*
  2342. Debug is output at the end of each layer */
  2343. #define VHA_CR_CNN_DEBUG_CTRL_LAYER (0x00000002U)
  2344. /*
  2345. Debug is output at the end of each pass */
  2346. #define VHA_CR_CNN_DEBUG_CTRL_PASS (0x00000003U)
  2347. #define VHA_CR_CNN_PRELOAD_CTRL_MASK (0x00000007U)
  2348. /*
  2349. Preloads are switched off */
  2350. #define VHA_CR_CNN_PRELOAD_CTRL_DISABLE (0x00000000U)
  2351. /*
  2352. Preloads are triggered 64 requests after the previous 32k boundary */
  2353. #define VHA_CR_CNN_PRELOAD_CTRL_N_64 (0x00000001U)
  2354. /*
  2355. Preloads are triggered 128 requests after the previous 32k boundary */
  2356. #define VHA_CR_CNN_PRELOAD_CTRL_N_128 (0x00000002U)
  2357. /*
  2358. Preloads are triggered 192 requests after the previous 32k boundary */
  2359. #define VHA_CR_CNN_PRELOAD_CTRL_N_192 (0x00000003U)
  2360. /*
  2361. Preloads are triggered 256 requests after the previous 32k boundary */
  2362. #define VHA_CR_CNN_PRELOAD_CTRL_N_256 (0x00000004U)
  2363. /*
  2364. Preloads are triggered 320 requests after the previous 32k boundary */
  2365. #define VHA_CR_CNN_PRELOAD_CTRL_N_320 (0x00000005U)
  2366. /*
  2367. Preloads are triggered 384 requests after the previous 32k boundary */
  2368. #define VHA_CR_CNN_PRELOAD_CTRL_N_384 (0x00000006U)
  2369. /*
  2370. Preloads are triggered 448 requests after the previous 32k boundary */
  2371. #define VHA_CR_CNN_PRELOAD_CTRL_N_448 (0x00000007U)
  2372. #define VHA_CR_VHA_EVENT_TYPE_VHA_MMU_PARITY_ERROR_SHIFT (29U)
  2373. #define VHA_CR_VHA_EVENT_TYPE_VHA_MMU_PARITY_ERROR_CLRMSK (0XDFFFFFFFU)
  2374. #define VHA_CR_VHA_EVENT_TYPE_VHA_MMU_PARITY_ERROR_EN (0X20000000U)
  2375. #define VHA_CR_VHA_EVENT_TYPE_VHA_PARITY_ERROR_SHIFT (28U)
  2376. #define VHA_CR_VHA_EVENT_TYPE_VHA_PARITY_ERROR_CLRMSK (0XEFFFFFFFU)
  2377. #define VHA_CR_VHA_EVENT_TYPE_VHA_PARITY_ERROR_EN (0X10000000U)
  2378. #define VHA_CR_VHA_EVENT_TYPE_VHA_ECC_INIT_DONE_SHIFT (25U)
  2379. #define VHA_CR_VHA_EVENT_TYPE_VHA_ECC_INIT_DONE_CLRMSK (0XFDFFFFFFU)
  2380. #define VHA_CR_VHA_EVENT_TYPE_VHA_ECC_INIT_DONE_EN (0X02000000U)
  2381. #define VHA_CR_VHA_EVENT_TYPE_VHA_ECC_DETECTION_SHIFT (24U)
  2382. #define VHA_CR_VHA_EVENT_TYPE_VHA_ECC_DETECTION_CLRMSK (0XFEFFFFFFU)
  2383. #define VHA_CR_VHA_EVENT_TYPE_VHA_ECC_DETECTION_EN (0X01000000U)
  2384. #define VHA_CR_VHA_EVENT_TYPE_VHA_ECC_CORRECTION_SHIFT (23U)
  2385. #define VHA_CR_VHA_EVENT_TYPE_VHA_ECC_CORRECTION_CLRMSK (0XFF7FFFFFU)
  2386. #define VHA_CR_VHA_EVENT_TYPE_VHA_ECC_CORRECTION_EN (0X00800000U)
  2387. #define VHA_CR_VHA_EVENT_TYPE_VHA_LOCKSTEP_ERROR_SHIFT (22U)
  2388. #define VHA_CR_VHA_EVENT_TYPE_VHA_LOCKSTEP_ERROR_CLRMSK (0XFFBFFFFFU)
  2389. #define VHA_CR_VHA_EVENT_TYPE_VHA_LOCKSTEP_ERROR_EN (0X00400000U)
  2390. #define VHA_CR_VHA_EVENT_TYPE_VHA_READY_SHIFT (21U)
  2391. #define VHA_CR_VHA_EVENT_TYPE_VHA_READY_CLRMSK (0XFFDFFFFFU)
  2392. #define VHA_CR_VHA_EVENT_TYPE_VHA_READY_EN (0X00200000U)
  2393. #define VHA_CR_VHA_EVENT_TYPE_VHA_ERROR_SHIFT (20U)
  2394. #define VHA_CR_VHA_EVENT_TYPE_VHA_ERROR_CLRMSK (0XFFEFFFFFU)
  2395. #define VHA_CR_VHA_EVENT_TYPE_VHA_ERROR_EN (0X00100000U)
  2396. #define VHA_CR_VHA_EVENT_TYPE_VHA_HL_WDT_SHIFT (19U)
  2397. #define VHA_CR_VHA_EVENT_TYPE_VHA_HL_WDT_CLRMSK (0XFFF7FFFFU)
  2398. #define VHA_CR_VHA_EVENT_TYPE_VHA_HL_WDT_EN (0X00080000U)
  2399. #define VHA_CR_VHA_EVENT_TYPE_VHA_AXI_ERROR_SHIFT (18U)
  2400. #define VHA_CR_VHA_EVENT_TYPE_VHA_AXI_ERROR_CLRMSK (0XFFFBFFFFU)
  2401. #define VHA_CR_VHA_EVENT_TYPE_VHA_AXI_ERROR_EN (0X00040000U)
  2402. #define VHA_CR_VHA_EVENT_TYPE_VHA_MMU_PAGE_FAULT_SHIFT (16U)
  2403. #define VHA_CR_VHA_EVENT_TYPE_VHA_MMU_PAGE_FAULT_CLRMSK (0XFFFEFFFFU)
  2404. #define VHA_CR_VHA_EVENT_TYPE_VHA_MMU_PAGE_FAULT_EN (0X00010000U)
  2405. #define VHA_CR_VHA_EVENT_TYPE_VHA_CNN0_MEM_WDT_SHIFT (3U)
  2406. #define VHA_CR_VHA_EVENT_TYPE_VHA_CNN0_MEM_WDT_CLRMSK (0XFFFFFFF7U)
  2407. #define VHA_CR_VHA_EVENT_TYPE_VHA_CNN0_MEM_WDT_EN (0X00000008U)
  2408. #define VHA_CR_VHA_EVENT_TYPE_VHA_CNN0_ERROR_SHIFT (1U)
  2409. #define VHA_CR_VHA_EVENT_TYPE_VHA_CNN0_ERROR_CLRMSK (0XFFFFFFFDU)
  2410. #define VHA_CR_VHA_EVENT_TYPE_VHA_CNN0_ERROR_EN (0X00000002U)
  2411. #define VHA_CR_VHA_EVENT_TYPE_VHA_CNN0_COMPLETE_SHIFT (0U)
  2412. #define VHA_CR_VHA_EVENT_TYPE_VHA_CNN0_COMPLETE_CLRMSK (0XFFFFFFFEU)
  2413. #define VHA_CR_VHA_EVENT_TYPE_VHA_CNN0_COMPLETE_EN (0X00000001U)
  2414. #define VHA_CR_VHA_EVENT_STATUS_TYPE_PARITY_SHIFT (31U)
  2415. #define VHA_CR_VHA_EVENT_STATUS_TYPE_PARITY_CLRMSK (0X7FFFFFFFU)
  2416. #define VHA_CR_VHA_EVENT_STATUS_TYPE_PARITY_EN (0X80000000U)
  2417. #define VHA_CR_VHA_EVENT_STATUS_TYPE_VHA_MMU_PARITY_ERROR_SHIFT (29U)
  2418. #define VHA_CR_VHA_EVENT_STATUS_TYPE_VHA_MMU_PARITY_ERROR_CLRMSK (0XDFFFFFFFU)
  2419. #define VHA_CR_VHA_EVENT_STATUS_TYPE_VHA_MMU_PARITY_ERROR_EN (0X20000000U)
  2420. #define VHA_CR_VHA_EVENT_STATUS_TYPE_VHA_PARITY_ERROR_SHIFT (28U)
  2421. #define VHA_CR_VHA_EVENT_STATUS_TYPE_VHA_PARITY_ERROR_CLRMSK (0XEFFFFFFFU)
  2422. #define VHA_CR_VHA_EVENT_STATUS_TYPE_VHA_PARITY_ERROR_EN (0X10000000U)
  2423. #define VHA_CR_VHA_EVENT_STATUS_TYPE_VHA_ECC_INIT_DONE_SHIFT (25U)
  2424. #define VHA_CR_VHA_EVENT_STATUS_TYPE_VHA_ECC_INIT_DONE_CLRMSK (0XFDFFFFFFU)
  2425. #define VHA_CR_VHA_EVENT_STATUS_TYPE_VHA_ECC_INIT_DONE_EN (0X02000000U)
  2426. #define VHA_CR_VHA_EVENT_STATUS_TYPE_VHA_ECC_DETECTION_SHIFT (24U)
  2427. #define VHA_CR_VHA_EVENT_STATUS_TYPE_VHA_ECC_DETECTION_CLRMSK (0XFEFFFFFFU)
  2428. #define VHA_CR_VHA_EVENT_STATUS_TYPE_VHA_ECC_DETECTION_EN (0X01000000U)
  2429. #define VHA_CR_VHA_EVENT_STATUS_TYPE_VHA_ECC_CORRECTION_SHIFT (23U)
  2430. #define VHA_CR_VHA_EVENT_STATUS_TYPE_VHA_ECC_CORRECTION_CLRMSK (0XFF7FFFFFU)
  2431. #define VHA_CR_VHA_EVENT_STATUS_TYPE_VHA_ECC_CORRECTION_EN (0X00800000U)
  2432. #define VHA_CR_VHA_EVENT_STATUS_TYPE_VHA_LOCKSTEP_ERROR_SHIFT (22U)
  2433. #define VHA_CR_VHA_EVENT_STATUS_TYPE_VHA_LOCKSTEP_ERROR_CLRMSK (0XFFBFFFFFU)
  2434. #define VHA_CR_VHA_EVENT_STATUS_TYPE_VHA_LOCKSTEP_ERROR_EN (0X00400000U)
  2435. #define VHA_CR_VHA_EVENT_STATUS_TYPE_VHA_READY_SHIFT (21U)
  2436. #define VHA_CR_VHA_EVENT_STATUS_TYPE_VHA_READY_CLRMSK (0XFFDFFFFFU)
  2437. #define VHA_CR_VHA_EVENT_STATUS_TYPE_VHA_READY_EN (0X00200000U)
  2438. #define VHA_CR_VHA_EVENT_STATUS_TYPE_VHA_ERROR_SHIFT (20U)
  2439. #define VHA_CR_VHA_EVENT_STATUS_TYPE_VHA_ERROR_CLRMSK (0XFFEFFFFFU)
  2440. #define VHA_CR_VHA_EVENT_STATUS_TYPE_VHA_ERROR_EN (0X00100000U)
  2441. #define VHA_CR_VHA_EVENT_STATUS_TYPE_VHA_HL_WDT_SHIFT (19U)
  2442. #define VHA_CR_VHA_EVENT_STATUS_TYPE_VHA_HL_WDT_CLRMSK (0XFFF7FFFFU)
  2443. #define VHA_CR_VHA_EVENT_STATUS_TYPE_VHA_HL_WDT_EN (0X00080000U)
  2444. #define VHA_CR_VHA_EVENT_STATUS_TYPE_VHA_AXI_ERROR_SHIFT (18U)
  2445. #define VHA_CR_VHA_EVENT_STATUS_TYPE_VHA_AXI_ERROR_CLRMSK (0XFFFBFFFFU)
  2446. #define VHA_CR_VHA_EVENT_STATUS_TYPE_VHA_AXI_ERROR_EN (0X00040000U)
  2447. #define VHA_CR_VHA_EVENT_STATUS_TYPE_VHA_MMU_PAGE_FAULT_SHIFT (16U)
  2448. #define VHA_CR_VHA_EVENT_STATUS_TYPE_VHA_MMU_PAGE_FAULT_CLRMSK (0XFFFEFFFFU)
  2449. #define VHA_CR_VHA_EVENT_STATUS_TYPE_VHA_MMU_PAGE_FAULT_EN (0X00010000U)
  2450. #define VHA_CR_VHA_EVENT_STATUS_TYPE_VHA_CNN0_MEM_WDT_SHIFT (3U)
  2451. #define VHA_CR_VHA_EVENT_STATUS_TYPE_VHA_CNN0_MEM_WDT_CLRMSK (0XFFFFFFF7U)
  2452. #define VHA_CR_VHA_EVENT_STATUS_TYPE_VHA_CNN0_MEM_WDT_EN (0X00000008U)
  2453. #define VHA_CR_VHA_EVENT_STATUS_TYPE_VHA_CNN0_ERROR_SHIFT (1U)
  2454. #define VHA_CR_VHA_EVENT_STATUS_TYPE_VHA_CNN0_ERROR_CLRMSK (0XFFFFFFFDU)
  2455. #define VHA_CR_VHA_EVENT_STATUS_TYPE_VHA_CNN0_ERROR_EN (0X00000002U)
  2456. #define VHA_CR_VHA_EVENT_STATUS_TYPE_VHA_CNN0_COMPLETE_SHIFT (0U)
  2457. #define VHA_CR_VHA_EVENT_STATUS_TYPE_VHA_CNN0_COMPLETE_CLRMSK (0XFFFFFFFEU)
  2458. #define VHA_CR_VHA_EVENT_STATUS_TYPE_VHA_CNN0_COMPLETE_EN (0X00000001U)
  2459. /*
  2460. Memory buffer will be used for MODEL only (CBUF, CMD , DEBUG, PERF) */
  2461. #define VHA_CR_ALT_ADDR_BUF_TYPE_MODEL_ONLY (0x00000000U)
  2462. /*
  2463. Memory buffer will be used for IO Only( OUTPACK , IBUF , ABUF, EWO ) or Both MODEL and IO */
  2464. #define VHA_CR_ALT_ADDR_BUF_TYPE_IO_OR_SHARED (0x00000001U)
  2465. /*
  2466. Register VHA_CR_OS0_CNN_CONTROL
  2467. */
  2468. #define VHA_CR_OS0_CNN_CONTROL (0x10000U)
  2469. #define VHA_CR_OS0_CNN_CONTROL_MASKFULL (IMG_UINT64_C(0x000000000000337F))
  2470. #define VHA_CR_OS0_CNN_CONTROL_CTXT_PASID_SHIFT (12U)
  2471. #define VHA_CR_OS0_CNN_CONTROL_CTXT_PASID_CLRMSK (0XFFFFCFFFU)
  2472. #define VHA_CR_OS0_CNN_CONTROL_PRIORITY_SHIFT (8U)
  2473. #define VHA_CR_OS0_CNN_CONTROL_PRIORITY_CLRMSK (0XFFFFFCFFU)
  2474. #define VHA_CR_OS0_CNN_CONTROL_CMD_SIZE_MIN1_SHIFT (1U)
  2475. #define VHA_CR_OS0_CNN_CONTROL_CMD_SIZE_MIN1_CLRMSK (0XFFFFFF81U)
  2476. #define VHA_CR_OS0_CNN_CONTROL_START_SHIFT (0U)
  2477. #define VHA_CR_OS0_CNN_CONTROL_START_CLRMSK (0XFFFFFFFEU)
  2478. #define VHA_CR_OS0_CNN_CONTROL_START_EN (0X00000001U)
  2479. #define VHA_CR_OS0_CNN_STATUS_STATE_MASK (0x00000003U)
  2480. /*
  2481. No requests are pending for this host*/
  2482. #define VHA_CR_OS0_CNN_STATUS_STATE_IDLE (0x00000000U)
  2483. /*
  2484. A command stream from this host is being processed*/
  2485. #define VHA_CR_OS0_CNN_STATUS_STATE_RUN (0x00000001U)
  2486. /*
  2487. The command stream from this host has been suspended due to higher priority request from another host*/
  2488. #define VHA_CR_OS0_CNN_STATUS_STATE_SUSPEND (0x00000002U)
  2489. /*
  2490. A command stream from this host is pending but not been started */
  2491. #define VHA_CR_OS0_CNN_STATUS_STATE_PENDING (0x00000003U)
  2492. /*
  2493. Register VHA_CR_OS0_CNN_STATUS
  2494. */
  2495. #define VHA_CR_OS0_CNN_STATUS (0x10008U)
  2496. #define VHA_CR_OS0_CNN_STATUS_MASKFULL (IMG_UINT64_C(0x00000000C1FFFFFF))
  2497. #define VHA_CR_OS0_CNN_STATUS_CURRENT_STATE_SHIFT (30U)
  2498. #define VHA_CR_OS0_CNN_STATUS_CURRENT_STATE_CLRMSK (0X3FFFFFFFU)
  2499. #define VHA_CR_OS0_CNN_STATUS_CURRENT_STATE_IDLE (00000000U)
  2500. #define VHA_CR_OS0_CNN_STATUS_CURRENT_STATE_RUN (0X40000000U)
  2501. #define VHA_CR_OS0_CNN_STATUS_CURRENT_STATE_SUSPEND (0X80000000U)
  2502. #define VHA_CR_OS0_CNN_STATUS_CURRENT_STATE_PENDING (0XC0000000U)
  2503. #define VHA_CR_OS0_CNN_STATUS_PARITY_SHIFT (24U)
  2504. #define VHA_CR_OS0_CNN_STATUS_PARITY_CLRMSK (0XFEFFFFFFU)
  2505. #define VHA_CR_OS0_CNN_STATUS_PARITY_EN (0X01000000U)
  2506. #define VHA_CR_OS0_CNN_STATUS_LAYER_COUNT_SHIFT (8U)
  2507. #define VHA_CR_OS0_CNN_STATUS_LAYER_COUNT_CLRMSK (0XFF0000FFU)
  2508. #define VHA_CR_OS0_CNN_STATUS_STREAM_COUNT_SHIFT (0U)
  2509. #define VHA_CR_OS0_CNN_STATUS_STREAM_COUNT_CLRMSK (0XFFFFFF00U)
  2510. /*
  2511. Register VHA_CR_OS0_CNN_STATUS2
  2512. */
  2513. #define VHA_CR_OS0_CNN_STATUS2 (0x10010U)
  2514. #define VHA_CR_OS0_CNN_STATUS2_MASKFULL (IMG_UINT64_C(0x000000000001FFFF))
  2515. #define VHA_CR_OS0_CNN_STATUS2_PASS_COUNT_SHIFT (0U)
  2516. #define VHA_CR_OS0_CNN_STATUS2_PASS_COUNT_CLRMSK (0XFFFE0000U)
  2517. /*
  2518. Register VHA_CR_OS0_CNN_CMD_BASE_ADDRESS
  2519. */
  2520. #define VHA_CR_OS0_CNN_CMD_BASE_ADDRESS (0x10020U)
  2521. #define VHA_CR_OS0_CNN_CMD_BASE_ADDRESS_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFF80))
  2522. #define VHA_CR_OS0_CNN_CMD_BASE_ADDRESS_BASE_ADDR_SHIFT (7U)
  2523. #define VHA_CR_OS0_CNN_CMD_BASE_ADDRESS_BASE_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF000000007F))
  2524. /*
  2525. Register VHA_CR_OS0_CNN_ALT_ADDRESS_USED
  2526. */
  2527. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED (0x10038U)
  2528. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  2529. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR15_BUF_TYPE_SHIFT (31U)
  2530. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR15_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFF7FFFFFFF))
  2531. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR15_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  2532. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR15_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000080000000))
  2533. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR14_BUF_TYPE_SHIFT (30U)
  2534. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR14_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFBFFFFFFF))
  2535. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR14_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  2536. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR14_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000040000000))
  2537. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR13_BUF_TYPE_SHIFT (29U)
  2538. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR13_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFDFFFFFFF))
  2539. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR13_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  2540. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR13_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000020000000))
  2541. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR12_BUF_TYPE_SHIFT (28U)
  2542. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR12_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFEFFFFFFF))
  2543. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR12_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  2544. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR12_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000010000000))
  2545. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR11_BUF_TYPE_SHIFT (27U)
  2546. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR11_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFF7FFFFFF))
  2547. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR11_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  2548. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR11_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000008000000))
  2549. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR10_BUF_TYPE_SHIFT (26U)
  2550. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR10_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFBFFFFFF))
  2551. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR10_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  2552. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR10_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000004000000))
  2553. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR9_BUF_TYPE_SHIFT (25U)
  2554. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR9_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFDFFFFFF))
  2555. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR9_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  2556. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR9_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000002000000))
  2557. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR8_BUF_TYPE_SHIFT (24U)
  2558. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR8_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFEFFFFFF))
  2559. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR8_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  2560. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR8_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000001000000))
  2561. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR7_BUF_TYPE_SHIFT (23U)
  2562. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR7_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF7FFFFF))
  2563. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR7_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  2564. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR7_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000000800000))
  2565. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR6_BUF_TYPE_SHIFT (22U)
  2566. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR6_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFBFFFFF))
  2567. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR6_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  2568. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR6_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000000400000))
  2569. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR5_BUF_TYPE_SHIFT (21U)
  2570. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR5_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFDFFFFF))
  2571. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR5_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  2572. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR5_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000000200000))
  2573. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR4_BUF_TYPE_SHIFT (20U)
  2574. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR4_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFEFFFFF))
  2575. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR4_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  2576. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR4_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000000100000))
  2577. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR3_BUF_TYPE_SHIFT (19U)
  2578. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR3_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF7FFFF))
  2579. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR3_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  2580. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR3_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000000080000))
  2581. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR2_BUF_TYPE_SHIFT (18U)
  2582. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR2_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFBFFFF))
  2583. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR2_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  2584. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR2_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000000040000))
  2585. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR1_BUF_TYPE_SHIFT (17U)
  2586. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR1_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFDFFFF))
  2587. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR1_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  2588. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR1_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000000020000))
  2589. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR0_BUF_TYPE_SHIFT (16U)
  2590. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR0_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFEFFFF))
  2591. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR0_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  2592. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR0_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000000010000))
  2593. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR15_USED_SHIFT (15U)
  2594. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR15_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF7FFF))
  2595. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR15_USED_EN (IMG_UINT64_C(0X0000000000008000))
  2596. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR14_USED_SHIFT (14U)
  2597. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR14_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFBFFF))
  2598. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR14_USED_EN (IMG_UINT64_C(0X0000000000004000))
  2599. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR13_USED_SHIFT (13U)
  2600. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR13_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFDFFF))
  2601. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR13_USED_EN (IMG_UINT64_C(0X0000000000002000))
  2602. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR12_USED_SHIFT (12U)
  2603. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR12_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFEFFF))
  2604. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR12_USED_EN (IMG_UINT64_C(0X0000000000001000))
  2605. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR11_USED_SHIFT (11U)
  2606. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR11_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF7FF))
  2607. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR11_USED_EN (IMG_UINT64_C(0X0000000000000800))
  2608. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR10_USED_SHIFT (10U)
  2609. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR10_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFBFF))
  2610. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR10_USED_EN (IMG_UINT64_C(0X0000000000000400))
  2611. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR9_USED_SHIFT (9U)
  2612. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR9_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFDFF))
  2613. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR9_USED_EN (IMG_UINT64_C(0X0000000000000200))
  2614. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR8_USED_SHIFT (8U)
  2615. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR8_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFEFF))
  2616. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR8_USED_EN (IMG_UINT64_C(0X0000000000000100))
  2617. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR7_USED_SHIFT (7U)
  2618. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR7_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFF7F))
  2619. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR7_USED_EN (IMG_UINT64_C(0X0000000000000080))
  2620. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR6_USED_SHIFT (6U)
  2621. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR6_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFBF))
  2622. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR6_USED_EN (IMG_UINT64_C(0X0000000000000040))
  2623. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR5_USED_SHIFT (5U)
  2624. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR5_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFDF))
  2625. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR5_USED_EN (IMG_UINT64_C(0X0000000000000020))
  2626. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR4_USED_SHIFT (4U)
  2627. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR4_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFEF))
  2628. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR4_USED_EN (IMG_UINT64_C(0X0000000000000010))
  2629. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR3_USED_SHIFT (3U)
  2630. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR3_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF7))
  2631. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR3_USED_EN (IMG_UINT64_C(0X0000000000000008))
  2632. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR2_USED_SHIFT (2U)
  2633. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR2_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFB))
  2634. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR2_USED_EN (IMG_UINT64_C(0X0000000000000004))
  2635. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR1_USED_SHIFT (1U)
  2636. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR1_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFD))
  2637. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR1_USED_EN (IMG_UINT64_C(0X0000000000000002))
  2638. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR0_USED_SHIFT (0U)
  2639. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR0_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  2640. #define VHA_CR_OS0_CNN_ALT_ADDRESS_USED_ALT_ADDR0_USED_EN (IMG_UINT64_C(0X0000000000000001))
  2641. /*
  2642. Register VHA_CR_OS0_CNN_ALT_ADDRESS0
  2643. */
  2644. #define VHA_CR_OS0_CNN_ALT_ADDRESS0 (0x10040U)
  2645. #define VHA_CR_OS0_CNN_ALT_ADDRESS0_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  2646. #define VHA_CR_OS0_CNN_ALT_ADDRESS0_ALT_ADDR_SHIFT (0U)
  2647. #define VHA_CR_OS0_CNN_ALT_ADDRESS0_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  2648. /*
  2649. Register VHA_CR_OS0_CNN_ALT_ADDRESS1
  2650. */
  2651. #define VHA_CR_OS0_CNN_ALT_ADDRESS1 (0x10048U)
  2652. #define VHA_CR_OS0_CNN_ALT_ADDRESS1_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  2653. #define VHA_CR_OS0_CNN_ALT_ADDRESS1_ALT_ADDR_SHIFT (0U)
  2654. #define VHA_CR_OS0_CNN_ALT_ADDRESS1_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  2655. /*
  2656. Register VHA_CR_OS0_CNN_ALT_ADDRESS2
  2657. */
  2658. #define VHA_CR_OS0_CNN_ALT_ADDRESS2 (0x10050U)
  2659. #define VHA_CR_OS0_CNN_ALT_ADDRESS2_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  2660. #define VHA_CR_OS0_CNN_ALT_ADDRESS2_ALT_ADDR_SHIFT (0U)
  2661. #define VHA_CR_OS0_CNN_ALT_ADDRESS2_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  2662. /*
  2663. Register VHA_CR_OS0_CNN_ALT_ADDRESS3
  2664. */
  2665. #define VHA_CR_OS0_CNN_ALT_ADDRESS3 (0x10058U)
  2666. #define VHA_CR_OS0_CNN_ALT_ADDRESS3_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  2667. #define VHA_CR_OS0_CNN_ALT_ADDRESS3_ALT_ADDR_SHIFT (0U)
  2668. #define VHA_CR_OS0_CNN_ALT_ADDRESS3_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  2669. /*
  2670. Register VHA_CR_OS0_CNN_ALT_ADDRESS4
  2671. */
  2672. #define VHA_CR_OS0_CNN_ALT_ADDRESS4 (0x10060U)
  2673. #define VHA_CR_OS0_CNN_ALT_ADDRESS4_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  2674. #define VHA_CR_OS0_CNN_ALT_ADDRESS4_ALT_ADDR_SHIFT (0U)
  2675. #define VHA_CR_OS0_CNN_ALT_ADDRESS4_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  2676. /*
  2677. Register VHA_CR_OS0_CNN_ALT_ADDRESS5
  2678. */
  2679. #define VHA_CR_OS0_CNN_ALT_ADDRESS5 (0x10068U)
  2680. #define VHA_CR_OS0_CNN_ALT_ADDRESS5_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  2681. #define VHA_CR_OS0_CNN_ALT_ADDRESS5_ALT_ADDR_SHIFT (0U)
  2682. #define VHA_CR_OS0_CNN_ALT_ADDRESS5_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  2683. /*
  2684. Register VHA_CR_OS0_CNN_ALT_ADDRESS6
  2685. */
  2686. #define VHA_CR_OS0_CNN_ALT_ADDRESS6 (0x10070U)
  2687. #define VHA_CR_OS0_CNN_ALT_ADDRESS6_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  2688. #define VHA_CR_OS0_CNN_ALT_ADDRESS6_ALT_ADDR_SHIFT (0U)
  2689. #define VHA_CR_OS0_CNN_ALT_ADDRESS6_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  2690. /*
  2691. Register VHA_CR_OS0_CNN_ALT_ADDRESS7
  2692. */
  2693. #define VHA_CR_OS0_CNN_ALT_ADDRESS7 (0x10078U)
  2694. #define VHA_CR_OS0_CNN_ALT_ADDRESS7_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  2695. #define VHA_CR_OS0_CNN_ALT_ADDRESS7_ALT_ADDR_SHIFT (0U)
  2696. #define VHA_CR_OS0_CNN_ALT_ADDRESS7_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  2697. /*
  2698. Register VHA_CR_OS0_CNN_WRITEBACK_CONTROL
  2699. */
  2700. #define VHA_CR_OS0_CNN_WRITEBACK_CONTROL (0x10080U)
  2701. #define VHA_CR_OS0_CNN_WRITEBACK_CONTROL_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  2702. #define VHA_CR_OS0_CNN_WRITEBACK_CONTROL_WRITE_BACK_VALUE_SHIFT (0U)
  2703. #define VHA_CR_OS0_CNN_WRITEBACK_CONTROL_WRITE_BACK_VALUE_CLRMSK (00000000U)
  2704. /*
  2705. Register VHA_CR_OS0_VHA_EVENT_ENABLE
  2706. */
  2707. #define VHA_CR_OS0_VHA_EVENT_ENABLE (0x10088U)
  2708. #define VHA_CR_OS0_VHA_EVENT_ENABLE_MASKFULL (IMG_UINT64_C(0x0000000033FD000B))
  2709. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_MMU_PARITY_ERROR_SHIFT (29U)
  2710. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_MMU_PARITY_ERROR_CLRMSK (0XDFFFFFFFU)
  2711. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_MMU_PARITY_ERROR_EN (0X20000000U)
  2712. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_PARITY_ERROR_SHIFT (28U)
  2713. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_PARITY_ERROR_CLRMSK (0XEFFFFFFFU)
  2714. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_PARITY_ERROR_EN (0X10000000U)
  2715. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_ECC_INIT_DONE_SHIFT (25U)
  2716. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_ECC_INIT_DONE_CLRMSK (0XFDFFFFFFU)
  2717. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_ECC_INIT_DONE_EN (0X02000000U)
  2718. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_ECC_DETECTION_SHIFT (24U)
  2719. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_ECC_DETECTION_CLRMSK (0XFEFFFFFFU)
  2720. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_ECC_DETECTION_EN (0X01000000U)
  2721. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_ECC_CORRECTION_SHIFT (23U)
  2722. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_ECC_CORRECTION_CLRMSK (0XFF7FFFFFU)
  2723. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_ECC_CORRECTION_EN (0X00800000U)
  2724. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_LOCKSTEP_ERROR_SHIFT (22U)
  2725. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_LOCKSTEP_ERROR_CLRMSK (0XFFBFFFFFU)
  2726. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_LOCKSTEP_ERROR_EN (0X00400000U)
  2727. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_READY_SHIFT (21U)
  2728. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_READY_CLRMSK (0XFFDFFFFFU)
  2729. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_READY_EN (0X00200000U)
  2730. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_ERROR_SHIFT (20U)
  2731. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_ERROR_CLRMSK (0XFFEFFFFFU)
  2732. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_ERROR_EN (0X00100000U)
  2733. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_HL_WDT_SHIFT (19U)
  2734. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_HL_WDT_CLRMSK (0XFFF7FFFFU)
  2735. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_HL_WDT_EN (0X00080000U)
  2736. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_AXI_ERROR_SHIFT (18U)
  2737. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_AXI_ERROR_CLRMSK (0XFFFBFFFFU)
  2738. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_AXI_ERROR_EN (0X00040000U)
  2739. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_MMU_PAGE_FAULT_SHIFT (16U)
  2740. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_MMU_PAGE_FAULT_CLRMSK (0XFFFEFFFFU)
  2741. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_MMU_PAGE_FAULT_EN (0X00010000U)
  2742. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_CNN0_MEM_WDT_SHIFT (3U)
  2743. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_CNN0_MEM_WDT_CLRMSK (0XFFFFFFF7U)
  2744. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_CNN0_MEM_WDT_EN (0X00000008U)
  2745. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_CNN0_ERROR_SHIFT (1U)
  2746. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_CNN0_ERROR_CLRMSK (0XFFFFFFFDU)
  2747. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_CNN0_ERROR_EN (0X00000002U)
  2748. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_CNN0_COMPLETE_SHIFT (0U)
  2749. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_CNN0_COMPLETE_CLRMSK (0XFFFFFFFEU)
  2750. #define VHA_CR_OS0_VHA_EVENT_ENABLE_VHA_CNN0_COMPLETE_EN (0X00000001U)
  2751. /*
  2752. Register VHA_CR_OS0_VHA_EVENT_STATUS
  2753. */
  2754. #define VHA_CR_OS0_VHA_EVENT_STATUS (0x10090U)
  2755. #define VHA_CR_OS0_VHA_EVENT_STATUS_MASKFULL (IMG_UINT64_C(0x00000000B3FD000B))
  2756. #define VHA_CR_OS0_VHA_EVENT_STATUS_PARITY_SHIFT (31U)
  2757. #define VHA_CR_OS0_VHA_EVENT_STATUS_PARITY_CLRMSK (0X7FFFFFFFU)
  2758. #define VHA_CR_OS0_VHA_EVENT_STATUS_PARITY_EN (0X80000000U)
  2759. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_MMU_PARITY_ERROR_SHIFT (29U)
  2760. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_MMU_PARITY_ERROR_CLRMSK (0XDFFFFFFFU)
  2761. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_MMU_PARITY_ERROR_EN (0X20000000U)
  2762. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_PARITY_ERROR_SHIFT (28U)
  2763. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_PARITY_ERROR_CLRMSK (0XEFFFFFFFU)
  2764. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_PARITY_ERROR_EN (0X10000000U)
  2765. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_ECC_INIT_DONE_SHIFT (25U)
  2766. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_ECC_INIT_DONE_CLRMSK (0XFDFFFFFFU)
  2767. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_ECC_INIT_DONE_EN (0X02000000U)
  2768. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_ECC_DETECTION_SHIFT (24U)
  2769. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_ECC_DETECTION_CLRMSK (0XFEFFFFFFU)
  2770. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_ECC_DETECTION_EN (0X01000000U)
  2771. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_ECC_CORRECTION_SHIFT (23U)
  2772. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_ECC_CORRECTION_CLRMSK (0XFF7FFFFFU)
  2773. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_ECC_CORRECTION_EN (0X00800000U)
  2774. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_LOCKSTEP_ERROR_SHIFT (22U)
  2775. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_LOCKSTEP_ERROR_CLRMSK (0XFFBFFFFFU)
  2776. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_LOCKSTEP_ERROR_EN (0X00400000U)
  2777. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_READY_SHIFT (21U)
  2778. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_READY_CLRMSK (0XFFDFFFFFU)
  2779. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_READY_EN (0X00200000U)
  2780. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_ERROR_SHIFT (20U)
  2781. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_ERROR_CLRMSK (0XFFEFFFFFU)
  2782. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_ERROR_EN (0X00100000U)
  2783. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_HL_WDT_SHIFT (19U)
  2784. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_HL_WDT_CLRMSK (0XFFF7FFFFU)
  2785. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_HL_WDT_EN (0X00080000U)
  2786. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_AXI_ERROR_SHIFT (18U)
  2787. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_AXI_ERROR_CLRMSK (0XFFFBFFFFU)
  2788. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_AXI_ERROR_EN (0X00040000U)
  2789. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_MMU_PAGE_FAULT_SHIFT (16U)
  2790. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_MMU_PAGE_FAULT_CLRMSK (0XFFFEFFFFU)
  2791. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_MMU_PAGE_FAULT_EN (0X00010000U)
  2792. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_CNN0_MEM_WDT_SHIFT (3U)
  2793. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_CNN0_MEM_WDT_CLRMSK (0XFFFFFFF7U)
  2794. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_CNN0_MEM_WDT_EN (0X00000008U)
  2795. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_CNN0_ERROR_SHIFT (1U)
  2796. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_CNN0_ERROR_CLRMSK (0XFFFFFFFDU)
  2797. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_CNN0_ERROR_EN (0X00000002U)
  2798. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_CNN0_COMPLETE_SHIFT (0U)
  2799. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_CNN0_COMPLETE_CLRMSK (0XFFFFFFFEU)
  2800. #define VHA_CR_OS0_VHA_EVENT_STATUS_VHA_CNN0_COMPLETE_EN (0X00000001U)
  2801. /*
  2802. Register VHA_CR_OS0_VHA_EVENT_CLEAR
  2803. */
  2804. #define VHA_CR_OS0_VHA_EVENT_CLEAR (0x10098U)
  2805. #define VHA_CR_OS0_VHA_EVENT_CLEAR_MASKFULL (IMG_UINT64_C(0x0000000033FD000B))
  2806. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_MMU_PARITY_ERROR_SHIFT (29U)
  2807. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_MMU_PARITY_ERROR_CLRMSK (0XDFFFFFFFU)
  2808. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_MMU_PARITY_ERROR_EN (0X20000000U)
  2809. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_PARITY_ERROR_SHIFT (28U)
  2810. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_PARITY_ERROR_CLRMSK (0XEFFFFFFFU)
  2811. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_PARITY_ERROR_EN (0X10000000U)
  2812. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_ECC_INIT_DONE_SHIFT (25U)
  2813. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_ECC_INIT_DONE_CLRMSK (0XFDFFFFFFU)
  2814. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_ECC_INIT_DONE_EN (0X02000000U)
  2815. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_ECC_DETECTION_SHIFT (24U)
  2816. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_ECC_DETECTION_CLRMSK (0XFEFFFFFFU)
  2817. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_ECC_DETECTION_EN (0X01000000U)
  2818. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_ECC_CORRECTION_SHIFT (23U)
  2819. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_ECC_CORRECTION_CLRMSK (0XFF7FFFFFU)
  2820. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_ECC_CORRECTION_EN (0X00800000U)
  2821. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_LOCKSTEP_ERROR_SHIFT (22U)
  2822. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_LOCKSTEP_ERROR_CLRMSK (0XFFBFFFFFU)
  2823. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_LOCKSTEP_ERROR_EN (0X00400000U)
  2824. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_READY_SHIFT (21U)
  2825. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_READY_CLRMSK (0XFFDFFFFFU)
  2826. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_READY_EN (0X00200000U)
  2827. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_ERROR_SHIFT (20U)
  2828. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_ERROR_CLRMSK (0XFFEFFFFFU)
  2829. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_ERROR_EN (0X00100000U)
  2830. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_HL_WDT_SHIFT (19U)
  2831. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_HL_WDT_CLRMSK (0XFFF7FFFFU)
  2832. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_HL_WDT_EN (0X00080000U)
  2833. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_AXI_ERROR_SHIFT (18U)
  2834. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_AXI_ERROR_CLRMSK (0XFFFBFFFFU)
  2835. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_AXI_ERROR_EN (0X00040000U)
  2836. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_MMU_PAGE_FAULT_SHIFT (16U)
  2837. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_MMU_PAGE_FAULT_CLRMSK (0XFFFEFFFFU)
  2838. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_MMU_PAGE_FAULT_EN (0X00010000U)
  2839. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_CNN0_MEM_WDT_SHIFT (3U)
  2840. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_CNN0_MEM_WDT_CLRMSK (0XFFFFFFF7U)
  2841. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_CNN0_MEM_WDT_EN (0X00000008U)
  2842. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_CNN0_ERROR_SHIFT (1U)
  2843. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_CNN0_ERROR_CLRMSK (0XFFFFFFFDU)
  2844. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_CNN0_ERROR_EN (0X00000002U)
  2845. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_CNN0_COMPLETE_SHIFT (0U)
  2846. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_CNN0_COMPLETE_CLRMSK (0XFFFFFFFEU)
  2847. #define VHA_CR_OS0_VHA_EVENT_CLEAR_VHA_CNN0_COMPLETE_EN (0X00000001U)
  2848. /*
  2849. Register VHA_CR_OS0_CNN_CRC_CONTROL
  2850. */
  2851. #define VHA_CR_OS0_CNN_CRC_CONTROL (0x10100U)
  2852. #define VHA_CR_OS0_CNN_CRC_CONTROL_MASKFULL (IMG_UINT64_C(0x0000000000000003))
  2853. #define VHA_CR_OS0_CNN_CRC_CONTROL_CNN_CRC_ENABLE_SHIFT (0U)
  2854. #define VHA_CR_OS0_CNN_CRC_CONTROL_CNN_CRC_ENABLE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFC))
  2855. #define VHA_CR_OS0_CNN_CRC_CONTROL_CNN_CRC_ENABLE_DISABLE (IMG_UINT64_C(0000000000000000))
  2856. #define VHA_CR_OS0_CNN_CRC_CONTROL_CNN_CRC_ENABLE_STREAM (IMG_UINT64_C(0x0000000000000001))
  2857. #define VHA_CR_OS0_CNN_CRC_CONTROL_CNN_CRC_ENABLE_LAYER (IMG_UINT64_C(0x0000000000000002))
  2858. #define VHA_CR_OS0_CNN_CRC_CONTROL_CNN_CRC_ENABLE_PASS (IMG_UINT64_C(0x0000000000000003))
  2859. /*
  2860. Register VHA_CR_OS0_CNN_CRC_ADDRESS
  2861. */
  2862. #define VHA_CR_OS0_CNN_CRC_ADDRESS (0x10108U)
  2863. #define VHA_CR_OS0_CNN_CRC_ADDRESS_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFF80))
  2864. #define VHA_CR_OS0_CNN_CRC_ADDRESS_CNN_CRC_ADDR_SHIFT (7U)
  2865. #define VHA_CR_OS0_CNN_CRC_ADDRESS_CNN_CRC_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF000000007F))
  2866. #define VHA_CR_OS0_CNN_CRC_ADDRESS_CNN_CRC_ADDR_ALIGNSHIFT (7U)
  2867. #define VHA_CR_OS0_CNN_CRC_ADDRESS_CNN_CRC_ADDR_ALIGNSIZE (128U)
  2868. /*
  2869. Register VHA_CR_OS0_CNN_DEBUG_ADDRESS
  2870. */
  2871. #define VHA_CR_OS0_CNN_DEBUG_ADDRESS (0x10110U)
  2872. #define VHA_CR_OS0_CNN_DEBUG_ADDRESS_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFF80))
  2873. #define VHA_CR_OS0_CNN_DEBUG_ADDRESS_CNN_DEBUG_ADDR_SHIFT (7U)
  2874. #define VHA_CR_OS0_CNN_DEBUG_ADDRESS_CNN_DEBUG_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF000000007F))
  2875. #define VHA_CR_OS0_CNN_DEBUG_ADDRESS_CNN_DEBUG_ADDR_ALIGNSHIFT (7U)
  2876. #define VHA_CR_OS0_CNN_DEBUG_ADDRESS_CNN_DEBUG_ADDR_ALIGNSIZE (128U)
  2877. /*
  2878. Register VHA_CR_OS0_CNN_DEBUG_SIZE
  2879. */
  2880. #define VHA_CR_OS0_CNN_DEBUG_SIZE (0x10118U)
  2881. #define VHA_CR_OS0_CNN_DEBUG_SIZE_MASKFULL (IMG_UINT64_C(0x0000000000FFFFE0))
  2882. #define VHA_CR_OS0_CNN_DEBUG_SIZE_CNN_DEBUG_SIZE_SHIFT (5U)
  2883. #define VHA_CR_OS0_CNN_DEBUG_SIZE_CNN_DEBUG_SIZE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF00001F))
  2884. #define VHA_CR_OS0_CNN_DEBUG_SIZE_CNN_DEBUG_SIZE_ALIGNSHIFT (5U)
  2885. #define VHA_CR_OS0_CNN_DEBUG_SIZE_CNN_DEBUG_SIZE_ALIGNSIZE (32U)
  2886. /*
  2887. Register VHA_CR_OS0_CNN_DEBUG_CONTROL
  2888. */
  2889. #define VHA_CR_OS0_CNN_DEBUG_CONTROL (0x10120U)
  2890. #define VHA_CR_OS0_CNN_DEBUG_CONTROL_MASKFULL (IMG_UINT64_C(0x000000000000000F))
  2891. #define VHA_CR_OS0_CNN_DEBUG_CONTROL_CNN_PERF_ENABLE_SHIFT (2U)
  2892. #define VHA_CR_OS0_CNN_DEBUG_CONTROL_CNN_PERF_ENABLE_CLRMSK (0XFFFFFFF3U)
  2893. #define VHA_CR_OS0_CNN_DEBUG_CONTROL_CNN_PERF_ENABLE_DISABLE (00000000U)
  2894. #define VHA_CR_OS0_CNN_DEBUG_CONTROL_CNN_PERF_ENABLE_STREAM (0X00000004U)
  2895. #define VHA_CR_OS0_CNN_DEBUG_CONTROL_CNN_PERF_ENABLE_LAYER (0X00000008U)
  2896. #define VHA_CR_OS0_CNN_DEBUG_CONTROL_CNN_PERF_ENABLE_PASS (0X0000000CU)
  2897. #define VHA_CR_OS0_CNN_DEBUG_CONTROL_CNN_BAND_ENABLE_SHIFT (0U)
  2898. #define VHA_CR_OS0_CNN_DEBUG_CONTROL_CNN_BAND_ENABLE_CLRMSK (0XFFFFFFFCU)
  2899. #define VHA_CR_OS0_CNN_DEBUG_CONTROL_CNN_BAND_ENABLE_DISABLE (00000000U)
  2900. #define VHA_CR_OS0_CNN_DEBUG_CONTROL_CNN_BAND_ENABLE_STREAM (0X00000001U)
  2901. #define VHA_CR_OS0_CNN_DEBUG_CONTROL_CNN_BAND_ENABLE_LAYER (0X00000002U)
  2902. #define VHA_CR_OS0_CNN_DEBUG_CONTROL_CNN_BAND_ENABLE_PASS (0X00000003U)
  2903. /*
  2904. Register VHA_CR_OS0_CNN_DEBUG_STATUS
  2905. */
  2906. #define VHA_CR_OS0_CNN_DEBUG_STATUS (0x10128U)
  2907. #define VHA_CR_OS0_CNN_DEBUG_STATUS_MASKFULL (IMG_UINT64_C(0x000000000007FFFF))
  2908. #define VHA_CR_OS0_CNN_DEBUG_STATUS_CNN_DEBUG_OFFSET_SHIFT (0U)
  2909. #define VHA_CR_OS0_CNN_DEBUG_STATUS_CNN_DEBUG_OFFSET_CLRMSK (0XFFF80000U)
  2910. /*
  2911. Register VHA_CR_OS0_CNN_PRELOAD_CONTROL
  2912. */
  2913. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL (0x10130U)
  2914. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MASKFULL (IMG_UINT64_C(0x0000000001FF7777))
  2915. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_SHIFT (22U)
  2916. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFE3FFFFF))
  2917. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_DISABLE (IMG_UINT64_C(0000000000000000))
  2918. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_N_64 (IMG_UINT64_C(0x0000000000400000))
  2919. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_N_128 (IMG_UINT64_C(0x0000000000800000))
  2920. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_N_192 (IMG_UINT64_C(0x0000000000c00000))
  2921. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_N_256 (IMG_UINT64_C(0x0000000001000000))
  2922. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_N_320 (IMG_UINT64_C(0x0000000001400000))
  2923. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_N_384 (IMG_UINT64_C(0x0000000001800000))
  2924. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_N_448 (IMG_UINT64_C(0x0000000001c00000))
  2925. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_SHIFT (19U)
  2926. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFC7FFFF))
  2927. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_DISABLE (IMG_UINT64_C(0000000000000000))
  2928. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_N_64 (IMG_UINT64_C(0x0000000000080000))
  2929. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_N_128 (IMG_UINT64_C(0x0000000000100000))
  2930. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_N_192 (IMG_UINT64_C(0x0000000000180000))
  2931. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_N_256 (IMG_UINT64_C(0x0000000000200000))
  2932. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_N_320 (IMG_UINT64_C(0x0000000000280000))
  2933. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_N_384 (IMG_UINT64_C(0x0000000000300000))
  2934. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_N_448 (IMG_UINT64_C(0x0000000000380000))
  2935. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_SHIFT (16U)
  2936. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF8FFFF))
  2937. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_DISABLE (IMG_UINT64_C(0000000000000000))
  2938. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_N_64 (IMG_UINT64_C(0x0000000000010000))
  2939. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_N_128 (IMG_UINT64_C(0x0000000000020000))
  2940. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_N_192 (IMG_UINT64_C(0x0000000000030000))
  2941. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_N_256 (IMG_UINT64_C(0x0000000000040000))
  2942. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_N_320 (IMG_UINT64_C(0x0000000000050000))
  2943. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_N_384 (IMG_UINT64_C(0x0000000000060000))
  2944. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_N_448 (IMG_UINT64_C(0x0000000000070000))
  2945. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_EWO_N_REQS_SHIFT (12U)
  2946. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_EWO_N_REQS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF8FFF))
  2947. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_EWO_N_REQS_DISABLE (IMG_UINT64_C(0000000000000000))
  2948. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_EWO_N_REQS_N_64 (IMG_UINT64_C(0x0000000000001000))
  2949. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_EWO_N_REQS_N_128 (IMG_UINT64_C(0x0000000000002000))
  2950. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_EWO_N_REQS_N_192 (IMG_UINT64_C(0x0000000000003000))
  2951. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_EWO_N_REQS_N_256 (IMG_UINT64_C(0x0000000000004000))
  2952. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_EWO_N_REQS_N_320 (IMG_UINT64_C(0x0000000000005000))
  2953. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_EWO_N_REQS_N_384 (IMG_UINT64_C(0x0000000000006000))
  2954. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_EWO_N_REQS_N_448 (IMG_UINT64_C(0x0000000000007000))
  2955. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_ABUF_N_REQS_SHIFT (8U)
  2956. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_ABUF_N_REQS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF8FF))
  2957. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_ABUF_N_REQS_DISABLE (IMG_UINT64_C(0000000000000000))
  2958. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_ABUF_N_REQS_N_64 (IMG_UINT64_C(0x0000000000000100))
  2959. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_ABUF_N_REQS_N_128 (IMG_UINT64_C(0x0000000000000200))
  2960. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_ABUF_N_REQS_N_192 (IMG_UINT64_C(0x0000000000000300))
  2961. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_ABUF_N_REQS_N_256 (IMG_UINT64_C(0x0000000000000400))
  2962. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_ABUF_N_REQS_N_320 (IMG_UINT64_C(0x0000000000000500))
  2963. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_ABUF_N_REQS_N_384 (IMG_UINT64_C(0x0000000000000600))
  2964. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_ABUF_N_REQS_N_448 (IMG_UINT64_C(0x0000000000000700))
  2965. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_CBUF_N_REQS_SHIFT (4U)
  2966. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_CBUF_N_REQS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFF8F))
  2967. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_CBUF_N_REQS_DISABLE (IMG_UINT64_C(0000000000000000))
  2968. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_CBUF_N_REQS_N_64 (IMG_UINT64_C(0x0000000000000010))
  2969. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_CBUF_N_REQS_N_128 (IMG_UINT64_C(0x0000000000000020))
  2970. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_CBUF_N_REQS_N_192 (IMG_UINT64_C(0x0000000000000030))
  2971. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_CBUF_N_REQS_N_256 (IMG_UINT64_C(0x0000000000000040))
  2972. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_CBUF_N_REQS_N_320 (IMG_UINT64_C(0x0000000000000050))
  2973. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_CBUF_N_REQS_N_384 (IMG_UINT64_C(0x0000000000000060))
  2974. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_CBUF_N_REQS_N_448 (IMG_UINT64_C(0x0000000000000070))
  2975. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_IBUF_N_REQS_SHIFT (0U)
  2976. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_IBUF_N_REQS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF8))
  2977. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_IBUF_N_REQS_DISABLE (IMG_UINT64_C(0000000000000000))
  2978. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_IBUF_N_REQS_N_64 (IMG_UINT64_C(0x0000000000000001))
  2979. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_IBUF_N_REQS_N_128 (IMG_UINT64_C(0x0000000000000002))
  2980. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_IBUF_N_REQS_N_192 (IMG_UINT64_C(0x0000000000000003))
  2981. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_IBUF_N_REQS_N_256 (IMG_UINT64_C(0x0000000000000004))
  2982. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_IBUF_N_REQS_N_320 (IMG_UINT64_C(0x0000000000000005))
  2983. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_IBUF_N_REQS_N_384 (IMG_UINT64_C(0x0000000000000006))
  2984. #define VHA_CR_OS0_CNN_PRELOAD_CONTROL_IBUF_N_REQS_N_448 (IMG_UINT64_C(0x0000000000000007))
  2985. /*
  2986. Register VHA_CR_OS0_CNN_ALT_ADDRESS8
  2987. */
  2988. #define VHA_CR_OS0_CNN_ALT_ADDRESS8 (0x10140U)
  2989. #define VHA_CR_OS0_CNN_ALT_ADDRESS8_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  2990. #define VHA_CR_OS0_CNN_ALT_ADDRESS8_ALT_ADDR_SHIFT (0U)
  2991. #define VHA_CR_OS0_CNN_ALT_ADDRESS8_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  2992. /*
  2993. Register VHA_CR_OS0_CNN_ALT_ADDRESS9
  2994. */
  2995. #define VHA_CR_OS0_CNN_ALT_ADDRESS9 (0x10148U)
  2996. #define VHA_CR_OS0_CNN_ALT_ADDRESS9_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  2997. #define VHA_CR_OS0_CNN_ALT_ADDRESS9_ALT_ADDR_SHIFT (0U)
  2998. #define VHA_CR_OS0_CNN_ALT_ADDRESS9_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  2999. /*
  3000. Register VHA_CR_OS0_CNN_ALT_ADDRESS10
  3001. */
  3002. #define VHA_CR_OS0_CNN_ALT_ADDRESS10 (0x10150U)
  3003. #define VHA_CR_OS0_CNN_ALT_ADDRESS10_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  3004. #define VHA_CR_OS0_CNN_ALT_ADDRESS10_ALT_ADDR_SHIFT (0U)
  3005. #define VHA_CR_OS0_CNN_ALT_ADDRESS10_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  3006. /*
  3007. Register VHA_CR_OS0_CNN_ALT_ADDRESS11
  3008. */
  3009. #define VHA_CR_OS0_CNN_ALT_ADDRESS11 (0x10158U)
  3010. #define VHA_CR_OS0_CNN_ALT_ADDRESS11_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  3011. #define VHA_CR_OS0_CNN_ALT_ADDRESS11_ALT_ADDR_SHIFT (0U)
  3012. #define VHA_CR_OS0_CNN_ALT_ADDRESS11_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  3013. /*
  3014. Register VHA_CR_OS0_CNN_ALT_ADDRESS12
  3015. */
  3016. #define VHA_CR_OS0_CNN_ALT_ADDRESS12 (0x10160U)
  3017. #define VHA_CR_OS0_CNN_ALT_ADDRESS12_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  3018. #define VHA_CR_OS0_CNN_ALT_ADDRESS12_ALT_ADDR_SHIFT (0U)
  3019. #define VHA_CR_OS0_CNN_ALT_ADDRESS12_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  3020. /*
  3021. Register VHA_CR_OS0_CNN_ALT_ADDRESS13
  3022. */
  3023. #define VHA_CR_OS0_CNN_ALT_ADDRESS13 (0x10168U)
  3024. #define VHA_CR_OS0_CNN_ALT_ADDRESS13_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  3025. #define VHA_CR_OS0_CNN_ALT_ADDRESS13_ALT_ADDR_SHIFT (0U)
  3026. #define VHA_CR_OS0_CNN_ALT_ADDRESS13_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  3027. /*
  3028. Register VHA_CR_OS0_CNN_ALT_ADDRESS14
  3029. */
  3030. #define VHA_CR_OS0_CNN_ALT_ADDRESS14 (0x10170U)
  3031. #define VHA_CR_OS0_CNN_ALT_ADDRESS14_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  3032. #define VHA_CR_OS0_CNN_ALT_ADDRESS14_ALT_ADDR_SHIFT (0U)
  3033. #define VHA_CR_OS0_CNN_ALT_ADDRESS14_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  3034. /*
  3035. Register VHA_CR_OS0_CNN_ALT_ADDRESS15
  3036. */
  3037. #define VHA_CR_OS0_CNN_ALT_ADDRESS15 (0x10178U)
  3038. #define VHA_CR_OS0_CNN_ALT_ADDRESS15_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  3039. #define VHA_CR_OS0_CNN_ALT_ADDRESS15_ALT_ADDR_SHIFT (0U)
  3040. #define VHA_CR_OS0_CNN_ALT_ADDRESS15_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  3041. /*
  3042. Register VHA_CR_OS0_CNN_PERFORMANCE
  3043. */
  3044. #define VHA_CR_OS0_CNN_PERFORMANCE (0x101A0U)
  3045. #define VHA_CR_OS0_CNN_PERFORMANCE_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  3046. #define VHA_CR_OS0_CNN_PERFORMANCE_VALUE_SHIFT (0U)
  3047. #define VHA_CR_OS0_CNN_PERFORMANCE_VALUE_CLRMSK (00000000U)
  3048. /*
  3049. Register VHA_CR_OS0_OCM_BASE_ADDR
  3050. */
  3051. #define VHA_CR_OS0_OCM_BASE_ADDR (0x10200U)
  3052. #define VHA_CR_OS0_OCM_BASE_ADDR_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  3053. #define VHA_CR_OS0_OCM_BASE_ADDR_BASE_ADDR_SHIFT (0U)
  3054. #define VHA_CR_OS0_OCM_BASE_ADDR_BASE_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  3055. /*
  3056. Register VHA_CR_OS0_SAVE_RESTORE_BUFFER_BASE_ADDR
  3057. */
  3058. #define VHA_CR_OS0_SAVE_RESTORE_BUFFER_BASE_ADDR (0x10208U)
  3059. #define VHA_CR_OS0_SAVE_RESTORE_BUFFER_BASE_ADDR_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  3060. #define VHA_CR_OS0_SAVE_RESTORE_BUFFER_BASE_ADDR_BASE_ADDR_SHIFT (0U)
  3061. #define VHA_CR_OS0_SAVE_RESTORE_BUFFER_BASE_ADDR_BASE_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  3062. /*
  3063. Register VHA_CR_OS0_SAVE_RESTORE_CTRL
  3064. */
  3065. #define VHA_CR_OS0_SAVE_RESTORE_CTRL (0x10210U)
  3066. #define VHA_CR_OS0_SAVE_RESTORE_CTRL_MASKFULL (IMG_UINT64_C(0x000000000000000F))
  3067. #define VHA_CR_OS0_SAVE_RESTORE_CTRL_N_REQS_SHIFT (1U)
  3068. #define VHA_CR_OS0_SAVE_RESTORE_CTRL_N_REQS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF1))
  3069. #define VHA_CR_OS0_SAVE_RESTORE_CTRL_N_REQS_DISABLE (IMG_UINT64_C(0000000000000000))
  3070. #define VHA_CR_OS0_SAVE_RESTORE_CTRL_N_REQS_N_64 (IMG_UINT64_C(0x0000000000000002))
  3071. #define VHA_CR_OS0_SAVE_RESTORE_CTRL_N_REQS_N_128 (IMG_UINT64_C(0x0000000000000004))
  3072. #define VHA_CR_OS0_SAVE_RESTORE_CTRL_N_REQS_N_192 (IMG_UINT64_C(0x0000000000000006))
  3073. #define VHA_CR_OS0_SAVE_RESTORE_CTRL_N_REQS_N_256 (IMG_UINT64_C(0x0000000000000008))
  3074. #define VHA_CR_OS0_SAVE_RESTORE_CTRL_N_REQS_N_320 (IMG_UINT64_C(0x000000000000000a))
  3075. #define VHA_CR_OS0_SAVE_RESTORE_CTRL_N_REQS_N_384 (IMG_UINT64_C(0x000000000000000c))
  3076. #define VHA_CR_OS0_SAVE_RESTORE_CTRL_N_REQS_N_448 (IMG_UINT64_C(0x000000000000000e))
  3077. #define VHA_CR_OS0_SAVE_RESTORE_CTRL_WRITE_CACHE_POLICY_SHIFT (0U)
  3078. #define VHA_CR_OS0_SAVE_RESTORE_CTRL_WRITE_CACHE_POLICY_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  3079. #define VHA_CR_OS0_SAVE_RESTORE_CTRL_WRITE_CACHE_POLICY_EN (IMG_UINT64_C(0X0000000000000001))
  3080. /*
  3081. Register VHA_CR_OS0_CNN_CRC_MASK_CTRL
  3082. */
  3083. #define VHA_CR_OS0_CNN_CRC_MASK_CTRL (0x10300U)
  3084. #define VHA_CR_OS0_CNN_CRC_MASK_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000000003))
  3085. #define VHA_CR_OS0_CNN_CRC_MASK_CTRL_LEVEL_SHIFT (0U)
  3086. #define VHA_CR_OS0_CNN_CRC_MASK_CTRL_LEVEL_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFC))
  3087. #define VHA_CR_OS0_CNN_CRC_MASK_CTRL_LEVEL_NO_MASK (IMG_UINT64_C(0000000000000000))
  3088. #define VHA_CR_OS0_CNN_CRC_MASK_CTRL_LEVEL_MASK_L1 (IMG_UINT64_C(0x0000000000000001))
  3089. #define VHA_CR_OS0_CNN_CRC_MASK_CTRL_LEVEL_MASK_L2 (IMG_UINT64_C(0x0000000000000002))
  3090. #define VHA_CR_OS0_CNN_CRC_MASK_CTRL_LEVEL_MASK_L3 (IMG_UINT64_C(0x0000000000000003))
  3091. /*
  3092. Register VHA_CR_OS0_MMU_CTRL_INVAL
  3093. */
  3094. #define VHA_CR_OS0_MMU_CTRL_INVAL (0x1E000U)
  3095. #define VHA_CR_OS0_MMU_CTRL_INVAL_MASKFULL (IMG_UINT64_C(0x0000000000000FFF))
  3096. #define VHA_CR_OS0_MMU_CTRL_INVAL_ALL_CONTEXTS_SHIFT (11U)
  3097. #define VHA_CR_OS0_MMU_CTRL_INVAL_ALL_CONTEXTS_CLRMSK (0XFFFFF7FFU)
  3098. #define VHA_CR_OS0_MMU_CTRL_INVAL_ALL_CONTEXTS_EN (0X00000800U)
  3099. #define VHA_CR_OS0_MMU_CTRL_INVAL_CONTEXT_SHIFT (3U)
  3100. #define VHA_CR_OS0_MMU_CTRL_INVAL_CONTEXT_CLRMSK (0XFFFFF807U)
  3101. #define VHA_CR_OS0_MMU_CTRL_INVAL_PC_SHIFT (2U)
  3102. #define VHA_CR_OS0_MMU_CTRL_INVAL_PC_CLRMSK (0XFFFFFFFBU)
  3103. #define VHA_CR_OS0_MMU_CTRL_INVAL_PC_EN (0X00000004U)
  3104. #define VHA_CR_OS0_MMU_CTRL_INVAL_PD_SHIFT (1U)
  3105. #define VHA_CR_OS0_MMU_CTRL_INVAL_PD_CLRMSK (0XFFFFFFFDU)
  3106. #define VHA_CR_OS0_MMU_CTRL_INVAL_PD_EN (0X00000002U)
  3107. #define VHA_CR_OS0_MMU_CTRL_INVAL_PT_SHIFT (0U)
  3108. #define VHA_CR_OS0_MMU_CTRL_INVAL_PT_CLRMSK (0XFFFFFFFEU)
  3109. #define VHA_CR_OS0_MMU_CTRL_INVAL_PT_EN (0X00000001U)
  3110. /*
  3111. Register VHA_CR_OS0_MMU_CTRL_INVAL_STATUS
  3112. */
  3113. #define VHA_CR_OS0_MMU_CTRL_INVAL_STATUS (0x1E038U)
  3114. #define VHA_CR_OS0_MMU_CTRL_INVAL_STATUS_MASKFULL (IMG_UINT64_C(0x0000000080000001))
  3115. #define VHA_CR_OS0_MMU_CTRL_INVAL_STATUS_PARITY_SHIFT (31U)
  3116. #define VHA_CR_OS0_MMU_CTRL_INVAL_STATUS_PARITY_CLRMSK (0X7FFFFFFFU)
  3117. #define VHA_CR_OS0_MMU_CTRL_INVAL_STATUS_PARITY_EN (0X80000000U)
  3118. #define VHA_CR_OS0_MMU_CTRL_INVAL_STATUS_PENDING_SHIFT (0U)
  3119. #define VHA_CR_OS0_MMU_CTRL_INVAL_STATUS_PENDING_CLRMSK (0XFFFFFFFEU)
  3120. #define VHA_CR_OS0_MMU_CTRL_INVAL_STATUS_PENDING_EN (0X00000001U)
  3121. /*
  3122. Register VHA_CR_OS0_MMU_CBASE_MAPPING_CONTEXT
  3123. */
  3124. #define VHA_CR_OS0_MMU_CBASE_MAPPING_CONTEXT (0x1E008U)
  3125. #define VHA_CR_OS0_MMU_CBASE_MAPPING_CONTEXT_MASKFULL (IMG_UINT64_C(0x00000000000000FF))
  3126. #define VHA_CR_OS0_MMU_CBASE_MAPPING_CONTEXT_ID_SHIFT (0U)
  3127. #define VHA_CR_OS0_MMU_CBASE_MAPPING_CONTEXT_ID_CLRMSK (0XFFFFFF00U)
  3128. /*
  3129. Register VHA_CR_OS0_MMU_CBASE_MAPPING
  3130. */
  3131. #define VHA_CR_OS0_MMU_CBASE_MAPPING (0x1E010U)
  3132. #define VHA_CR_OS0_MMU_CBASE_MAPPING_MASKFULL (IMG_UINT64_C(0x000000001FFFFFFF))
  3133. #define VHA_CR_OS0_MMU_CBASE_MAPPING_INVALID_SHIFT (28U)
  3134. #define VHA_CR_OS0_MMU_CBASE_MAPPING_INVALID_CLRMSK (0XEFFFFFFFU)
  3135. #define VHA_CR_OS0_MMU_CBASE_MAPPING_INVALID_EN (0X10000000U)
  3136. #define VHA_CR_OS0_MMU_CBASE_MAPPING_BASE_ADDR_SHIFT (0U)
  3137. #define VHA_CR_OS0_MMU_CBASE_MAPPING_BASE_ADDR_CLRMSK (0XF0000000U)
  3138. #define VHA_CR_OS0_MMU_CBASE_MAPPING_BASE_ADDR_ALIGNSHIFT (12U)
  3139. #define VHA_CR_OS0_MMU_CBASE_MAPPING_BASE_ADDR_ALIGNSIZE (4096U)
  3140. /*
  3141. Register VHA_CR_OS0_MMU_FAULT_STATUS1
  3142. */
  3143. #define VHA_CR_OS0_MMU_FAULT_STATUS1 (0x1E018U)
  3144. #define VHA_CR_OS0_MMU_FAULT_STATUS1_MASKFULL (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
  3145. #define VHA_CR_OS0_MMU_FAULT_STATUS1_LEVEL_SHIFT (62U)
  3146. #define VHA_CR_OS0_MMU_FAULT_STATUS1_LEVEL_CLRMSK (IMG_UINT64_C(0X3FFFFFFFFFFFFFFF))
  3147. #define VHA_CR_OS0_MMU_FAULT_STATUS1_REQ_ID_SHIFT (56U)
  3148. #define VHA_CR_OS0_MMU_FAULT_STATUS1_REQ_ID_CLRMSK (IMG_UINT64_C(0XC0FFFFFFFFFFFFFF))
  3149. #define VHA_CR_OS0_MMU_FAULT_STATUS1_CONTEXT_SHIFT (48U)
  3150. #define VHA_CR_OS0_MMU_FAULT_STATUS1_CONTEXT_CLRMSK (IMG_UINT64_C(0XFF00FFFFFFFFFFFF))
  3151. #define VHA_CR_OS0_MMU_FAULT_STATUS1_ADDRESS_SHIFT (4U)
  3152. #define VHA_CR_OS0_MMU_FAULT_STATUS1_ADDRESS_CLRMSK (IMG_UINT64_C(0XFFFF00000000000F))
  3153. #define VHA_CR_OS0_MMU_FAULT_STATUS1_RNW_SHIFT (3U)
  3154. #define VHA_CR_OS0_MMU_FAULT_STATUS1_RNW_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF7))
  3155. #define VHA_CR_OS0_MMU_FAULT_STATUS1_RNW_EN (IMG_UINT64_C(0X0000000000000008))
  3156. #define VHA_CR_OS0_MMU_FAULT_STATUS1_TYPE_SHIFT (1U)
  3157. #define VHA_CR_OS0_MMU_FAULT_STATUS1_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF9))
  3158. #define VHA_CR_OS0_MMU_FAULT_STATUS1_FAULT_SHIFT (0U)
  3159. #define VHA_CR_OS0_MMU_FAULT_STATUS1_FAULT_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  3160. #define VHA_CR_OS0_MMU_FAULT_STATUS1_FAULT_EN (IMG_UINT64_C(0X0000000000000001))
  3161. /*
  3162. Register VHA_CR_OS0_MMU_FAULT_STATUS2
  3163. */
  3164. #define VHA_CR_OS0_MMU_FAULT_STATUS2 (0x1E020U)
  3165. #define VHA_CR_OS0_MMU_FAULT_STATUS2_MASKFULL (IMG_UINT64_C(0x000000003FFF07FF))
  3166. #define VHA_CR_OS0_MMU_FAULT_STATUS2_WRITEBACK_SHIFT (29U)
  3167. #define VHA_CR_OS0_MMU_FAULT_STATUS2_WRITEBACK_CLRMSK (0XDFFFFFFFU)
  3168. #define VHA_CR_OS0_MMU_FAULT_STATUS2_WRITEBACK_EN (0X20000000U)
  3169. #define VHA_CR_OS0_MMU_FAULT_STATUS2_CLEANUNIQUE_SHIFT (28U)
  3170. #define VHA_CR_OS0_MMU_FAULT_STATUS2_CLEANUNIQUE_CLRMSK (0XEFFFFFFFU)
  3171. #define VHA_CR_OS0_MMU_FAULT_STATUS2_CLEANUNIQUE_EN (0X10000000U)
  3172. #define VHA_CR_OS0_MMU_FAULT_STATUS2_BANK_SHIFT (24U)
  3173. #define VHA_CR_OS0_MMU_FAULT_STATUS2_BANK_CLRMSK (0XF0FFFFFFU)
  3174. #define VHA_CR_OS0_MMU_FAULT_STATUS2_TLB_ENTRY_SHIFT (16U)
  3175. #define VHA_CR_OS0_MMU_FAULT_STATUS2_TLB_ENTRY_CLRMSK (0XFF00FFFFU)
  3176. #define VHA_CR_OS0_MMU_FAULT_STATUS2_FBM_FAULT_SHIFT (10U)
  3177. #define VHA_CR_OS0_MMU_FAULT_STATUS2_FBM_FAULT_CLRMSK (0XFFFFFBFFU)
  3178. #define VHA_CR_OS0_MMU_FAULT_STATUS2_FBM_FAULT_EN (0X00000400U)
  3179. #define VHA_CR_OS0_MMU_FAULT_STATUS2_BIF_ID_SHIFT (0U)
  3180. #define VHA_CR_OS0_MMU_FAULT_STATUS2_BIF_ID_CLRMSK (0XFFFFFC00U)
  3181. /*
  3182. Register VHA_CR_OS0_MMU_CTRL_LEGACY
  3183. */
  3184. #define VHA_CR_OS0_MMU_CTRL_LEGACY (0x1E040U)
  3185. #define VHA_CR_OS0_MMU_CTRL_LEGACY_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  3186. #define VHA_CR_OS0_MMU_CTRL_LEGACY_RESERVED_SHIFT (0U)
  3187. #define VHA_CR_OS0_MMU_CTRL_LEGACY_RESERVED_CLRMSK (0XFFFFFFFEU)
  3188. #define VHA_CR_OS0_MMU_CTRL_LEGACY_RESERVED_EN (0X00000001U)
  3189. /*
  3190. Register VHA_CR_OS1_CNN_CONTROL
  3191. */
  3192. #define VHA_CR_OS1_CNN_CONTROL (0x20000U)
  3193. #define VHA_CR_OS1_CNN_CONTROL_MASKFULL (IMG_UINT64_C(0x000000000000337F))
  3194. #define VHA_CR_OS1_CNN_CONTROL_CTXT_PASID_SHIFT (12U)
  3195. #define VHA_CR_OS1_CNN_CONTROL_CTXT_PASID_CLRMSK (0XFFFFCFFFU)
  3196. #define VHA_CR_OS1_CNN_CONTROL_PRIORITY_SHIFT (8U)
  3197. #define VHA_CR_OS1_CNN_CONTROL_PRIORITY_CLRMSK (0XFFFFFCFFU)
  3198. #define VHA_CR_OS1_CNN_CONTROL_CMD_SIZE_MIN1_SHIFT (1U)
  3199. #define VHA_CR_OS1_CNN_CONTROL_CMD_SIZE_MIN1_CLRMSK (0XFFFFFF81U)
  3200. #define VHA_CR_OS1_CNN_CONTROL_START_SHIFT (0U)
  3201. #define VHA_CR_OS1_CNN_CONTROL_START_CLRMSK (0XFFFFFFFEU)
  3202. #define VHA_CR_OS1_CNN_CONTROL_START_EN (0X00000001U)
  3203. #define VHA_CR_OS1_CNN_STATUS_STATE_MASK (0x00000003U)
  3204. /*
  3205. No requests are pending for this host*/
  3206. #define VHA_CR_OS1_CNN_STATUS_STATE_IDLE (0x00000000U)
  3207. /*
  3208. A command stream from this host is being processed*/
  3209. #define VHA_CR_OS1_CNN_STATUS_STATE_RUN (0x00000001U)
  3210. /*
  3211. The command stream from this host has been suspended due to higher priority request from another host*/
  3212. #define VHA_CR_OS1_CNN_STATUS_STATE_SUSPEND (0x00000002U)
  3213. /*
  3214. A command stream from this host is pending but not been started */
  3215. #define VHA_CR_OS1_CNN_STATUS_STATE_PENDING (0x00000003U)
  3216. /*
  3217. Register VHA_CR_OS1_CNN_STATUS
  3218. */
  3219. #define VHA_CR_OS1_CNN_STATUS (0x20008U)
  3220. #define VHA_CR_OS1_CNN_STATUS_MASKFULL (IMG_UINT64_C(0x00000000C1FFFFFF))
  3221. #define VHA_CR_OS1_CNN_STATUS_CURRENT_STATE_SHIFT (30U)
  3222. #define VHA_CR_OS1_CNN_STATUS_CURRENT_STATE_CLRMSK (0X3FFFFFFFU)
  3223. #define VHA_CR_OS1_CNN_STATUS_CURRENT_STATE_IDLE (00000000U)
  3224. #define VHA_CR_OS1_CNN_STATUS_CURRENT_STATE_RUN (0X40000000U)
  3225. #define VHA_CR_OS1_CNN_STATUS_CURRENT_STATE_SUSPEND (0X80000000U)
  3226. #define VHA_CR_OS1_CNN_STATUS_CURRENT_STATE_PENDING (0XC0000000U)
  3227. #define VHA_CR_OS1_CNN_STATUS_PARITY_SHIFT (24U)
  3228. #define VHA_CR_OS1_CNN_STATUS_PARITY_CLRMSK (0XFEFFFFFFU)
  3229. #define VHA_CR_OS1_CNN_STATUS_PARITY_EN (0X01000000U)
  3230. #define VHA_CR_OS1_CNN_STATUS_LAYER_COUNT_SHIFT (8U)
  3231. #define VHA_CR_OS1_CNN_STATUS_LAYER_COUNT_CLRMSK (0XFF0000FFU)
  3232. #define VHA_CR_OS1_CNN_STATUS_STREAM_COUNT_SHIFT (0U)
  3233. #define VHA_CR_OS1_CNN_STATUS_STREAM_COUNT_CLRMSK (0XFFFFFF00U)
  3234. /*
  3235. Register VHA_CR_OS1_CNN_STATUS2
  3236. */
  3237. #define VHA_CR_OS1_CNN_STATUS2 (0x20010U)
  3238. #define VHA_CR_OS1_CNN_STATUS2_MASKFULL (IMG_UINT64_C(0x000000000001FFFF))
  3239. #define VHA_CR_OS1_CNN_STATUS2_PASS_COUNT_SHIFT (0U)
  3240. #define VHA_CR_OS1_CNN_STATUS2_PASS_COUNT_CLRMSK (0XFFFE0000U)
  3241. /*
  3242. Register VHA_CR_OS1_CNN_CMD_BASE_ADDRESS
  3243. */
  3244. #define VHA_CR_OS1_CNN_CMD_BASE_ADDRESS (0x20020U)
  3245. #define VHA_CR_OS1_CNN_CMD_BASE_ADDRESS_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFF80))
  3246. #define VHA_CR_OS1_CNN_CMD_BASE_ADDRESS_BASE_ADDR_SHIFT (7U)
  3247. #define VHA_CR_OS1_CNN_CMD_BASE_ADDRESS_BASE_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF000000007F))
  3248. /*
  3249. Register VHA_CR_OS1_CNN_ALT_ADDRESS_USED
  3250. */
  3251. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED (0x20038U)
  3252. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  3253. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR15_BUF_TYPE_SHIFT (31U)
  3254. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR15_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFF7FFFFFFF))
  3255. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR15_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  3256. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR15_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000080000000))
  3257. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR14_BUF_TYPE_SHIFT (30U)
  3258. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR14_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFBFFFFFFF))
  3259. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR14_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  3260. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR14_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000040000000))
  3261. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR13_BUF_TYPE_SHIFT (29U)
  3262. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR13_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFDFFFFFFF))
  3263. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR13_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  3264. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR13_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000020000000))
  3265. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR12_BUF_TYPE_SHIFT (28U)
  3266. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR12_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFEFFFFFFF))
  3267. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR12_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  3268. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR12_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000010000000))
  3269. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR11_BUF_TYPE_SHIFT (27U)
  3270. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR11_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFF7FFFFFF))
  3271. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR11_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  3272. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR11_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000008000000))
  3273. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR10_BUF_TYPE_SHIFT (26U)
  3274. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR10_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFBFFFFFF))
  3275. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR10_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  3276. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR10_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000004000000))
  3277. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR9_BUF_TYPE_SHIFT (25U)
  3278. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR9_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFDFFFFFF))
  3279. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR9_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  3280. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR9_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000002000000))
  3281. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR8_BUF_TYPE_SHIFT (24U)
  3282. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR8_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFEFFFFFF))
  3283. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR8_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  3284. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR8_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000001000000))
  3285. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR7_BUF_TYPE_SHIFT (23U)
  3286. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR7_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF7FFFFF))
  3287. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR7_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  3288. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR7_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000000800000))
  3289. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR6_BUF_TYPE_SHIFT (22U)
  3290. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR6_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFBFFFFF))
  3291. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR6_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  3292. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR6_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000000400000))
  3293. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR5_BUF_TYPE_SHIFT (21U)
  3294. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR5_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFDFFFFF))
  3295. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR5_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  3296. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR5_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000000200000))
  3297. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR4_BUF_TYPE_SHIFT (20U)
  3298. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR4_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFEFFFFF))
  3299. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR4_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  3300. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR4_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000000100000))
  3301. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR3_BUF_TYPE_SHIFT (19U)
  3302. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR3_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF7FFFF))
  3303. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR3_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  3304. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR3_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000000080000))
  3305. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR2_BUF_TYPE_SHIFT (18U)
  3306. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR2_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFBFFFF))
  3307. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR2_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  3308. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR2_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000000040000))
  3309. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR1_BUF_TYPE_SHIFT (17U)
  3310. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR1_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFDFFFF))
  3311. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR1_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  3312. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR1_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000000020000))
  3313. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR0_BUF_TYPE_SHIFT (16U)
  3314. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR0_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFEFFFF))
  3315. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR0_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  3316. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR0_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000000010000))
  3317. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR15_USED_SHIFT (15U)
  3318. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR15_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF7FFF))
  3319. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR15_USED_EN (IMG_UINT64_C(0X0000000000008000))
  3320. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR14_USED_SHIFT (14U)
  3321. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR14_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFBFFF))
  3322. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR14_USED_EN (IMG_UINT64_C(0X0000000000004000))
  3323. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR13_USED_SHIFT (13U)
  3324. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR13_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFDFFF))
  3325. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR13_USED_EN (IMG_UINT64_C(0X0000000000002000))
  3326. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR12_USED_SHIFT (12U)
  3327. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR12_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFEFFF))
  3328. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR12_USED_EN (IMG_UINT64_C(0X0000000000001000))
  3329. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR11_USED_SHIFT (11U)
  3330. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR11_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF7FF))
  3331. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR11_USED_EN (IMG_UINT64_C(0X0000000000000800))
  3332. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR10_USED_SHIFT (10U)
  3333. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR10_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFBFF))
  3334. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR10_USED_EN (IMG_UINT64_C(0X0000000000000400))
  3335. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR9_USED_SHIFT (9U)
  3336. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR9_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFDFF))
  3337. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR9_USED_EN (IMG_UINT64_C(0X0000000000000200))
  3338. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR8_USED_SHIFT (8U)
  3339. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR8_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFEFF))
  3340. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR8_USED_EN (IMG_UINT64_C(0X0000000000000100))
  3341. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR7_USED_SHIFT (7U)
  3342. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR7_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFF7F))
  3343. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR7_USED_EN (IMG_UINT64_C(0X0000000000000080))
  3344. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR6_USED_SHIFT (6U)
  3345. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR6_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFBF))
  3346. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR6_USED_EN (IMG_UINT64_C(0X0000000000000040))
  3347. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR5_USED_SHIFT (5U)
  3348. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR5_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFDF))
  3349. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR5_USED_EN (IMG_UINT64_C(0X0000000000000020))
  3350. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR4_USED_SHIFT (4U)
  3351. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR4_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFEF))
  3352. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR4_USED_EN (IMG_UINT64_C(0X0000000000000010))
  3353. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR3_USED_SHIFT (3U)
  3354. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR3_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF7))
  3355. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR3_USED_EN (IMG_UINT64_C(0X0000000000000008))
  3356. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR2_USED_SHIFT (2U)
  3357. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR2_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFB))
  3358. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR2_USED_EN (IMG_UINT64_C(0X0000000000000004))
  3359. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR1_USED_SHIFT (1U)
  3360. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR1_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFD))
  3361. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR1_USED_EN (IMG_UINT64_C(0X0000000000000002))
  3362. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR0_USED_SHIFT (0U)
  3363. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR0_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  3364. #define VHA_CR_OS1_CNN_ALT_ADDRESS_USED_ALT_ADDR0_USED_EN (IMG_UINT64_C(0X0000000000000001))
  3365. /*
  3366. Register VHA_CR_OS1_CNN_ALT_ADDRESS0
  3367. */
  3368. #define VHA_CR_OS1_CNN_ALT_ADDRESS0 (0x20040U)
  3369. #define VHA_CR_OS1_CNN_ALT_ADDRESS0_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  3370. #define VHA_CR_OS1_CNN_ALT_ADDRESS0_ALT_ADDR_SHIFT (0U)
  3371. #define VHA_CR_OS1_CNN_ALT_ADDRESS0_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  3372. /*
  3373. Register VHA_CR_OS1_CNN_ALT_ADDRESS1
  3374. */
  3375. #define VHA_CR_OS1_CNN_ALT_ADDRESS1 (0x20048U)
  3376. #define VHA_CR_OS1_CNN_ALT_ADDRESS1_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  3377. #define VHA_CR_OS1_CNN_ALT_ADDRESS1_ALT_ADDR_SHIFT (0U)
  3378. #define VHA_CR_OS1_CNN_ALT_ADDRESS1_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  3379. /*
  3380. Register VHA_CR_OS1_CNN_ALT_ADDRESS2
  3381. */
  3382. #define VHA_CR_OS1_CNN_ALT_ADDRESS2 (0x20050U)
  3383. #define VHA_CR_OS1_CNN_ALT_ADDRESS2_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  3384. #define VHA_CR_OS1_CNN_ALT_ADDRESS2_ALT_ADDR_SHIFT (0U)
  3385. #define VHA_CR_OS1_CNN_ALT_ADDRESS2_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  3386. /*
  3387. Register VHA_CR_OS1_CNN_ALT_ADDRESS3
  3388. */
  3389. #define VHA_CR_OS1_CNN_ALT_ADDRESS3 (0x20058U)
  3390. #define VHA_CR_OS1_CNN_ALT_ADDRESS3_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  3391. #define VHA_CR_OS1_CNN_ALT_ADDRESS3_ALT_ADDR_SHIFT (0U)
  3392. #define VHA_CR_OS1_CNN_ALT_ADDRESS3_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  3393. /*
  3394. Register VHA_CR_OS1_CNN_ALT_ADDRESS4
  3395. */
  3396. #define VHA_CR_OS1_CNN_ALT_ADDRESS4 (0x20060U)
  3397. #define VHA_CR_OS1_CNN_ALT_ADDRESS4_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  3398. #define VHA_CR_OS1_CNN_ALT_ADDRESS4_ALT_ADDR_SHIFT (0U)
  3399. #define VHA_CR_OS1_CNN_ALT_ADDRESS4_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  3400. /*
  3401. Register VHA_CR_OS1_CNN_ALT_ADDRESS5
  3402. */
  3403. #define VHA_CR_OS1_CNN_ALT_ADDRESS5 (0x20068U)
  3404. #define VHA_CR_OS1_CNN_ALT_ADDRESS5_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  3405. #define VHA_CR_OS1_CNN_ALT_ADDRESS5_ALT_ADDR_SHIFT (0U)
  3406. #define VHA_CR_OS1_CNN_ALT_ADDRESS5_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  3407. /*
  3408. Register VHA_CR_OS1_CNN_ALT_ADDRESS6
  3409. */
  3410. #define VHA_CR_OS1_CNN_ALT_ADDRESS6 (0x20070U)
  3411. #define VHA_CR_OS1_CNN_ALT_ADDRESS6_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  3412. #define VHA_CR_OS1_CNN_ALT_ADDRESS6_ALT_ADDR_SHIFT (0U)
  3413. #define VHA_CR_OS1_CNN_ALT_ADDRESS6_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  3414. /*
  3415. Register VHA_CR_OS1_CNN_ALT_ADDRESS7
  3416. */
  3417. #define VHA_CR_OS1_CNN_ALT_ADDRESS7 (0x20078U)
  3418. #define VHA_CR_OS1_CNN_ALT_ADDRESS7_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  3419. #define VHA_CR_OS1_CNN_ALT_ADDRESS7_ALT_ADDR_SHIFT (0U)
  3420. #define VHA_CR_OS1_CNN_ALT_ADDRESS7_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  3421. /*
  3422. Register VHA_CR_OS1_CNN_WRITEBACK_CONTROL
  3423. */
  3424. #define VHA_CR_OS1_CNN_WRITEBACK_CONTROL (0x20080U)
  3425. #define VHA_CR_OS1_CNN_WRITEBACK_CONTROL_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  3426. #define VHA_CR_OS1_CNN_WRITEBACK_CONTROL_WRITE_BACK_VALUE_SHIFT (0U)
  3427. #define VHA_CR_OS1_CNN_WRITEBACK_CONTROL_WRITE_BACK_VALUE_CLRMSK (00000000U)
  3428. /*
  3429. Register VHA_CR_OS1_VHA_EVENT_ENABLE
  3430. */
  3431. #define VHA_CR_OS1_VHA_EVENT_ENABLE (0x20088U)
  3432. #define VHA_CR_OS1_VHA_EVENT_ENABLE_MASKFULL (IMG_UINT64_C(0x0000000033FD000B))
  3433. #define VHA_CR_OS1_VHA_EVENT_ENABLE_VHA_MMU_PARITY_ERROR_SHIFT (29U)
  3434. #define VHA_CR_OS1_VHA_EVENT_ENABLE_VHA_MMU_PARITY_ERROR_CLRMSK (0XDFFFFFFFU)
  3435. #define VHA_CR_OS1_VHA_EVENT_ENABLE_VHA_MMU_PARITY_ERROR_EN (0X20000000U)
  3436. #define VHA_CR_OS1_VHA_EVENT_ENABLE_VHA_PARITY_ERROR_SHIFT (28U)
  3437. #define VHA_CR_OS1_VHA_EVENT_ENABLE_VHA_PARITY_ERROR_CLRMSK (0XEFFFFFFFU)
  3438. #define VHA_CR_OS1_VHA_EVENT_ENABLE_VHA_PARITY_ERROR_EN (0X10000000U)
  3439. #define VHA_CR_OS1_VHA_EVENT_ENABLE_VHA_ECC_INIT_DONE_SHIFT (25U)
  3440. #define VHA_CR_OS1_VHA_EVENT_ENABLE_VHA_ECC_INIT_DONE_CLRMSK (0XFDFFFFFFU)
  3441. #define VHA_CR_OS1_VHA_EVENT_ENABLE_VHA_ECC_INIT_DONE_EN (0X02000000U)
  3442. #define VHA_CR_OS1_VHA_EVENT_ENABLE_VHA_ECC_DETECTION_SHIFT (24U)
  3443. #define VHA_CR_OS1_VHA_EVENT_ENABLE_VHA_ECC_DETECTION_CLRMSK (0XFEFFFFFFU)
  3444. #define VHA_CR_OS1_VHA_EVENT_ENABLE_VHA_ECC_DETECTION_EN (0X01000000U)
  3445. #define VHA_CR_OS1_VHA_EVENT_ENABLE_VHA_ECC_CORRECTION_SHIFT (23U)
  3446. #define VHA_CR_OS1_VHA_EVENT_ENABLE_VHA_ECC_CORRECTION_CLRMSK (0XFF7FFFFFU)
  3447. #define VHA_CR_OS1_VHA_EVENT_ENABLE_VHA_ECC_CORRECTION_EN (0X00800000U)
  3448. #define VHA_CR_OS1_VHA_EVENT_ENABLE_VHA_LOCKSTEP_ERROR_SHIFT (22U)
  3449. #define VHA_CR_OS1_VHA_EVENT_ENABLE_VHA_LOCKSTEP_ERROR_CLRMSK (0XFFBFFFFFU)
  3450. #define VHA_CR_OS1_VHA_EVENT_ENABLE_VHA_LOCKSTEP_ERROR_EN (0X00400000U)
  3451. #define VHA_CR_OS1_VHA_EVENT_ENABLE_VHA_READY_SHIFT (21U)
  3452. #define VHA_CR_OS1_VHA_EVENT_ENABLE_VHA_READY_CLRMSK (0XFFDFFFFFU)
  3453. #define VHA_CR_OS1_VHA_EVENT_ENABLE_VHA_READY_EN (0X00200000U)
  3454. #define VHA_CR_OS1_VHA_EVENT_ENABLE_VHA_ERROR_SHIFT (20U)
  3455. #define VHA_CR_OS1_VHA_EVENT_ENABLE_VHA_ERROR_CLRMSK (0XFFEFFFFFU)
  3456. #define VHA_CR_OS1_VHA_EVENT_ENABLE_VHA_ERROR_EN (0X00100000U)
  3457. #define VHA_CR_OS1_VHA_EVENT_ENABLE_VHA_HL_WDT_SHIFT (19U)
  3458. #define VHA_CR_OS1_VHA_EVENT_ENABLE_VHA_HL_WDT_CLRMSK (0XFFF7FFFFU)
  3459. #define VHA_CR_OS1_VHA_EVENT_ENABLE_VHA_HL_WDT_EN (0X00080000U)
  3460. #define VHA_CR_OS1_VHA_EVENT_ENABLE_VHA_AXI_ERROR_SHIFT (18U)
  3461. #define VHA_CR_OS1_VHA_EVENT_ENABLE_VHA_AXI_ERROR_CLRMSK (0XFFFBFFFFU)
  3462. #define VHA_CR_OS1_VHA_EVENT_ENABLE_VHA_AXI_ERROR_EN (0X00040000U)
  3463. #define VHA_CR_OS1_VHA_EVENT_ENABLE_VHA_MMU_PAGE_FAULT_SHIFT (16U)
  3464. #define VHA_CR_OS1_VHA_EVENT_ENABLE_VHA_MMU_PAGE_FAULT_CLRMSK (0XFFFEFFFFU)
  3465. #define VHA_CR_OS1_VHA_EVENT_ENABLE_VHA_MMU_PAGE_FAULT_EN (0X00010000U)
  3466. #define VHA_CR_OS1_VHA_EVENT_ENABLE_VHA_CNN0_MEM_WDT_SHIFT (3U)
  3467. #define VHA_CR_OS1_VHA_EVENT_ENABLE_VHA_CNN0_MEM_WDT_CLRMSK (0XFFFFFFF7U)
  3468. #define VHA_CR_OS1_VHA_EVENT_ENABLE_VHA_CNN0_MEM_WDT_EN (0X00000008U)
  3469. #define VHA_CR_OS1_VHA_EVENT_ENABLE_VHA_CNN0_ERROR_SHIFT (1U)
  3470. #define VHA_CR_OS1_VHA_EVENT_ENABLE_VHA_CNN0_ERROR_CLRMSK (0XFFFFFFFDU)
  3471. #define VHA_CR_OS1_VHA_EVENT_ENABLE_VHA_CNN0_ERROR_EN (0X00000002U)
  3472. #define VHA_CR_OS1_VHA_EVENT_ENABLE_VHA_CNN0_COMPLETE_SHIFT (0U)
  3473. #define VHA_CR_OS1_VHA_EVENT_ENABLE_VHA_CNN0_COMPLETE_CLRMSK (0XFFFFFFFEU)
  3474. #define VHA_CR_OS1_VHA_EVENT_ENABLE_VHA_CNN0_COMPLETE_EN (0X00000001U)
  3475. /*
  3476. Register VHA_CR_OS1_VHA_EVENT_STATUS
  3477. */
  3478. #define VHA_CR_OS1_VHA_EVENT_STATUS (0x20090U)
  3479. #define VHA_CR_OS1_VHA_EVENT_STATUS_MASKFULL (IMG_UINT64_C(0x00000000B3FD000B))
  3480. #define VHA_CR_OS1_VHA_EVENT_STATUS_PARITY_SHIFT (31U)
  3481. #define VHA_CR_OS1_VHA_EVENT_STATUS_PARITY_CLRMSK (0X7FFFFFFFU)
  3482. #define VHA_CR_OS1_VHA_EVENT_STATUS_PARITY_EN (0X80000000U)
  3483. #define VHA_CR_OS1_VHA_EVENT_STATUS_VHA_MMU_PARITY_ERROR_SHIFT (29U)
  3484. #define VHA_CR_OS1_VHA_EVENT_STATUS_VHA_MMU_PARITY_ERROR_CLRMSK (0XDFFFFFFFU)
  3485. #define VHA_CR_OS1_VHA_EVENT_STATUS_VHA_MMU_PARITY_ERROR_EN (0X20000000U)
  3486. #define VHA_CR_OS1_VHA_EVENT_STATUS_VHA_PARITY_ERROR_SHIFT (28U)
  3487. #define VHA_CR_OS1_VHA_EVENT_STATUS_VHA_PARITY_ERROR_CLRMSK (0XEFFFFFFFU)
  3488. #define VHA_CR_OS1_VHA_EVENT_STATUS_VHA_PARITY_ERROR_EN (0X10000000U)
  3489. #define VHA_CR_OS1_VHA_EVENT_STATUS_VHA_ECC_INIT_DONE_SHIFT (25U)
  3490. #define VHA_CR_OS1_VHA_EVENT_STATUS_VHA_ECC_INIT_DONE_CLRMSK (0XFDFFFFFFU)
  3491. #define VHA_CR_OS1_VHA_EVENT_STATUS_VHA_ECC_INIT_DONE_EN (0X02000000U)
  3492. #define VHA_CR_OS1_VHA_EVENT_STATUS_VHA_ECC_DETECTION_SHIFT (24U)
  3493. #define VHA_CR_OS1_VHA_EVENT_STATUS_VHA_ECC_DETECTION_CLRMSK (0XFEFFFFFFU)
  3494. #define VHA_CR_OS1_VHA_EVENT_STATUS_VHA_ECC_DETECTION_EN (0X01000000U)
  3495. #define VHA_CR_OS1_VHA_EVENT_STATUS_VHA_ECC_CORRECTION_SHIFT (23U)
  3496. #define VHA_CR_OS1_VHA_EVENT_STATUS_VHA_ECC_CORRECTION_CLRMSK (0XFF7FFFFFU)
  3497. #define VHA_CR_OS1_VHA_EVENT_STATUS_VHA_ECC_CORRECTION_EN (0X00800000U)
  3498. #define VHA_CR_OS1_VHA_EVENT_STATUS_VHA_LOCKSTEP_ERROR_SHIFT (22U)
  3499. #define VHA_CR_OS1_VHA_EVENT_STATUS_VHA_LOCKSTEP_ERROR_CLRMSK (0XFFBFFFFFU)
  3500. #define VHA_CR_OS1_VHA_EVENT_STATUS_VHA_LOCKSTEP_ERROR_EN (0X00400000U)
  3501. #define VHA_CR_OS1_VHA_EVENT_STATUS_VHA_READY_SHIFT (21U)
  3502. #define VHA_CR_OS1_VHA_EVENT_STATUS_VHA_READY_CLRMSK (0XFFDFFFFFU)
  3503. #define VHA_CR_OS1_VHA_EVENT_STATUS_VHA_READY_EN (0X00200000U)
  3504. #define VHA_CR_OS1_VHA_EVENT_STATUS_VHA_ERROR_SHIFT (20U)
  3505. #define VHA_CR_OS1_VHA_EVENT_STATUS_VHA_ERROR_CLRMSK (0XFFEFFFFFU)
  3506. #define VHA_CR_OS1_VHA_EVENT_STATUS_VHA_ERROR_EN (0X00100000U)
  3507. #define VHA_CR_OS1_VHA_EVENT_STATUS_VHA_HL_WDT_SHIFT (19U)
  3508. #define VHA_CR_OS1_VHA_EVENT_STATUS_VHA_HL_WDT_CLRMSK (0XFFF7FFFFU)
  3509. #define VHA_CR_OS1_VHA_EVENT_STATUS_VHA_HL_WDT_EN (0X00080000U)
  3510. #define VHA_CR_OS1_VHA_EVENT_STATUS_VHA_AXI_ERROR_SHIFT (18U)
  3511. #define VHA_CR_OS1_VHA_EVENT_STATUS_VHA_AXI_ERROR_CLRMSK (0XFFFBFFFFU)
  3512. #define VHA_CR_OS1_VHA_EVENT_STATUS_VHA_AXI_ERROR_EN (0X00040000U)
  3513. #define VHA_CR_OS1_VHA_EVENT_STATUS_VHA_MMU_PAGE_FAULT_SHIFT (16U)
  3514. #define VHA_CR_OS1_VHA_EVENT_STATUS_VHA_MMU_PAGE_FAULT_CLRMSK (0XFFFEFFFFU)
  3515. #define VHA_CR_OS1_VHA_EVENT_STATUS_VHA_MMU_PAGE_FAULT_EN (0X00010000U)
  3516. #define VHA_CR_OS1_VHA_EVENT_STATUS_VHA_CNN0_MEM_WDT_SHIFT (3U)
  3517. #define VHA_CR_OS1_VHA_EVENT_STATUS_VHA_CNN0_MEM_WDT_CLRMSK (0XFFFFFFF7U)
  3518. #define VHA_CR_OS1_VHA_EVENT_STATUS_VHA_CNN0_MEM_WDT_EN (0X00000008U)
  3519. #define VHA_CR_OS1_VHA_EVENT_STATUS_VHA_CNN0_ERROR_SHIFT (1U)
  3520. #define VHA_CR_OS1_VHA_EVENT_STATUS_VHA_CNN0_ERROR_CLRMSK (0XFFFFFFFDU)
  3521. #define VHA_CR_OS1_VHA_EVENT_STATUS_VHA_CNN0_ERROR_EN (0X00000002U)
  3522. #define VHA_CR_OS1_VHA_EVENT_STATUS_VHA_CNN0_COMPLETE_SHIFT (0U)
  3523. #define VHA_CR_OS1_VHA_EVENT_STATUS_VHA_CNN0_COMPLETE_CLRMSK (0XFFFFFFFEU)
  3524. #define VHA_CR_OS1_VHA_EVENT_STATUS_VHA_CNN0_COMPLETE_EN (0X00000001U)
  3525. /*
  3526. Register VHA_CR_OS1_VHA_EVENT_CLEAR
  3527. */
  3528. #define VHA_CR_OS1_VHA_EVENT_CLEAR (0x20098U)
  3529. #define VHA_CR_OS1_VHA_EVENT_CLEAR_MASKFULL (IMG_UINT64_C(0x0000000033FD000B))
  3530. #define VHA_CR_OS1_VHA_EVENT_CLEAR_VHA_MMU_PARITY_ERROR_SHIFT (29U)
  3531. #define VHA_CR_OS1_VHA_EVENT_CLEAR_VHA_MMU_PARITY_ERROR_CLRMSK (0XDFFFFFFFU)
  3532. #define VHA_CR_OS1_VHA_EVENT_CLEAR_VHA_MMU_PARITY_ERROR_EN (0X20000000U)
  3533. #define VHA_CR_OS1_VHA_EVENT_CLEAR_VHA_PARITY_ERROR_SHIFT (28U)
  3534. #define VHA_CR_OS1_VHA_EVENT_CLEAR_VHA_PARITY_ERROR_CLRMSK (0XEFFFFFFFU)
  3535. #define VHA_CR_OS1_VHA_EVENT_CLEAR_VHA_PARITY_ERROR_EN (0X10000000U)
  3536. #define VHA_CR_OS1_VHA_EVENT_CLEAR_VHA_ECC_INIT_DONE_SHIFT (25U)
  3537. #define VHA_CR_OS1_VHA_EVENT_CLEAR_VHA_ECC_INIT_DONE_CLRMSK (0XFDFFFFFFU)
  3538. #define VHA_CR_OS1_VHA_EVENT_CLEAR_VHA_ECC_INIT_DONE_EN (0X02000000U)
  3539. #define VHA_CR_OS1_VHA_EVENT_CLEAR_VHA_ECC_DETECTION_SHIFT (24U)
  3540. #define VHA_CR_OS1_VHA_EVENT_CLEAR_VHA_ECC_DETECTION_CLRMSK (0XFEFFFFFFU)
  3541. #define VHA_CR_OS1_VHA_EVENT_CLEAR_VHA_ECC_DETECTION_EN (0X01000000U)
  3542. #define VHA_CR_OS1_VHA_EVENT_CLEAR_VHA_ECC_CORRECTION_SHIFT (23U)
  3543. #define VHA_CR_OS1_VHA_EVENT_CLEAR_VHA_ECC_CORRECTION_CLRMSK (0XFF7FFFFFU)
  3544. #define VHA_CR_OS1_VHA_EVENT_CLEAR_VHA_ECC_CORRECTION_EN (0X00800000U)
  3545. #define VHA_CR_OS1_VHA_EVENT_CLEAR_VHA_LOCKSTEP_ERROR_SHIFT (22U)
  3546. #define VHA_CR_OS1_VHA_EVENT_CLEAR_VHA_LOCKSTEP_ERROR_CLRMSK (0XFFBFFFFFU)
  3547. #define VHA_CR_OS1_VHA_EVENT_CLEAR_VHA_LOCKSTEP_ERROR_EN (0X00400000U)
  3548. #define VHA_CR_OS1_VHA_EVENT_CLEAR_VHA_READY_SHIFT (21U)
  3549. #define VHA_CR_OS1_VHA_EVENT_CLEAR_VHA_READY_CLRMSK (0XFFDFFFFFU)
  3550. #define VHA_CR_OS1_VHA_EVENT_CLEAR_VHA_READY_EN (0X00200000U)
  3551. #define VHA_CR_OS1_VHA_EVENT_CLEAR_VHA_ERROR_SHIFT (20U)
  3552. #define VHA_CR_OS1_VHA_EVENT_CLEAR_VHA_ERROR_CLRMSK (0XFFEFFFFFU)
  3553. #define VHA_CR_OS1_VHA_EVENT_CLEAR_VHA_ERROR_EN (0X00100000U)
  3554. #define VHA_CR_OS1_VHA_EVENT_CLEAR_VHA_HL_WDT_SHIFT (19U)
  3555. #define VHA_CR_OS1_VHA_EVENT_CLEAR_VHA_HL_WDT_CLRMSK (0XFFF7FFFFU)
  3556. #define VHA_CR_OS1_VHA_EVENT_CLEAR_VHA_HL_WDT_EN (0X00080000U)
  3557. #define VHA_CR_OS1_VHA_EVENT_CLEAR_VHA_AXI_ERROR_SHIFT (18U)
  3558. #define VHA_CR_OS1_VHA_EVENT_CLEAR_VHA_AXI_ERROR_CLRMSK (0XFFFBFFFFU)
  3559. #define VHA_CR_OS1_VHA_EVENT_CLEAR_VHA_AXI_ERROR_EN (0X00040000U)
  3560. #define VHA_CR_OS1_VHA_EVENT_CLEAR_VHA_MMU_PAGE_FAULT_SHIFT (16U)
  3561. #define VHA_CR_OS1_VHA_EVENT_CLEAR_VHA_MMU_PAGE_FAULT_CLRMSK (0XFFFEFFFFU)
  3562. #define VHA_CR_OS1_VHA_EVENT_CLEAR_VHA_MMU_PAGE_FAULT_EN (0X00010000U)
  3563. #define VHA_CR_OS1_VHA_EVENT_CLEAR_VHA_CNN0_MEM_WDT_SHIFT (3U)
  3564. #define VHA_CR_OS1_VHA_EVENT_CLEAR_VHA_CNN0_MEM_WDT_CLRMSK (0XFFFFFFF7U)
  3565. #define VHA_CR_OS1_VHA_EVENT_CLEAR_VHA_CNN0_MEM_WDT_EN (0X00000008U)
  3566. #define VHA_CR_OS1_VHA_EVENT_CLEAR_VHA_CNN0_ERROR_SHIFT (1U)
  3567. #define VHA_CR_OS1_VHA_EVENT_CLEAR_VHA_CNN0_ERROR_CLRMSK (0XFFFFFFFDU)
  3568. #define VHA_CR_OS1_VHA_EVENT_CLEAR_VHA_CNN0_ERROR_EN (0X00000002U)
  3569. #define VHA_CR_OS1_VHA_EVENT_CLEAR_VHA_CNN0_COMPLETE_SHIFT (0U)
  3570. #define VHA_CR_OS1_VHA_EVENT_CLEAR_VHA_CNN0_COMPLETE_CLRMSK (0XFFFFFFFEU)
  3571. #define VHA_CR_OS1_VHA_EVENT_CLEAR_VHA_CNN0_COMPLETE_EN (0X00000001U)
  3572. /*
  3573. Register VHA_CR_OS1_CNN_CRC_CONTROL
  3574. */
  3575. #define VHA_CR_OS1_CNN_CRC_CONTROL (0x20100U)
  3576. #define VHA_CR_OS1_CNN_CRC_CONTROL_MASKFULL (IMG_UINT64_C(0x0000000000000003))
  3577. #define VHA_CR_OS1_CNN_CRC_CONTROL_CNN_CRC_ENABLE_SHIFT (0U)
  3578. #define VHA_CR_OS1_CNN_CRC_CONTROL_CNN_CRC_ENABLE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFC))
  3579. #define VHA_CR_OS1_CNN_CRC_CONTROL_CNN_CRC_ENABLE_DISABLE (IMG_UINT64_C(0000000000000000))
  3580. #define VHA_CR_OS1_CNN_CRC_CONTROL_CNN_CRC_ENABLE_STREAM (IMG_UINT64_C(0x0000000000000001))
  3581. #define VHA_CR_OS1_CNN_CRC_CONTROL_CNN_CRC_ENABLE_LAYER (IMG_UINT64_C(0x0000000000000002))
  3582. #define VHA_CR_OS1_CNN_CRC_CONTROL_CNN_CRC_ENABLE_PASS (IMG_UINT64_C(0x0000000000000003))
  3583. /*
  3584. Register VHA_CR_OS1_CNN_CRC_ADDRESS
  3585. */
  3586. #define VHA_CR_OS1_CNN_CRC_ADDRESS (0x20108U)
  3587. #define VHA_CR_OS1_CNN_CRC_ADDRESS_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFF80))
  3588. #define VHA_CR_OS1_CNN_CRC_ADDRESS_CNN_CRC_ADDR_SHIFT (7U)
  3589. #define VHA_CR_OS1_CNN_CRC_ADDRESS_CNN_CRC_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF000000007F))
  3590. #define VHA_CR_OS1_CNN_CRC_ADDRESS_CNN_CRC_ADDR_ALIGNSHIFT (7U)
  3591. #define VHA_CR_OS1_CNN_CRC_ADDRESS_CNN_CRC_ADDR_ALIGNSIZE (128U)
  3592. /*
  3593. Register VHA_CR_OS1_CNN_DEBUG_ADDRESS
  3594. */
  3595. #define VHA_CR_OS1_CNN_DEBUG_ADDRESS (0x20110U)
  3596. #define VHA_CR_OS1_CNN_DEBUG_ADDRESS_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFF80))
  3597. #define VHA_CR_OS1_CNN_DEBUG_ADDRESS_CNN_DEBUG_ADDR_SHIFT (7U)
  3598. #define VHA_CR_OS1_CNN_DEBUG_ADDRESS_CNN_DEBUG_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF000000007F))
  3599. #define VHA_CR_OS1_CNN_DEBUG_ADDRESS_CNN_DEBUG_ADDR_ALIGNSHIFT (7U)
  3600. #define VHA_CR_OS1_CNN_DEBUG_ADDRESS_CNN_DEBUG_ADDR_ALIGNSIZE (128U)
  3601. /*
  3602. Register VHA_CR_OS1_CNN_DEBUG_SIZE
  3603. */
  3604. #define VHA_CR_OS1_CNN_DEBUG_SIZE (0x20118U)
  3605. #define VHA_CR_OS1_CNN_DEBUG_SIZE_MASKFULL (IMG_UINT64_C(0x0000000000FFFFE0))
  3606. #define VHA_CR_OS1_CNN_DEBUG_SIZE_CNN_DEBUG_SIZE_SHIFT (5U)
  3607. #define VHA_CR_OS1_CNN_DEBUG_SIZE_CNN_DEBUG_SIZE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF00001F))
  3608. #define VHA_CR_OS1_CNN_DEBUG_SIZE_CNN_DEBUG_SIZE_ALIGNSHIFT (5U)
  3609. #define VHA_CR_OS1_CNN_DEBUG_SIZE_CNN_DEBUG_SIZE_ALIGNSIZE (32U)
  3610. /*
  3611. Register VHA_CR_OS1_CNN_DEBUG_CONTROL
  3612. */
  3613. #define VHA_CR_OS1_CNN_DEBUG_CONTROL (0x20120U)
  3614. #define VHA_CR_OS1_CNN_DEBUG_CONTROL_MASKFULL (IMG_UINT64_C(0x000000000000000F))
  3615. #define VHA_CR_OS1_CNN_DEBUG_CONTROL_CNN_PERF_ENABLE_SHIFT (2U)
  3616. #define VHA_CR_OS1_CNN_DEBUG_CONTROL_CNN_PERF_ENABLE_CLRMSK (0XFFFFFFF3U)
  3617. #define VHA_CR_OS1_CNN_DEBUG_CONTROL_CNN_PERF_ENABLE_DISABLE (00000000U)
  3618. #define VHA_CR_OS1_CNN_DEBUG_CONTROL_CNN_PERF_ENABLE_STREAM (0X00000004U)
  3619. #define VHA_CR_OS1_CNN_DEBUG_CONTROL_CNN_PERF_ENABLE_LAYER (0X00000008U)
  3620. #define VHA_CR_OS1_CNN_DEBUG_CONTROL_CNN_PERF_ENABLE_PASS (0X0000000CU)
  3621. #define VHA_CR_OS1_CNN_DEBUG_CONTROL_CNN_BAND_ENABLE_SHIFT (0U)
  3622. #define VHA_CR_OS1_CNN_DEBUG_CONTROL_CNN_BAND_ENABLE_CLRMSK (0XFFFFFFFCU)
  3623. #define VHA_CR_OS1_CNN_DEBUG_CONTROL_CNN_BAND_ENABLE_DISABLE (00000000U)
  3624. #define VHA_CR_OS1_CNN_DEBUG_CONTROL_CNN_BAND_ENABLE_STREAM (0X00000001U)
  3625. #define VHA_CR_OS1_CNN_DEBUG_CONTROL_CNN_BAND_ENABLE_LAYER (0X00000002U)
  3626. #define VHA_CR_OS1_CNN_DEBUG_CONTROL_CNN_BAND_ENABLE_PASS (0X00000003U)
  3627. /*
  3628. Register VHA_CR_OS1_CNN_DEBUG_STATUS
  3629. */
  3630. #define VHA_CR_OS1_CNN_DEBUG_STATUS (0x20128U)
  3631. #define VHA_CR_OS1_CNN_DEBUG_STATUS_MASKFULL (IMG_UINT64_C(0x000000000007FFFF))
  3632. #define VHA_CR_OS1_CNN_DEBUG_STATUS_CNN_DEBUG_OFFSET_SHIFT (0U)
  3633. #define VHA_CR_OS1_CNN_DEBUG_STATUS_CNN_DEBUG_OFFSET_CLRMSK (0XFFF80000U)
  3634. /*
  3635. Register VHA_CR_OS1_CNN_PRELOAD_CONTROL
  3636. */
  3637. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL (0x20130U)
  3638. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_MASKFULL (IMG_UINT64_C(0x0000000001FF7777))
  3639. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_SHIFT (22U)
  3640. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFE3FFFFF))
  3641. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_DISABLE (IMG_UINT64_C(0000000000000000))
  3642. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_N_64 (IMG_UINT64_C(0x0000000000400000))
  3643. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_N_128 (IMG_UINT64_C(0x0000000000800000))
  3644. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_N_192 (IMG_UINT64_C(0x0000000000c00000))
  3645. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_N_256 (IMG_UINT64_C(0x0000000001000000))
  3646. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_N_320 (IMG_UINT64_C(0x0000000001400000))
  3647. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_N_384 (IMG_UINT64_C(0x0000000001800000))
  3648. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_N_448 (IMG_UINT64_C(0x0000000001c00000))
  3649. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_SHIFT (19U)
  3650. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFC7FFFF))
  3651. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_DISABLE (IMG_UINT64_C(0000000000000000))
  3652. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_N_64 (IMG_UINT64_C(0x0000000000080000))
  3653. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_N_128 (IMG_UINT64_C(0x0000000000100000))
  3654. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_N_192 (IMG_UINT64_C(0x0000000000180000))
  3655. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_N_256 (IMG_UINT64_C(0x0000000000200000))
  3656. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_N_320 (IMG_UINT64_C(0x0000000000280000))
  3657. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_N_384 (IMG_UINT64_C(0x0000000000300000))
  3658. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_N_448 (IMG_UINT64_C(0x0000000000380000))
  3659. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_SHIFT (16U)
  3660. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF8FFFF))
  3661. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_DISABLE (IMG_UINT64_C(0000000000000000))
  3662. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_N_64 (IMG_UINT64_C(0x0000000000010000))
  3663. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_N_128 (IMG_UINT64_C(0x0000000000020000))
  3664. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_N_192 (IMG_UINT64_C(0x0000000000030000))
  3665. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_N_256 (IMG_UINT64_C(0x0000000000040000))
  3666. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_N_320 (IMG_UINT64_C(0x0000000000050000))
  3667. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_N_384 (IMG_UINT64_C(0x0000000000060000))
  3668. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_N_448 (IMG_UINT64_C(0x0000000000070000))
  3669. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_EWO_N_REQS_SHIFT (12U)
  3670. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_EWO_N_REQS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF8FFF))
  3671. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_EWO_N_REQS_DISABLE (IMG_UINT64_C(0000000000000000))
  3672. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_EWO_N_REQS_N_64 (IMG_UINT64_C(0x0000000000001000))
  3673. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_EWO_N_REQS_N_128 (IMG_UINT64_C(0x0000000000002000))
  3674. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_EWO_N_REQS_N_192 (IMG_UINT64_C(0x0000000000003000))
  3675. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_EWO_N_REQS_N_256 (IMG_UINT64_C(0x0000000000004000))
  3676. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_EWO_N_REQS_N_320 (IMG_UINT64_C(0x0000000000005000))
  3677. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_EWO_N_REQS_N_384 (IMG_UINT64_C(0x0000000000006000))
  3678. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_EWO_N_REQS_N_448 (IMG_UINT64_C(0x0000000000007000))
  3679. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_ABUF_N_REQS_SHIFT (8U)
  3680. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_ABUF_N_REQS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF8FF))
  3681. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_ABUF_N_REQS_DISABLE (IMG_UINT64_C(0000000000000000))
  3682. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_ABUF_N_REQS_N_64 (IMG_UINT64_C(0x0000000000000100))
  3683. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_ABUF_N_REQS_N_128 (IMG_UINT64_C(0x0000000000000200))
  3684. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_ABUF_N_REQS_N_192 (IMG_UINT64_C(0x0000000000000300))
  3685. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_ABUF_N_REQS_N_256 (IMG_UINT64_C(0x0000000000000400))
  3686. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_ABUF_N_REQS_N_320 (IMG_UINT64_C(0x0000000000000500))
  3687. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_ABUF_N_REQS_N_384 (IMG_UINT64_C(0x0000000000000600))
  3688. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_ABUF_N_REQS_N_448 (IMG_UINT64_C(0x0000000000000700))
  3689. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_CBUF_N_REQS_SHIFT (4U)
  3690. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_CBUF_N_REQS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFF8F))
  3691. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_CBUF_N_REQS_DISABLE (IMG_UINT64_C(0000000000000000))
  3692. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_CBUF_N_REQS_N_64 (IMG_UINT64_C(0x0000000000000010))
  3693. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_CBUF_N_REQS_N_128 (IMG_UINT64_C(0x0000000000000020))
  3694. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_CBUF_N_REQS_N_192 (IMG_UINT64_C(0x0000000000000030))
  3695. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_CBUF_N_REQS_N_256 (IMG_UINT64_C(0x0000000000000040))
  3696. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_CBUF_N_REQS_N_320 (IMG_UINT64_C(0x0000000000000050))
  3697. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_CBUF_N_REQS_N_384 (IMG_UINT64_C(0x0000000000000060))
  3698. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_CBUF_N_REQS_N_448 (IMG_UINT64_C(0x0000000000000070))
  3699. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_IBUF_N_REQS_SHIFT (0U)
  3700. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_IBUF_N_REQS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF8))
  3701. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_IBUF_N_REQS_DISABLE (IMG_UINT64_C(0000000000000000))
  3702. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_IBUF_N_REQS_N_64 (IMG_UINT64_C(0x0000000000000001))
  3703. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_IBUF_N_REQS_N_128 (IMG_UINT64_C(0x0000000000000002))
  3704. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_IBUF_N_REQS_N_192 (IMG_UINT64_C(0x0000000000000003))
  3705. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_IBUF_N_REQS_N_256 (IMG_UINT64_C(0x0000000000000004))
  3706. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_IBUF_N_REQS_N_320 (IMG_UINT64_C(0x0000000000000005))
  3707. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_IBUF_N_REQS_N_384 (IMG_UINT64_C(0x0000000000000006))
  3708. #define VHA_CR_OS1_CNN_PRELOAD_CONTROL_IBUF_N_REQS_N_448 (IMG_UINT64_C(0x0000000000000007))
  3709. /*
  3710. Register VHA_CR_OS1_CNN_ALT_ADDRESS8
  3711. */
  3712. #define VHA_CR_OS1_CNN_ALT_ADDRESS8 (0x20140U)
  3713. #define VHA_CR_OS1_CNN_ALT_ADDRESS8_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  3714. #define VHA_CR_OS1_CNN_ALT_ADDRESS8_ALT_ADDR_SHIFT (0U)
  3715. #define VHA_CR_OS1_CNN_ALT_ADDRESS8_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  3716. /*
  3717. Register VHA_CR_OS1_CNN_ALT_ADDRESS9
  3718. */
  3719. #define VHA_CR_OS1_CNN_ALT_ADDRESS9 (0x20148U)
  3720. #define VHA_CR_OS1_CNN_ALT_ADDRESS9_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  3721. #define VHA_CR_OS1_CNN_ALT_ADDRESS9_ALT_ADDR_SHIFT (0U)
  3722. #define VHA_CR_OS1_CNN_ALT_ADDRESS9_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  3723. /*
  3724. Register VHA_CR_OS1_CNN_ALT_ADDRESS10
  3725. */
  3726. #define VHA_CR_OS1_CNN_ALT_ADDRESS10 (0x20150U)
  3727. #define VHA_CR_OS1_CNN_ALT_ADDRESS10_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  3728. #define VHA_CR_OS1_CNN_ALT_ADDRESS10_ALT_ADDR_SHIFT (0U)
  3729. #define VHA_CR_OS1_CNN_ALT_ADDRESS10_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  3730. /*
  3731. Register VHA_CR_OS1_CNN_ALT_ADDRESS11
  3732. */
  3733. #define VHA_CR_OS1_CNN_ALT_ADDRESS11 (0x20158U)
  3734. #define VHA_CR_OS1_CNN_ALT_ADDRESS11_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  3735. #define VHA_CR_OS1_CNN_ALT_ADDRESS11_ALT_ADDR_SHIFT (0U)
  3736. #define VHA_CR_OS1_CNN_ALT_ADDRESS11_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  3737. /*
  3738. Register VHA_CR_OS1_CNN_ALT_ADDRESS12
  3739. */
  3740. #define VHA_CR_OS1_CNN_ALT_ADDRESS12 (0x20160U)
  3741. #define VHA_CR_OS1_CNN_ALT_ADDRESS12_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  3742. #define VHA_CR_OS1_CNN_ALT_ADDRESS12_ALT_ADDR_SHIFT (0U)
  3743. #define VHA_CR_OS1_CNN_ALT_ADDRESS12_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  3744. /*
  3745. Register VHA_CR_OS1_CNN_ALT_ADDRESS13
  3746. */
  3747. #define VHA_CR_OS1_CNN_ALT_ADDRESS13 (0x20168U)
  3748. #define VHA_CR_OS1_CNN_ALT_ADDRESS13_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  3749. #define VHA_CR_OS1_CNN_ALT_ADDRESS13_ALT_ADDR_SHIFT (0U)
  3750. #define VHA_CR_OS1_CNN_ALT_ADDRESS13_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  3751. /*
  3752. Register VHA_CR_OS1_CNN_ALT_ADDRESS14
  3753. */
  3754. #define VHA_CR_OS1_CNN_ALT_ADDRESS14 (0x20170U)
  3755. #define VHA_CR_OS1_CNN_ALT_ADDRESS14_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  3756. #define VHA_CR_OS1_CNN_ALT_ADDRESS14_ALT_ADDR_SHIFT (0U)
  3757. #define VHA_CR_OS1_CNN_ALT_ADDRESS14_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  3758. /*
  3759. Register VHA_CR_OS1_CNN_ALT_ADDRESS15
  3760. */
  3761. #define VHA_CR_OS1_CNN_ALT_ADDRESS15 (0x20178U)
  3762. #define VHA_CR_OS1_CNN_ALT_ADDRESS15_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  3763. #define VHA_CR_OS1_CNN_ALT_ADDRESS15_ALT_ADDR_SHIFT (0U)
  3764. #define VHA_CR_OS1_CNN_ALT_ADDRESS15_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  3765. /*
  3766. Register VHA_CR_OS1_CNN_PERFORMANCE
  3767. */
  3768. #define VHA_CR_OS1_CNN_PERFORMANCE (0x201A0U)
  3769. #define VHA_CR_OS1_CNN_PERFORMANCE_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  3770. #define VHA_CR_OS1_CNN_PERFORMANCE_VALUE_SHIFT (0U)
  3771. #define VHA_CR_OS1_CNN_PERFORMANCE_VALUE_CLRMSK (00000000U)
  3772. /*
  3773. Register VHA_CR_OS1_OCM_BASE_ADDR
  3774. */
  3775. #define VHA_CR_OS1_OCM_BASE_ADDR (0x20200U)
  3776. #define VHA_CR_OS1_OCM_BASE_ADDR_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  3777. #define VHA_CR_OS1_OCM_BASE_ADDR_BASE_ADDR_SHIFT (0U)
  3778. #define VHA_CR_OS1_OCM_BASE_ADDR_BASE_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  3779. /*
  3780. Register VHA_CR_OS1_SAVE_RESTORE_BUFFER_BASE_ADDR
  3781. */
  3782. #define VHA_CR_OS1_SAVE_RESTORE_BUFFER_BASE_ADDR (0x20208U)
  3783. #define VHA_CR_OS1_SAVE_RESTORE_BUFFER_BASE_ADDR_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  3784. #define VHA_CR_OS1_SAVE_RESTORE_BUFFER_BASE_ADDR_BASE_ADDR_SHIFT (0U)
  3785. #define VHA_CR_OS1_SAVE_RESTORE_BUFFER_BASE_ADDR_BASE_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  3786. /*
  3787. Register VHA_CR_OS1_SAVE_RESTORE_CTRL
  3788. */
  3789. #define VHA_CR_OS1_SAVE_RESTORE_CTRL (0x20210U)
  3790. #define VHA_CR_OS1_SAVE_RESTORE_CTRL_MASKFULL (IMG_UINT64_C(0x000000000000000F))
  3791. #define VHA_CR_OS1_SAVE_RESTORE_CTRL_N_REQS_SHIFT (1U)
  3792. #define VHA_CR_OS1_SAVE_RESTORE_CTRL_N_REQS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF1))
  3793. #define VHA_CR_OS1_SAVE_RESTORE_CTRL_N_REQS_DISABLE (IMG_UINT64_C(0000000000000000))
  3794. #define VHA_CR_OS1_SAVE_RESTORE_CTRL_N_REQS_N_64 (IMG_UINT64_C(0x0000000000000002))
  3795. #define VHA_CR_OS1_SAVE_RESTORE_CTRL_N_REQS_N_128 (IMG_UINT64_C(0x0000000000000004))
  3796. #define VHA_CR_OS1_SAVE_RESTORE_CTRL_N_REQS_N_192 (IMG_UINT64_C(0x0000000000000006))
  3797. #define VHA_CR_OS1_SAVE_RESTORE_CTRL_N_REQS_N_256 (IMG_UINT64_C(0x0000000000000008))
  3798. #define VHA_CR_OS1_SAVE_RESTORE_CTRL_N_REQS_N_320 (IMG_UINT64_C(0x000000000000000a))
  3799. #define VHA_CR_OS1_SAVE_RESTORE_CTRL_N_REQS_N_384 (IMG_UINT64_C(0x000000000000000c))
  3800. #define VHA_CR_OS1_SAVE_RESTORE_CTRL_N_REQS_N_448 (IMG_UINT64_C(0x000000000000000e))
  3801. #define VHA_CR_OS1_SAVE_RESTORE_CTRL_WRITE_CACHE_POLICY_SHIFT (0U)
  3802. #define VHA_CR_OS1_SAVE_RESTORE_CTRL_WRITE_CACHE_POLICY_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  3803. #define VHA_CR_OS1_SAVE_RESTORE_CTRL_WRITE_CACHE_POLICY_EN (IMG_UINT64_C(0X0000000000000001))
  3804. /*
  3805. Register VHA_CR_OS1_CNN_CRC_MASK_CTRL
  3806. */
  3807. #define VHA_CR_OS1_CNN_CRC_MASK_CTRL (0x20300U)
  3808. #define VHA_CR_OS1_CNN_CRC_MASK_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000000003))
  3809. #define VHA_CR_OS1_CNN_CRC_MASK_CTRL_LEVEL_SHIFT (0U)
  3810. #define VHA_CR_OS1_CNN_CRC_MASK_CTRL_LEVEL_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFC))
  3811. #define VHA_CR_OS1_CNN_CRC_MASK_CTRL_LEVEL_NO_MASK (IMG_UINT64_C(0000000000000000))
  3812. #define VHA_CR_OS1_CNN_CRC_MASK_CTRL_LEVEL_MASK_L1 (IMG_UINT64_C(0x0000000000000001))
  3813. #define VHA_CR_OS1_CNN_CRC_MASK_CTRL_LEVEL_MASK_L2 (IMG_UINT64_C(0x0000000000000002))
  3814. #define VHA_CR_OS1_CNN_CRC_MASK_CTRL_LEVEL_MASK_L3 (IMG_UINT64_C(0x0000000000000003))
  3815. /*
  3816. Register VHA_CR_OS1_MMU_CTRL_INVAL
  3817. */
  3818. #define VHA_CR_OS1_MMU_CTRL_INVAL (0x2E000U)
  3819. #define VHA_CR_OS1_MMU_CTRL_INVAL_MASKFULL (IMG_UINT64_C(0x0000000000000FFF))
  3820. #define VHA_CR_OS1_MMU_CTRL_INVAL_ALL_CONTEXTS_SHIFT (11U)
  3821. #define VHA_CR_OS1_MMU_CTRL_INVAL_ALL_CONTEXTS_CLRMSK (0XFFFFF7FFU)
  3822. #define VHA_CR_OS1_MMU_CTRL_INVAL_ALL_CONTEXTS_EN (0X00000800U)
  3823. #define VHA_CR_OS1_MMU_CTRL_INVAL_CONTEXT_SHIFT (3U)
  3824. #define VHA_CR_OS1_MMU_CTRL_INVAL_CONTEXT_CLRMSK (0XFFFFF807U)
  3825. #define VHA_CR_OS1_MMU_CTRL_INVAL_PC_SHIFT (2U)
  3826. #define VHA_CR_OS1_MMU_CTRL_INVAL_PC_CLRMSK (0XFFFFFFFBU)
  3827. #define VHA_CR_OS1_MMU_CTRL_INVAL_PC_EN (0X00000004U)
  3828. #define VHA_CR_OS1_MMU_CTRL_INVAL_PD_SHIFT (1U)
  3829. #define VHA_CR_OS1_MMU_CTRL_INVAL_PD_CLRMSK (0XFFFFFFFDU)
  3830. #define VHA_CR_OS1_MMU_CTRL_INVAL_PD_EN (0X00000002U)
  3831. #define VHA_CR_OS1_MMU_CTRL_INVAL_PT_SHIFT (0U)
  3832. #define VHA_CR_OS1_MMU_CTRL_INVAL_PT_CLRMSK (0XFFFFFFFEU)
  3833. #define VHA_CR_OS1_MMU_CTRL_INVAL_PT_EN (0X00000001U)
  3834. /*
  3835. Register VHA_CR_OS1_MMU_CTRL_INVAL_STATUS
  3836. */
  3837. #define VHA_CR_OS1_MMU_CTRL_INVAL_STATUS (0x2E038U)
  3838. #define VHA_CR_OS1_MMU_CTRL_INVAL_STATUS_MASKFULL (IMG_UINT64_C(0x0000000080000001))
  3839. #define VHA_CR_OS1_MMU_CTRL_INVAL_STATUS_PARITY_SHIFT (31U)
  3840. #define VHA_CR_OS1_MMU_CTRL_INVAL_STATUS_PARITY_CLRMSK (0X7FFFFFFFU)
  3841. #define VHA_CR_OS1_MMU_CTRL_INVAL_STATUS_PARITY_EN (0X80000000U)
  3842. #define VHA_CR_OS1_MMU_CTRL_INVAL_STATUS_PENDING_SHIFT (0U)
  3843. #define VHA_CR_OS1_MMU_CTRL_INVAL_STATUS_PENDING_CLRMSK (0XFFFFFFFEU)
  3844. #define VHA_CR_OS1_MMU_CTRL_INVAL_STATUS_PENDING_EN (0X00000001U)
  3845. /*
  3846. Register VHA_CR_OS1_MMU_CBASE_MAPPING_CONTEXT
  3847. */
  3848. #define VHA_CR_OS1_MMU_CBASE_MAPPING_CONTEXT (0x2E008U)
  3849. #define VHA_CR_OS1_MMU_CBASE_MAPPING_CONTEXT_MASKFULL (IMG_UINT64_C(0x00000000000000FF))
  3850. #define VHA_CR_OS1_MMU_CBASE_MAPPING_CONTEXT_ID_SHIFT (0U)
  3851. #define VHA_CR_OS1_MMU_CBASE_MAPPING_CONTEXT_ID_CLRMSK (0XFFFFFF00U)
  3852. /*
  3853. Register VHA_CR_OS1_MMU_CBASE_MAPPING
  3854. */
  3855. #define VHA_CR_OS1_MMU_CBASE_MAPPING (0x2E010U)
  3856. #define VHA_CR_OS1_MMU_CBASE_MAPPING_MASKFULL (IMG_UINT64_C(0x000000001FFFFFFF))
  3857. #define VHA_CR_OS1_MMU_CBASE_MAPPING_INVALID_SHIFT (28U)
  3858. #define VHA_CR_OS1_MMU_CBASE_MAPPING_INVALID_CLRMSK (0XEFFFFFFFU)
  3859. #define VHA_CR_OS1_MMU_CBASE_MAPPING_INVALID_EN (0X10000000U)
  3860. #define VHA_CR_OS1_MMU_CBASE_MAPPING_BASE_ADDR_SHIFT (0U)
  3861. #define VHA_CR_OS1_MMU_CBASE_MAPPING_BASE_ADDR_CLRMSK (0XF0000000U)
  3862. #define VHA_CR_OS1_MMU_CBASE_MAPPING_BASE_ADDR_ALIGNSHIFT (12U)
  3863. #define VHA_CR_OS1_MMU_CBASE_MAPPING_BASE_ADDR_ALIGNSIZE (4096U)
  3864. /*
  3865. Register VHA_CR_OS1_MMU_FAULT_STATUS1
  3866. */
  3867. #define VHA_CR_OS1_MMU_FAULT_STATUS1 (0x2E018U)
  3868. #define VHA_CR_OS1_MMU_FAULT_STATUS1_MASKFULL (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
  3869. #define VHA_CR_OS1_MMU_FAULT_STATUS1_LEVEL_SHIFT (62U)
  3870. #define VHA_CR_OS1_MMU_FAULT_STATUS1_LEVEL_CLRMSK (IMG_UINT64_C(0X3FFFFFFFFFFFFFFF))
  3871. #define VHA_CR_OS1_MMU_FAULT_STATUS1_REQ_ID_SHIFT (56U)
  3872. #define VHA_CR_OS1_MMU_FAULT_STATUS1_REQ_ID_CLRMSK (IMG_UINT64_C(0XC0FFFFFFFFFFFFFF))
  3873. #define VHA_CR_OS1_MMU_FAULT_STATUS1_CONTEXT_SHIFT (48U)
  3874. #define VHA_CR_OS1_MMU_FAULT_STATUS1_CONTEXT_CLRMSK (IMG_UINT64_C(0XFF00FFFFFFFFFFFF))
  3875. #define VHA_CR_OS1_MMU_FAULT_STATUS1_ADDRESS_SHIFT (4U)
  3876. #define VHA_CR_OS1_MMU_FAULT_STATUS1_ADDRESS_CLRMSK (IMG_UINT64_C(0XFFFF00000000000F))
  3877. #define VHA_CR_OS1_MMU_FAULT_STATUS1_RNW_SHIFT (3U)
  3878. #define VHA_CR_OS1_MMU_FAULT_STATUS1_RNW_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF7))
  3879. #define VHA_CR_OS1_MMU_FAULT_STATUS1_RNW_EN (IMG_UINT64_C(0X0000000000000008))
  3880. #define VHA_CR_OS1_MMU_FAULT_STATUS1_TYPE_SHIFT (1U)
  3881. #define VHA_CR_OS1_MMU_FAULT_STATUS1_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF9))
  3882. #define VHA_CR_OS1_MMU_FAULT_STATUS1_FAULT_SHIFT (0U)
  3883. #define VHA_CR_OS1_MMU_FAULT_STATUS1_FAULT_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  3884. #define VHA_CR_OS1_MMU_FAULT_STATUS1_FAULT_EN (IMG_UINT64_C(0X0000000000000001))
  3885. /*
  3886. Register VHA_CR_OS1_MMU_FAULT_STATUS2
  3887. */
  3888. #define VHA_CR_OS1_MMU_FAULT_STATUS2 (0x2E020U)
  3889. #define VHA_CR_OS1_MMU_FAULT_STATUS2_MASKFULL (IMG_UINT64_C(0x000000003FFF07FF))
  3890. #define VHA_CR_OS1_MMU_FAULT_STATUS2_WRITEBACK_SHIFT (29U)
  3891. #define VHA_CR_OS1_MMU_FAULT_STATUS2_WRITEBACK_CLRMSK (0XDFFFFFFFU)
  3892. #define VHA_CR_OS1_MMU_FAULT_STATUS2_WRITEBACK_EN (0X20000000U)
  3893. #define VHA_CR_OS1_MMU_FAULT_STATUS2_CLEANUNIQUE_SHIFT (28U)
  3894. #define VHA_CR_OS1_MMU_FAULT_STATUS2_CLEANUNIQUE_CLRMSK (0XEFFFFFFFU)
  3895. #define VHA_CR_OS1_MMU_FAULT_STATUS2_CLEANUNIQUE_EN (0X10000000U)
  3896. #define VHA_CR_OS1_MMU_FAULT_STATUS2_BANK_SHIFT (24U)
  3897. #define VHA_CR_OS1_MMU_FAULT_STATUS2_BANK_CLRMSK (0XF0FFFFFFU)
  3898. #define VHA_CR_OS1_MMU_FAULT_STATUS2_TLB_ENTRY_SHIFT (16U)
  3899. #define VHA_CR_OS1_MMU_FAULT_STATUS2_TLB_ENTRY_CLRMSK (0XFF00FFFFU)
  3900. #define VHA_CR_OS1_MMU_FAULT_STATUS2_FBM_FAULT_SHIFT (10U)
  3901. #define VHA_CR_OS1_MMU_FAULT_STATUS2_FBM_FAULT_CLRMSK (0XFFFFFBFFU)
  3902. #define VHA_CR_OS1_MMU_FAULT_STATUS2_FBM_FAULT_EN (0X00000400U)
  3903. #define VHA_CR_OS1_MMU_FAULT_STATUS2_BIF_ID_SHIFT (0U)
  3904. #define VHA_CR_OS1_MMU_FAULT_STATUS2_BIF_ID_CLRMSK (0XFFFFFC00U)
  3905. /*
  3906. Register VHA_CR_OS1_MMU_CTRL_LEGACY
  3907. */
  3908. #define VHA_CR_OS1_MMU_CTRL_LEGACY (0x2E040U)
  3909. #define VHA_CR_OS1_MMU_CTRL_LEGACY_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  3910. #define VHA_CR_OS1_MMU_CTRL_LEGACY_RESERVED_SHIFT (0U)
  3911. #define VHA_CR_OS1_MMU_CTRL_LEGACY_RESERVED_CLRMSK (0XFFFFFFFEU)
  3912. #define VHA_CR_OS1_MMU_CTRL_LEGACY_RESERVED_EN (0X00000001U)
  3913. /*
  3914. Register VHA_CR_OS2_CNN_CONTROL
  3915. */
  3916. #define VHA_CR_OS2_CNN_CONTROL (0x30000U)
  3917. #define VHA_CR_OS2_CNN_CONTROL_MASKFULL (IMG_UINT64_C(0x000000000000337F))
  3918. #define VHA_CR_OS2_CNN_CONTROL_CTXT_PASID_SHIFT (12U)
  3919. #define VHA_CR_OS2_CNN_CONTROL_CTXT_PASID_CLRMSK (0XFFFFCFFFU)
  3920. #define VHA_CR_OS2_CNN_CONTROL_PRIORITY_SHIFT (8U)
  3921. #define VHA_CR_OS2_CNN_CONTROL_PRIORITY_CLRMSK (0XFFFFFCFFU)
  3922. #define VHA_CR_OS2_CNN_CONTROL_CMD_SIZE_MIN1_SHIFT (1U)
  3923. #define VHA_CR_OS2_CNN_CONTROL_CMD_SIZE_MIN1_CLRMSK (0XFFFFFF81U)
  3924. #define VHA_CR_OS2_CNN_CONTROL_START_SHIFT (0U)
  3925. #define VHA_CR_OS2_CNN_CONTROL_START_CLRMSK (0XFFFFFFFEU)
  3926. #define VHA_CR_OS2_CNN_CONTROL_START_EN (0X00000001U)
  3927. #define VHA_CR_OS2_CNN_STATUS_STATE_MASK (0x00000003U)
  3928. /*
  3929. No requests are pending for this host*/
  3930. #define VHA_CR_OS2_CNN_STATUS_STATE_IDLE (0x00000000U)
  3931. /*
  3932. A command stream from this host is being processed*/
  3933. #define VHA_CR_OS2_CNN_STATUS_STATE_RUN (0x00000001U)
  3934. /*
  3935. The command stream from this host has been suspended due to higher priority request from another host*/
  3936. #define VHA_CR_OS2_CNN_STATUS_STATE_SUSPEND (0x00000002U)
  3937. /*
  3938. A command stream from this host is pending but not been started */
  3939. #define VHA_CR_OS2_CNN_STATUS_STATE_PENDING (0x00000003U)
  3940. /*
  3941. Register VHA_CR_OS2_CNN_STATUS
  3942. */
  3943. #define VHA_CR_OS2_CNN_STATUS (0x30008U)
  3944. #define VHA_CR_OS2_CNN_STATUS_MASKFULL (IMG_UINT64_C(0x00000000C1FFFFFF))
  3945. #define VHA_CR_OS2_CNN_STATUS_CURRENT_STATE_SHIFT (30U)
  3946. #define VHA_CR_OS2_CNN_STATUS_CURRENT_STATE_CLRMSK (0X3FFFFFFFU)
  3947. #define VHA_CR_OS2_CNN_STATUS_CURRENT_STATE_IDLE (00000000U)
  3948. #define VHA_CR_OS2_CNN_STATUS_CURRENT_STATE_RUN (0X40000000U)
  3949. #define VHA_CR_OS2_CNN_STATUS_CURRENT_STATE_SUSPEND (0X80000000U)
  3950. #define VHA_CR_OS2_CNN_STATUS_CURRENT_STATE_PENDING (0XC0000000U)
  3951. #define VHA_CR_OS2_CNN_STATUS_PARITY_SHIFT (24U)
  3952. #define VHA_CR_OS2_CNN_STATUS_PARITY_CLRMSK (0XFEFFFFFFU)
  3953. #define VHA_CR_OS2_CNN_STATUS_PARITY_EN (0X01000000U)
  3954. #define VHA_CR_OS2_CNN_STATUS_LAYER_COUNT_SHIFT (8U)
  3955. #define VHA_CR_OS2_CNN_STATUS_LAYER_COUNT_CLRMSK (0XFF0000FFU)
  3956. #define VHA_CR_OS2_CNN_STATUS_STREAM_COUNT_SHIFT (0U)
  3957. #define VHA_CR_OS2_CNN_STATUS_STREAM_COUNT_CLRMSK (0XFFFFFF00U)
  3958. /*
  3959. Register VHA_CR_OS2_CNN_STATUS2
  3960. */
  3961. #define VHA_CR_OS2_CNN_STATUS2 (0x30010U)
  3962. #define VHA_CR_OS2_CNN_STATUS2_MASKFULL (IMG_UINT64_C(0x000000000001FFFF))
  3963. #define VHA_CR_OS2_CNN_STATUS2_PASS_COUNT_SHIFT (0U)
  3964. #define VHA_CR_OS2_CNN_STATUS2_PASS_COUNT_CLRMSK (0XFFFE0000U)
  3965. /*
  3966. Register VHA_CR_OS2_CNN_CMD_BASE_ADDRESS
  3967. */
  3968. #define VHA_CR_OS2_CNN_CMD_BASE_ADDRESS (0x30020U)
  3969. #define VHA_CR_OS2_CNN_CMD_BASE_ADDRESS_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFF80))
  3970. #define VHA_CR_OS2_CNN_CMD_BASE_ADDRESS_BASE_ADDR_SHIFT (7U)
  3971. #define VHA_CR_OS2_CNN_CMD_BASE_ADDRESS_BASE_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF000000007F))
  3972. /*
  3973. Register VHA_CR_OS2_CNN_ALT_ADDRESS_USED
  3974. */
  3975. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED (0x30038U)
  3976. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  3977. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR15_BUF_TYPE_SHIFT (31U)
  3978. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR15_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFF7FFFFFFF))
  3979. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR15_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  3980. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR15_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000080000000))
  3981. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR14_BUF_TYPE_SHIFT (30U)
  3982. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR14_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFBFFFFFFF))
  3983. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR14_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  3984. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR14_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000040000000))
  3985. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR13_BUF_TYPE_SHIFT (29U)
  3986. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR13_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFDFFFFFFF))
  3987. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR13_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  3988. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR13_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000020000000))
  3989. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR12_BUF_TYPE_SHIFT (28U)
  3990. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR12_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFEFFFFFFF))
  3991. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR12_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  3992. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR12_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000010000000))
  3993. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR11_BUF_TYPE_SHIFT (27U)
  3994. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR11_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFF7FFFFFF))
  3995. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR11_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  3996. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR11_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000008000000))
  3997. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR10_BUF_TYPE_SHIFT (26U)
  3998. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR10_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFBFFFFFF))
  3999. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR10_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  4000. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR10_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000004000000))
  4001. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR9_BUF_TYPE_SHIFT (25U)
  4002. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR9_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFDFFFFFF))
  4003. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR9_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  4004. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR9_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000002000000))
  4005. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR8_BUF_TYPE_SHIFT (24U)
  4006. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR8_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFEFFFFFF))
  4007. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR8_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  4008. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR8_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000001000000))
  4009. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR7_BUF_TYPE_SHIFT (23U)
  4010. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR7_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF7FFFFF))
  4011. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR7_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  4012. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR7_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000000800000))
  4013. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR6_BUF_TYPE_SHIFT (22U)
  4014. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR6_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFBFFFFF))
  4015. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR6_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  4016. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR6_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000000400000))
  4017. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR5_BUF_TYPE_SHIFT (21U)
  4018. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR5_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFDFFFFF))
  4019. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR5_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  4020. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR5_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000000200000))
  4021. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR4_BUF_TYPE_SHIFT (20U)
  4022. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR4_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFEFFFFF))
  4023. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR4_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  4024. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR4_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000000100000))
  4025. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR3_BUF_TYPE_SHIFT (19U)
  4026. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR3_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF7FFFF))
  4027. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR3_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  4028. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR3_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000000080000))
  4029. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR2_BUF_TYPE_SHIFT (18U)
  4030. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR2_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFBFFFF))
  4031. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR2_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  4032. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR2_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000000040000))
  4033. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR1_BUF_TYPE_SHIFT (17U)
  4034. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR1_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFDFFFF))
  4035. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR1_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  4036. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR1_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000000020000))
  4037. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR0_BUF_TYPE_SHIFT (16U)
  4038. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR0_BUF_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFEFFFF))
  4039. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR0_BUF_TYPE_MODEL_ONLY (IMG_UINT64_C(0000000000000000))
  4040. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR0_BUF_TYPE_IO_OR_SHARED (IMG_UINT64_C(0x0000000000010000))
  4041. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR15_USED_SHIFT (15U)
  4042. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR15_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF7FFF))
  4043. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR15_USED_EN (IMG_UINT64_C(0X0000000000008000))
  4044. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR14_USED_SHIFT (14U)
  4045. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR14_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFBFFF))
  4046. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR14_USED_EN (IMG_UINT64_C(0X0000000000004000))
  4047. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR13_USED_SHIFT (13U)
  4048. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR13_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFDFFF))
  4049. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR13_USED_EN (IMG_UINT64_C(0X0000000000002000))
  4050. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR12_USED_SHIFT (12U)
  4051. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR12_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFEFFF))
  4052. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR12_USED_EN (IMG_UINT64_C(0X0000000000001000))
  4053. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR11_USED_SHIFT (11U)
  4054. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR11_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF7FF))
  4055. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR11_USED_EN (IMG_UINT64_C(0X0000000000000800))
  4056. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR10_USED_SHIFT (10U)
  4057. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR10_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFBFF))
  4058. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR10_USED_EN (IMG_UINT64_C(0X0000000000000400))
  4059. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR9_USED_SHIFT (9U)
  4060. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR9_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFDFF))
  4061. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR9_USED_EN (IMG_UINT64_C(0X0000000000000200))
  4062. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR8_USED_SHIFT (8U)
  4063. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR8_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFEFF))
  4064. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR8_USED_EN (IMG_UINT64_C(0X0000000000000100))
  4065. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR7_USED_SHIFT (7U)
  4066. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR7_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFF7F))
  4067. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR7_USED_EN (IMG_UINT64_C(0X0000000000000080))
  4068. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR6_USED_SHIFT (6U)
  4069. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR6_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFBF))
  4070. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR6_USED_EN (IMG_UINT64_C(0X0000000000000040))
  4071. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR5_USED_SHIFT (5U)
  4072. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR5_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFDF))
  4073. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR5_USED_EN (IMG_UINT64_C(0X0000000000000020))
  4074. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR4_USED_SHIFT (4U)
  4075. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR4_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFEF))
  4076. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR4_USED_EN (IMG_UINT64_C(0X0000000000000010))
  4077. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR3_USED_SHIFT (3U)
  4078. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR3_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF7))
  4079. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR3_USED_EN (IMG_UINT64_C(0X0000000000000008))
  4080. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR2_USED_SHIFT (2U)
  4081. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR2_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFB))
  4082. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR2_USED_EN (IMG_UINT64_C(0X0000000000000004))
  4083. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR1_USED_SHIFT (1U)
  4084. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR1_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFD))
  4085. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR1_USED_EN (IMG_UINT64_C(0X0000000000000002))
  4086. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR0_USED_SHIFT (0U)
  4087. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR0_USED_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  4088. #define VHA_CR_OS2_CNN_ALT_ADDRESS_USED_ALT_ADDR0_USED_EN (IMG_UINT64_C(0X0000000000000001))
  4089. /*
  4090. Register VHA_CR_OS2_CNN_ALT_ADDRESS0
  4091. */
  4092. #define VHA_CR_OS2_CNN_ALT_ADDRESS0 (0x30040U)
  4093. #define VHA_CR_OS2_CNN_ALT_ADDRESS0_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  4094. #define VHA_CR_OS2_CNN_ALT_ADDRESS0_ALT_ADDR_SHIFT (0U)
  4095. #define VHA_CR_OS2_CNN_ALT_ADDRESS0_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  4096. /*
  4097. Register VHA_CR_OS2_CNN_ALT_ADDRESS1
  4098. */
  4099. #define VHA_CR_OS2_CNN_ALT_ADDRESS1 (0x30048U)
  4100. #define VHA_CR_OS2_CNN_ALT_ADDRESS1_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  4101. #define VHA_CR_OS2_CNN_ALT_ADDRESS1_ALT_ADDR_SHIFT (0U)
  4102. #define VHA_CR_OS2_CNN_ALT_ADDRESS1_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  4103. /*
  4104. Register VHA_CR_OS2_CNN_ALT_ADDRESS2
  4105. */
  4106. #define VHA_CR_OS2_CNN_ALT_ADDRESS2 (0x30050U)
  4107. #define VHA_CR_OS2_CNN_ALT_ADDRESS2_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  4108. #define VHA_CR_OS2_CNN_ALT_ADDRESS2_ALT_ADDR_SHIFT (0U)
  4109. #define VHA_CR_OS2_CNN_ALT_ADDRESS2_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  4110. /*
  4111. Register VHA_CR_OS2_CNN_ALT_ADDRESS3
  4112. */
  4113. #define VHA_CR_OS2_CNN_ALT_ADDRESS3 (0x30058U)
  4114. #define VHA_CR_OS2_CNN_ALT_ADDRESS3_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  4115. #define VHA_CR_OS2_CNN_ALT_ADDRESS3_ALT_ADDR_SHIFT (0U)
  4116. #define VHA_CR_OS2_CNN_ALT_ADDRESS3_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  4117. /*
  4118. Register VHA_CR_OS2_CNN_ALT_ADDRESS4
  4119. */
  4120. #define VHA_CR_OS2_CNN_ALT_ADDRESS4 (0x30060U)
  4121. #define VHA_CR_OS2_CNN_ALT_ADDRESS4_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  4122. #define VHA_CR_OS2_CNN_ALT_ADDRESS4_ALT_ADDR_SHIFT (0U)
  4123. #define VHA_CR_OS2_CNN_ALT_ADDRESS4_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  4124. /*
  4125. Register VHA_CR_OS2_CNN_ALT_ADDRESS5
  4126. */
  4127. #define VHA_CR_OS2_CNN_ALT_ADDRESS5 (0x30068U)
  4128. #define VHA_CR_OS2_CNN_ALT_ADDRESS5_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  4129. #define VHA_CR_OS2_CNN_ALT_ADDRESS5_ALT_ADDR_SHIFT (0U)
  4130. #define VHA_CR_OS2_CNN_ALT_ADDRESS5_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  4131. /*
  4132. Register VHA_CR_OS2_CNN_ALT_ADDRESS6
  4133. */
  4134. #define VHA_CR_OS2_CNN_ALT_ADDRESS6 (0x30070U)
  4135. #define VHA_CR_OS2_CNN_ALT_ADDRESS6_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  4136. #define VHA_CR_OS2_CNN_ALT_ADDRESS6_ALT_ADDR_SHIFT (0U)
  4137. #define VHA_CR_OS2_CNN_ALT_ADDRESS6_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  4138. /*
  4139. Register VHA_CR_OS2_CNN_ALT_ADDRESS7
  4140. */
  4141. #define VHA_CR_OS2_CNN_ALT_ADDRESS7 (0x30078U)
  4142. #define VHA_CR_OS2_CNN_ALT_ADDRESS7_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  4143. #define VHA_CR_OS2_CNN_ALT_ADDRESS7_ALT_ADDR_SHIFT (0U)
  4144. #define VHA_CR_OS2_CNN_ALT_ADDRESS7_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  4145. /*
  4146. Register VHA_CR_OS2_CNN_WRITEBACK_CONTROL
  4147. */
  4148. #define VHA_CR_OS2_CNN_WRITEBACK_CONTROL (0x30080U)
  4149. #define VHA_CR_OS2_CNN_WRITEBACK_CONTROL_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  4150. #define VHA_CR_OS2_CNN_WRITEBACK_CONTROL_WRITE_BACK_VALUE_SHIFT (0U)
  4151. #define VHA_CR_OS2_CNN_WRITEBACK_CONTROL_WRITE_BACK_VALUE_CLRMSK (00000000U)
  4152. /*
  4153. Register VHA_CR_OS2_VHA_EVENT_ENABLE
  4154. */
  4155. #define VHA_CR_OS2_VHA_EVENT_ENABLE (0x30088U)
  4156. #define VHA_CR_OS2_VHA_EVENT_ENABLE_MASKFULL (IMG_UINT64_C(0x0000000033FD000B))
  4157. #define VHA_CR_OS2_VHA_EVENT_ENABLE_VHA_MMU_PARITY_ERROR_SHIFT (29U)
  4158. #define VHA_CR_OS2_VHA_EVENT_ENABLE_VHA_MMU_PARITY_ERROR_CLRMSK (0XDFFFFFFFU)
  4159. #define VHA_CR_OS2_VHA_EVENT_ENABLE_VHA_MMU_PARITY_ERROR_EN (0X20000000U)
  4160. #define VHA_CR_OS2_VHA_EVENT_ENABLE_VHA_PARITY_ERROR_SHIFT (28U)
  4161. #define VHA_CR_OS2_VHA_EVENT_ENABLE_VHA_PARITY_ERROR_CLRMSK (0XEFFFFFFFU)
  4162. #define VHA_CR_OS2_VHA_EVENT_ENABLE_VHA_PARITY_ERROR_EN (0X10000000U)
  4163. #define VHA_CR_OS2_VHA_EVENT_ENABLE_VHA_ECC_INIT_DONE_SHIFT (25U)
  4164. #define VHA_CR_OS2_VHA_EVENT_ENABLE_VHA_ECC_INIT_DONE_CLRMSK (0XFDFFFFFFU)
  4165. #define VHA_CR_OS2_VHA_EVENT_ENABLE_VHA_ECC_INIT_DONE_EN (0X02000000U)
  4166. #define VHA_CR_OS2_VHA_EVENT_ENABLE_VHA_ECC_DETECTION_SHIFT (24U)
  4167. #define VHA_CR_OS2_VHA_EVENT_ENABLE_VHA_ECC_DETECTION_CLRMSK (0XFEFFFFFFU)
  4168. #define VHA_CR_OS2_VHA_EVENT_ENABLE_VHA_ECC_DETECTION_EN (0X01000000U)
  4169. #define VHA_CR_OS2_VHA_EVENT_ENABLE_VHA_ECC_CORRECTION_SHIFT (23U)
  4170. #define VHA_CR_OS2_VHA_EVENT_ENABLE_VHA_ECC_CORRECTION_CLRMSK (0XFF7FFFFFU)
  4171. #define VHA_CR_OS2_VHA_EVENT_ENABLE_VHA_ECC_CORRECTION_EN (0X00800000U)
  4172. #define VHA_CR_OS2_VHA_EVENT_ENABLE_VHA_LOCKSTEP_ERROR_SHIFT (22U)
  4173. #define VHA_CR_OS2_VHA_EVENT_ENABLE_VHA_LOCKSTEP_ERROR_CLRMSK (0XFFBFFFFFU)
  4174. #define VHA_CR_OS2_VHA_EVENT_ENABLE_VHA_LOCKSTEP_ERROR_EN (0X00400000U)
  4175. #define VHA_CR_OS2_VHA_EVENT_ENABLE_VHA_READY_SHIFT (21U)
  4176. #define VHA_CR_OS2_VHA_EVENT_ENABLE_VHA_READY_CLRMSK (0XFFDFFFFFU)
  4177. #define VHA_CR_OS2_VHA_EVENT_ENABLE_VHA_READY_EN (0X00200000U)
  4178. #define VHA_CR_OS2_VHA_EVENT_ENABLE_VHA_ERROR_SHIFT (20U)
  4179. #define VHA_CR_OS2_VHA_EVENT_ENABLE_VHA_ERROR_CLRMSK (0XFFEFFFFFU)
  4180. #define VHA_CR_OS2_VHA_EVENT_ENABLE_VHA_ERROR_EN (0X00100000U)
  4181. #define VHA_CR_OS2_VHA_EVENT_ENABLE_VHA_HL_WDT_SHIFT (19U)
  4182. #define VHA_CR_OS2_VHA_EVENT_ENABLE_VHA_HL_WDT_CLRMSK (0XFFF7FFFFU)
  4183. #define VHA_CR_OS2_VHA_EVENT_ENABLE_VHA_HL_WDT_EN (0X00080000U)
  4184. #define VHA_CR_OS2_VHA_EVENT_ENABLE_VHA_AXI_ERROR_SHIFT (18U)
  4185. #define VHA_CR_OS2_VHA_EVENT_ENABLE_VHA_AXI_ERROR_CLRMSK (0XFFFBFFFFU)
  4186. #define VHA_CR_OS2_VHA_EVENT_ENABLE_VHA_AXI_ERROR_EN (0X00040000U)
  4187. #define VHA_CR_OS2_VHA_EVENT_ENABLE_VHA_MMU_PAGE_FAULT_SHIFT (16U)
  4188. #define VHA_CR_OS2_VHA_EVENT_ENABLE_VHA_MMU_PAGE_FAULT_CLRMSK (0XFFFEFFFFU)
  4189. #define VHA_CR_OS2_VHA_EVENT_ENABLE_VHA_MMU_PAGE_FAULT_EN (0X00010000U)
  4190. #define VHA_CR_OS2_VHA_EVENT_ENABLE_VHA_CNN0_MEM_WDT_SHIFT (3U)
  4191. #define VHA_CR_OS2_VHA_EVENT_ENABLE_VHA_CNN0_MEM_WDT_CLRMSK (0XFFFFFFF7U)
  4192. #define VHA_CR_OS2_VHA_EVENT_ENABLE_VHA_CNN0_MEM_WDT_EN (0X00000008U)
  4193. #define VHA_CR_OS2_VHA_EVENT_ENABLE_VHA_CNN0_ERROR_SHIFT (1U)
  4194. #define VHA_CR_OS2_VHA_EVENT_ENABLE_VHA_CNN0_ERROR_CLRMSK (0XFFFFFFFDU)
  4195. #define VHA_CR_OS2_VHA_EVENT_ENABLE_VHA_CNN0_ERROR_EN (0X00000002U)
  4196. #define VHA_CR_OS2_VHA_EVENT_ENABLE_VHA_CNN0_COMPLETE_SHIFT (0U)
  4197. #define VHA_CR_OS2_VHA_EVENT_ENABLE_VHA_CNN0_COMPLETE_CLRMSK (0XFFFFFFFEU)
  4198. #define VHA_CR_OS2_VHA_EVENT_ENABLE_VHA_CNN0_COMPLETE_EN (0X00000001U)
  4199. /*
  4200. Register VHA_CR_OS2_VHA_EVENT_STATUS
  4201. */
  4202. #define VHA_CR_OS2_VHA_EVENT_STATUS (0x30090U)
  4203. #define VHA_CR_OS2_VHA_EVENT_STATUS_MASKFULL (IMG_UINT64_C(0x00000000B3FD000B))
  4204. #define VHA_CR_OS2_VHA_EVENT_STATUS_PARITY_SHIFT (31U)
  4205. #define VHA_CR_OS2_VHA_EVENT_STATUS_PARITY_CLRMSK (0X7FFFFFFFU)
  4206. #define VHA_CR_OS2_VHA_EVENT_STATUS_PARITY_EN (0X80000000U)
  4207. #define VHA_CR_OS2_VHA_EVENT_STATUS_VHA_MMU_PARITY_ERROR_SHIFT (29U)
  4208. #define VHA_CR_OS2_VHA_EVENT_STATUS_VHA_MMU_PARITY_ERROR_CLRMSK (0XDFFFFFFFU)
  4209. #define VHA_CR_OS2_VHA_EVENT_STATUS_VHA_MMU_PARITY_ERROR_EN (0X20000000U)
  4210. #define VHA_CR_OS2_VHA_EVENT_STATUS_VHA_PARITY_ERROR_SHIFT (28U)
  4211. #define VHA_CR_OS2_VHA_EVENT_STATUS_VHA_PARITY_ERROR_CLRMSK (0XEFFFFFFFU)
  4212. #define VHA_CR_OS2_VHA_EVENT_STATUS_VHA_PARITY_ERROR_EN (0X10000000U)
  4213. #define VHA_CR_OS2_VHA_EVENT_STATUS_VHA_ECC_INIT_DONE_SHIFT (25U)
  4214. #define VHA_CR_OS2_VHA_EVENT_STATUS_VHA_ECC_INIT_DONE_CLRMSK (0XFDFFFFFFU)
  4215. #define VHA_CR_OS2_VHA_EVENT_STATUS_VHA_ECC_INIT_DONE_EN (0X02000000U)
  4216. #define VHA_CR_OS2_VHA_EVENT_STATUS_VHA_ECC_DETECTION_SHIFT (24U)
  4217. #define VHA_CR_OS2_VHA_EVENT_STATUS_VHA_ECC_DETECTION_CLRMSK (0XFEFFFFFFU)
  4218. #define VHA_CR_OS2_VHA_EVENT_STATUS_VHA_ECC_DETECTION_EN (0X01000000U)
  4219. #define VHA_CR_OS2_VHA_EVENT_STATUS_VHA_ECC_CORRECTION_SHIFT (23U)
  4220. #define VHA_CR_OS2_VHA_EVENT_STATUS_VHA_ECC_CORRECTION_CLRMSK (0XFF7FFFFFU)
  4221. #define VHA_CR_OS2_VHA_EVENT_STATUS_VHA_ECC_CORRECTION_EN (0X00800000U)
  4222. #define VHA_CR_OS2_VHA_EVENT_STATUS_VHA_LOCKSTEP_ERROR_SHIFT (22U)
  4223. #define VHA_CR_OS2_VHA_EVENT_STATUS_VHA_LOCKSTEP_ERROR_CLRMSK (0XFFBFFFFFU)
  4224. #define VHA_CR_OS2_VHA_EVENT_STATUS_VHA_LOCKSTEP_ERROR_EN (0X00400000U)
  4225. #define VHA_CR_OS2_VHA_EVENT_STATUS_VHA_READY_SHIFT (21U)
  4226. #define VHA_CR_OS2_VHA_EVENT_STATUS_VHA_READY_CLRMSK (0XFFDFFFFFU)
  4227. #define VHA_CR_OS2_VHA_EVENT_STATUS_VHA_READY_EN (0X00200000U)
  4228. #define VHA_CR_OS2_VHA_EVENT_STATUS_VHA_ERROR_SHIFT (20U)
  4229. #define VHA_CR_OS2_VHA_EVENT_STATUS_VHA_ERROR_CLRMSK (0XFFEFFFFFU)
  4230. #define VHA_CR_OS2_VHA_EVENT_STATUS_VHA_ERROR_EN (0X00100000U)
  4231. #define VHA_CR_OS2_VHA_EVENT_STATUS_VHA_HL_WDT_SHIFT (19U)
  4232. #define VHA_CR_OS2_VHA_EVENT_STATUS_VHA_HL_WDT_CLRMSK (0XFFF7FFFFU)
  4233. #define VHA_CR_OS2_VHA_EVENT_STATUS_VHA_HL_WDT_EN (0X00080000U)
  4234. #define VHA_CR_OS2_VHA_EVENT_STATUS_VHA_AXI_ERROR_SHIFT (18U)
  4235. #define VHA_CR_OS2_VHA_EVENT_STATUS_VHA_AXI_ERROR_CLRMSK (0XFFFBFFFFU)
  4236. #define VHA_CR_OS2_VHA_EVENT_STATUS_VHA_AXI_ERROR_EN (0X00040000U)
  4237. #define VHA_CR_OS2_VHA_EVENT_STATUS_VHA_MMU_PAGE_FAULT_SHIFT (16U)
  4238. #define VHA_CR_OS2_VHA_EVENT_STATUS_VHA_MMU_PAGE_FAULT_CLRMSK (0XFFFEFFFFU)
  4239. #define VHA_CR_OS2_VHA_EVENT_STATUS_VHA_MMU_PAGE_FAULT_EN (0X00010000U)
  4240. #define VHA_CR_OS2_VHA_EVENT_STATUS_VHA_CNN0_MEM_WDT_SHIFT (3U)
  4241. #define VHA_CR_OS2_VHA_EVENT_STATUS_VHA_CNN0_MEM_WDT_CLRMSK (0XFFFFFFF7U)
  4242. #define VHA_CR_OS2_VHA_EVENT_STATUS_VHA_CNN0_MEM_WDT_EN (0X00000008U)
  4243. #define VHA_CR_OS2_VHA_EVENT_STATUS_VHA_CNN0_ERROR_SHIFT (1U)
  4244. #define VHA_CR_OS2_VHA_EVENT_STATUS_VHA_CNN0_ERROR_CLRMSK (0XFFFFFFFDU)
  4245. #define VHA_CR_OS2_VHA_EVENT_STATUS_VHA_CNN0_ERROR_EN (0X00000002U)
  4246. #define VHA_CR_OS2_VHA_EVENT_STATUS_VHA_CNN0_COMPLETE_SHIFT (0U)
  4247. #define VHA_CR_OS2_VHA_EVENT_STATUS_VHA_CNN0_COMPLETE_CLRMSK (0XFFFFFFFEU)
  4248. #define VHA_CR_OS2_VHA_EVENT_STATUS_VHA_CNN0_COMPLETE_EN (0X00000001U)
  4249. /*
  4250. Register VHA_CR_OS2_VHA_EVENT_CLEAR
  4251. */
  4252. #define VHA_CR_OS2_VHA_EVENT_CLEAR (0x30098U)
  4253. #define VHA_CR_OS2_VHA_EVENT_CLEAR_MASKFULL (IMG_UINT64_C(0x0000000033FD000B))
  4254. #define VHA_CR_OS2_VHA_EVENT_CLEAR_VHA_MMU_PARITY_ERROR_SHIFT (29U)
  4255. #define VHA_CR_OS2_VHA_EVENT_CLEAR_VHA_MMU_PARITY_ERROR_CLRMSK (0XDFFFFFFFU)
  4256. #define VHA_CR_OS2_VHA_EVENT_CLEAR_VHA_MMU_PARITY_ERROR_EN (0X20000000U)
  4257. #define VHA_CR_OS2_VHA_EVENT_CLEAR_VHA_PARITY_ERROR_SHIFT (28U)
  4258. #define VHA_CR_OS2_VHA_EVENT_CLEAR_VHA_PARITY_ERROR_CLRMSK (0XEFFFFFFFU)
  4259. #define VHA_CR_OS2_VHA_EVENT_CLEAR_VHA_PARITY_ERROR_EN (0X10000000U)
  4260. #define VHA_CR_OS2_VHA_EVENT_CLEAR_VHA_ECC_INIT_DONE_SHIFT (25U)
  4261. #define VHA_CR_OS2_VHA_EVENT_CLEAR_VHA_ECC_INIT_DONE_CLRMSK (0XFDFFFFFFU)
  4262. #define VHA_CR_OS2_VHA_EVENT_CLEAR_VHA_ECC_INIT_DONE_EN (0X02000000U)
  4263. #define VHA_CR_OS2_VHA_EVENT_CLEAR_VHA_ECC_DETECTION_SHIFT (24U)
  4264. #define VHA_CR_OS2_VHA_EVENT_CLEAR_VHA_ECC_DETECTION_CLRMSK (0XFEFFFFFFU)
  4265. #define VHA_CR_OS2_VHA_EVENT_CLEAR_VHA_ECC_DETECTION_EN (0X01000000U)
  4266. #define VHA_CR_OS2_VHA_EVENT_CLEAR_VHA_ECC_CORRECTION_SHIFT (23U)
  4267. #define VHA_CR_OS2_VHA_EVENT_CLEAR_VHA_ECC_CORRECTION_CLRMSK (0XFF7FFFFFU)
  4268. #define VHA_CR_OS2_VHA_EVENT_CLEAR_VHA_ECC_CORRECTION_EN (0X00800000U)
  4269. #define VHA_CR_OS2_VHA_EVENT_CLEAR_VHA_LOCKSTEP_ERROR_SHIFT (22U)
  4270. #define VHA_CR_OS2_VHA_EVENT_CLEAR_VHA_LOCKSTEP_ERROR_CLRMSK (0XFFBFFFFFU)
  4271. #define VHA_CR_OS2_VHA_EVENT_CLEAR_VHA_LOCKSTEP_ERROR_EN (0X00400000U)
  4272. #define VHA_CR_OS2_VHA_EVENT_CLEAR_VHA_READY_SHIFT (21U)
  4273. #define VHA_CR_OS2_VHA_EVENT_CLEAR_VHA_READY_CLRMSK (0XFFDFFFFFU)
  4274. #define VHA_CR_OS2_VHA_EVENT_CLEAR_VHA_READY_EN (0X00200000U)
  4275. #define VHA_CR_OS2_VHA_EVENT_CLEAR_VHA_ERROR_SHIFT (20U)
  4276. #define VHA_CR_OS2_VHA_EVENT_CLEAR_VHA_ERROR_CLRMSK (0XFFEFFFFFU)
  4277. #define VHA_CR_OS2_VHA_EVENT_CLEAR_VHA_ERROR_EN (0X00100000U)
  4278. #define VHA_CR_OS2_VHA_EVENT_CLEAR_VHA_HL_WDT_SHIFT (19U)
  4279. #define VHA_CR_OS2_VHA_EVENT_CLEAR_VHA_HL_WDT_CLRMSK (0XFFF7FFFFU)
  4280. #define VHA_CR_OS2_VHA_EVENT_CLEAR_VHA_HL_WDT_EN (0X00080000U)
  4281. #define VHA_CR_OS2_VHA_EVENT_CLEAR_VHA_AXI_ERROR_SHIFT (18U)
  4282. #define VHA_CR_OS2_VHA_EVENT_CLEAR_VHA_AXI_ERROR_CLRMSK (0XFFFBFFFFU)
  4283. #define VHA_CR_OS2_VHA_EVENT_CLEAR_VHA_AXI_ERROR_EN (0X00040000U)
  4284. #define VHA_CR_OS2_VHA_EVENT_CLEAR_VHA_MMU_PAGE_FAULT_SHIFT (16U)
  4285. #define VHA_CR_OS2_VHA_EVENT_CLEAR_VHA_MMU_PAGE_FAULT_CLRMSK (0XFFFEFFFFU)
  4286. #define VHA_CR_OS2_VHA_EVENT_CLEAR_VHA_MMU_PAGE_FAULT_EN (0X00010000U)
  4287. #define VHA_CR_OS2_VHA_EVENT_CLEAR_VHA_CNN0_MEM_WDT_SHIFT (3U)
  4288. #define VHA_CR_OS2_VHA_EVENT_CLEAR_VHA_CNN0_MEM_WDT_CLRMSK (0XFFFFFFF7U)
  4289. #define VHA_CR_OS2_VHA_EVENT_CLEAR_VHA_CNN0_MEM_WDT_EN (0X00000008U)
  4290. #define VHA_CR_OS2_VHA_EVENT_CLEAR_VHA_CNN0_ERROR_SHIFT (1U)
  4291. #define VHA_CR_OS2_VHA_EVENT_CLEAR_VHA_CNN0_ERROR_CLRMSK (0XFFFFFFFDU)
  4292. #define VHA_CR_OS2_VHA_EVENT_CLEAR_VHA_CNN0_ERROR_EN (0X00000002U)
  4293. #define VHA_CR_OS2_VHA_EVENT_CLEAR_VHA_CNN0_COMPLETE_SHIFT (0U)
  4294. #define VHA_CR_OS2_VHA_EVENT_CLEAR_VHA_CNN0_COMPLETE_CLRMSK (0XFFFFFFFEU)
  4295. #define VHA_CR_OS2_VHA_EVENT_CLEAR_VHA_CNN0_COMPLETE_EN (0X00000001U)
  4296. /*
  4297. Register VHA_CR_OS2_CNN_CRC_CONTROL
  4298. */
  4299. #define VHA_CR_OS2_CNN_CRC_CONTROL (0x30100U)
  4300. #define VHA_CR_OS2_CNN_CRC_CONTROL_MASKFULL (IMG_UINT64_C(0x0000000000000003))
  4301. #define VHA_CR_OS2_CNN_CRC_CONTROL_CNN_CRC_ENABLE_SHIFT (0U)
  4302. #define VHA_CR_OS2_CNN_CRC_CONTROL_CNN_CRC_ENABLE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFC))
  4303. #define VHA_CR_OS2_CNN_CRC_CONTROL_CNN_CRC_ENABLE_DISABLE (IMG_UINT64_C(0000000000000000))
  4304. #define VHA_CR_OS2_CNN_CRC_CONTROL_CNN_CRC_ENABLE_STREAM (IMG_UINT64_C(0x0000000000000001))
  4305. #define VHA_CR_OS2_CNN_CRC_CONTROL_CNN_CRC_ENABLE_LAYER (IMG_UINT64_C(0x0000000000000002))
  4306. #define VHA_CR_OS2_CNN_CRC_CONTROL_CNN_CRC_ENABLE_PASS (IMG_UINT64_C(0x0000000000000003))
  4307. /*
  4308. Register VHA_CR_OS2_CNN_CRC_ADDRESS
  4309. */
  4310. #define VHA_CR_OS2_CNN_CRC_ADDRESS (0x30108U)
  4311. #define VHA_CR_OS2_CNN_CRC_ADDRESS_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFF80))
  4312. #define VHA_CR_OS2_CNN_CRC_ADDRESS_CNN_CRC_ADDR_SHIFT (7U)
  4313. #define VHA_CR_OS2_CNN_CRC_ADDRESS_CNN_CRC_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF000000007F))
  4314. #define VHA_CR_OS2_CNN_CRC_ADDRESS_CNN_CRC_ADDR_ALIGNSHIFT (7U)
  4315. #define VHA_CR_OS2_CNN_CRC_ADDRESS_CNN_CRC_ADDR_ALIGNSIZE (128U)
  4316. /*
  4317. Register VHA_CR_OS2_CNN_DEBUG_ADDRESS
  4318. */
  4319. #define VHA_CR_OS2_CNN_DEBUG_ADDRESS (0x30110U)
  4320. #define VHA_CR_OS2_CNN_DEBUG_ADDRESS_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFF80))
  4321. #define VHA_CR_OS2_CNN_DEBUG_ADDRESS_CNN_DEBUG_ADDR_SHIFT (7U)
  4322. #define VHA_CR_OS2_CNN_DEBUG_ADDRESS_CNN_DEBUG_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF000000007F))
  4323. #define VHA_CR_OS2_CNN_DEBUG_ADDRESS_CNN_DEBUG_ADDR_ALIGNSHIFT (7U)
  4324. #define VHA_CR_OS2_CNN_DEBUG_ADDRESS_CNN_DEBUG_ADDR_ALIGNSIZE (128U)
  4325. /*
  4326. Register VHA_CR_OS2_CNN_DEBUG_SIZE
  4327. */
  4328. #define VHA_CR_OS2_CNN_DEBUG_SIZE (0x30118U)
  4329. #define VHA_CR_OS2_CNN_DEBUG_SIZE_MASKFULL (IMG_UINT64_C(0x0000000000FFFFE0))
  4330. #define VHA_CR_OS2_CNN_DEBUG_SIZE_CNN_DEBUG_SIZE_SHIFT (5U)
  4331. #define VHA_CR_OS2_CNN_DEBUG_SIZE_CNN_DEBUG_SIZE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFF00001F))
  4332. #define VHA_CR_OS2_CNN_DEBUG_SIZE_CNN_DEBUG_SIZE_ALIGNSHIFT (5U)
  4333. #define VHA_CR_OS2_CNN_DEBUG_SIZE_CNN_DEBUG_SIZE_ALIGNSIZE (32U)
  4334. /*
  4335. Register VHA_CR_OS2_CNN_DEBUG_CONTROL
  4336. */
  4337. #define VHA_CR_OS2_CNN_DEBUG_CONTROL (0x30120U)
  4338. #define VHA_CR_OS2_CNN_DEBUG_CONTROL_MASKFULL (IMG_UINT64_C(0x000000000000000F))
  4339. #define VHA_CR_OS2_CNN_DEBUG_CONTROL_CNN_PERF_ENABLE_SHIFT (2U)
  4340. #define VHA_CR_OS2_CNN_DEBUG_CONTROL_CNN_PERF_ENABLE_CLRMSK (0XFFFFFFF3U)
  4341. #define VHA_CR_OS2_CNN_DEBUG_CONTROL_CNN_PERF_ENABLE_DISABLE (00000000U)
  4342. #define VHA_CR_OS2_CNN_DEBUG_CONTROL_CNN_PERF_ENABLE_STREAM (0X00000004U)
  4343. #define VHA_CR_OS2_CNN_DEBUG_CONTROL_CNN_PERF_ENABLE_LAYER (0X00000008U)
  4344. #define VHA_CR_OS2_CNN_DEBUG_CONTROL_CNN_PERF_ENABLE_PASS (0X0000000CU)
  4345. #define VHA_CR_OS2_CNN_DEBUG_CONTROL_CNN_BAND_ENABLE_SHIFT (0U)
  4346. #define VHA_CR_OS2_CNN_DEBUG_CONTROL_CNN_BAND_ENABLE_CLRMSK (0XFFFFFFFCU)
  4347. #define VHA_CR_OS2_CNN_DEBUG_CONTROL_CNN_BAND_ENABLE_DISABLE (00000000U)
  4348. #define VHA_CR_OS2_CNN_DEBUG_CONTROL_CNN_BAND_ENABLE_STREAM (0X00000001U)
  4349. #define VHA_CR_OS2_CNN_DEBUG_CONTROL_CNN_BAND_ENABLE_LAYER (0X00000002U)
  4350. #define VHA_CR_OS2_CNN_DEBUG_CONTROL_CNN_BAND_ENABLE_PASS (0X00000003U)
  4351. /*
  4352. Register VHA_CR_OS2_CNN_DEBUG_STATUS
  4353. */
  4354. #define VHA_CR_OS2_CNN_DEBUG_STATUS (0x30128U)
  4355. #define VHA_CR_OS2_CNN_DEBUG_STATUS_MASKFULL (IMG_UINT64_C(0x000000000007FFFF))
  4356. #define VHA_CR_OS2_CNN_DEBUG_STATUS_CNN_DEBUG_OFFSET_SHIFT (0U)
  4357. #define VHA_CR_OS2_CNN_DEBUG_STATUS_CNN_DEBUG_OFFSET_CLRMSK (0XFFF80000U)
  4358. /*
  4359. Register VHA_CR_OS2_CNN_PRELOAD_CONTROL
  4360. */
  4361. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL (0x30130U)
  4362. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_MASKFULL (IMG_UINT64_C(0x0000000001FF7777))
  4363. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_SHIFT (22U)
  4364. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFE3FFFFF))
  4365. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_DISABLE (IMG_UINT64_C(0000000000000000))
  4366. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_N_64 (IMG_UINT64_C(0x0000000000400000))
  4367. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_N_128 (IMG_UINT64_C(0x0000000000800000))
  4368. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_N_192 (IMG_UINT64_C(0x0000000000c00000))
  4369. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_N_256 (IMG_UINT64_C(0x0000000001000000))
  4370. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_N_320 (IMG_UINT64_C(0x0000000001400000))
  4371. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_N_384 (IMG_UINT64_C(0x0000000001800000))
  4372. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_MMM_WR_N_REQS_N_448 (IMG_UINT64_C(0x0000000001c00000))
  4373. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_SHIFT (19U)
  4374. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFC7FFFF))
  4375. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_DISABLE (IMG_UINT64_C(0000000000000000))
  4376. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_N_64 (IMG_UINT64_C(0x0000000000080000))
  4377. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_N_128 (IMG_UINT64_C(0x0000000000100000))
  4378. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_N_192 (IMG_UINT64_C(0x0000000000180000))
  4379. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_N_256 (IMG_UINT64_C(0x0000000000200000))
  4380. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_N_320 (IMG_UINT64_C(0x0000000000280000))
  4381. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_N_384 (IMG_UINT64_C(0x0000000000300000))
  4382. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_MMM_RD_N_REQS_N_448 (IMG_UINT64_C(0x0000000000380000))
  4383. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_SHIFT (16U)
  4384. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF8FFFF))
  4385. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_DISABLE (IMG_UINT64_C(0000000000000000))
  4386. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_N_64 (IMG_UINT64_C(0x0000000000010000))
  4387. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_N_128 (IMG_UINT64_C(0x0000000000020000))
  4388. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_N_192 (IMG_UINT64_C(0x0000000000030000))
  4389. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_N_256 (IMG_UINT64_C(0x0000000000040000))
  4390. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_N_320 (IMG_UINT64_C(0x0000000000050000))
  4391. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_N_384 (IMG_UINT64_C(0x0000000000060000))
  4392. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_OUTPACK_N_REQS_N_448 (IMG_UINT64_C(0x0000000000070000))
  4393. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_EWO_N_REQS_SHIFT (12U)
  4394. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_EWO_N_REQS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF8FFF))
  4395. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_EWO_N_REQS_DISABLE (IMG_UINT64_C(0000000000000000))
  4396. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_EWO_N_REQS_N_64 (IMG_UINT64_C(0x0000000000001000))
  4397. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_EWO_N_REQS_N_128 (IMG_UINT64_C(0x0000000000002000))
  4398. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_EWO_N_REQS_N_192 (IMG_UINT64_C(0x0000000000003000))
  4399. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_EWO_N_REQS_N_256 (IMG_UINT64_C(0x0000000000004000))
  4400. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_EWO_N_REQS_N_320 (IMG_UINT64_C(0x0000000000005000))
  4401. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_EWO_N_REQS_N_384 (IMG_UINT64_C(0x0000000000006000))
  4402. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_EWO_N_REQS_N_448 (IMG_UINT64_C(0x0000000000007000))
  4403. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_ABUF_N_REQS_SHIFT (8U)
  4404. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_ABUF_N_REQS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF8FF))
  4405. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_ABUF_N_REQS_DISABLE (IMG_UINT64_C(0000000000000000))
  4406. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_ABUF_N_REQS_N_64 (IMG_UINT64_C(0x0000000000000100))
  4407. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_ABUF_N_REQS_N_128 (IMG_UINT64_C(0x0000000000000200))
  4408. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_ABUF_N_REQS_N_192 (IMG_UINT64_C(0x0000000000000300))
  4409. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_ABUF_N_REQS_N_256 (IMG_UINT64_C(0x0000000000000400))
  4410. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_ABUF_N_REQS_N_320 (IMG_UINT64_C(0x0000000000000500))
  4411. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_ABUF_N_REQS_N_384 (IMG_UINT64_C(0x0000000000000600))
  4412. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_ABUF_N_REQS_N_448 (IMG_UINT64_C(0x0000000000000700))
  4413. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_CBUF_N_REQS_SHIFT (4U)
  4414. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_CBUF_N_REQS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFF8F))
  4415. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_CBUF_N_REQS_DISABLE (IMG_UINT64_C(0000000000000000))
  4416. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_CBUF_N_REQS_N_64 (IMG_UINT64_C(0x0000000000000010))
  4417. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_CBUF_N_REQS_N_128 (IMG_UINT64_C(0x0000000000000020))
  4418. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_CBUF_N_REQS_N_192 (IMG_UINT64_C(0x0000000000000030))
  4419. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_CBUF_N_REQS_N_256 (IMG_UINT64_C(0x0000000000000040))
  4420. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_CBUF_N_REQS_N_320 (IMG_UINT64_C(0x0000000000000050))
  4421. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_CBUF_N_REQS_N_384 (IMG_UINT64_C(0x0000000000000060))
  4422. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_CBUF_N_REQS_N_448 (IMG_UINT64_C(0x0000000000000070))
  4423. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_IBUF_N_REQS_SHIFT (0U)
  4424. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_IBUF_N_REQS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF8))
  4425. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_IBUF_N_REQS_DISABLE (IMG_UINT64_C(0000000000000000))
  4426. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_IBUF_N_REQS_N_64 (IMG_UINT64_C(0x0000000000000001))
  4427. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_IBUF_N_REQS_N_128 (IMG_UINT64_C(0x0000000000000002))
  4428. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_IBUF_N_REQS_N_192 (IMG_UINT64_C(0x0000000000000003))
  4429. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_IBUF_N_REQS_N_256 (IMG_UINT64_C(0x0000000000000004))
  4430. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_IBUF_N_REQS_N_320 (IMG_UINT64_C(0x0000000000000005))
  4431. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_IBUF_N_REQS_N_384 (IMG_UINT64_C(0x0000000000000006))
  4432. #define VHA_CR_OS2_CNN_PRELOAD_CONTROL_IBUF_N_REQS_N_448 (IMG_UINT64_C(0x0000000000000007))
  4433. /*
  4434. Register VHA_CR_OS2_CNN_ALT_ADDRESS8
  4435. */
  4436. #define VHA_CR_OS2_CNN_ALT_ADDRESS8 (0x30140U)
  4437. #define VHA_CR_OS2_CNN_ALT_ADDRESS8_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  4438. #define VHA_CR_OS2_CNN_ALT_ADDRESS8_ALT_ADDR_SHIFT (0U)
  4439. #define VHA_CR_OS2_CNN_ALT_ADDRESS8_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  4440. /*
  4441. Register VHA_CR_OS2_CNN_ALT_ADDRESS9
  4442. */
  4443. #define VHA_CR_OS2_CNN_ALT_ADDRESS9 (0x30148U)
  4444. #define VHA_CR_OS2_CNN_ALT_ADDRESS9_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  4445. #define VHA_CR_OS2_CNN_ALT_ADDRESS9_ALT_ADDR_SHIFT (0U)
  4446. #define VHA_CR_OS2_CNN_ALT_ADDRESS9_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  4447. /*
  4448. Register VHA_CR_OS2_CNN_ALT_ADDRESS10
  4449. */
  4450. #define VHA_CR_OS2_CNN_ALT_ADDRESS10 (0x30150U)
  4451. #define VHA_CR_OS2_CNN_ALT_ADDRESS10_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  4452. #define VHA_CR_OS2_CNN_ALT_ADDRESS10_ALT_ADDR_SHIFT (0U)
  4453. #define VHA_CR_OS2_CNN_ALT_ADDRESS10_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  4454. /*
  4455. Register VHA_CR_OS2_CNN_ALT_ADDRESS11
  4456. */
  4457. #define VHA_CR_OS2_CNN_ALT_ADDRESS11 (0x30158U)
  4458. #define VHA_CR_OS2_CNN_ALT_ADDRESS11_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  4459. #define VHA_CR_OS2_CNN_ALT_ADDRESS11_ALT_ADDR_SHIFT (0U)
  4460. #define VHA_CR_OS2_CNN_ALT_ADDRESS11_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  4461. /*
  4462. Register VHA_CR_OS2_CNN_ALT_ADDRESS12
  4463. */
  4464. #define VHA_CR_OS2_CNN_ALT_ADDRESS12 (0x30160U)
  4465. #define VHA_CR_OS2_CNN_ALT_ADDRESS12_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  4466. #define VHA_CR_OS2_CNN_ALT_ADDRESS12_ALT_ADDR_SHIFT (0U)
  4467. #define VHA_CR_OS2_CNN_ALT_ADDRESS12_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  4468. /*
  4469. Register VHA_CR_OS2_CNN_ALT_ADDRESS13
  4470. */
  4471. #define VHA_CR_OS2_CNN_ALT_ADDRESS13 (0x30168U)
  4472. #define VHA_CR_OS2_CNN_ALT_ADDRESS13_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  4473. #define VHA_CR_OS2_CNN_ALT_ADDRESS13_ALT_ADDR_SHIFT (0U)
  4474. #define VHA_CR_OS2_CNN_ALT_ADDRESS13_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  4475. /*
  4476. Register VHA_CR_OS2_CNN_ALT_ADDRESS14
  4477. */
  4478. #define VHA_CR_OS2_CNN_ALT_ADDRESS14 (0x30170U)
  4479. #define VHA_CR_OS2_CNN_ALT_ADDRESS14_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  4480. #define VHA_CR_OS2_CNN_ALT_ADDRESS14_ALT_ADDR_SHIFT (0U)
  4481. #define VHA_CR_OS2_CNN_ALT_ADDRESS14_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  4482. /*
  4483. Register VHA_CR_OS2_CNN_ALT_ADDRESS15
  4484. */
  4485. #define VHA_CR_OS2_CNN_ALT_ADDRESS15 (0x30178U)
  4486. #define VHA_CR_OS2_CNN_ALT_ADDRESS15_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  4487. #define VHA_CR_OS2_CNN_ALT_ADDRESS15_ALT_ADDR_SHIFT (0U)
  4488. #define VHA_CR_OS2_CNN_ALT_ADDRESS15_ALT_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  4489. /*
  4490. Register VHA_CR_OS2_CNN_PERFORMANCE
  4491. */
  4492. #define VHA_CR_OS2_CNN_PERFORMANCE (0x301A0U)
  4493. #define VHA_CR_OS2_CNN_PERFORMANCE_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  4494. #define VHA_CR_OS2_CNN_PERFORMANCE_VALUE_SHIFT (0U)
  4495. #define VHA_CR_OS2_CNN_PERFORMANCE_VALUE_CLRMSK (00000000U)
  4496. /*
  4497. Register VHA_CR_OS2_OCM_BASE_ADDR
  4498. */
  4499. #define VHA_CR_OS2_OCM_BASE_ADDR (0x30200U)
  4500. #define VHA_CR_OS2_OCM_BASE_ADDR_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  4501. #define VHA_CR_OS2_OCM_BASE_ADDR_BASE_ADDR_SHIFT (0U)
  4502. #define VHA_CR_OS2_OCM_BASE_ADDR_BASE_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  4503. /*
  4504. Register VHA_CR_OS2_SAVE_RESTORE_BUFFER_BASE_ADDR
  4505. */
  4506. #define VHA_CR_OS2_SAVE_RESTORE_BUFFER_BASE_ADDR (0x30208U)
  4507. #define VHA_CR_OS2_SAVE_RESTORE_BUFFER_BASE_ADDR_MASKFULL (IMG_UINT64_C(0x000000FFFFFFFFFF))
  4508. #define VHA_CR_OS2_SAVE_RESTORE_BUFFER_BASE_ADDR_BASE_ADDR_SHIFT (0U)
  4509. #define VHA_CR_OS2_SAVE_RESTORE_BUFFER_BASE_ADDR_BASE_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFF0000000000))
  4510. /*
  4511. Register VHA_CR_OS2_SAVE_RESTORE_CTRL
  4512. */
  4513. #define VHA_CR_OS2_SAVE_RESTORE_CTRL (0x30210U)
  4514. #define VHA_CR_OS2_SAVE_RESTORE_CTRL_MASKFULL (IMG_UINT64_C(0x000000000000000F))
  4515. #define VHA_CR_OS2_SAVE_RESTORE_CTRL_N_REQS_SHIFT (1U)
  4516. #define VHA_CR_OS2_SAVE_RESTORE_CTRL_N_REQS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF1))
  4517. #define VHA_CR_OS2_SAVE_RESTORE_CTRL_N_REQS_DISABLE (IMG_UINT64_C(0000000000000000))
  4518. #define VHA_CR_OS2_SAVE_RESTORE_CTRL_N_REQS_N_64 (IMG_UINT64_C(0x0000000000000002))
  4519. #define VHA_CR_OS2_SAVE_RESTORE_CTRL_N_REQS_N_128 (IMG_UINT64_C(0x0000000000000004))
  4520. #define VHA_CR_OS2_SAVE_RESTORE_CTRL_N_REQS_N_192 (IMG_UINT64_C(0x0000000000000006))
  4521. #define VHA_CR_OS2_SAVE_RESTORE_CTRL_N_REQS_N_256 (IMG_UINT64_C(0x0000000000000008))
  4522. #define VHA_CR_OS2_SAVE_RESTORE_CTRL_N_REQS_N_320 (IMG_UINT64_C(0x000000000000000a))
  4523. #define VHA_CR_OS2_SAVE_RESTORE_CTRL_N_REQS_N_384 (IMG_UINT64_C(0x000000000000000c))
  4524. #define VHA_CR_OS2_SAVE_RESTORE_CTRL_N_REQS_N_448 (IMG_UINT64_C(0x000000000000000e))
  4525. #define VHA_CR_OS2_SAVE_RESTORE_CTRL_WRITE_CACHE_POLICY_SHIFT (0U)
  4526. #define VHA_CR_OS2_SAVE_RESTORE_CTRL_WRITE_CACHE_POLICY_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  4527. #define VHA_CR_OS2_SAVE_RESTORE_CTRL_WRITE_CACHE_POLICY_EN (IMG_UINT64_C(0X0000000000000001))
  4528. /*
  4529. Register VHA_CR_OS2_CNN_CRC_MASK_CTRL
  4530. */
  4531. #define VHA_CR_OS2_CNN_CRC_MASK_CTRL (0x30300U)
  4532. #define VHA_CR_OS2_CNN_CRC_MASK_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000000003))
  4533. #define VHA_CR_OS2_CNN_CRC_MASK_CTRL_LEVEL_SHIFT (0U)
  4534. #define VHA_CR_OS2_CNN_CRC_MASK_CTRL_LEVEL_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFC))
  4535. #define VHA_CR_OS2_CNN_CRC_MASK_CTRL_LEVEL_NO_MASK (IMG_UINT64_C(0000000000000000))
  4536. #define VHA_CR_OS2_CNN_CRC_MASK_CTRL_LEVEL_MASK_L1 (IMG_UINT64_C(0x0000000000000001))
  4537. #define VHA_CR_OS2_CNN_CRC_MASK_CTRL_LEVEL_MASK_L2 (IMG_UINT64_C(0x0000000000000002))
  4538. #define VHA_CR_OS2_CNN_CRC_MASK_CTRL_LEVEL_MASK_L3 (IMG_UINT64_C(0x0000000000000003))
  4539. /*
  4540. Register VHA_CR_OS2_MMU_CTRL_INVAL
  4541. */
  4542. #define VHA_CR_OS2_MMU_CTRL_INVAL (0x3E000U)
  4543. #define VHA_CR_OS2_MMU_CTRL_INVAL_MASKFULL (IMG_UINT64_C(0x0000000000000FFF))
  4544. #define VHA_CR_OS2_MMU_CTRL_INVAL_ALL_CONTEXTS_SHIFT (11U)
  4545. #define VHA_CR_OS2_MMU_CTRL_INVAL_ALL_CONTEXTS_CLRMSK (0XFFFFF7FFU)
  4546. #define VHA_CR_OS2_MMU_CTRL_INVAL_ALL_CONTEXTS_EN (0X00000800U)
  4547. #define VHA_CR_OS2_MMU_CTRL_INVAL_CONTEXT_SHIFT (3U)
  4548. #define VHA_CR_OS2_MMU_CTRL_INVAL_CONTEXT_CLRMSK (0XFFFFF807U)
  4549. #define VHA_CR_OS2_MMU_CTRL_INVAL_PC_SHIFT (2U)
  4550. #define VHA_CR_OS2_MMU_CTRL_INVAL_PC_CLRMSK (0XFFFFFFFBU)
  4551. #define VHA_CR_OS2_MMU_CTRL_INVAL_PC_EN (0X00000004U)
  4552. #define VHA_CR_OS2_MMU_CTRL_INVAL_PD_SHIFT (1U)
  4553. #define VHA_CR_OS2_MMU_CTRL_INVAL_PD_CLRMSK (0XFFFFFFFDU)
  4554. #define VHA_CR_OS2_MMU_CTRL_INVAL_PD_EN (0X00000002U)
  4555. #define VHA_CR_OS2_MMU_CTRL_INVAL_PT_SHIFT (0U)
  4556. #define VHA_CR_OS2_MMU_CTRL_INVAL_PT_CLRMSK (0XFFFFFFFEU)
  4557. #define VHA_CR_OS2_MMU_CTRL_INVAL_PT_EN (0X00000001U)
  4558. /*
  4559. Register VHA_CR_OS2_MMU_CTRL_INVAL_STATUS
  4560. */
  4561. #define VHA_CR_OS2_MMU_CTRL_INVAL_STATUS (0x3E038U)
  4562. #define VHA_CR_OS2_MMU_CTRL_INVAL_STATUS_MASKFULL (IMG_UINT64_C(0x0000000080000001))
  4563. #define VHA_CR_OS2_MMU_CTRL_INVAL_STATUS_PARITY_SHIFT (31U)
  4564. #define VHA_CR_OS2_MMU_CTRL_INVAL_STATUS_PARITY_CLRMSK (0X7FFFFFFFU)
  4565. #define VHA_CR_OS2_MMU_CTRL_INVAL_STATUS_PARITY_EN (0X80000000U)
  4566. #define VHA_CR_OS2_MMU_CTRL_INVAL_STATUS_PENDING_SHIFT (0U)
  4567. #define VHA_CR_OS2_MMU_CTRL_INVAL_STATUS_PENDING_CLRMSK (0XFFFFFFFEU)
  4568. #define VHA_CR_OS2_MMU_CTRL_INVAL_STATUS_PENDING_EN (0X00000001U)
  4569. /*
  4570. Register VHA_CR_OS2_MMU_CBASE_MAPPING_CONTEXT
  4571. */
  4572. #define VHA_CR_OS2_MMU_CBASE_MAPPING_CONTEXT (0x3E008U)
  4573. #define VHA_CR_OS2_MMU_CBASE_MAPPING_CONTEXT_MASKFULL (IMG_UINT64_C(0x00000000000000FF))
  4574. #define VHA_CR_OS2_MMU_CBASE_MAPPING_CONTEXT_ID_SHIFT (0U)
  4575. #define VHA_CR_OS2_MMU_CBASE_MAPPING_CONTEXT_ID_CLRMSK (0XFFFFFF00U)
  4576. /*
  4577. Register VHA_CR_OS2_MMU_CBASE_MAPPING
  4578. */
  4579. #define VHA_CR_OS2_MMU_CBASE_MAPPING (0x3E010U)
  4580. #define VHA_CR_OS2_MMU_CBASE_MAPPING_MASKFULL (IMG_UINT64_C(0x000000001FFFFFFF))
  4581. #define VHA_CR_OS2_MMU_CBASE_MAPPING_INVALID_SHIFT (28U)
  4582. #define VHA_CR_OS2_MMU_CBASE_MAPPING_INVALID_CLRMSK (0XEFFFFFFFU)
  4583. #define VHA_CR_OS2_MMU_CBASE_MAPPING_INVALID_EN (0X10000000U)
  4584. #define VHA_CR_OS2_MMU_CBASE_MAPPING_BASE_ADDR_SHIFT (0U)
  4585. #define VHA_CR_OS2_MMU_CBASE_MAPPING_BASE_ADDR_CLRMSK (0XF0000000U)
  4586. #define VHA_CR_OS2_MMU_CBASE_MAPPING_BASE_ADDR_ALIGNSHIFT (12U)
  4587. #define VHA_CR_OS2_MMU_CBASE_MAPPING_BASE_ADDR_ALIGNSIZE (4096U)
  4588. /*
  4589. Register VHA_CR_OS2_MMU_FAULT_STATUS1
  4590. */
  4591. #define VHA_CR_OS2_MMU_FAULT_STATUS1 (0x3E018U)
  4592. #define VHA_CR_OS2_MMU_FAULT_STATUS1_MASKFULL (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
  4593. #define VHA_CR_OS2_MMU_FAULT_STATUS1_LEVEL_SHIFT (62U)
  4594. #define VHA_CR_OS2_MMU_FAULT_STATUS1_LEVEL_CLRMSK (IMG_UINT64_C(0X3FFFFFFFFFFFFFFF))
  4595. #define VHA_CR_OS2_MMU_FAULT_STATUS1_REQ_ID_SHIFT (56U)
  4596. #define VHA_CR_OS2_MMU_FAULT_STATUS1_REQ_ID_CLRMSK (IMG_UINT64_C(0XC0FFFFFFFFFFFFFF))
  4597. #define VHA_CR_OS2_MMU_FAULT_STATUS1_CONTEXT_SHIFT (48U)
  4598. #define VHA_CR_OS2_MMU_FAULT_STATUS1_CONTEXT_CLRMSK (IMG_UINT64_C(0XFF00FFFFFFFFFFFF))
  4599. #define VHA_CR_OS2_MMU_FAULT_STATUS1_ADDRESS_SHIFT (4U)
  4600. #define VHA_CR_OS2_MMU_FAULT_STATUS1_ADDRESS_CLRMSK (IMG_UINT64_C(0XFFFF00000000000F))
  4601. #define VHA_CR_OS2_MMU_FAULT_STATUS1_RNW_SHIFT (3U)
  4602. #define VHA_CR_OS2_MMU_FAULT_STATUS1_RNW_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF7))
  4603. #define VHA_CR_OS2_MMU_FAULT_STATUS1_RNW_EN (IMG_UINT64_C(0X0000000000000008))
  4604. #define VHA_CR_OS2_MMU_FAULT_STATUS1_TYPE_SHIFT (1U)
  4605. #define VHA_CR_OS2_MMU_FAULT_STATUS1_TYPE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF9))
  4606. #define VHA_CR_OS2_MMU_FAULT_STATUS1_FAULT_SHIFT (0U)
  4607. #define VHA_CR_OS2_MMU_FAULT_STATUS1_FAULT_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  4608. #define VHA_CR_OS2_MMU_FAULT_STATUS1_FAULT_EN (IMG_UINT64_C(0X0000000000000001))
  4609. /*
  4610. Register VHA_CR_OS2_MMU_FAULT_STATUS2
  4611. */
  4612. #define VHA_CR_OS2_MMU_FAULT_STATUS2 (0x3E020U)
  4613. #define VHA_CR_OS2_MMU_FAULT_STATUS2_MASKFULL (IMG_UINT64_C(0x000000003FFF07FF))
  4614. #define VHA_CR_OS2_MMU_FAULT_STATUS2_WRITEBACK_SHIFT (29U)
  4615. #define VHA_CR_OS2_MMU_FAULT_STATUS2_WRITEBACK_CLRMSK (0XDFFFFFFFU)
  4616. #define VHA_CR_OS2_MMU_FAULT_STATUS2_WRITEBACK_EN (0X20000000U)
  4617. #define VHA_CR_OS2_MMU_FAULT_STATUS2_CLEANUNIQUE_SHIFT (28U)
  4618. #define VHA_CR_OS2_MMU_FAULT_STATUS2_CLEANUNIQUE_CLRMSK (0XEFFFFFFFU)
  4619. #define VHA_CR_OS2_MMU_FAULT_STATUS2_CLEANUNIQUE_EN (0X10000000U)
  4620. #define VHA_CR_OS2_MMU_FAULT_STATUS2_BANK_SHIFT (24U)
  4621. #define VHA_CR_OS2_MMU_FAULT_STATUS2_BANK_CLRMSK (0XF0FFFFFFU)
  4622. #define VHA_CR_OS2_MMU_FAULT_STATUS2_TLB_ENTRY_SHIFT (16U)
  4623. #define VHA_CR_OS2_MMU_FAULT_STATUS2_TLB_ENTRY_CLRMSK (0XFF00FFFFU)
  4624. #define VHA_CR_OS2_MMU_FAULT_STATUS2_FBM_FAULT_SHIFT (10U)
  4625. #define VHA_CR_OS2_MMU_FAULT_STATUS2_FBM_FAULT_CLRMSK (0XFFFFFBFFU)
  4626. #define VHA_CR_OS2_MMU_FAULT_STATUS2_FBM_FAULT_EN (0X00000400U)
  4627. #define VHA_CR_OS2_MMU_FAULT_STATUS2_BIF_ID_SHIFT (0U)
  4628. #define VHA_CR_OS2_MMU_FAULT_STATUS2_BIF_ID_CLRMSK (0XFFFFFC00U)
  4629. /*
  4630. Register VHA_CR_OS2_MMU_CTRL_LEGACY
  4631. */
  4632. #define VHA_CR_OS2_MMU_CTRL_LEGACY (0x3E040U)
  4633. #define VHA_CR_OS2_MMU_CTRL_LEGACY_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  4634. #define VHA_CR_OS2_MMU_CTRL_LEGACY_RESERVED_SHIFT (0U)
  4635. #define VHA_CR_OS2_MMU_CTRL_LEGACY_RESERVED_CLRMSK (0XFFFFFFFEU)
  4636. #define VHA_CR_OS2_MMU_CTRL_LEGACY_RESERVED_EN (0X00000001U)
  4637. #define VHA_CR_ACE_PROT_CTRL_ENUM_PROT_MASK (0x00000007U)
  4638. /*
  4639. Unprivileged secure data access*/
  4640. #define VHA_CR_ACE_PROT_CTRL_ENUM_PROT_UNPRIVILEGED_SECURE_DATA (0x00000000U)
  4641. /*
  4642. Privileged secure data access*/
  4643. #define VHA_CR_ACE_PROT_CTRL_ENUM_PROT_PRIVILEGED_SECURE_DATA (0x00000001U)
  4644. /*
  4645. Unprivileged non-secure data access*/
  4646. #define VHA_CR_ACE_PROT_CTRL_ENUM_PROT_UNPRIVILEGED_NONSECURE_DATA (0x00000002U)
  4647. /*
  4648. Privileged non-secure data access*/
  4649. #define VHA_CR_ACE_PROT_CTRL_ENUM_PROT_PRIVILEGED_NONSECURE_DATA (0x00000003U)
  4650. /*
  4651. Unprivileged secure instruction access*/
  4652. #define VHA_CR_ACE_PROT_CTRL_ENUM_PROT_UNPRIVILEGED_SECURE_INSTRUCTION (0x00000004U)
  4653. /*
  4654. Privileged secure instruction access*/
  4655. #define VHA_CR_ACE_PROT_CTRL_ENUM_PROT_PRIVILEGED_SECURE_INSTRUCTION (0x00000005U)
  4656. /*
  4657. Unprivileged non-secure instruction access*/
  4658. #define VHA_CR_ACE_PROT_CTRL_ENUM_PROT_UNPRIVILEGED_NONSECURE_INSTRUCTION (0x00000006U)
  4659. /*
  4660. Privileged non-secure instruction access*/
  4661. #define VHA_CR_ACE_PROT_CTRL_ENUM_PROT_PRIVILEGED_NONSECURE_INSTRUCTION (0x00000007U)
  4662. /*
  4663. Register VHA_CR_ACE_PROT_CTRL
  4664. */
  4665. #define VHA_CR_ACE_PROT_CTRL (0x40000U)
  4666. #define VHA_CR_ACE_PROT_CTRL_MASKFULL (IMG_UINT64_C(0x0707070707070707))
  4667. #define VHA_CR_ACE_PROT_CTRL_OSID7_SHIFT (56U)
  4668. #define VHA_CR_ACE_PROT_CTRL_OSID7_CLRMSK (IMG_UINT64_C(0XF8FFFFFFFFFFFFFF))
  4669. #define VHA_CR_ACE_PROT_CTRL_OSID7_UNPRIVILEGED_SECURE_DATA (IMG_UINT64_C(0000000000000000))
  4670. #define VHA_CR_ACE_PROT_CTRL_OSID7_PRIVILEGED_SECURE_DATA (IMG_UINT64_C(0x0100000000000000))
  4671. #define VHA_CR_ACE_PROT_CTRL_OSID7_UNPRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0200000000000000))
  4672. #define VHA_CR_ACE_PROT_CTRL_OSID7_PRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0300000000000000))
  4673. #define VHA_CR_ACE_PROT_CTRL_OSID7_UNPRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0400000000000000))
  4674. #define VHA_CR_ACE_PROT_CTRL_OSID7_PRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0500000000000000))
  4675. #define VHA_CR_ACE_PROT_CTRL_OSID7_UNPRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0600000000000000))
  4676. #define VHA_CR_ACE_PROT_CTRL_OSID7_PRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0700000000000000))
  4677. #define VHA_CR_ACE_PROT_CTRL_OSID6_SHIFT (48U)
  4678. #define VHA_CR_ACE_PROT_CTRL_OSID6_CLRMSK (IMG_UINT64_C(0XFFF8FFFFFFFFFFFF))
  4679. #define VHA_CR_ACE_PROT_CTRL_OSID6_UNPRIVILEGED_SECURE_DATA (IMG_UINT64_C(0000000000000000))
  4680. #define VHA_CR_ACE_PROT_CTRL_OSID6_PRIVILEGED_SECURE_DATA (IMG_UINT64_C(0x0001000000000000))
  4681. #define VHA_CR_ACE_PROT_CTRL_OSID6_UNPRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0002000000000000))
  4682. #define VHA_CR_ACE_PROT_CTRL_OSID6_PRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0003000000000000))
  4683. #define VHA_CR_ACE_PROT_CTRL_OSID6_UNPRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0004000000000000))
  4684. #define VHA_CR_ACE_PROT_CTRL_OSID6_PRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0005000000000000))
  4685. #define VHA_CR_ACE_PROT_CTRL_OSID6_UNPRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0006000000000000))
  4686. #define VHA_CR_ACE_PROT_CTRL_OSID6_PRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0007000000000000))
  4687. #define VHA_CR_ACE_PROT_CTRL_OSID5_SHIFT (40U)
  4688. #define VHA_CR_ACE_PROT_CTRL_OSID5_CLRMSK (IMG_UINT64_C(0XFFFFF8FFFFFFFFFF))
  4689. #define VHA_CR_ACE_PROT_CTRL_OSID5_UNPRIVILEGED_SECURE_DATA (IMG_UINT64_C(0000000000000000))
  4690. #define VHA_CR_ACE_PROT_CTRL_OSID5_PRIVILEGED_SECURE_DATA (IMG_UINT64_C(0x0000010000000000))
  4691. #define VHA_CR_ACE_PROT_CTRL_OSID5_UNPRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0000020000000000))
  4692. #define VHA_CR_ACE_PROT_CTRL_OSID5_PRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0000030000000000))
  4693. #define VHA_CR_ACE_PROT_CTRL_OSID5_UNPRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0000040000000000))
  4694. #define VHA_CR_ACE_PROT_CTRL_OSID5_PRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0000050000000000))
  4695. #define VHA_CR_ACE_PROT_CTRL_OSID5_UNPRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0000060000000000))
  4696. #define VHA_CR_ACE_PROT_CTRL_OSID5_PRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0000070000000000))
  4697. #define VHA_CR_ACE_PROT_CTRL_OSID4_SHIFT (32U)
  4698. #define VHA_CR_ACE_PROT_CTRL_OSID4_CLRMSK (IMG_UINT64_C(0XFFFFFFF8FFFFFFFF))
  4699. #define VHA_CR_ACE_PROT_CTRL_OSID4_UNPRIVILEGED_SECURE_DATA (IMG_UINT64_C(0000000000000000))
  4700. #define VHA_CR_ACE_PROT_CTRL_OSID4_PRIVILEGED_SECURE_DATA (IMG_UINT64_C(0x0000000100000000))
  4701. #define VHA_CR_ACE_PROT_CTRL_OSID4_UNPRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0000000200000000))
  4702. #define VHA_CR_ACE_PROT_CTRL_OSID4_PRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0000000300000000))
  4703. #define VHA_CR_ACE_PROT_CTRL_OSID4_UNPRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0000000400000000))
  4704. #define VHA_CR_ACE_PROT_CTRL_OSID4_PRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0000000500000000))
  4705. #define VHA_CR_ACE_PROT_CTRL_OSID4_UNPRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0000000600000000))
  4706. #define VHA_CR_ACE_PROT_CTRL_OSID4_PRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0000000700000000))
  4707. #define VHA_CR_ACE_PROT_CTRL_OSID3_SHIFT (24U)
  4708. #define VHA_CR_ACE_PROT_CTRL_OSID3_CLRMSK (IMG_UINT64_C(0XFFFFFFFFF8FFFFFF))
  4709. #define VHA_CR_ACE_PROT_CTRL_OSID3_UNPRIVILEGED_SECURE_DATA (IMG_UINT64_C(0000000000000000))
  4710. #define VHA_CR_ACE_PROT_CTRL_OSID3_PRIVILEGED_SECURE_DATA (IMG_UINT64_C(0x0000000001000000))
  4711. #define VHA_CR_ACE_PROT_CTRL_OSID3_UNPRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0000000002000000))
  4712. #define VHA_CR_ACE_PROT_CTRL_OSID3_PRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0000000003000000))
  4713. #define VHA_CR_ACE_PROT_CTRL_OSID3_UNPRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0000000004000000))
  4714. #define VHA_CR_ACE_PROT_CTRL_OSID3_PRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0000000005000000))
  4715. #define VHA_CR_ACE_PROT_CTRL_OSID3_UNPRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0000000006000000))
  4716. #define VHA_CR_ACE_PROT_CTRL_OSID3_PRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0000000007000000))
  4717. #define VHA_CR_ACE_PROT_CTRL_OSID2_SHIFT (16U)
  4718. #define VHA_CR_ACE_PROT_CTRL_OSID2_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFF8FFFF))
  4719. #define VHA_CR_ACE_PROT_CTRL_OSID2_UNPRIVILEGED_SECURE_DATA (IMG_UINT64_C(0000000000000000))
  4720. #define VHA_CR_ACE_PROT_CTRL_OSID2_PRIVILEGED_SECURE_DATA (IMG_UINT64_C(0x0000000000010000))
  4721. #define VHA_CR_ACE_PROT_CTRL_OSID2_UNPRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0000000000020000))
  4722. #define VHA_CR_ACE_PROT_CTRL_OSID2_PRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0000000000030000))
  4723. #define VHA_CR_ACE_PROT_CTRL_OSID2_UNPRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0000000000040000))
  4724. #define VHA_CR_ACE_PROT_CTRL_OSID2_PRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0000000000050000))
  4725. #define VHA_CR_ACE_PROT_CTRL_OSID2_UNPRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0000000000060000))
  4726. #define VHA_CR_ACE_PROT_CTRL_OSID2_PRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0000000000070000))
  4727. #define VHA_CR_ACE_PROT_CTRL_OSID1_SHIFT (8U)
  4728. #define VHA_CR_ACE_PROT_CTRL_OSID1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFF8FF))
  4729. #define VHA_CR_ACE_PROT_CTRL_OSID1_UNPRIVILEGED_SECURE_DATA (IMG_UINT64_C(0000000000000000))
  4730. #define VHA_CR_ACE_PROT_CTRL_OSID1_PRIVILEGED_SECURE_DATA (IMG_UINT64_C(0x0000000000000100))
  4731. #define VHA_CR_ACE_PROT_CTRL_OSID1_UNPRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0000000000000200))
  4732. #define VHA_CR_ACE_PROT_CTRL_OSID1_PRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0000000000000300))
  4733. #define VHA_CR_ACE_PROT_CTRL_OSID1_UNPRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0000000000000400))
  4734. #define VHA_CR_ACE_PROT_CTRL_OSID1_PRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0000000000000500))
  4735. #define VHA_CR_ACE_PROT_CTRL_OSID1_UNPRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0000000000000600))
  4736. #define VHA_CR_ACE_PROT_CTRL_OSID1_PRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0000000000000700))
  4737. #define VHA_CR_ACE_PROT_CTRL_OSID0_SHIFT (0U)
  4738. #define VHA_CR_ACE_PROT_CTRL_OSID0_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFF8))
  4739. #define VHA_CR_ACE_PROT_CTRL_OSID0_UNPRIVILEGED_SECURE_DATA (IMG_UINT64_C(0000000000000000))
  4740. #define VHA_CR_ACE_PROT_CTRL_OSID0_PRIVILEGED_SECURE_DATA (IMG_UINT64_C(0x0000000000000001))
  4741. #define VHA_CR_ACE_PROT_CTRL_OSID0_UNPRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0000000000000002))
  4742. #define VHA_CR_ACE_PROT_CTRL_OSID0_PRIVILEGED_NONSECURE_DATA (IMG_UINT64_C(0x0000000000000003))
  4743. #define VHA_CR_ACE_PROT_CTRL_OSID0_UNPRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0000000000000004))
  4744. #define VHA_CR_ACE_PROT_CTRL_OSID0_PRIVILEGED_SECURE_INSTRUCTION (IMG_UINT64_C(0x0000000000000005))
  4745. #define VHA_CR_ACE_PROT_CTRL_OSID0_UNPRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0000000000000006))
  4746. #define VHA_CR_ACE_PROT_CTRL_OSID0_PRIVILEGED_NONSECURE_INSTRUCTION (IMG_UINT64_C(0x0000000000000007))
  4747. /*
  4748. Register VHA_CR_REQ_CTXT_OVERRIDE
  4749. */
  4750. #define VHA_CR_REQ_CTXT_OVERRIDE (0x40010U)
  4751. #define VHA_CR_REQ_CTXT_OVERRIDE_MASKFULL (IMG_UINT64_C(0x0000000000000007))
  4752. #define VHA_CR_REQ_CTXT_OVERRIDE_OVERRIDE_OS2_SHIFT (2U)
  4753. #define VHA_CR_REQ_CTXT_OVERRIDE_OVERRIDE_OS2_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFB))
  4754. #define VHA_CR_REQ_CTXT_OVERRIDE_OVERRIDE_OS2_EN (IMG_UINT64_C(0X0000000000000004))
  4755. #define VHA_CR_REQ_CTXT_OVERRIDE_OVERRIDE_OS1_SHIFT (1U)
  4756. #define VHA_CR_REQ_CTXT_OVERRIDE_OVERRIDE_OS1_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFD))
  4757. #define VHA_CR_REQ_CTXT_OVERRIDE_OVERRIDE_OS1_EN (IMG_UINT64_C(0X0000000000000002))
  4758. #define VHA_CR_REQ_CTXT_OVERRIDE_OVERRIDE_OS0_SHIFT (0U)
  4759. #define VHA_CR_REQ_CTXT_OVERRIDE_OVERRIDE_OS0_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  4760. #define VHA_CR_REQ_CTXT_OVERRIDE_OVERRIDE_OS0_EN (IMG_UINT64_C(0X0000000000000001))
  4761. /*
  4762. Register VHA_CR_CNN_CMD_PRIORITY_LIMITS
  4763. */
  4764. #define VHA_CR_CNN_CMD_PRIORITY_LIMITS (0x40018U)
  4765. #define VHA_CR_CNN_CMD_PRIORITY_LIMITS_MASKFULL (IMG_UINT64_C(0x000000000000019B))
  4766. #define VHA_CR_CNN_CMD_PRIORITY_LIMITS_OS2_LIMIT_SHIFT (7U)
  4767. #define VHA_CR_CNN_CMD_PRIORITY_LIMITS_OS2_LIMIT_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFE7F))
  4768. #define VHA_CR_CNN_CMD_PRIORITY_LIMITS_OS1_LIMIT_SHIFT (3U)
  4769. #define VHA_CR_CNN_CMD_PRIORITY_LIMITS_OS1_LIMIT_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFE7))
  4770. #define VHA_CR_CNN_CMD_PRIORITY_LIMITS_OS0_LIMIT_SHIFT (0U)
  4771. #define VHA_CR_CNN_CMD_PRIORITY_LIMITS_OS0_LIMIT_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFC))
  4772. /*
  4773. Register VHA_CR_OS0_MMU_CTRL
  4774. */
  4775. #define VHA_CR_OS0_MMU_CTRL (0x40020U)
  4776. #define VHA_CR_OS0_MMU_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  4777. #define VHA_CR_OS0_MMU_CTRL_BYPASS_SHIFT (0U)
  4778. #define VHA_CR_OS0_MMU_CTRL_BYPASS_CLRMSK (0XFFFFFFFEU)
  4779. #define VHA_CR_OS0_MMU_CTRL_BYPASS_EN (0X00000001U)
  4780. /*
  4781. Register VHA_CR_OS1_MMU_CTRL
  4782. */
  4783. #define VHA_CR_OS1_MMU_CTRL (0x40028U)
  4784. #define VHA_CR_OS1_MMU_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  4785. #define VHA_CR_OS1_MMU_CTRL_BYPASS_SHIFT (0U)
  4786. #define VHA_CR_OS1_MMU_CTRL_BYPASS_CLRMSK (0XFFFFFFFEU)
  4787. #define VHA_CR_OS1_MMU_CTRL_BYPASS_EN (0X00000001U)
  4788. /*
  4789. Register VHA_CR_OS2_MMU_CTRL
  4790. */
  4791. #define VHA_CR_OS2_MMU_CTRL (0x40030U)
  4792. #define VHA_CR_OS2_MMU_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  4793. #define VHA_CR_OS2_MMU_CTRL_BYPASS_SHIFT (0U)
  4794. #define VHA_CR_OS2_MMU_CTRL_BYPASS_CLRMSK (0XFFFFFFFEU)
  4795. #define VHA_CR_OS2_MMU_CTRL_BYPASS_EN (0X00000001U)
  4796. /*
  4797. Register VHA_CR_SOCIF_BUS_SECURE
  4798. */
  4799. #define VHA_CR_SOCIF_BUS_SECURE (0x4A100U)
  4800. #define VHA_CR_SOCIF_BUS_SECURE_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  4801. #define VHA_CR_SOCIF_BUS_SECURE_ENABLE_SHIFT (0U)
  4802. #define VHA_CR_SOCIF_BUS_SECURE_ENABLE_CLRMSK (0XFFFFFFFEU)
  4803. #define VHA_CR_SOCIF_BUS_SECURE_ENABLE_EN (0X00000001U)
  4804. #endif /* _VHA_CR_AURA_H_ */
  4805. /*****************************************************************************
  4806. End of file (vha_cr_aura.h)
  4807. *****************************************************************************/