nn_sys_cr_gyrus.h 15 KB

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  1. /*************************************************************************/ /*!
  2. @Title Hardware definition file nn_sys_cr_gyrus.h
  3. @Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved
  4. */ /**************************************************************************/
  5. /* **** Autogenerated C -- do not edit **** */
  6. /*
  7. */
  8. #ifndef _NN_SYS_CR_GYRUS_H_
  9. #define _NN_SYS_CR_GYRUS_H_
  10. #define NN_SYS_CR_GYRUS_REVISION 1
  11. /*
  12. Register NN_SYS_CR_PRODUCT_ID
  13. */
  14. #define NN_SYS_CR_PRODUCT_ID (0x0018U)
  15. #define NN_SYS_CR_PRODUCT_ID_MASKFULL (IMG_UINT64_C(0x00000000FFFF0000))
  16. #define NN_SYS_CR_PRODUCT_ID_IMG_PRODUCT_ID_SHIFT (16U)
  17. #define NN_SYS_CR_PRODUCT_ID_IMG_PRODUCT_ID_CLRMSK (IMG_UINT64_C(0XFFFFFFFF0000FFFF))
  18. /*
  19. Register NN_SYS_CR_CORE_ID
  20. */
  21. #define NN_SYS_CR_CORE_ID (0x0020U)
  22. #define NN_SYS_CR_CORE_ID_MASKFULL (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
  23. #define NN_SYS_CR_CORE_ID_BRANCH_ID_SHIFT (48U)
  24. #define NN_SYS_CR_CORE_ID_BRANCH_ID_CLRMSK (IMG_UINT64_C(0X0000FFFFFFFFFFFF))
  25. #define NN_SYS_CR_CORE_ID_VERSION_ID_SHIFT (32U)
  26. #define NN_SYS_CR_CORE_ID_VERSION_ID_CLRMSK (IMG_UINT64_C(0XFFFF0000FFFFFFFF))
  27. #define NN_SYS_CR_CORE_ID_NUMBER_OF_SCALABLE_UNITS_SHIFT (16U)
  28. #define NN_SYS_CR_CORE_ID_NUMBER_OF_SCALABLE_UNITS_CLRMSK (IMG_UINT64_C(0XFFFFFFFF0000FFFF))
  29. #define NN_SYS_CR_CORE_ID_CONFIG_ID_SHIFT (0U)
  30. #define NN_SYS_CR_CORE_ID_CONFIG_ID_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFF0000))
  31. /*
  32. Register NN_SYS_CR_CORE_IP_INTEGRATOR_ID
  33. */
  34. #define NN_SYS_CR_CORE_IP_INTEGRATOR_ID (0x0028U)
  35. #define NN_SYS_CR_CORE_IP_INTEGRATOR_ID_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  36. #define NN_SYS_CR_CORE_IP_INTEGRATOR_ID_VALUE_SHIFT (0U)
  37. #define NN_SYS_CR_CORE_IP_INTEGRATOR_ID_VALUE_CLRMSK (IMG_UINT64_C(0XFFFFFFFF00000000))
  38. /*
  39. Register NN_SYS_CR_CORE_IP_CHANGELIST
  40. */
  41. #define NN_SYS_CR_CORE_IP_CHANGELIST (0x0030U)
  42. #define NN_SYS_CR_CORE_IP_CHANGELIST_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  43. #define NN_SYS_CR_CORE_IP_CHANGELIST_VALUE_SHIFT (0U)
  44. #define NN_SYS_CR_CORE_IP_CHANGELIST_VALUE_CLRMSK (IMG_UINT64_C(0XFFFFFFFF00000000))
  45. #define NN_SYS_CR_CLK_CTRL_MODE_MASK (0x00000003U)
  46. /*
  47. The domain clock is forced off */
  48. #define NN_SYS_CR_CLK_CTRL_MODE_OFF (0x00000000U)
  49. /*
  50. The domain clock is forced on */
  51. #define NN_SYS_CR_CLK_CTRL_MODE_ON (0x00000001U)
  52. /*
  53. Automatic clock gating is active, the domain clock is only on whilst data is being processed */
  54. #define NN_SYS_CR_CLK_CTRL_MODE_AUTO (0x00000002U)
  55. /*
  56. Register NN_SYS_CR_CLK_CTRL
  57. */
  58. #define NN_SYS_CR_CLK_CTRL (0x0200U)
  59. #define NN_SYS_CR_CLK_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000000003))
  60. #define NN_SYS_CR_CLK_CTRL_NN_SYS_SHIFT (0U)
  61. #define NN_SYS_CR_CLK_CTRL_NN_SYS_CLRMSK (0XFFFFFFFCU)
  62. #define NN_SYS_CR_CLK_CTRL_NN_SYS_OFF (00000000U)
  63. #define NN_SYS_CR_CLK_CTRL_NN_SYS_ON (0X00000001U)
  64. #define NN_SYS_CR_CLK_CTRL_NN_SYS_AUTO (0X00000002U)
  65. /*
  66. Clock is gated and the module is inactive */
  67. #define NN_SYS_CR_CLK_STATUS_MODE_GATED (0x00000000U)
  68. /*
  69. Clock is running */
  70. #define NN_SYS_CR_CLK_STATUS_MODE_RUNNING (0x00000001U)
  71. /*
  72. Register NN_SYS_CR_CLK_STATUS
  73. */
  74. #define NN_SYS_CR_CLK_STATUS (0x0208U)
  75. #define NN_SYS_CR_CLK_STATUS_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  76. #define NN_SYS_CR_CLK_STATUS_NN_SYS_SHIFT (0U)
  77. #define NN_SYS_CR_CLK_STATUS_NN_SYS_CLRMSK (0XFFFFFFFEU)
  78. #define NN_SYS_CR_CLK_STATUS_NN_SYS_GATED (00000000U)
  79. #define NN_SYS_CR_CLK_STATUS_NN_SYS_RUNNING (0X00000001U)
  80. /*
  81. Register NN_SYS_CR_EVENT_CLEAR
  82. */
  83. #define NN_SYS_CR_EVENT_CLEAR (0x0210U)
  84. #define NN_SYS_CR_EVENT_CLEAR_MASKFULL (IMG_UINT64_C(0x0000000000000003))
  85. #define NN_SYS_CR_EVENT_CLEAR_NN_SYS_PWR_ABORT_SHIFT (1U)
  86. #define NN_SYS_CR_EVENT_CLEAR_NN_SYS_PWR_ABORT_CLRMSK (0XFFFFFFFDU)
  87. #define NN_SYS_CR_EVENT_CLEAR_NN_SYS_PWR_ABORT_EN (0X00000002U)
  88. #define NN_SYS_CR_EVENT_CLEAR_NN_SYS_PWR_COMPLETE_SHIFT (0U)
  89. #define NN_SYS_CR_EVENT_CLEAR_NN_SYS_PWR_COMPLETE_CLRMSK (0XFFFFFFFEU)
  90. #define NN_SYS_CR_EVENT_CLEAR_NN_SYS_PWR_COMPLETE_EN (0X00000001U)
  91. /*
  92. Register NN_SYS_CR_EVENT_ENABLE
  93. */
  94. #define NN_SYS_CR_EVENT_ENABLE (0x0218U)
  95. #define NN_SYS_CR_EVENT_ENABLE_MASKFULL (IMG_UINT64_C(0x0000000000000003))
  96. #define NN_SYS_CR_EVENT_ENABLE_NN_SYS_PWR_ABORT_SHIFT (1U)
  97. #define NN_SYS_CR_EVENT_ENABLE_NN_SYS_PWR_ABORT_CLRMSK (0XFFFFFFFDU)
  98. #define NN_SYS_CR_EVENT_ENABLE_NN_SYS_PWR_ABORT_EN (0X00000002U)
  99. #define NN_SYS_CR_EVENT_ENABLE_NN_SYS_PWR_COMPLETE_SHIFT (0U)
  100. #define NN_SYS_CR_EVENT_ENABLE_NN_SYS_PWR_COMPLETE_CLRMSK (0XFFFFFFFEU)
  101. #define NN_SYS_CR_EVENT_ENABLE_NN_SYS_PWR_COMPLETE_EN (0X00000001U)
  102. /*
  103. Register NN_SYS_CR_EVENT_STATUS
  104. */
  105. #define NN_SYS_CR_EVENT_STATUS (0x0220U)
  106. #define NN_SYS_CR_EVENT_STATUS_MASKFULL (IMG_UINT64_C(0x0000000000000003))
  107. #define NN_SYS_CR_EVENT_STATUS_NN_SYS_PWR_ABORT_SHIFT (1U)
  108. #define NN_SYS_CR_EVENT_STATUS_NN_SYS_PWR_ABORT_CLRMSK (0XFFFFFFFDU)
  109. #define NN_SYS_CR_EVENT_STATUS_NN_SYS_PWR_ABORT_EN (0X00000002U)
  110. #define NN_SYS_CR_EVENT_STATUS_NN_SYS_PWR_COMPLETE_SHIFT (0U)
  111. #define NN_SYS_CR_EVENT_STATUS_NN_SYS_PWR_COMPLETE_CLRMSK (0XFFFFFFFEU)
  112. #define NN_SYS_CR_EVENT_STATUS_NN_SYS_PWR_COMPLETE_EN (0X00000001U)
  113. /*
  114. Register NN_SYS_CR_IDLE_HYSTERESIS_COUNT
  115. */
  116. #define NN_SYS_CR_IDLE_HYSTERESIS_COUNT (0x0228U)
  117. #define NN_SYS_CR_IDLE_HYSTERESIS_COUNT_MASKFULL (IMG_UINT64_C(0x000000000000001F))
  118. #define NN_SYS_CR_IDLE_HYSTERESIS_COUNT_NN_SYS_SHIFT (0U)
  119. #define NN_SYS_CR_IDLE_HYSTERESIS_COUNT_NN_SYS_CLRMSK (0XFFFFFFE0U)
  120. /*
  121. Power event type is power down */
  122. #define NN_SYS_CR_POWER_EVENT_MODE_POWER_DOWN (0x00000000U)
  123. /*
  124. Power event type is power up */
  125. #define NN_SYS_CR_POWER_EVENT_MODE_POWER_UP (0x00000001U)
  126. /*
  127. Register NN_SYS_CR_POWER_EVENT
  128. */
  129. #define NN_SYS_CR_POWER_EVENT (0x0230U)
  130. #define NN_SYS_CR_POWER_EVENT_MASKFULL (IMG_UINT64_C(0x0000000000000033))
  131. #define NN_SYS_CR_POWER_EVENT_DOMAIN_NNA_SHIFT (5U)
  132. #define NN_SYS_CR_POWER_EVENT_DOMAIN_NNA_CLRMSK (0XFFFFFFDFU)
  133. #define NN_SYS_CR_POWER_EVENT_DOMAIN_NNA_EN (0X00000020U)
  134. #define NN_SYS_CR_POWER_EVENT_DOMAIN_NNSYS_SHIFT (4U)
  135. #define NN_SYS_CR_POWER_EVENT_DOMAIN_NNSYS_CLRMSK (0XFFFFFFEFU)
  136. #define NN_SYS_CR_POWER_EVENT_DOMAIN_NNSYS_EN (0X00000010U)
  137. #define NN_SYS_CR_POWER_EVENT_REQUEST_SHIFT (1U)
  138. #define NN_SYS_CR_POWER_EVENT_REQUEST_CLRMSK (0XFFFFFFFDU)
  139. #define NN_SYS_CR_POWER_EVENT_REQUEST_POWER_DOWN (00000000U)
  140. #define NN_SYS_CR_POWER_EVENT_REQUEST_POWER_UP (0X00000002U)
  141. #define NN_SYS_CR_POWER_EVENT_TYPE_SHIFT (0U)
  142. #define NN_SYS_CR_POWER_EVENT_TYPE_CLRMSK (0XFFFFFFFEU)
  143. #define NN_SYS_CR_POWER_EVENT_TYPE_EN (0X00000001U)
  144. /*
  145. Register NN_SYS_CR_RESET_CLK_CTRL
  146. */
  147. #define NN_SYS_CR_RESET_CLK_CTRL (0x0238U)
  148. #define NN_SYS_CR_RESET_CLK_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000000003))
  149. #define NN_SYS_CR_RESET_CLK_CTRL_NN_SYS_SHIFT (0U)
  150. #define NN_SYS_CR_RESET_CLK_CTRL_NN_SYS_CLRMSK (0XFFFFFFFCU)
  151. /*
  152. Register NN_SYS_CR_RESET_CTRL
  153. */
  154. #define NN_SYS_CR_RESET_CTRL (0x0240U)
  155. #define NN_SYS_CR_RESET_CTRL_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  156. #define NN_SYS_CR_RESET_CTRL_NN_SYS_SHIFT (0U)
  157. #define NN_SYS_CR_RESET_CTRL_NN_SYS_CLRMSK (0XFFFFFFFEU)
  158. #define NN_SYS_CR_RESET_CTRL_NN_SYS_EN (0X00000001U)
  159. /*
  160. Register NN_SYS_CR_SOCIF_WAKEUP_ENABLE
  161. */
  162. #define NN_SYS_CR_SOCIF_WAKEUP_ENABLE (0x0248U)
  163. #define NN_SYS_CR_SOCIF_WAKEUP_ENABLE_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  164. #define NN_SYS_CR_SOCIF_WAKEUP_ENABLE_ALWAYS_SHIFT (0U)
  165. #define NN_SYS_CR_SOCIF_WAKEUP_ENABLE_ALWAYS_CLRMSK (0XFFFFFFFEU)
  166. #define NN_SYS_CR_SOCIF_WAKEUP_ENABLE_ALWAYS_EN (0X00000001U)
  167. /*
  168. Register NN_SYS_CR_AXI_EXACCESS
  169. */
  170. #define NN_SYS_CR_AXI_EXACCESS (0x0250U)
  171. #define NN_SYS_CR_AXI_EXACCESS_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  172. #define NN_SYS_CR_AXI_EXACCESS_SOCIF_ENABLE_SHIFT (0U)
  173. #define NN_SYS_CR_AXI_EXACCESS_SOCIF_ENABLE_CLRMSK (0XFFFFFFFEU)
  174. #define NN_SYS_CR_AXI_EXACCESS_SOCIF_ENABLE_EN (0X00000001U)
  175. /*
  176. Register NN_SYS_CR_REGBANK_REQUEST_INVALID
  177. */
  178. #define NN_SYS_CR_REGBANK_REQUEST_INVALID (0x0258U)
  179. #define NN_SYS_CR_REGBANK_REQUEST_INVALID_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  180. #define NN_SYS_CR_REGBANK_REQUEST_INVALID_FLAG_SHIFT (0U)
  181. #define NN_SYS_CR_REGBANK_REQUEST_INVALID_FLAG_CLRMSK (0XFFFFFFFEU)
  182. #define NN_SYS_CR_REGBANK_REQUEST_INVALID_FLAG_EN (0X00000001U)
  183. /*
  184. Register NN_SYS_CR_NOC_LOWER_ADDR1
  185. */
  186. #define NN_SYS_CR_NOC_LOWER_ADDR1 (0x0268U)
  187. #define NN_SYS_CR_NOC_LOWER_ADDR1_MASKFULL (IMG_UINT64_C(0x0000000FFFFFFFFF))
  188. #define NN_SYS_CR_NOC_LOWER_ADDR1_LOWER_ADDR_SHIFT (0U)
  189. #define NN_SYS_CR_NOC_LOWER_ADDR1_LOWER_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFFF000000000))
  190. /*
  191. Register NN_SYS_CR_NOC_UPPER_ADDR1
  192. */
  193. #define NN_SYS_CR_NOC_UPPER_ADDR1 (0x0278U)
  194. #define NN_SYS_CR_NOC_UPPER_ADDR1_MASKFULL (IMG_UINT64_C(0x0000000FFFFFFFFF))
  195. #define NN_SYS_CR_NOC_UPPER_ADDR1_UPPER_ADDR_SHIFT (0U)
  196. #define NN_SYS_CR_NOC_UPPER_ADDR1_UPPER_ADDR_CLRMSK (IMG_UINT64_C(0XFFFFFFF000000000))
  197. /*
  198. Register NN_SYS_CR_SYS_BUS_DIRECT_ACCESS
  199. */
  200. #define NN_SYS_CR_SYS_BUS_DIRECT_ACCESS (0x0280U)
  201. #define NN_SYS_CR_SYS_BUS_DIRECT_ACCESS_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  202. #define NN_SYS_CR_SYS_BUS_DIRECT_ACCESS_SYS_BUS_DIRECT_ACCESS_SHIFT (0U)
  203. #define NN_SYS_CR_SYS_BUS_DIRECT_ACCESS_SYS_BUS_DIRECT_ACCESS_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  204. #define NN_SYS_CR_SYS_BUS_DIRECT_ACCESS_SYS_BUS_DIRECT_ACCESS_EN (IMG_UINT64_C(0X0000000000000001))
  205. /*
  206. Register NN_SYS_CR_NNPU_ACE_QOS_CTRL
  207. */
  208. #define NN_SYS_CR_NNPU_ACE_QOS_CTRL (0x02A0U)
  209. #define NN_SYS_CR_NNPU_ACE_QOS_CTRL_MASKFULL (IMG_UINT64_C(0x000000000000FFFF))
  210. #define NN_SYS_CR_NNPU_ACE_QOS_CTRL_CRITICAL_SHIFT (12U)
  211. #define NN_SYS_CR_NNPU_ACE_QOS_CTRL_CRITICAL_CLRMSK (0XFFFF0FFFU)
  212. #define NN_SYS_CR_NNPU_ACE_QOS_CTRL_HIGH_SHIFT (8U)
  213. #define NN_SYS_CR_NNPU_ACE_QOS_CTRL_HIGH_CLRMSK (0XFFFFF0FFU)
  214. #define NN_SYS_CR_NNPU_ACE_QOS_CTRL_MEDIUM_SHIFT (4U)
  215. #define NN_SYS_CR_NNPU_ACE_QOS_CTRL_MEDIUM_CLRMSK (0XFFFFFF0FU)
  216. #define NN_SYS_CR_NNPU_ACE_QOS_CTRL_LOW_SHIFT (0U)
  217. #define NN_SYS_CR_NNPU_ACE_QOS_CTRL_LOW_CLRMSK (0XFFFFFFF0U)
  218. #define NN_SYS_CR_NNPU_ACE_QOS_SEL_ENUM_PRIORITIES_MASK (0x00000003U)
  219. /*
  220. Low */
  221. #define NN_SYS_CR_NNPU_ACE_QOS_SEL_ENUM_PRIORITIES_LOW (0x00000000U)
  222. /*
  223. Medium */
  224. #define NN_SYS_CR_NNPU_ACE_QOS_SEL_ENUM_PRIORITIES_MEDIUM (0x00000001U)
  225. /*
  226. High */
  227. #define NN_SYS_CR_NNPU_ACE_QOS_SEL_ENUM_PRIORITIES_HIGH (0x00000002U)
  228. /*
  229. Critical */
  230. #define NN_SYS_CR_NNPU_ACE_QOS_SEL_ENUM_PRIORITIES_CRITICAL (0x00000003U)
  231. /*
  232. Register NN_SYS_CR_NNPU_ACE_QOS_SEL
  233. */
  234. #define NN_SYS_CR_NNPU_ACE_QOS_SEL (0x02A8U)
  235. #define NN_SYS_CR_NNPU_ACE_QOS_SEL_MASKFULL (IMG_UINT64_C(0x00000000000000F1))
  236. #define NN_SYS_CR_NNPU_ACE_QOS_SEL_MMU_SHIFT (6U)
  237. #define NN_SYS_CR_NNPU_ACE_QOS_SEL_MMU_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFF3F))
  238. #define NN_SYS_CR_NNPU_ACE_QOS_SEL_MMU_LOW (IMG_UINT64_C(0000000000000000))
  239. #define NN_SYS_CR_NNPU_ACE_QOS_SEL_MMU_MEDIUM (IMG_UINT64_C(0x0000000000000040))
  240. #define NN_SYS_CR_NNPU_ACE_QOS_SEL_MMU_HIGH (IMG_UINT64_C(0x0000000000000080))
  241. #define NN_SYS_CR_NNPU_ACE_QOS_SEL_MMU_CRITICAL (IMG_UINT64_C(0x00000000000000c0))
  242. #define NN_SYS_CR_NNPU_ACE_QOS_SEL_NON_MMU_SHIFT (4U)
  243. #define NN_SYS_CR_NNPU_ACE_QOS_SEL_NON_MMU_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFCF))
  244. #define NN_SYS_CR_NNPU_ACE_QOS_SEL_NON_MMU_LOW (IMG_UINT64_C(0000000000000000))
  245. #define NN_SYS_CR_NNPU_ACE_QOS_SEL_NON_MMU_MEDIUM (IMG_UINT64_C(0x0000000000000010))
  246. #define NN_SYS_CR_NNPU_ACE_QOS_SEL_NON_MMU_HIGH (IMG_UINT64_C(0x0000000000000020))
  247. #define NN_SYS_CR_NNPU_ACE_QOS_SEL_NON_MMU_CRITICAL (IMG_UINT64_C(0x0000000000000030))
  248. #define NN_SYS_CR_NNPU_ACE_QOS_SEL_NNPU_QOS_ENABLE_SHIFT (0U)
  249. #define NN_SYS_CR_NNPU_ACE_QOS_SEL_NNPU_QOS_ENABLE_CLRMSK (IMG_UINT64_C(0XFFFFFFFFFFFFFFFE))
  250. #define NN_SYS_CR_NNPU_ACE_QOS_SEL_NNPU_QOS_ENABLE_EN (IMG_UINT64_C(0X0000000000000001))
  251. /*
  252. Register NN_SYS_CR_RTM_CTRL
  253. */
  254. #define NN_SYS_CR_RTM_CTRL (0x1000U)
  255. #define NN_SYS_CR_RTM_CTRL_MASKFULL (IMG_UINT64_C(0x00000000C0000FF8))
  256. #define NN_SYS_CR_RTM_CTRL_RTM_ENABLE_SHIFT (31U)
  257. #define NN_SYS_CR_RTM_CTRL_RTM_ENABLE_CLRMSK (0X7FFFFFFFU)
  258. #define NN_SYS_CR_RTM_CTRL_RTM_ENABLE_EN (0X80000000U)
  259. #define NN_SYS_CR_RTM_CTRL_RTM_CHECK_SHIFT (30U)
  260. #define NN_SYS_CR_RTM_CTRL_RTM_CHECK_CLRMSK (0XBFFFFFFFU)
  261. #define NN_SYS_CR_RTM_CTRL_RTM_CHECK_EN (0X40000000U)
  262. #define NN_SYS_CR_RTM_CTRL_RTM_SELECTOR_SHIFT (3U)
  263. #define NN_SYS_CR_RTM_CTRL_RTM_SELECTOR_CLRMSK (0XFFFFF007U)
  264. /*
  265. Register NN_SYS_CR_RTM_DATA
  266. */
  267. #define NN_SYS_CR_RTM_DATA (0x1008U)
  268. #define NN_SYS_CR_RTM_DATA_MASKFULL (IMG_UINT64_C(0x00000000FFFFFFFF))
  269. #define NN_SYS_CR_RTM_DATA_RTM_DATA_SHIFT (0U)
  270. #define NN_SYS_CR_RTM_DATA_RTM_DATA_CLRMSK (00000000U)
  271. /*
  272. Register NN_SYS_CR_SOCIF_BUS_UNTRUSTED
  273. */
  274. #define NN_SYS_CR_SOCIF_BUS_UNTRUSTED (0x1A000U)
  275. #define NN_SYS_CR_SOCIF_BUS_UNTRUSTED_MASKFULL (IMG_UINT64_C(0xFFFFFFFFFFFFFFFF))
  276. #define NN_SYS_CR_SOCIF_BUS_UNTRUSTED_VALUE_SHIFT (0U)
  277. #define NN_SYS_CR_SOCIF_BUS_UNTRUSTED_VALUE_CLRMSK (IMG_UINT64_C(0000000000000000))
  278. /*
  279. Register NN_SYS_CR_SOCIF_BUS_SECURE
  280. */
  281. #define NN_SYS_CR_SOCIF_BUS_SECURE (0x1A100U)
  282. #define NN_SYS_CR_SOCIF_BUS_SECURE_MASKFULL (IMG_UINT64_C(0x0000000000000001))
  283. #define NN_SYS_CR_SOCIF_BUS_SECURE_ENABLE_SHIFT (0U)
  284. #define NN_SYS_CR_SOCIF_BUS_SECURE_ENABLE_CLRMSK (0XFFFFFFFEU)
  285. #define NN_SYS_CR_SOCIF_BUS_SECURE_ENABLE_EN (0X00000001U)
  286. #endif /* _NN_SYS_CR_GYRUS_H_ */
  287. /*****************************************************************************
  288. End of file (nn_sys_cr_gyrus.h)
  289. *****************************************************************************/