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- From a1ce531ab24b1ef5e69dbf29ecbfc6898b454ec1 Mon Sep 17 00:00:00 2001
- From: Rick Chen <rick@andestech.com>
- Date: Tue, 2 Apr 2019 15:56:43 +0800
- Subject: [PATCH 16/18] riscv: dts: ae350 support SMP
- Signed-off-by: Rick Chen <rick@andestech.com>
- Cc: Greentime Hu <greentime@andestech.com>
- Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
- Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
- ---
- arch/riscv/dts/ae350_32.dts | 81 +++++++++++++++++++++++++++----------
- arch/riscv/dts/ae350_64.dts | 81 +++++++++++++++++++++++++++----------
- 2 files changed, 118 insertions(+), 44 deletions(-)
- diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts
- index 0679827313..2ec01a5ce7 100644
- --- a/arch/riscv/dts/ae350_32.dts
- +++ b/arch/riscv/dts/ae350_32.dts
- @@ -26,16 +26,49 @@
- status = "okay";
- compatible = "riscv";
- riscv,isa = "rv32imafdc";
- + riscv,priv-major = <1>;
- + riscv,priv-minor = <10>;
- mmu-type = "riscv,sv32";
- clock-frequency = <60000000>;
- + i-cache-size = <0x8000>;
- + i-cache-line-size = <32>;
- d-cache-size = <0x8000>;
- d-cache-line-size = <32>;
- + next-level-cache = <&L2>;
- CPU0_intc: interrupt-controller {
- #interrupt-cells = <1>;
- interrupt-controller;
- compatible = "riscv,cpu-intc";
- };
- };
- + CPU1: cpu@1 {
- + device_type = "cpu";
- + reg = <1>;
- + status = "okay";
- + compatible = "riscv";
- + riscv,isa = "rv32imafdc";
- + riscv,priv-major = <1>;
- + riscv,priv-minor = <10>;
- + mmu-type = "riscv,sv32";
- + clock-frequency = <60000000>;
- + i-cache-size = <0x8000>;
- + i-cache-line-size = <32>;
- + d-cache-size = <0x8000>;
- + d-cache-line-size = <32>;
- + next-level-cache = <&L2>;
- + CPU1_intc: interrupt-controller {
- + #interrupt-cells = <1>;
- + interrupt-controller;
- + compatible = "riscv,cpu-intc";
- + };
- + };
- +
- + L2: l2-cache@e0500000 {
- + compatible = "cache";
- + cache-level = <2>;
- + cache-size = <0x40000>;
- + reg = <0x0 0xe0500000 0x0 0x40000>;
- + };
- };
-
- memory@0 {
- @@ -46,32 +79,32 @@
- soc {
- #address-cells = <1>;
- #size-cells = <1>;
- - compatible = "andestech,riscv-ae350-soc";
- + compatible = "simple-bus";
- ranges;
-
- - plic0: interrupt-controller@e4000000 {
- - compatible = "riscv,plic0";
- - #address-cells = <1>;
- - #interrupt-cells = <1>;
- - interrupt-controller;
- - reg = <0xe4000000 0x2000000>;
- - riscv,ndev=<71>;
- - interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9>;
- - };
- + plic0: interrupt-controller@e4000000 {
- + compatible = "riscv,plic0";
- + #address-cells = <1>;
- + #interrupt-cells = <1>;
- + interrupt-controller;
- + reg = <0xe4000000 0x2000000>;
- + riscv,ndev=<71>;
- + interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9 &CPU1_intc 11 &CPU1_intc 9>;
- + };
-
- - plic1: interrupt-controller@e6400000 {
- - compatible = "riscv,plic1";
- - #address-cells = <1>;
- - #interrupt-cells = <1>;
- - interrupt-controller;
- - reg = <0xe6400000 0x400000>;
- - riscv,ndev=<1>;
- - interrupts-extended = <&CPU0_intc 3>;
- - };
- + plic1: interrupt-controller@e6400000 {
- + compatible = "riscv,plic1";
- + #address-cells = <1>;
- + #interrupt-cells = <1>;
- + interrupt-controller;
- + reg = <0xe6400000 0x400000>;
- + riscv,ndev=<2>;
- + interrupts-extended = <&CPU0_intc 3 &CPU1_intc 3>;
- + };
-
- - plmt0@e6000000 {
- - compatible = "riscv,plmt0";
- - interrupts-extended = <&CPU0_intc 7>;
- + plmt0@e6000000 {
- + compatible = "riscv,plmt0";
- + interrupts-extended = <&CPU0_intc 7 &CPU1_intc 7>;
- reg = <0xe6000000 0x100000>;
- };
- };
- @@ -146,6 +179,10 @@
- interrupt-parent = <&plic0>;
- };
-
- + pmu {
- + compatible = "riscv,base-pmu";
- + };
- +
- virtio_mmio@fe007000 {
- interrupts = <0x17 0x4>;
- interrupt-parent = <0x2>;
- diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts
- index e48c298645..cde5cdeff8 100644
- --- a/arch/riscv/dts/ae350_64.dts
- +++ b/arch/riscv/dts/ae350_64.dts
- @@ -26,16 +26,49 @@
- status = "okay";
- compatible = "riscv";
- riscv,isa = "rv64imafdc";
- + riscv,priv-major = <1>;
- + riscv,priv-minor = <10>;
- mmu-type = "riscv,sv39";
- clock-frequency = <60000000>;
- + i-cache-size = <0x8000>;
- + i-cache-line-size = <32>;
- d-cache-size = <0x8000>;
- d-cache-line-size = <32>;
- + next-level-cache = <&L2>;
- CPU0_intc: interrupt-controller {
- #interrupt-cells = <1>;
- interrupt-controller;
- compatible = "riscv,cpu-intc";
- };
- };
- + CPU1: cpu@1 {
- + device_type = "cpu";
- + reg = <1>;
- + status = "okay";
- + compatible = "riscv";
- + riscv,isa = "rv64imafdc";
- + riscv,priv-major = <1>;
- + riscv,priv-minor = <10>;
- + mmu-type = "riscv,sv39";
- + clock-frequency = <60000000>;
- + i-cache-size = <0x8000>;
- + i-cache-line-size = <32>;
- + d-cache-size = <0x8000>;
- + d-cache-line-size = <32>;
- + next-level-cache = <&L2>;
- + CPU1_intc: interrupt-controller {
- + #interrupt-cells = <1>;
- + interrupt-controller;
- + compatible = "riscv,cpu-intc";
- + };
- + };
- +
- + L2: l2-cache@e0500000 {
- + compatible = "cache";
- + cache-level = <2>;
- + cache-size = <0x40000>;
- + reg = <0x0 0xe0500000 0x0 0x40000>;
- + };
- };
-
- memory@0 {
- @@ -46,32 +79,32 @@
- soc {
- #address-cells = <2>;
- #size-cells = <2>;
- - compatible = "andestech,riscv-ae350-soc";
- + compatible = "simple-bus";
- ranges;
-
- - plic0: interrupt-controller@e4000000 {
- - compatible = "riscv,plic0";
- - #address-cells = <2>;
- - #interrupt-cells = <2>;
- - interrupt-controller;
- - reg = <0x0 0xe4000000 0x0 0x2000000>;
- - riscv,ndev=<71>;
- - interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9>;
- - };
- + plic0: interrupt-controller@e4000000 {
- + compatible = "riscv,plic0";
- + #address-cells = <2>;
- + #interrupt-cells = <2>;
- + interrupt-controller;
- + reg = <0x0 0xe4000000 0x0 0x2000000>;
- + riscv,ndev=<71>;
- + interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9 &CPU1_intc 11 &CPU1_intc 9>;
- + };
-
- - plic1: interrupt-controller@e6400000 {
- - compatible = "riscv,plic1";
- - #address-cells = <2>;
- - #interrupt-cells = <2>;
- - interrupt-controller;
- - reg = <0x0 0xe6400000 0x0 0x400000>;
- - riscv,ndev=<1>;
- - interrupts-extended = <&CPU0_intc 3>;
- - };
- + plic1: interrupt-controller@e6400000 {
- + compatible = "riscv,plic1";
- + #address-cells = <2>;
- + #interrupt-cells = <2>;
- + interrupt-controller;
- + reg = <0x0 0xe6400000 0x0 0x400000>;
- + riscv,ndev=<2>;
- + interrupts-extended = <&CPU0_intc 3 &CPU1_intc 3>;
- + };
-
- - plmt0@e6000000 {
- - compatible = "riscv,plmt0";
- - interrupts-extended = <&CPU0_intc 7>;
- + plmt0@e6000000 {
- + compatible = "riscv,plmt0";
- + interrupts-extended = <&CPU0_intc 7 &CPU1_intc 7>;
- reg = <0x0 0xe6000000 0x0 0x100000>;
- };
- };
- @@ -146,6 +179,10 @@
- interrupt-parent = <&plic0>;
- };
-
- + pmu {
- + compatible = "riscv,base-pmu";
- + };
- +
- virtio_mmio@fe007000 {
- interrupts = <0x17 0x4>;
- interrupt-parent = <0x2>;
- --
- 2.21.0
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