0016-riscv-dts-ae350-support-SMP.patch 6.6 KB

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  1. From a1ce531ab24b1ef5e69dbf29ecbfc6898b454ec1 Mon Sep 17 00:00:00 2001
  2. From: Rick Chen <rick@andestech.com>
  3. Date: Tue, 2 Apr 2019 15:56:43 +0800
  4. Subject: [PATCH 16/18] riscv: dts: ae350 support SMP
  5. Signed-off-by: Rick Chen <rick@andestech.com>
  6. Cc: Greentime Hu <greentime@andestech.com>
  7. Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
  8. Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
  9. ---
  10. arch/riscv/dts/ae350_32.dts | 81 +++++++++++++++++++++++++++----------
  11. arch/riscv/dts/ae350_64.dts | 81 +++++++++++++++++++++++++++----------
  12. 2 files changed, 118 insertions(+), 44 deletions(-)
  13. diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts
  14. index 0679827313..2ec01a5ce7 100644
  15. --- a/arch/riscv/dts/ae350_32.dts
  16. +++ b/arch/riscv/dts/ae350_32.dts
  17. @@ -26,16 +26,49 @@
  18. status = "okay";
  19. compatible = "riscv";
  20. riscv,isa = "rv32imafdc";
  21. + riscv,priv-major = <1>;
  22. + riscv,priv-minor = <10>;
  23. mmu-type = "riscv,sv32";
  24. clock-frequency = <60000000>;
  25. + i-cache-size = <0x8000>;
  26. + i-cache-line-size = <32>;
  27. d-cache-size = <0x8000>;
  28. d-cache-line-size = <32>;
  29. + next-level-cache = <&L2>;
  30. CPU0_intc: interrupt-controller {
  31. #interrupt-cells = <1>;
  32. interrupt-controller;
  33. compatible = "riscv,cpu-intc";
  34. };
  35. };
  36. + CPU1: cpu@1 {
  37. + device_type = "cpu";
  38. + reg = <1>;
  39. + status = "okay";
  40. + compatible = "riscv";
  41. + riscv,isa = "rv32imafdc";
  42. + riscv,priv-major = <1>;
  43. + riscv,priv-minor = <10>;
  44. + mmu-type = "riscv,sv32";
  45. + clock-frequency = <60000000>;
  46. + i-cache-size = <0x8000>;
  47. + i-cache-line-size = <32>;
  48. + d-cache-size = <0x8000>;
  49. + d-cache-line-size = <32>;
  50. + next-level-cache = <&L2>;
  51. + CPU1_intc: interrupt-controller {
  52. + #interrupt-cells = <1>;
  53. + interrupt-controller;
  54. + compatible = "riscv,cpu-intc";
  55. + };
  56. + };
  57. +
  58. + L2: l2-cache@e0500000 {
  59. + compatible = "cache";
  60. + cache-level = <2>;
  61. + cache-size = <0x40000>;
  62. + reg = <0x0 0xe0500000 0x0 0x40000>;
  63. + };
  64. };
  65. memory@0 {
  66. @@ -46,32 +79,32 @@
  67. soc {
  68. #address-cells = <1>;
  69. #size-cells = <1>;
  70. - compatible = "andestech,riscv-ae350-soc";
  71. + compatible = "simple-bus";
  72. ranges;
  73. - plic0: interrupt-controller@e4000000 {
  74. - compatible = "riscv,plic0";
  75. - #address-cells = <1>;
  76. - #interrupt-cells = <1>;
  77. - interrupt-controller;
  78. - reg = <0xe4000000 0x2000000>;
  79. - riscv,ndev=<71>;
  80. - interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9>;
  81. - };
  82. + plic0: interrupt-controller@e4000000 {
  83. + compatible = "riscv,plic0";
  84. + #address-cells = <1>;
  85. + #interrupt-cells = <1>;
  86. + interrupt-controller;
  87. + reg = <0xe4000000 0x2000000>;
  88. + riscv,ndev=<71>;
  89. + interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9 &CPU1_intc 11 &CPU1_intc 9>;
  90. + };
  91. - plic1: interrupt-controller@e6400000 {
  92. - compatible = "riscv,plic1";
  93. - #address-cells = <1>;
  94. - #interrupt-cells = <1>;
  95. - interrupt-controller;
  96. - reg = <0xe6400000 0x400000>;
  97. - riscv,ndev=<1>;
  98. - interrupts-extended = <&CPU0_intc 3>;
  99. - };
  100. + plic1: interrupt-controller@e6400000 {
  101. + compatible = "riscv,plic1";
  102. + #address-cells = <1>;
  103. + #interrupt-cells = <1>;
  104. + interrupt-controller;
  105. + reg = <0xe6400000 0x400000>;
  106. + riscv,ndev=<2>;
  107. + interrupts-extended = <&CPU0_intc 3 &CPU1_intc 3>;
  108. + };
  109. - plmt0@e6000000 {
  110. - compatible = "riscv,plmt0";
  111. - interrupts-extended = <&CPU0_intc 7>;
  112. + plmt0@e6000000 {
  113. + compatible = "riscv,plmt0";
  114. + interrupts-extended = <&CPU0_intc 7 &CPU1_intc 7>;
  115. reg = <0xe6000000 0x100000>;
  116. };
  117. };
  118. @@ -146,6 +179,10 @@
  119. interrupt-parent = <&plic0>;
  120. };
  121. + pmu {
  122. + compatible = "riscv,base-pmu";
  123. + };
  124. +
  125. virtio_mmio@fe007000 {
  126. interrupts = <0x17 0x4>;
  127. interrupt-parent = <0x2>;
  128. diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts
  129. index e48c298645..cde5cdeff8 100644
  130. --- a/arch/riscv/dts/ae350_64.dts
  131. +++ b/arch/riscv/dts/ae350_64.dts
  132. @@ -26,16 +26,49 @@
  133. status = "okay";
  134. compatible = "riscv";
  135. riscv,isa = "rv64imafdc";
  136. + riscv,priv-major = <1>;
  137. + riscv,priv-minor = <10>;
  138. mmu-type = "riscv,sv39";
  139. clock-frequency = <60000000>;
  140. + i-cache-size = <0x8000>;
  141. + i-cache-line-size = <32>;
  142. d-cache-size = <0x8000>;
  143. d-cache-line-size = <32>;
  144. + next-level-cache = <&L2>;
  145. CPU0_intc: interrupt-controller {
  146. #interrupt-cells = <1>;
  147. interrupt-controller;
  148. compatible = "riscv,cpu-intc";
  149. };
  150. };
  151. + CPU1: cpu@1 {
  152. + device_type = "cpu";
  153. + reg = <1>;
  154. + status = "okay";
  155. + compatible = "riscv";
  156. + riscv,isa = "rv64imafdc";
  157. + riscv,priv-major = <1>;
  158. + riscv,priv-minor = <10>;
  159. + mmu-type = "riscv,sv39";
  160. + clock-frequency = <60000000>;
  161. + i-cache-size = <0x8000>;
  162. + i-cache-line-size = <32>;
  163. + d-cache-size = <0x8000>;
  164. + d-cache-line-size = <32>;
  165. + next-level-cache = <&L2>;
  166. + CPU1_intc: interrupt-controller {
  167. + #interrupt-cells = <1>;
  168. + interrupt-controller;
  169. + compatible = "riscv,cpu-intc";
  170. + };
  171. + };
  172. +
  173. + L2: l2-cache@e0500000 {
  174. + compatible = "cache";
  175. + cache-level = <2>;
  176. + cache-size = <0x40000>;
  177. + reg = <0x0 0xe0500000 0x0 0x40000>;
  178. + };
  179. };
  180. memory@0 {
  181. @@ -46,32 +79,32 @@
  182. soc {
  183. #address-cells = <2>;
  184. #size-cells = <2>;
  185. - compatible = "andestech,riscv-ae350-soc";
  186. + compatible = "simple-bus";
  187. ranges;
  188. - plic0: interrupt-controller@e4000000 {
  189. - compatible = "riscv,plic0";
  190. - #address-cells = <2>;
  191. - #interrupt-cells = <2>;
  192. - interrupt-controller;
  193. - reg = <0x0 0xe4000000 0x0 0x2000000>;
  194. - riscv,ndev=<71>;
  195. - interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9>;
  196. - };
  197. + plic0: interrupt-controller@e4000000 {
  198. + compatible = "riscv,plic0";
  199. + #address-cells = <2>;
  200. + #interrupt-cells = <2>;
  201. + interrupt-controller;
  202. + reg = <0x0 0xe4000000 0x0 0x2000000>;
  203. + riscv,ndev=<71>;
  204. + interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9 &CPU1_intc 11 &CPU1_intc 9>;
  205. + };
  206. - plic1: interrupt-controller@e6400000 {
  207. - compatible = "riscv,plic1";
  208. - #address-cells = <2>;
  209. - #interrupt-cells = <2>;
  210. - interrupt-controller;
  211. - reg = <0x0 0xe6400000 0x0 0x400000>;
  212. - riscv,ndev=<1>;
  213. - interrupts-extended = <&CPU0_intc 3>;
  214. - };
  215. + plic1: interrupt-controller@e6400000 {
  216. + compatible = "riscv,plic1";
  217. + #address-cells = <2>;
  218. + #interrupt-cells = <2>;
  219. + interrupt-controller;
  220. + reg = <0x0 0xe6400000 0x0 0x400000>;
  221. + riscv,ndev=<2>;
  222. + interrupts-extended = <&CPU0_intc 3 &CPU1_intc 3>;
  223. + };
  224. - plmt0@e6000000 {
  225. - compatible = "riscv,plmt0";
  226. - interrupts-extended = <&CPU0_intc 7>;
  227. + plmt0@e6000000 {
  228. + compatible = "riscv,plmt0";
  229. + interrupts-extended = <&CPU0_intc 7 &CPU1_intc 7>;
  230. reg = <0x0 0xe6000000 0x0 0x100000>;
  231. };
  232. };
  233. @@ -146,6 +179,10 @@
  234. interrupt-parent = <&plic0>;
  235. };
  236. + pmu {
  237. + compatible = "riscv,base-pmu";
  238. + };
  239. +
  240. virtio_mmio@fe007000 {
  241. interrupts = <0x17 0x4>;
  242. interrupt-parent = <0x2>;
  243. --
  244. 2.21.0