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- From dda00ae4ef357233a72c74e6c02d27b70c844422 Mon Sep 17 00:00:00 2001
- From: Rick Chen <rick@andestech.com>
- Date: Tue, 2 Apr 2019 15:56:42 +0800
- Subject: [PATCH 15/18] riscv: ax25: Andes specific cache shall only support in
- M-mode
- Limit the cache configuration only can be supported in M mode.
- It can not be manipulated in S mode.
- Signed-off-by: Rick Chen <rick@andestech.com>
- Cc: Greentime Hu <greentime@andestech.com>
- Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
- Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
- ---
- arch/riscv/cpu/ax25/Kconfig | 1 +
- 1 file changed, 1 insertion(+)
- diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig
- index 68bd4e9419..6b4b92e692 100644
- --- a/arch/riscv/cpu/ax25/Kconfig
- +++ b/arch/riscv/cpu/ax25/Kconfig
- @@ -14,6 +14,7 @@ if RISCV_NDS
-
- config RISCV_NDS_CACHE
- bool "AndeStar V5 families specific cache support"
- + depends on RISCV_MMODE
- help
- Provide Andes Technology AndeStar V5 families specific cache support.
-
- --
- 2.21.0
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