0015-riscv-ax25-Andes-specific-cache-shall-only-support-i.patch 1000 B

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  1. From dda00ae4ef357233a72c74e6c02d27b70c844422 Mon Sep 17 00:00:00 2001
  2. From: Rick Chen <rick@andestech.com>
  3. Date: Tue, 2 Apr 2019 15:56:42 +0800
  4. Subject: [PATCH 15/18] riscv: ax25: Andes specific cache shall only support in
  5. M-mode
  6. Limit the cache configuration only can be supported in M mode.
  7. It can not be manipulated in S mode.
  8. Signed-off-by: Rick Chen <rick@andestech.com>
  9. Cc: Greentime Hu <greentime@andestech.com>
  10. Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
  11. Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
  12. ---
  13. arch/riscv/cpu/ax25/Kconfig | 1 +
  14. 1 file changed, 1 insertion(+)
  15. diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig
  16. index 68bd4e9419..6b4b92e692 100644
  17. --- a/arch/riscv/cpu/ax25/Kconfig
  18. +++ b/arch/riscv/cpu/ax25/Kconfig
  19. @@ -14,6 +14,7 @@ if RISCV_NDS
  20. config RISCV_NDS_CACHE
  21. bool "AndeStar V5 families specific cache support"
  22. + depends on RISCV_MMODE
  23. help
  24. Provide Andes Technology AndeStar V5 families specific cache support.
  25. --
  26. 2.21.0