0008-riscv-do-not-rely-on-hart-ID-passed-by-previous-boot.patch 1.4 KB

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  1. From e04324025275dee6e3e9a968c8d12e98c9b47567 Mon Sep 17 00:00:00 2001
  2. From: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
  3. Date: Sun, 17 Mar 2019 19:28:39 +0100
  4. Subject: [PATCH 08/18] riscv: do not rely on hart ID passed by previous boot
  5. stage
  6. RISC-V U-Boot expects the hart ID to be passed to it via register a0 by
  7. the previous boot stage. Machine mode firmware such as BBL and OpenSBI
  8. do this when starting their payload (U-Boot) in supervisor mode. If
  9. U-Boot is running in machine mode, this task must be handled by the boot
  10. ROM. Explicitly populate register a0 with the hart ID from the mhartid
  11. CSR to avoid possible problems on RISC-V processors with a boot ROM that
  12. does not handle this task.
  13. Suggested-by: Rick Chen <rick@andestech.com>
  14. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
  15. Reviewed-by: Anup Patel <anup.patel@wdc.com>
  16. Reviewed-by: Atish Patra <atish.patra@wdc.com>
  17. Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
  18. Tested-by: Bin Meng <bmeng.cn@gmail.com>
  19. Reviewed-by: Rick Chen <rick@andestech.com>
  20. Tested-by: Rick Chen <rick@andestech.com>
  21. ---
  22. arch/riscv/cpu/start.S | 4 ++++
  23. 1 file changed, 4 insertions(+)
  24. diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
  25. index f55b8cbc37..5ac899b141 100644
  26. --- a/arch/riscv/cpu/start.S
  27. +++ b/arch/riscv/cpu/start.S
  28. @@ -36,6 +36,10 @@
  29. .section .text
  30. .globl _start
  31. _start:
  32. +#ifdef CONFIG_RISCV_MMODE
  33. + csrr a0, mhartid
  34. +#endif
  35. +
  36. /* save hart id and dtb pointer */
  37. mv tp, a0
  38. mv s1, a1
  39. --
  40. 2.21.0