0005-riscv-save-hart-ID-in-register-tp-instead-of-s0.patch 1.3 KB

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  1. From 1446b26f7652124f0e3e98c348cdbc4fc55eb0cb Mon Sep 17 00:00:00 2001
  2. From: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
  3. Date: Sun, 17 Mar 2019 19:28:36 +0100
  4. Subject: [PATCH 05/18] riscv: save hart ID in register tp instead of s0
  5. The hart ID passed by the previous boot stage is currently stored in
  6. register s0. If we divert the control flow inside a function, which is
  7. required as part of multi-hart support, the function epilog may not be
  8. called, clobbering register s0. Save the hart ID in the unallocatable
  9. register tp instead to protect the hart ID.
  10. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
  11. Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
  12. Reviewed-by: Rick Chen <rick@andestech.com>
  13. Reviewed-by: Anup Patel <anup.patel@wdc.com>
  14. ---
  15. arch/riscv/cpu/start.S | 4 ++--
  16. 1 file changed, 2 insertions(+), 2 deletions(-)
  17. diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
  18. index a30f6f7194..bcc0ff696d 100644
  19. --- a/arch/riscv/cpu/start.S
  20. +++ b/arch/riscv/cpu/start.S
  21. @@ -36,7 +36,7 @@
  22. .globl _start
  23. _start:
  24. /* save hart id and dtb pointer */
  25. - mv s0, a0
  26. + mv tp, a0
  27. mv s1, a1
  28. la t0, trap_entry
  29. @@ -64,7 +64,7 @@ call_board_init_f_0:
  30. jal board_init_f_init_reserve
  31. /* save the boot hart id to global_data */
  32. - SREG s0, GD_BOOT_HART(gp)
  33. + SREG tp, GD_BOOT_HART(gp)
  34. /* Enable cache */
  35. jal icache_enable
  36. --
  37. 2.21.0