0003-riscv-implement-IPI-platform-functions-using-SBI.patch 2.3 KB

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  1. From f152febb2a97696f7c7e6df46bf585cfc962a835 Mon Sep 17 00:00:00 2001
  2. From: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
  3. Date: Sun, 17 Mar 2019 19:28:34 +0100
  4. Subject: [PATCH 03/18] riscv: implement IPI platform functions using SBI
  5. The supervisor binary interface (SBI) provides the necessary functions
  6. to implement the platform IPI functions riscv_send_ipi() and
  7. riscv_clear_ipi(). Use it to implement them.
  8. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs
  9. running in supervisor mode. Support for machine mode is already
  10. available for CPUs that include the SiFive CLINT.
  11. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
  12. Reviewed-by: Anup Patel <anup.patel@wdc.com>
  13. Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
  14. Reviewed-by: Atish Patra <atish.patra@wdc.com>
  15. Tested-by: Bin Meng <bmeng.cn@gmail.com>
  16. ---
  17. arch/riscv/Kconfig | 5 +++++
  18. arch/riscv/lib/Makefile | 1 +
  19. arch/riscv/lib/sbi_ipi.c | 25 +++++++++++++++++++++++++
  20. 3 files changed, 31 insertions(+)
  21. create mode 100644 arch/riscv/lib/sbi_ipi.c
  22. diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
  23. index 4d7a115569..9da609b33b 100644
  24. --- a/arch/riscv/Kconfig
  25. +++ b/arch/riscv/Kconfig
  26. @@ -139,4 +139,9 @@ config NR_CPUS
  27. Stack memory is pre-allocated. U-Boot must therefore know the
  28. maximum number of CPUs that may be present.
  29. +config SBI_IPI
  30. + bool
  31. + default y if RISCV_SMODE
  32. + depends on SMP
  33. +
  34. endmenu
  35. diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
  36. index 19370f9749..35dbf643e4 100644
  37. --- a/arch/riscv/lib/Makefile
  38. +++ b/arch/riscv/lib/Makefile
  39. @@ -13,6 +13,7 @@ obj-$(CONFIG_RISCV_RDTIME) += rdtime.o
  40. obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o
  41. obj-y += interrupts.o
  42. obj-y += reset.o
  43. +obj-$(CONFIG_SBI_IPI) += sbi_ipi.o
  44. obj-y += setjmp.o
  45. obj-$(CONFIG_SMP) += smp.o
  46. diff --git a/arch/riscv/lib/sbi_ipi.c b/arch/riscv/lib/sbi_ipi.c
  47. new file mode 100644
  48. index 0000000000..170346da68
  49. --- /dev/null
  50. +++ b/arch/riscv/lib/sbi_ipi.c
  51. @@ -0,0 +1,25 @@
  52. +// SPDX-License-Identifier: GPL-2.0+
  53. +/*
  54. + * Copyright (C) 2019 Fraunhofer AISEC,
  55. + * Lukas Auer <lukas.auer@aisec.fraunhofer.de>
  56. + */
  57. +
  58. +#include <common.h>
  59. +#include <asm/sbi.h>
  60. +
  61. +int riscv_send_ipi(int hart)
  62. +{
  63. + ulong mask;
  64. +
  65. + mask = 1UL << hart;
  66. + sbi_send_ipi(&mask);
  67. +
  68. + return 0;
  69. +}
  70. +
  71. +int riscv_clear_ipi(int hart)
  72. +{
  73. + sbi_clear_ipi();
  74. +
  75. + return 0;
  76. +}
  77. --
  78. 2.21.0