0002-riscv-import-the-supervisor-binary-interface-header-.patch 3.3 KB

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  1. From 34a0626fc344f51cd768efecdd52628b677fb9a8 Mon Sep 17 00:00:00 2001
  2. From: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
  3. Date: Sun, 17 Mar 2019 19:28:33 +0100
  4. Subject: [PATCH 02/18] riscv: import the supervisor binary interface header
  5. file
  6. Import the supervisor binary interface (SBI) header file from Linux
  7. (arch/riscv/include/asm/sbi.h). The last change to it was in commit
  8. 6d60b6ee0c97 ("RISC-V: Device, timer, IRQs, and the SBI").
  9. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
  10. Reviewed-by: Anup Patel <anup.patel@wdc.com>
  11. Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
  12. Reviewed-by: Atish Patra <atish.patra@wdc.com>
  13. ---
  14. arch/riscv/include/asm/sbi.h | 94 ++++++++++++++++++++++++++++++++++++
  15. 1 file changed, 94 insertions(+)
  16. create mode 100644 arch/riscv/include/asm/sbi.h
  17. diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
  18. new file mode 100644
  19. index 0000000000..ced57defdd
  20. --- /dev/null
  21. +++ b/arch/riscv/include/asm/sbi.h
  22. @@ -0,0 +1,94 @@
  23. +/* SPDX-License-Identifier: GPL-2.0 */
  24. +/*
  25. + * Copyright (C) 2015 Regents of the University of California
  26. + *
  27. + * Taken from Linux arch/riscv/include/asm/sbi.h
  28. + */
  29. +
  30. +#ifndef _ASM_RISCV_SBI_H
  31. +#define _ASM_RISCV_SBI_H
  32. +
  33. +#include <linux/types.h>
  34. +
  35. +#define SBI_SET_TIMER 0
  36. +#define SBI_CONSOLE_PUTCHAR 1
  37. +#define SBI_CONSOLE_GETCHAR 2
  38. +#define SBI_CLEAR_IPI 3
  39. +#define SBI_SEND_IPI 4
  40. +#define SBI_REMOTE_FENCE_I 5
  41. +#define SBI_REMOTE_SFENCE_VMA 6
  42. +#define SBI_REMOTE_SFENCE_VMA_ASID 7
  43. +#define SBI_SHUTDOWN 8
  44. +
  45. +#define SBI_CALL(which, arg0, arg1, arg2) ({ \
  46. + register uintptr_t a0 asm ("a0") = (uintptr_t)(arg0); \
  47. + register uintptr_t a1 asm ("a1") = (uintptr_t)(arg1); \
  48. + register uintptr_t a2 asm ("a2") = (uintptr_t)(arg2); \
  49. + register uintptr_t a7 asm ("a7") = (uintptr_t)(which); \
  50. + asm volatile ("ecall" \
  51. + : "+r" (a0) \
  52. + : "r" (a1), "r" (a2), "r" (a7) \
  53. + : "memory"); \
  54. + a0; \
  55. +})
  56. +
  57. +/* Lazy implementations until SBI is finalized */
  58. +#define SBI_CALL_0(which) SBI_CALL(which, 0, 0, 0)
  59. +#define SBI_CALL_1(which, arg0) SBI_CALL(which, arg0, 0, 0)
  60. +#define SBI_CALL_2(which, arg0, arg1) SBI_CALL(which, arg0, arg1, 0)
  61. +
  62. +static inline void sbi_console_putchar(int ch)
  63. +{
  64. + SBI_CALL_1(SBI_CONSOLE_PUTCHAR, ch);
  65. +}
  66. +
  67. +static inline int sbi_console_getchar(void)
  68. +{
  69. + return SBI_CALL_0(SBI_CONSOLE_GETCHAR);
  70. +}
  71. +
  72. +static inline void sbi_set_timer(uint64_t stime_value)
  73. +{
  74. +#if __riscv_xlen == 32
  75. + SBI_CALL_2(SBI_SET_TIMER, stime_value, stime_value >> 32);
  76. +#else
  77. + SBI_CALL_1(SBI_SET_TIMER, stime_value);
  78. +#endif
  79. +}
  80. +
  81. +static inline void sbi_shutdown(void)
  82. +{
  83. + SBI_CALL_0(SBI_SHUTDOWN);
  84. +}
  85. +
  86. +static inline void sbi_clear_ipi(void)
  87. +{
  88. + SBI_CALL_0(SBI_CLEAR_IPI);
  89. +}
  90. +
  91. +static inline void sbi_send_ipi(const unsigned long *hart_mask)
  92. +{
  93. + SBI_CALL_1(SBI_SEND_IPI, hart_mask);
  94. +}
  95. +
  96. +static inline void sbi_remote_fence_i(const unsigned long *hart_mask)
  97. +{
  98. + SBI_CALL_1(SBI_REMOTE_FENCE_I, hart_mask);
  99. +}
  100. +
  101. +static inline void sbi_remote_sfence_vma(const unsigned long *hart_mask,
  102. + unsigned long start,
  103. + unsigned long size)
  104. +{
  105. + SBI_CALL_1(SBI_REMOTE_SFENCE_VMA, hart_mask);
  106. +}
  107. +
  108. +static inline void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
  109. + unsigned long start,
  110. + unsigned long size,
  111. + unsigned long asid)
  112. +{
  113. + SBI_CALL_1(SBI_REMOTE_SFENCE_VMA_ASID, hart_mask);
  114. +}
  115. +
  116. +#endif
  117. --
  118. 2.21.0