0001-riscv-add-infrastructure-for-calling-functions-on-ot.patch 7.9 KB

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  1. From fa33f08fd657b8568ede929df8a79bd113e9c5b1 Mon Sep 17 00:00:00 2001
  2. From: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
  3. Date: Sun, 17 Mar 2019 19:28:32 +0100
  4. Subject: [PATCH 01/18] riscv: add infrastructure for calling functions on
  5. other harts
  6. Harts on RISC-V boot independently, U-Boot is responsible for managing
  7. them. Functions are called on other harts with smp_call_function(),
  8. which sends inter-processor interrupts (IPIs) to all other available
  9. harts. Available harts are those marked as available in the device tree
  10. and present in the available_harts mask stored in global data. The
  11. available_harts mask is used to register all harts that have entered
  12. U-Boot. Functions are specified with their address and two function
  13. arguments (argument 2 and 3). The first function argument is always the
  14. hart ID of the hart calling the function. On the other harts, the IPI
  15. interrupt handler handle_ipi() must be called on software interrupts to
  16. handle the request and call the specified function.
  17. Functions are stored in the ipi_data data structure. Every hart has its
  18. own data structure in global data. While this is not required at the
  19. moment (all harts are expected to boot Linux), this does allow future
  20. expansion, where other harts may be used for monitoring or other tasks.
  21. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
  22. Reviewed-by: Anup Patel <anup.patel@wdc.com>
  23. Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
  24. Tested-by: Bin Meng <bmeng.cn@gmail.com>
  25. ---
  26. arch/riscv/Kconfig | 19 +++++
  27. arch/riscv/include/asm/global_data.h | 6 ++
  28. arch/riscv/include/asm/smp.h | 53 ++++++++++++
  29. arch/riscv/lib/Makefile | 1 +
  30. arch/riscv/lib/smp.c | 118 +++++++++++++++++++++++++++
  31. 5 files changed, 197 insertions(+)
  32. create mode 100644 arch/riscv/include/asm/smp.h
  33. create mode 100644 arch/riscv/lib/smp.c
  34. diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
  35. index 36512a8995..4d7a115569 100644
  36. --- a/arch/riscv/Kconfig
  37. +++ b/arch/riscv/Kconfig
  38. @@ -120,4 +120,23 @@ config RISCV_RDTIME
  39. config SYS_MALLOC_F_LEN
  40. default 0x1000
  41. +config SMP
  42. + bool "Symmetric Multi-Processing"
  43. + help
  44. + This enables support for systems with more than one CPU. If
  45. + you say N here, U-Boot will run on single and multiprocessor
  46. + machines, but will use only one CPU of a multiprocessor
  47. + machine. If you say Y here, U-Boot will run on many, but not
  48. + all, single processor machines.
  49. +
  50. +config NR_CPUS
  51. + int "Maximum number of CPUs (2-32)"
  52. + range 2 32
  53. + depends on SMP
  54. + default 8
  55. + help
  56. + On multiprocessor machines, U-Boot sets up a stack for each CPU.
  57. + Stack memory is pre-allocated. U-Boot must therefore know the
  58. + maximum number of CPUs that may be present.
  59. +
  60. endmenu
  61. diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h
  62. index a3a342c6e1..80e3165e39 100644
  63. --- a/arch/riscv/include/asm/global_data.h
  64. +++ b/arch/riscv/include/asm/global_data.h
  65. @@ -10,12 +10,18 @@
  66. #ifndef __ASM_GBL_DATA_H
  67. #define __ASM_GBL_DATA_H
  68. +#include <asm/smp.h>
  69. +
  70. /* Architecture-specific global data */
  71. struct arch_global_data {
  72. long boot_hart; /* boot hart id */
  73. #ifdef CONFIG_SIFIVE_CLINT
  74. void __iomem *clint; /* clint base address */
  75. #endif
  76. +#ifdef CONFIG_SMP
  77. + struct ipi_data ipi[CONFIG_NR_CPUS];
  78. +#endif
  79. + ulong available_harts;
  80. };
  81. #include <asm-generic/global_data.h>
  82. diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h
  83. new file mode 100644
  84. index 0000000000..bc863fdbaf
  85. --- /dev/null
  86. +++ b/arch/riscv/include/asm/smp.h
  87. @@ -0,0 +1,53 @@
  88. +/* SPDX-License-Identifier: GPL-2.0 */
  89. +/*
  90. + * Copyright (C) 2019 Fraunhofer AISEC,
  91. + * Lukas Auer <lukas.auer@aisec.fraunhofer.de>
  92. + */
  93. +
  94. +#ifndef _ASM_RISCV_SMP_H
  95. +#define _ASM_RISCV_SMP_H
  96. +
  97. +/**
  98. + * struct ipi_data - Inter-processor interrupt (IPI) data structure
  99. + *
  100. + * IPIs are used for SMP support to communicate to other harts what function to
  101. + * call. Functions are in the form
  102. + * void (*addr)(ulong hart, ulong arg0, ulong arg1).
  103. + *
  104. + * The function address and the two arguments, arg0 and arg1, are stored in the
  105. + * IPI data structure. The hart ID is inserted by the hart handling the IPI and
  106. + * calling the function.
  107. + *
  108. + * @addr: Address of function
  109. + * @arg0: First argument of function
  110. + * @arg1: Second argument of function
  111. + */
  112. +struct ipi_data {
  113. + ulong addr;
  114. + ulong arg0;
  115. + ulong arg1;
  116. +};
  117. +
  118. +/**
  119. + * handle_ipi() - interrupt handler for software interrupts
  120. + *
  121. + * The IPI interrupt handler must be called to handle software interrupts. It
  122. + * calls the function specified in the hart's IPI data structure.
  123. + *
  124. + * @hart: Hart ID of the current hart
  125. + */
  126. +void handle_ipi(ulong hart);
  127. +
  128. +/**
  129. + * smp_call_function() - Call a function on all other harts
  130. + *
  131. + * Send IPIs with the specified function call to all harts.
  132. + *
  133. + * @addr: Address of function
  134. + * @arg0: First argument of function
  135. + * @arg1: Second argument of function
  136. + * @return 0 if OK, -ve on error
  137. + */
  138. +int smp_call_function(ulong addr, ulong arg0, ulong arg1);
  139. +
  140. +#endif
  141. diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
  142. index edfa61690c..19370f9749 100644
  143. --- a/arch/riscv/lib/Makefile
  144. +++ b/arch/riscv/lib/Makefile
  145. @@ -14,6 +14,7 @@ obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o
  146. obj-y += interrupts.o
  147. obj-y += reset.o
  148. obj-y += setjmp.o
  149. +obj-$(CONFIG_SMP) += smp.o
  150. # For building EFI apps
  151. CFLAGS_$(EFI_CRT0) := $(CFLAGS_EFI)
  152. diff --git a/arch/riscv/lib/smp.c b/arch/riscv/lib/smp.c
  153. new file mode 100644
  154. index 0000000000..caa292ccd2
  155. --- /dev/null
  156. +++ b/arch/riscv/lib/smp.c
  157. @@ -0,0 +1,118 @@
  158. +// SPDX-License-Identifier: GPL-2.0+
  159. +/*
  160. + * Copyright (C) 2019 Fraunhofer AISEC,
  161. + * Lukas Auer <lukas.auer@aisec.fraunhofer.de>
  162. + */
  163. +
  164. +#include <common.h>
  165. +#include <dm.h>
  166. +#include <asm/barrier.h>
  167. +#include <asm/smp.h>
  168. +
  169. +DECLARE_GLOBAL_DATA_PTR;
  170. +
  171. +/**
  172. + * riscv_send_ipi() - Send inter-processor interrupt (IPI)
  173. + *
  174. + * Platform code must provide this function.
  175. + *
  176. + * @hart: Hart ID of receiving hart
  177. + * @return 0 if OK, -ve on error
  178. + */
  179. +extern int riscv_send_ipi(int hart);
  180. +
  181. +/**
  182. + * riscv_clear_ipi() - Clear inter-processor interrupt (IPI)
  183. + *
  184. + * Platform code must provide this function.
  185. + *
  186. + * @hart: Hart ID of hart to be cleared
  187. + * @return 0 if OK, -ve on error
  188. + */
  189. +extern int riscv_clear_ipi(int hart);
  190. +
  191. +static int send_ipi_many(struct ipi_data *ipi)
  192. +{
  193. + ofnode node, cpus;
  194. + u32 reg;
  195. + int ret;
  196. +
  197. + cpus = ofnode_path("/cpus");
  198. + if (!ofnode_valid(cpus)) {
  199. + pr_err("Can't find cpus node!\n");
  200. + return -EINVAL;
  201. + }
  202. +
  203. + ofnode_for_each_subnode(node, cpus) {
  204. + /* skip if hart is marked as not available in the device tree */
  205. + if (!ofnode_is_available(node))
  206. + continue;
  207. +
  208. + /* read hart ID of CPU */
  209. + ret = ofnode_read_u32(node, "reg", &reg);
  210. + if (ret)
  211. + continue;
  212. +
  213. + /* skip if it is the hart we are running on */
  214. + if (reg == gd->arch.boot_hart)
  215. + continue;
  216. +
  217. + if (reg >= CONFIG_NR_CPUS) {
  218. + pr_err("Hart ID %d is out of range, increase CONFIG_NR_CPUS\n",
  219. + reg);
  220. + continue;
  221. + }
  222. +
  223. + /* skip if hart is not available */
  224. + if (!(gd->arch.available_harts & (1 << reg)))
  225. + continue;
  226. +
  227. + gd->arch.ipi[reg].addr = ipi->addr;
  228. + gd->arch.ipi[reg].arg0 = ipi->arg0;
  229. + gd->arch.ipi[reg].arg1 = ipi->arg1;
  230. +
  231. + ret = riscv_send_ipi(reg);
  232. + if (ret) {
  233. + pr_err("Cannot send IPI to hart %d\n", reg);
  234. + return ret;
  235. + }
  236. + }
  237. +
  238. + return 0;
  239. +}
  240. +
  241. +void handle_ipi(ulong hart)
  242. +{
  243. + int ret;
  244. + void (*smp_function)(ulong hart, ulong arg0, ulong arg1);
  245. +
  246. + if (hart >= CONFIG_NR_CPUS)
  247. + return;
  248. +
  249. + ret = riscv_clear_ipi(hart);
  250. + if (ret) {
  251. + pr_err("Cannot clear IPI of hart %ld\n", hart);
  252. + return;
  253. + }
  254. +
  255. + __smp_mb();
  256. +
  257. + smp_function = (void (*)(ulong, ulong, ulong))gd->arch.ipi[hart].addr;
  258. + invalidate_icache_all();
  259. +
  260. + smp_function(hart, gd->arch.ipi[hart].arg0, gd->arch.ipi[hart].arg1);
  261. +}
  262. +
  263. +int smp_call_function(ulong addr, ulong arg0, ulong arg1)
  264. +{
  265. + int ret = 0;
  266. + struct ipi_data ipi;
  267. +
  268. + ipi.addr = addr;
  269. + ipi.arg0 = arg0;
  270. + ipi.arg1 = arg1;
  271. +
  272. + ret = send_ipi_many(&ipi);
  273. +
  274. + return ret;
  275. +}
  276. --
  277. 2.21.0