0005-gpio-sifive-support-GPIO-on-SiFive-SoCs.patch 12 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409
  1. From 9b081d5eb7cd900b8ed96c1ee01f515de11fb174 Mon Sep 17 00:00:00 2001
  2. From: "Wesley W. Terpstra" <wesley@sifive.com>
  3. Date: Wed, 21 Feb 2018 15:43:02 -0800
  4. Subject: [PATCH 05/10] gpio-sifive: support GPIO on SiFive SoCs
  5. ---
  6. .../devicetree/bindings/gpio/gpio-sifive.txt | 28 ++
  7. drivers/gpio/Kconfig | 7 +
  8. drivers/gpio/Makefile | 1 +
  9. drivers/gpio/gpio-sifive.c | 322 ++++++++++++++++++
  10. 4 files changed, 358 insertions(+)
  11. create mode 100644 Documentation/devicetree/bindings/gpio/gpio-sifive.txt
  12. create mode 100644 drivers/gpio/gpio-sifive.c
  13. diff --git a/Documentation/devicetree/bindings/gpio/gpio-sifive.txt b/Documentation/devicetree/bindings/gpio/gpio-sifive.txt
  14. new file mode 100644
  15. index 000000000000..bf41eed81dbf
  16. --- /dev/null
  17. +++ b/Documentation/devicetree/bindings/gpio/gpio-sifive.txt
  18. @@ -0,0 +1,28 @@
  19. +SiFive GPIO controller bindings
  20. +
  21. +Required properties:
  22. +- compatible:
  23. + - "sifive,gpio0"
  24. +- reg: Physical base address and length of the controller's registers.
  25. +- #gpio-cells : Should be 2
  26. + - The first cell is the gpio offset number.
  27. + - The second cell indicates the polarity of the GPIO
  28. +- gpio-controller : Marks the device node as a GPIO controller.
  29. +- interrupt-controller: Mark the device node as an interrupt controller
  30. +- #interrupt-cells : Should be 2.
  31. + - The first cell is the GPIO offset number within the GPIO controller.
  32. + - The second cell is the edge/level to use for interrupt generation.
  33. +- interrupts: Specify the interrupts, one per GPIO
  34. +
  35. +Example:
  36. +
  37. +gpio: gpio@10060000 {
  38. + compatible = "sifive,gpio0";
  39. + interrupt-parent = <&plic>;
  40. + interrupts = <7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22>;
  41. + reg = <0x0 0x10060000 0x0 0x1000>;
  42. + gpio-controller;
  43. + #gpio-cells = <2>;
  44. + interrupt-controller;
  45. + #interrupt-cells = <2>;
  46. +};
  47. diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
  48. index 3f50526a771f..2a0115b0df97 100644
  49. --- a/drivers/gpio/Kconfig
  50. +++ b/drivers/gpio/Kconfig
  51. @@ -451,6 +451,13 @@ config GPIO_SAMA5D2_PIOBU
  52. The difference from regular GPIOs is that they
  53. maintain their value during backup/self-refresh.
  54. +config GPIO_SIFIVE
  55. + bool "SiFive GPIO support"
  56. + depends on OF_GPIO
  57. + select GPIOLIB_IRQCHIP
  58. + help
  59. + Say yes here to support the GPIO device on SiFive SoCs.
  60. +
  61. config GPIO_SIOX
  62. tristate "SIOX GPIO support"
  63. depends on SIOX
  64. diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
  65. index 54d55274b93a..660e2e70f05c 100644
  66. --- a/drivers/gpio/Makefile
  67. +++ b/drivers/gpio/Makefile
  68. @@ -114,6 +114,7 @@ obj-$(CONFIG_ARCH_SA1100) += gpio-sa1100.o
  69. obj-$(CONFIG_GPIO_SAMA5D2_PIOBU) += gpio-sama5d2-piobu.o
  70. obj-$(CONFIG_GPIO_SCH) += gpio-sch.o
  71. obj-$(CONFIG_GPIO_SCH311X) += gpio-sch311x.o
  72. +obj-$(CONFIG_GPIO_SIFIVE) += gpio-sifive.o
  73. obj-$(CONFIG_GPIO_SNPS_CREG) += gpio-creg-snps.o
  74. obj-$(CONFIG_GPIO_SODAVILLE) += gpio-sodaville.o
  75. obj-$(CONFIG_GPIO_SPEAR_SPICS) += gpio-spear-spics.o
  76. diff --git a/drivers/gpio/gpio-sifive.c b/drivers/gpio/gpio-sifive.c
  77. new file mode 100644
  78. index 000000000000..6482ebbc00ce
  79. --- /dev/null
  80. +++ b/drivers/gpio/gpio-sifive.c
  81. @@ -0,0 +1,322 @@
  82. +/*
  83. + * SiFive GPIO driver
  84. + *
  85. + * Copyright (C) 2018 SiFive, Inc.
  86. + *
  87. + * This program is free software; you can redistribute it and/or modify
  88. + * it under the terms of the GNU General Public License version 2 as
  89. + * published by the Free Software Foundation.
  90. + */
  91. +#include <linux/bitops.h>
  92. +#include <linux/device.h>
  93. +#include <linux/errno.h>
  94. +#include <linux/of_irq.h>
  95. +#include <linux/gpio/driver.h>
  96. +#include <linux/irqchip/chained_irq.h>
  97. +#include <linux/init.h>
  98. +#include <linux/of.h>
  99. +#include <linux/pinctrl/consumer.h>
  100. +#include <linux/platform_device.h>
  101. +#include <linux/pm.h>
  102. +#include <linux/slab.h>
  103. +#include <linux/spinlock.h>
  104. +
  105. +#define GPIO_INPUT_VAL 0x00
  106. +#define GPIO_INPUT_EN 0x04
  107. +#define GPIO_OUTPUT_EN 0x08
  108. +#define GPIO_OUTPUT_VAL 0x0C
  109. +#define GPIO_RISE_IE 0x18
  110. +#define GPIO_RISE_IP 0x1C
  111. +#define GPIO_FALL_IE 0x20
  112. +#define GPIO_FALL_IP 0x24
  113. +#define GPIO_HIGH_IE 0x28
  114. +#define GPIO_HIGH_IP 0x2C
  115. +#define GPIO_LOW_IE 0x30
  116. +#define GPIO_LOW_IP 0x34
  117. +#define GPIO_OUTPUT_XOR 0x40
  118. +
  119. +#define MAX_GPIO 32
  120. +
  121. +struct sifive_gpio {
  122. + raw_spinlock_t lock;
  123. + void __iomem *base;
  124. + struct gpio_chip gc;
  125. + unsigned long enabled;
  126. + unsigned trigger[MAX_GPIO];
  127. + unsigned int irq_parent[MAX_GPIO];
  128. + struct sifive_gpio *self_ptr[MAX_GPIO];
  129. +};
  130. +
  131. +static void sifive_assign_bit(void __iomem *ptr, int offset, int value)
  132. +{
  133. + // It's frustrating that we are not allowed to use the device atomics
  134. + // which are GUARANTEED to be supported by this device on RISC-V
  135. + u32 bit = BIT(offset), old = ioread32(ptr);
  136. + if (value)
  137. + iowrite32(old | bit, ptr);
  138. + else
  139. + iowrite32(old & ~bit, ptr);
  140. +}
  141. +
  142. +static int sifive_direction_input(struct gpio_chip *gc, unsigned offset)
  143. +{
  144. + struct sifive_gpio *chip = gpiochip_get_data(gc);
  145. + unsigned long flags;
  146. +
  147. + if (offset >= gc->ngpio)
  148. + return -EINVAL;
  149. +
  150. + raw_spin_lock_irqsave(&chip->lock, flags);
  151. + sifive_assign_bit(chip->base + GPIO_OUTPUT_EN, offset, 0);
  152. + sifive_assign_bit(chip->base + GPIO_INPUT_EN, offset, 1);
  153. + raw_spin_unlock_irqrestore(&chip->lock, flags);
  154. +
  155. + return 0;
  156. +}
  157. +
  158. +static int sifive_direction_output(struct gpio_chip *gc, unsigned offset, int value)
  159. +{
  160. + struct sifive_gpio *chip = gpiochip_get_data(gc);
  161. + unsigned long flags;
  162. +
  163. + if (offset >= gc->ngpio)
  164. + return -EINVAL;
  165. +
  166. + raw_spin_lock_irqsave(&chip->lock, flags);
  167. + sifive_assign_bit(chip->base + GPIO_INPUT_EN, offset, 0);
  168. + sifive_assign_bit(chip->base + GPIO_OUTPUT_VAL, offset, value);
  169. + sifive_assign_bit(chip->base + GPIO_OUTPUT_EN, offset, 1);
  170. + raw_spin_unlock_irqrestore(&chip->lock, flags);
  171. +
  172. + return 0;
  173. +}
  174. +
  175. +static int sifive_get_direction(struct gpio_chip *gc, unsigned offset)
  176. +{
  177. + struct sifive_gpio *chip = gpiochip_get_data(gc);
  178. +
  179. + if (offset >= gc->ngpio)
  180. + return -EINVAL;
  181. +
  182. + return !(ioread32(chip->base + GPIO_OUTPUT_EN) & BIT(offset));
  183. +}
  184. +
  185. +static int sifive_get_value(struct gpio_chip *gc, unsigned offset)
  186. +{
  187. + struct sifive_gpio *chip = gpiochip_get_data(gc);
  188. +
  189. + if (offset >= gc->ngpio)
  190. + return -EINVAL;
  191. +
  192. + return !!(ioread32(chip->base + GPIO_INPUT_VAL) & BIT(offset));
  193. +}
  194. +
  195. +static void sifive_set_value(struct gpio_chip *gc, unsigned offset, int value)
  196. +{
  197. + struct sifive_gpio *chip = gpiochip_get_data(gc);
  198. + unsigned long flags;
  199. +
  200. + if (offset >= gc->ngpio)
  201. + return;
  202. +
  203. + raw_spin_lock_irqsave(&chip->lock, flags);
  204. + sifive_assign_bit(chip->base + GPIO_OUTPUT_VAL, offset, value);
  205. + raw_spin_unlock_irqrestore(&chip->lock, flags);
  206. +}
  207. +
  208. +static void sifive_set_ie(struct sifive_gpio *chip, int offset)
  209. +{
  210. + unsigned long flags;
  211. + unsigned trigger;
  212. +
  213. + raw_spin_lock_irqsave(&chip->lock, flags);
  214. + trigger = (chip->enabled & BIT(offset)) ? chip->trigger[offset] : 0;
  215. + sifive_assign_bit(chip->base + GPIO_RISE_IE, offset, trigger & IRQ_TYPE_EDGE_RISING);
  216. + sifive_assign_bit(chip->base + GPIO_FALL_IE, offset, trigger & IRQ_TYPE_EDGE_FALLING);
  217. + sifive_assign_bit(chip->base + GPIO_HIGH_IE, offset, trigger & IRQ_TYPE_LEVEL_HIGH);
  218. + sifive_assign_bit(chip->base + GPIO_LOW_IE, offset, trigger & IRQ_TYPE_LEVEL_LOW);
  219. + raw_spin_unlock_irqrestore(&chip->lock, flags);
  220. +}
  221. +
  222. +static int sifive_irq_set_type(struct irq_data *d, unsigned trigger)
  223. +{
  224. + struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  225. + struct sifive_gpio *chip = gpiochip_get_data(gc);
  226. + int offset = irqd_to_hwirq(d);
  227. +
  228. + if (offset < 0 || offset >= gc->ngpio)
  229. + return -EINVAL;
  230. +
  231. + chip->trigger[offset] = trigger;
  232. + sifive_set_ie(chip, offset);
  233. + return 0;
  234. +}
  235. +
  236. +/* chained_irq_{enter,exit} already mask the parent */
  237. +static void sifive_irq_mask(struct irq_data *d) { }
  238. +static void sifive_irq_unmask(struct irq_data *d) { }
  239. +
  240. +static void sifive_irq_enable(struct irq_data *d)
  241. +{
  242. + struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  243. + struct sifive_gpio *chip = gpiochip_get_data(gc);
  244. + int offset = irqd_to_hwirq(d) % MAX_GPIO; // must not fail
  245. + u32 bit = BIT(offset);
  246. +
  247. + /* Switch to input */
  248. + sifive_direction_input(gc, offset);
  249. +
  250. + /* Clear any sticky pending interrupts */
  251. + iowrite32(bit, chip->base + GPIO_RISE_IP);
  252. + iowrite32(bit, chip->base + GPIO_FALL_IP);
  253. + iowrite32(bit, chip->base + GPIO_HIGH_IP);
  254. + iowrite32(bit, chip->base + GPIO_LOW_IP);
  255. +
  256. + /* Enable interrupts */
  257. + assign_bit(offset, &chip->enabled, 1);
  258. + sifive_set_ie(chip, offset);
  259. +}
  260. +
  261. +static void sifive_irq_disable(struct irq_data *d)
  262. +{
  263. + struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  264. + struct sifive_gpio *chip = gpiochip_get_data(gc);
  265. + int offset = irqd_to_hwirq(d) % MAX_GPIO; // must not fail
  266. +
  267. + assign_bit(offset, &chip->enabled, 0);
  268. + sifive_set_ie(chip, offset);
  269. +}
  270. +
  271. +static struct irq_chip sifive_irqchip = {
  272. + .name = "sifive-gpio",
  273. + .irq_set_type = sifive_irq_set_type,
  274. + .irq_mask = sifive_irq_mask,
  275. + .irq_unmask = sifive_irq_unmask,
  276. + .irq_enable = sifive_irq_enable,
  277. + .irq_disable = sifive_irq_disable,
  278. +};
  279. +
  280. +static void sifive_irq_handler(struct irq_desc *desc)
  281. +{
  282. + struct irq_chip *irqchip = irq_desc_get_chip(desc);
  283. + struct sifive_gpio **self_ptr = irq_desc_get_handler_data(desc);
  284. + struct sifive_gpio *chip = *self_ptr;
  285. + int offset = self_ptr - &chip->self_ptr[0];
  286. + u32 bit = BIT(offset);
  287. +
  288. + chained_irq_enter(irqchip, desc);
  289. +
  290. + /* Re-arm the edge triggers so don't miss the next one */
  291. + iowrite32(bit, chip->base + GPIO_RISE_IP);
  292. + iowrite32(bit, chip->base + GPIO_FALL_IP);
  293. +
  294. + generic_handle_irq(irq_find_mapping(chip->gc.irq.domain, offset));
  295. +
  296. + /* Re-arm the level triggers after handling to prevent spurious refire */
  297. + iowrite32(bit, chip->base + GPIO_HIGH_IP);
  298. + iowrite32(bit, chip->base + GPIO_LOW_IP);
  299. +
  300. + chained_irq_exit(irqchip, desc);
  301. +}
  302. +
  303. +static int sifive_gpio_probe(struct platform_device *pdev)
  304. +{
  305. + struct device *dev = &pdev->dev;
  306. + struct device_node *node = pdev->dev.of_node;
  307. + struct sifive_gpio *chip;
  308. + struct resource *res;
  309. + int gpio, irq, ret, ngpio;
  310. +
  311. + chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
  312. + if (!chip) {
  313. + dev_err(dev, "out of memory\n");
  314. + return -ENOMEM;
  315. + }
  316. +
  317. + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  318. + chip->base = devm_ioremap_resource(dev, res);
  319. + if (IS_ERR(chip->base)) {
  320. + dev_err(dev, "failed to allocate device memory\n");
  321. + return PTR_ERR(chip->base);
  322. + }
  323. +
  324. + ngpio = of_irq_count(node);
  325. + if (ngpio >= MAX_GPIO) {
  326. + dev_err(dev, "too many interrupts\n");
  327. + return -EINVAL;
  328. + }
  329. +
  330. + raw_spin_lock_init(&chip->lock);
  331. + chip->gc.direction_input = sifive_direction_input;
  332. + chip->gc.direction_output = sifive_direction_output;
  333. + chip->gc.get_direction = sifive_get_direction;
  334. + chip->gc.get = sifive_get_value;
  335. + chip->gc.set = sifive_set_value;
  336. + chip->gc.base = -1;
  337. + chip->gc.ngpio = ngpio;
  338. + chip->gc.label = dev_name(dev);
  339. + chip->gc.parent = dev;
  340. + chip->gc.owner = THIS_MODULE;
  341. +
  342. + ret = gpiochip_add_data(&chip->gc, chip);
  343. + if (ret)
  344. + return ret;
  345. +
  346. + /* Disable all GPIO interrupts before enabling parent interrupts */
  347. + iowrite32(0, chip->base + GPIO_RISE_IE);
  348. + iowrite32(0, chip->base + GPIO_FALL_IE);
  349. + iowrite32(0, chip->base + GPIO_HIGH_IE);
  350. + iowrite32(0, chip->base + GPIO_LOW_IE);
  351. + chip->enabled = 0;
  352. +
  353. + ret = gpiochip_irqchip_add(&chip->gc, &sifive_irqchip, 0, handle_simple_irq, IRQ_TYPE_NONE);
  354. + if (ret) {
  355. + dev_err(dev, "could not add irqchip\n");
  356. + gpiochip_remove(&chip->gc);
  357. + return ret;
  358. + }
  359. +
  360. + chip->gc.irq.num_parents = ngpio;
  361. + chip->gc.irq.parents = &chip->irq_parent[0];
  362. + chip->gc.irq.map = &chip->irq_parent[0];
  363. +
  364. + for (gpio = 0; gpio < ngpio; ++gpio) {
  365. + irq = platform_get_irq(pdev, gpio);
  366. + if (irq < 0) {
  367. + dev_err(dev, "invalid IRQ\n");
  368. + gpiochip_remove(&chip->gc);
  369. + return -ENODEV;
  370. + }
  371. +
  372. + chip->irq_parent[gpio] = irq;
  373. + chip->self_ptr[gpio] = chip;
  374. + chip->trigger[gpio] = IRQ_TYPE_LEVEL_HIGH;
  375. + }
  376. +
  377. + for (gpio = 0; gpio < ngpio; ++gpio) {
  378. + irq = chip->irq_parent[gpio];
  379. + irq_set_chained_handler_and_data(irq, sifive_irq_handler, &chip->self_ptr[gpio]);
  380. + irq_set_parent(irq_find_mapping(chip->gc.irq.domain, gpio), irq);
  381. + }
  382. +
  383. + platform_set_drvdata(pdev, chip);
  384. + dev_info(dev, "SiFive GPIO chip registered %d GPIOs\n", ngpio);
  385. +
  386. + return 0;
  387. +}
  388. +
  389. +static const struct of_device_id sifive_gpio_match[] = {
  390. + {
  391. + .compatible = "sifive,gpio0",
  392. + },
  393. + { },
  394. +};
  395. +
  396. +static struct platform_driver sifive_gpio_driver = {
  397. + .probe = sifive_gpio_probe,
  398. + .driver = {
  399. + .name = "sifive_gpio",
  400. + .of_match_table = of_match_ptr(sifive_gpio_match),
  401. + },
  402. +};
  403. +builtin_platform_driver(sifive_gpio_driver)
  404. --
  405. 2.21.0