0001-tty-serial-add-driver-for-the-SiFive-UART.patch 33 KB

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  1. From 322175de5296868fa55aa911ea7ba936a985a29a Mon Sep 17 00:00:00 2001
  2. From: Paul Walmsley <paul.walmsley@sifive.com>
  3. Date: Sat, 20 Oct 2018 03:10:47 -0700
  4. Subject: [PATCH 01/10] tty: serial: add driver for the SiFive UART
  5. Add a serial driver for the SiFive UART, found on SiFive FU540 devices
  6. (among others).
  7. The underlying serial IP block is relatively basic, and currently does
  8. not support serial break detection. Further information on the IP
  9. block can be found in the documentation and Chisel sources:
  10. https://static.dev.sifive.com/FU540-C000-v1.0.pdf
  11. https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/uart
  12. This driver was written in collaboration with Wesley Terpstra
  13. <wesley@sifive.com>.
  14. Boot-tested on a SiFive HiFive Unleashed A00 board.
  15. Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  16. Cc: Jiri Slaby <jslaby@suse.com>
  17. Cc: Palmer Dabbelt <palmer@sifive.com>
  18. Cc: Wesley Terpstra <wesley@sifive.com>
  19. Cc: linux-serial@vger.kernel.org
  20. Cc: linux-riscv@lists.infradead.org
  21. Cc: linux-kernel@vger.kernel.org
  22. Cc: Julia Lawall <julia.lawall@lip6.fr>
  23. Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
  24. Signed-off-by: Paul Walmsley <paul@pwsan.com>
  25. ---
  26. drivers/tty/serial/Kconfig | 24 +
  27. drivers/tty/serial/Makefile | 1 +
  28. drivers/tty/serial/sifive.c | 1067 ++++++++++++++++++++++++++++++
  29. include/uapi/linux/serial_core.h | 3 +
  30. 4 files changed, 1095 insertions(+)
  31. create mode 100644 drivers/tty/serial/sifive.c
  32. diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
  33. index 72966bc0ac76..561e053b690a 100644
  34. --- a/drivers/tty/serial/Kconfig
  35. +++ b/drivers/tty/serial/Kconfig
  36. @@ -1095,6 +1095,30 @@ config SERIAL_OMAP_CONSOLE
  37. your boot loader about how to pass options to the kernel at
  38. boot time.)
  39. +config SERIAL_SIFIVE
  40. + tristate "SiFive UART support"
  41. + depends on OF
  42. + select SERIAL_CORE
  43. + help
  44. + Select this option if you are building a kernel for a device that
  45. + contains a SiFive UART IP block. This type of UART is present on
  46. + SiFive FU540 SoCs, among others.
  47. +
  48. +config SERIAL_SIFIVE_CONSOLE
  49. + bool "Console on SiFive UART"
  50. + depends on SERIAL_SIFIVE=y
  51. + select SERIAL_CORE_CONSOLE
  52. + help
  53. + Select this option if you would like to use a SiFive UART as the
  54. + system console.
  55. +
  56. + Even if you say Y here, the currently visible virtual console
  57. + (/dev/tty0) will still be used as the system console by default, but
  58. + you can alter that using a kernel command line option such as
  59. + "console=ttySIFx". (Try "man bootparam" or see the documentation of
  60. + your boot loader about how to pass options to the kernel at
  61. + boot time.)
  62. +
  63. config SERIAL_LANTIQ
  64. bool "Lantiq serial driver"
  65. depends on LANTIQ
  66. diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile
  67. index 40b702aaa85e..2aff1d07d08b 100644
  68. --- a/drivers/tty/serial/Makefile
  69. +++ b/drivers/tty/serial/Makefile
  70. @@ -92,6 +92,7 @@ obj-$(CONFIG_SERIAL_PIC32) += pic32_uart.o
  71. obj-$(CONFIG_SERIAL_MPS2_UART) += mps2-uart.o
  72. obj-$(CONFIG_SERIAL_OWL) += owl-uart.o
  73. obj-$(CONFIG_SERIAL_RDA) += rda-uart.o
  74. +obj-$(CONFIG_SERIAL_SIFIVE) += sifive.o
  75. # GPIOLIB helpers for modem control lines
  76. obj-$(CONFIG_SERIAL_MCTRL_GPIO) += serial_mctrl_gpio.o
  77. diff --git a/drivers/tty/serial/sifive.c b/drivers/tty/serial/sifive.c
  78. new file mode 100644
  79. index 000000000000..80c06039fb57
  80. --- /dev/null
  81. +++ b/drivers/tty/serial/sifive.c
  82. @@ -0,0 +1,1067 @@
  83. +// SPDX-License-Identifier: GPL-2.0+
  84. +/*
  85. + * SiFive UART driver
  86. + * Copyright (C) 2018 Paul Walmsley <paul@pwsan.com>
  87. + * Copyright (C) 2018 SiFive
  88. + *
  89. + * This program is free software; you can redistribute it and/or modify
  90. + * it under the terms of the GNU General Public License as published by
  91. + * the Free Software Foundation; either version 2 of the License, or
  92. + * (at your option) any later version.
  93. + *
  94. + * This program is distributed in the hope that it will be useful,
  95. + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  96. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  97. + * GNU General Public License for more details.
  98. + *
  99. + * Based partially on:
  100. + * - drivers/tty/serial/pxa.c
  101. + * - drivers/tty/serial/amba-pl011.c
  102. + * - drivers/tty/serial/uartlite.c
  103. + * - drivers/tty/serial/omap-serial.c
  104. + * - drivers/pwm/pwm-sifive.c
  105. + *
  106. + * See the following sources for further documentation:
  107. + * - Chapter 19 "Universal Asynchronous Receiver/Transmitter (UART)" of
  108. + * SiFive FE310-G000 v2p3
  109. + * - The tree/master/src/main/scala/devices/uart directory of
  110. + * https://github.com/sifive/sifive-blocks/
  111. + *
  112. + * The SiFive UART design is not 8250-compatible. The following common
  113. + * features are not supported:
  114. + * - Word lengths other than 8 bits
  115. + * - Break handling
  116. + * - Parity
  117. + * - Flow control
  118. + * - Modem signals (DSR, RI, etc.)
  119. + * On the other hand, the design is free from the baggage of the 8250
  120. + * programming model.
  121. + */
  122. +
  123. +#include <linux/clk.h>
  124. +#include <linux/console.h>
  125. +#include <linux/delay.h>
  126. +#include <linux/init.h>
  127. +#include <linux/io.h>
  128. +#include <linux/irq.h>
  129. +#include <linux/module.h>
  130. +#include <linux/of.h>
  131. +#include <linux/of_irq.h>
  132. +#include <linux/platform_device.h>
  133. +#include <linux/serial_core.h>
  134. +#include <linux/serial_reg.h>
  135. +#include <linux/slab.h>
  136. +#include <linux/tty.h>
  137. +#include <linux/tty_flip.h>
  138. +
  139. +/*
  140. + * Register offsets
  141. + */
  142. +
  143. +/* TXDATA */
  144. +#define SIFIVE_SERIAL_TXDATA_OFFS 0x0
  145. +#define SIFIVE_SERIAL_TXDATA_FULL_SHIFT 31
  146. +#define SIFIVE_SERIAL_TXDATA_FULL_MASK (1 << SIFIVE_SERIAL_TXDATA_FULL_SHIFT)
  147. +#define SIFIVE_SERIAL_TXDATA_DATA_SHIFT 0
  148. +#define SIFIVE_SERIAL_TXDATA_DATA_MASK (0xff << SIFIVE_SERIAL_TXDATA_DATA_SHIFT)
  149. +
  150. +/* RXDATA */
  151. +#define SIFIVE_SERIAL_RXDATA_OFFS 0x4
  152. +#define SIFIVE_SERIAL_RXDATA_EMPTY_SHIFT 31
  153. +#define SIFIVE_SERIAL_RXDATA_EMPTY_MASK (1 << SIFIVE_SERIAL_RXDATA_EMPTY_SHIFT)
  154. +#define SIFIVE_SERIAL_RXDATA_DATA_SHIFT 0
  155. +#define SIFIVE_SERIAL_RXDATA_DATA_MASK (0xff << SIFIVE_SERIAL_RXDATA_DATA_SHIFT)
  156. +
  157. +/* TXCTRL */
  158. +#define SIFIVE_SERIAL_TXCTRL_OFFS 0x8
  159. +#define SIFIVE_SERIAL_TXCTRL_TXCNT_SHIFT 16
  160. +#define SIFIVE_SERIAL_TXCTRL_TXCNT_MASK (0x7 << SIFIVE_SERIAL_TXCTRL_TXCNT_SHIFT)
  161. +#define SIFIVE_SERIAL_TXCTRL_NSTOP_SHIFT 1
  162. +#define SIFIVE_SERIAL_TXCTRL_NSTOP_MASK (1 << SIFIVE_SERIAL_TXCTRL_NSTOP_SHIFT)
  163. +#define SIFIVE_SERIAL_TXCTRL_TXEN_SHIFT 0
  164. +#define SIFIVE_SERIAL_TXCTRL_TXEN_MASK (1 << SIFIVE_SERIAL_TXCTRL_TXEN_SHIFT)
  165. +
  166. +/* RXCTRL */
  167. +#define SIFIVE_SERIAL_RXCTRL_OFFS 0xC
  168. +#define SIFIVE_SERIAL_RXCTRL_RXCNT_SHIFT 16
  169. +#define SIFIVE_SERIAL_RXCTRL_RXCNT_MASK (0x7 << SIFIVE_SERIAL_TXCTRL_TXCNT_SHIFT)
  170. +#define SIFIVE_SERIAL_RXCTRL_RXEN_SHIFT 0
  171. +#define SIFIVE_SERIAL_RXCTRL_RXEN_MASK (1 << SIFIVE_SERIAL_RXCTRL_RXEN_SHIFT)
  172. +
  173. +/* IE */
  174. +#define SIFIVE_SERIAL_IE_OFFS 0x10
  175. +#define SIFIVE_SERIAL_IE_RXWM_SHIFT 1
  176. +#define SIFIVE_SERIAL_IE_RXWM_MASK (1 << SIFIVE_SERIAL_IE_RXWM_SHIFT)
  177. +#define SIFIVE_SERIAL_IE_TXWM_SHIFT 0
  178. +#define SIFIVE_SERIAL_IE_TXWM_MASK (1 << SIFIVE_SERIAL_IE_TXWM_SHIFT)
  179. +
  180. +/* IP */
  181. +#define SIFIVE_SERIAL_IP_OFFS 0x14
  182. +#define SIFIVE_SERIAL_IP_RXWM_SHIFT 1
  183. +#define SIFIVE_SERIAL_IP_RXWM_MASK (1 << SIFIVE_SERIAL_IP_RXWM_SHIFT)
  184. +#define SIFIVE_SERIAL_IP_TXWM_SHIFT 0
  185. +#define SIFIVE_SERIAL_IP_TXWM_MASK (1 << SIFIVE_SERIAL_IP_TXWM_SHIFT)
  186. +
  187. +/* DIV */
  188. +#define SIFIVE_SERIAL_DIV_OFFS 0x18
  189. +#define SIFIVE_SERIAL_DIV_DIV_SHIFT 0
  190. +#define SIFIVE_SERIAL_DIV_DIV_MASK (0xffff << SIFIVE_SERIAL_IP_DIV_SHIFT)
  191. +
  192. +/*
  193. + * Config macros
  194. + */
  195. +
  196. +/*
  197. + * SIFIVE_SERIAL_MAX_PORTS: maximum number of UARTs on a device that can
  198. + * host a serial console
  199. + */
  200. +#define SIFIVE_SERIAL_MAX_PORTS 8
  201. +
  202. +/*
  203. + * SIFIVE_DEFAULT_BAUD_RATE: default baud rate that the driver should
  204. + * configure itself to use
  205. + */
  206. +#define SIFIVE_DEFAULT_BAUD_RATE 115200
  207. +
  208. +/* SIFIVE_SERIAL_NAME: our driver's name that we pass to the operating system */
  209. +#define SIFIVE_SERIAL_NAME "sifive-serial"
  210. +
  211. +/* SIFIVE_TTY_PREFIX: tty name prefix for SiFive serial ports */
  212. +#define SIFIVE_TTY_PREFIX "ttySIF"
  213. +
  214. +/* SIFIVE_TX_FIFO_DEPTH: depth of the TX FIFO (in bytes) */
  215. +#define SIFIVE_TX_FIFO_DEPTH 8
  216. +
  217. +/* SIFIVE_RX_FIFO_DEPTH: depth of the TX FIFO (in bytes) */
  218. +#define SIFIVE_RX_FIFO_DEPTH 8
  219. +
  220. +#if (SIFIVE_TX_FIFO_DEPTH != SIFIVE_RX_FIFO_DEPTH)
  221. +#error Driver does not support configurations with different TX, RX FIFO sizes
  222. +#endif
  223. +
  224. +/*
  225. + *
  226. + */
  227. +
  228. +/**
  229. + * sifive_serial_port - driver-specific data extension to struct uart_port
  230. + * @port: struct uart_port embedded in this struct
  231. + * @dev: struct device *
  232. + * @ier: shadowed copy of the interrupt enable register
  233. + * @clkin_rate: input clock to the UART IP block.
  234. + * @baud_rate: UART serial line rate (e.g., 115200 baud)
  235. + * @clk_notifier: clock rate change notifier for upstream clock changes
  236. + *
  237. + * Configuration data specific to this SiFive UART.
  238. + */
  239. +struct sifive_serial_port {
  240. + struct uart_port port;
  241. + struct device *dev;
  242. + unsigned char ier;
  243. + unsigned long clkin_rate;
  244. + unsigned long baud_rate;
  245. + struct clk *clk;
  246. + struct notifier_block clk_notifier;
  247. +};
  248. +
  249. +/*
  250. + * Structure container-of macros
  251. + */
  252. +
  253. +#define port_to_sifive_serial_port(p) (container_of((p), \
  254. + struct sifive_serial_port, \
  255. + port))
  256. +
  257. +#define notifier_to_sifive_serial_port(nb) (container_of((nb), \
  258. + struct sifive_serial_port, \
  259. + clk_notifier))
  260. +
  261. +/*
  262. + * Forward declarations
  263. + */
  264. +static void sifive_serial_stop_tx(struct uart_port *port);
  265. +
  266. +/*
  267. + * Internal functions
  268. + */
  269. +
  270. +/**
  271. + * __ssp_early_writel() - write to a SiFive serial port register (early)
  272. + * @port: pointer to a struct uart_port record
  273. + * @offs: register address offset from the IP block base address
  274. + * @v: value to write to the register
  275. + *
  276. + * Given a pointer @port to a struct uart_port record, write the value
  277. + * @v to the IP block register address offset @offs. This function is
  278. + * intended for early console use.
  279. + *
  280. + * Context: Intended to be used only by the earlyconsole code.
  281. + */
  282. +static void __ssp_early_writel(u32 v, u16 offs, struct uart_port *port)
  283. +{
  284. + writel_relaxed(v, port->membase + offs);
  285. +}
  286. +
  287. +/**
  288. + * __ssp_early_readl() - read from a SiFive serial port register (early)
  289. + * @port: pointer to a struct uart_port record
  290. + * @offs: register address offset from the IP block base address
  291. + *
  292. + * Given a pointer @port to a struct uart_port record, read the
  293. + * contents of the IP block register located at offset @offs from the
  294. + * IP block base and return it. This function is intended for early
  295. + * console use.
  296. + *
  297. + * Context: Intended to be called only by the earlyconsole code or by
  298. + * __ssp_readl() or __ssp_writel() (in this driver)
  299. + *
  300. + * Returns: the register value read from the UART.
  301. + */
  302. +static u32 __ssp_early_readl(struct uart_port *port, u16 offs)
  303. +{
  304. + return readl_relaxed(port->membase + offs);
  305. +}
  306. +
  307. +/**
  308. + * __ssp_writel() - write to a SiFive serial port register
  309. + * @v: value to write to the register
  310. + * @offs: register address offset from the IP block base address
  311. + * @ssp: pointer to a struct sifive_serial_port record
  312. + *
  313. + * Write the value @v to the IP block register located at offset @offs from the
  314. + * IP block base, given a pointer @ssp to a struct sifive_serial_port record.
  315. + *
  316. + * Context: Any context.
  317. + */
  318. +static void __ssp_writel(u32 v, u16 offs, struct sifive_serial_port *ssp)
  319. +{
  320. + __ssp_early_writel(v, offs, &ssp->port);
  321. +}
  322. +
  323. +/**
  324. + * __ssp_readl() - read from a SiFive serial port register
  325. + * @ssp: pointer to a struct sifive_serial_port record
  326. + * @offs: register address offset from the IP block base address
  327. + *
  328. + * Read the contents of the IP block register located at offset @offs from the
  329. + * IP block base, given a pointer @ssp to a struct sifive_serial_port record.
  330. + *
  331. + * Context: Any context.
  332. + *
  333. + * Returns: the value of the UART register
  334. + */
  335. +static u32 __ssp_readl(struct sifive_serial_port *ssp, u16 offs)
  336. +{
  337. + return __ssp_early_readl(&ssp->port, offs);
  338. +}
  339. +
  340. +/**
  341. + * sifive_serial_is_txfifo_full() - is the TXFIFO full?
  342. + * @ssp: pointer to a struct sifive_serial_port
  343. + *
  344. + * Read the transmit FIFO "full" bit, returning a non-zero value if the
  345. + * TX FIFO is full, or zero if space remains. Intended to be used to prevent
  346. + * writes to the TX FIFO when it's full.
  347. + *
  348. + * Returns: SIFIVE_SERIAL_TXDATA_FULL_MASK (non-zero) if the transmit FIFO
  349. + * is full, or 0 if space remains.
  350. + */
  351. +static int sifive_serial_is_txfifo_full(struct sifive_serial_port *ssp)
  352. +{
  353. + return __ssp_readl(ssp, SIFIVE_SERIAL_TXDATA_OFFS) &
  354. + SIFIVE_SERIAL_TXDATA_FULL_MASK;
  355. +}
  356. +
  357. +/**
  358. + * __ssp_transmit_char() - enqueue a byte to transmit onto the TX FIFO
  359. + * @ssp: pointer to a struct sifive_serial_port
  360. + * @ch: character to transmit
  361. + *
  362. + * Enqueue a byte @ch onto the transmit FIFO, given a pointer @ssp to the
  363. + * struct sifive_serial_port * to transmit on. Caller should first check to
  364. + * ensure that the TXFIFO has space; see sifive_serial_is_txfifo_full().
  365. + *
  366. + * Context: Any context.
  367. + */
  368. +static void __ssp_transmit_char(struct sifive_serial_port *ssp, int ch)
  369. +{
  370. + __ssp_writel(ch, SIFIVE_SERIAL_TXDATA_OFFS, ssp);
  371. +}
  372. +
  373. +/**
  374. + * __ssp_transmit_chars() - enqueue multiple bytes onto the TX FIFO
  375. + * @ssp: pointer to a struct sifive_serial_port
  376. + *
  377. + * Transfer up to a TX FIFO size's worth of characters from the Linux serial
  378. + * transmit buffer to the SiFive UART TX FIFO.
  379. + *
  380. + * Context: Any context. Expects @ssp->port.lock to be held by caller.
  381. + */
  382. +static void __ssp_transmit_chars(struct sifive_serial_port *ssp)
  383. +{
  384. + struct circ_buf *xmit = &ssp->port.state->xmit;
  385. + int count;
  386. +
  387. + if (ssp->port.x_char) {
  388. + __ssp_transmit_char(ssp, ssp->port.x_char);
  389. + ssp->port.icount.tx++;
  390. + ssp->port.x_char = 0;
  391. + return;
  392. + }
  393. + if (uart_circ_empty(xmit) || uart_tx_stopped(&ssp->port)) {
  394. + sifive_serial_stop_tx(&ssp->port);
  395. + return;
  396. + }
  397. + count = SIFIVE_TX_FIFO_DEPTH;
  398. + do {
  399. + __ssp_transmit_char(ssp, xmit->buf[xmit->tail]);
  400. + xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
  401. + ssp->port.icount.tx++;
  402. + if (uart_circ_empty(xmit))
  403. + break;
  404. + } while (--count > 0);
  405. +
  406. + if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
  407. + uart_write_wakeup(&ssp->port);
  408. +
  409. + if (uart_circ_empty(xmit))
  410. + sifive_serial_stop_tx(&ssp->port);
  411. +}
  412. +
  413. +/**
  414. + * __ssp_enable_txwm() - enable transmit watermark interrupts
  415. + * @ssp: pointer to a struct sifive_serial_port
  416. + *
  417. + * Enable interrupt generation when the transmit FIFO watermark is reached
  418. + * on the SiFive UART referred to by @ssp.
  419. + */
  420. +static void __ssp_enable_txwm(struct sifive_serial_port *ssp)
  421. +{
  422. + if (ssp->ier & SIFIVE_SERIAL_IE_TXWM_MASK)
  423. + return;
  424. +
  425. + ssp->ier |= SIFIVE_SERIAL_IE_TXWM_MASK;
  426. + __ssp_writel(ssp->ier, SIFIVE_SERIAL_IE_OFFS, ssp);
  427. +}
  428. +
  429. +/**
  430. + * __ssp_enable_rxwm() - enable receive watermark interrupts
  431. + * @ssp: pointer to a struct sifive_serial_port
  432. + *
  433. + * Enable interrupt generation when the receive FIFO watermark is reached
  434. + * on the SiFive UART referred to by @ssp.
  435. + */
  436. +static void __ssp_enable_rxwm(struct sifive_serial_port *ssp)
  437. +{
  438. + if (ssp->ier & SIFIVE_SERIAL_IE_RXWM_MASK)
  439. + return;
  440. +
  441. + ssp->ier |= SIFIVE_SERIAL_IE_RXWM_MASK;
  442. + __ssp_writel(ssp->ier, SIFIVE_SERIAL_IE_OFFS, ssp);
  443. +}
  444. +
  445. +/**
  446. + * __ssp_disable_txwm() - disable transmit watermark interrupts
  447. + * @ssp: pointer to a struct sifive_serial_port
  448. + *
  449. + * Disable interrupt generation when the transmit FIFO watermark is reached
  450. + * on the UART referred to by @ssp.
  451. + */
  452. +static void __ssp_disable_txwm(struct sifive_serial_port *ssp)
  453. +{
  454. + if (!(ssp->ier & SIFIVE_SERIAL_IE_TXWM_MASK))
  455. + return;
  456. +
  457. + ssp->ier &= ~SIFIVE_SERIAL_IE_TXWM_MASK;
  458. + __ssp_writel(ssp->ier, SIFIVE_SERIAL_IE_OFFS, ssp);
  459. +}
  460. +
  461. +/**
  462. + * __ssp_disable_rxwm() - disable receive watermark interrupts
  463. + * @ssp: pointer to a struct sifive_serial_port
  464. + *
  465. + * Disable interrupt generation when the receive FIFO watermark is reached
  466. + * on the UART referred to by @ssp.
  467. + */
  468. +static void __ssp_disable_rxwm(struct sifive_serial_port *ssp)
  469. +{
  470. + if (!(ssp->ier & SIFIVE_SERIAL_IE_RXWM_MASK))
  471. + return;
  472. +
  473. + ssp->ier &= ~SIFIVE_SERIAL_IE_RXWM_MASK;
  474. + __ssp_writel(ssp->ier, SIFIVE_SERIAL_IE_OFFS, ssp);
  475. +}
  476. +
  477. +/**
  478. + * __ssp_receive_char() - receive a byte from the UART
  479. + * @ssp: pointer to a struct sifive_serial_port
  480. + * @is_empty: char pointer to return whether the RX FIFO is empty
  481. + *
  482. + * Try to read a byte from the SiFive UART RX FIFO, referenced by
  483. + * @ssp, and to return it. Also returns the RX FIFO empty bit in
  484. + * the char pointed to by @ch. The caller must pass the byte back to the
  485. + * Linux serial layer if needed.
  486. + *
  487. + * Returns: the byte read from the UART RX FIFO.
  488. + */
  489. +static char __ssp_receive_char(struct sifive_serial_port *ssp, char *is_empty)
  490. +{
  491. + u32 v;
  492. + u8 ch;
  493. +
  494. + v = __ssp_readl(ssp, SIFIVE_SERIAL_RXDATA_OFFS);
  495. +
  496. + if (!is_empty)
  497. + WARN_ON(1);
  498. + else
  499. + *is_empty = (v & SIFIVE_SERIAL_RXDATA_EMPTY_MASK) >>
  500. + SIFIVE_SERIAL_RXDATA_EMPTY_SHIFT;
  501. +
  502. + ch = (v & SIFIVE_SERIAL_RXDATA_DATA_MASK) >>
  503. + SIFIVE_SERIAL_RXDATA_DATA_SHIFT;
  504. +
  505. + return ch;
  506. +}
  507. +
  508. +/**
  509. + * __ssp_receive_chars() - receive multiple bytes from the UART
  510. + * @ssp: pointer to a struct sifive_serial_port
  511. + *
  512. + * Receive up to an RX FIFO's worth of bytes from the SiFive UART referred
  513. + * to by @ssp and pass them up to the Linux serial layer.
  514. + *
  515. + * Context: Expects ssp->port.lock to be held by caller.
  516. + */
  517. +static void __ssp_receive_chars(struct sifive_serial_port *ssp)
  518. +{
  519. + unsigned char ch;
  520. + char is_empty;
  521. + int c;
  522. +
  523. + for (c = SIFIVE_RX_FIFO_DEPTH; c > 0; --c) {
  524. + ch = __ssp_receive_char(ssp, &is_empty);
  525. + if (is_empty)
  526. + break;
  527. +
  528. + ssp->port.icount.rx++;
  529. + uart_insert_char(&ssp->port, 0, 0, ch, TTY_NORMAL);
  530. + }
  531. +
  532. + spin_unlock(&ssp->port.lock);
  533. + tty_flip_buffer_push(&ssp->port.state->port);
  534. + spin_lock(&ssp->port.lock);
  535. +}
  536. +
  537. +/**
  538. + * __ssp_update_div() - calculate the divisor setting by the line rate
  539. + * @ssp: pointer to a struct sifive_serial_port
  540. + *
  541. + * Calculate the appropriate value of the clock divisor for the UART
  542. + * and target line rate referred to by @ssp and write it into the
  543. + * hardware.
  544. + */
  545. +static void __ssp_update_div(struct sifive_serial_port *ssp)
  546. +{
  547. + u16 div;
  548. +
  549. + div = DIV_ROUND_UP(ssp->clkin_rate, ssp->baud_rate) - 1;
  550. +
  551. + __ssp_writel(div, SIFIVE_SERIAL_DIV_OFFS, ssp);
  552. +}
  553. +
  554. +/**
  555. + * __ssp_update_baud_rate() - set the UART "baud rate"
  556. + * @ssp: pointer to a struct sifive_serial_port
  557. + * @rate: new target bit rate
  558. + *
  559. + * Calculate the UART divisor value for the target bit rate @rate for the
  560. + * SiFive UART described by @ssp and program it into the UART. There may
  561. + * be some error between the target bit rate and the actual bit rate implemented
  562. + * by the UART due to clock ratio granularity.
  563. + */
  564. +static void __ssp_update_baud_rate(struct sifive_serial_port *ssp,
  565. + unsigned int rate)
  566. +{
  567. + if (ssp->baud_rate == rate)
  568. + return;
  569. +
  570. + ssp->baud_rate = rate;
  571. + __ssp_update_div(ssp);
  572. +}
  573. +
  574. +/**
  575. + * __ssp_set_stop_bits() - set the number of stop bits
  576. + * @ssp: pointer to a struct sifive_serial_port
  577. + * @nstop: 1 or 2 (stop bits)
  578. + *
  579. + * Program the SiFive UART referred to by @ssp to use @nstop stop bits.
  580. + */
  581. +static void __ssp_set_stop_bits(struct sifive_serial_port *ssp, char nstop)
  582. +{
  583. + u32 v;
  584. +
  585. + if (nstop < 1 || nstop > 2) {
  586. + WARN_ON(1);
  587. + return;
  588. + }
  589. +
  590. + v = __ssp_readl(ssp, SIFIVE_SERIAL_TXCTRL_OFFS);
  591. + v &= ~SIFIVE_SERIAL_TXCTRL_NSTOP_MASK;
  592. + v |= (nstop - 1) << SIFIVE_SERIAL_TXCTRL_NSTOP_SHIFT;
  593. + __ssp_writel(v, SIFIVE_SERIAL_TXCTRL_OFFS, ssp);
  594. +}
  595. +
  596. +/**
  597. + * __ssp_wait_for_xmitr() - wait for an empty slot on the TX FIFO
  598. + * @ssp: pointer to a struct sifive_serial_port
  599. + *
  600. + * Delay while the UART TX FIFO referred to by @ssp is marked as full.
  601. + *
  602. + * Context: Any context.
  603. + */
  604. +static void __maybe_unused __ssp_wait_for_xmitr(struct sifive_serial_port *ssp)
  605. +{
  606. + while (sifive_serial_is_txfifo_full(ssp))
  607. + udelay(1); /* XXX Could probably be more intelligent here */
  608. +}
  609. +
  610. +/*
  611. + * Linux serial API functions
  612. + */
  613. +
  614. +static void sifive_serial_stop_tx(struct uart_port *port)
  615. +{
  616. + struct sifive_serial_port *ssp = port_to_sifive_serial_port(port);
  617. +
  618. + __ssp_disable_txwm(ssp);
  619. +}
  620. +
  621. +static void sifive_serial_stop_rx(struct uart_port *port)
  622. +{
  623. + struct sifive_serial_port *ssp = port_to_sifive_serial_port(port);
  624. +
  625. + __ssp_disable_rxwm(ssp);
  626. +}
  627. +
  628. +static void sifive_serial_start_tx(struct uart_port *port)
  629. +{
  630. + struct sifive_serial_port *ssp = port_to_sifive_serial_port(port);
  631. +
  632. + __ssp_enable_txwm(ssp);
  633. +}
  634. +
  635. +static irqreturn_t sifive_serial_irq(int irq, void *dev_id)
  636. +{
  637. + struct sifive_serial_port *ssp = dev_id;
  638. + u32 ip;
  639. +
  640. + spin_lock(&ssp->port.lock);
  641. +
  642. + ip = __ssp_readl(ssp, SIFIVE_SERIAL_IP_OFFS);
  643. + if (!ip) {
  644. + spin_unlock(&ssp->port.lock);
  645. + return IRQ_NONE;
  646. + }
  647. +
  648. + if (ip & SIFIVE_SERIAL_IP_RXWM_MASK)
  649. + __ssp_receive_chars(ssp);
  650. + if (ip & SIFIVE_SERIAL_IP_TXWM_MASK)
  651. + __ssp_transmit_chars(ssp);
  652. +
  653. + spin_unlock(&ssp->port.lock);
  654. +
  655. + return IRQ_HANDLED;
  656. +}
  657. +
  658. +static unsigned int sifive_serial_tx_empty(struct uart_port *port)
  659. +{
  660. + return TIOCSER_TEMT;
  661. +}
  662. +
  663. +static unsigned int sifive_serial_get_mctrl(struct uart_port *port)
  664. +{
  665. + return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR;
  666. +}
  667. +
  668. +static void sifive_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
  669. +{
  670. + /* IP block does not support these signals */
  671. +}
  672. +
  673. +static void sifive_serial_break_ctl(struct uart_port *port, int break_state)
  674. +{
  675. + /* IP block does not support sending a break */
  676. +}
  677. +
  678. +static int sifive_serial_startup(struct uart_port *port)
  679. +{
  680. + struct sifive_serial_port *ssp = port_to_sifive_serial_port(port);
  681. +
  682. + __ssp_enable_rxwm(ssp);
  683. +
  684. + return 0;
  685. +}
  686. +
  687. +static void sifive_serial_shutdown(struct uart_port *port)
  688. +{
  689. + struct sifive_serial_port *ssp = port_to_sifive_serial_port(port);
  690. +
  691. + __ssp_disable_rxwm(ssp);
  692. + __ssp_disable_txwm(ssp);
  693. +}
  694. +
  695. +/**
  696. + * sifive_serial_clk_notifier() - clock post-rate-change notifier
  697. + * @nb: pointer to the struct notifier_block, from the notifier code
  698. + * @event: event mask from the notifier code
  699. + * @data: pointer to the struct clk_notifier_data from the notifier code
  700. + *
  701. + * On the V0 SoC, the UART IP block is derived from the CPU clock source
  702. + * after a synchronous divide-by-two divider, so any CPU clock rate change
  703. + * requires the UART baud rate to be updated. This presumably could corrupt any
  704. + * serial word currently being transmitted or received. It would probably
  705. + * be better to stop receives and transmits, then complete the baud rate
  706. + * change, then re-enable them.
  707. + */
  708. +static int sifive_serial_clk_notifier(struct notifier_block *nb,
  709. + unsigned long event, void *data)
  710. +{
  711. + struct clk_notifier_data *cnd = data;
  712. + struct sifive_serial_port *ssp = notifier_to_sifive_serial_port(nb);
  713. +
  714. + if (event == POST_RATE_CHANGE && ssp->clkin_rate != cnd->new_rate) {
  715. + ssp->clkin_rate = cnd->new_rate;
  716. + __ssp_update_div(ssp);
  717. + }
  718. +
  719. + return NOTIFY_OK;
  720. +}
  721. +
  722. +static void sifive_serial_set_termios(struct uart_port *port,
  723. + struct ktermios *termios,
  724. + struct ktermios *old)
  725. +{
  726. + struct sifive_serial_port *ssp = port_to_sifive_serial_port(port);
  727. + unsigned long flags;
  728. + u32 v, old_v;
  729. + int rate;
  730. + char nstop;
  731. +
  732. + if ((termios->c_cflag & CSIZE) != CS8) {
  733. + dev_err(ssp->port.dev, "only 8-bit words supported\n");
  734. + return;
  735. + }
  736. +
  737. + /* Set number of stop bits */
  738. + nstop = (termios->c_cflag & CSTOPB) ? 2 : 1;
  739. + __ssp_set_stop_bits(ssp, nstop);
  740. +
  741. + /* Set line rate */
  742. + rate = uart_get_baud_rate(port, termios, old, 0, ssp->clkin_rate / 16);
  743. + __ssp_update_baud_rate(ssp, rate);
  744. +
  745. + spin_lock_irqsave(&ssp->port.lock, flags);
  746. +
  747. + /*
  748. + * Update the per-port timeout.
  749. + */
  750. + uart_update_timeout(port, termios->c_cflag, rate);
  751. +
  752. + ssp->port.read_status_mask = 0;
  753. + if (termios->c_iflag & INPCK) {
  754. + dev_err(ssp->port.dev, "INPCK flag not supported\n");
  755. + goto ssst_out;
  756. + }
  757. + if (termios->c_iflag & (BRKINT | PARMRK)) {
  758. + dev_err(ssp->port.dev, "BRKINT/PARMRK flag not supported\n");
  759. + goto ssst_out;
  760. + }
  761. +
  762. + /*
  763. + * ignore all characters if CREAD is not set
  764. + */
  765. + v = __ssp_readl(ssp, SIFIVE_SERIAL_RXCTRL_OFFS);
  766. + old_v = v;
  767. + if ((termios->c_cflag & CREAD) == 0)
  768. + v &= SIFIVE_SERIAL_RXCTRL_RXEN_MASK;
  769. + else
  770. + v |= SIFIVE_SERIAL_RXCTRL_RXEN_MASK;
  771. + if (v != old_v)
  772. + __ssp_writel(v, SIFIVE_SERIAL_RXCTRL_OFFS, ssp);
  773. +
  774. +ssst_out:
  775. + spin_unlock_irqrestore(&ssp->port.lock, flags);
  776. +}
  777. +
  778. +static void sifive_serial_release_port(struct uart_port *port)
  779. +{
  780. +}
  781. +
  782. +static int sifive_serial_request_port(struct uart_port *port)
  783. +{
  784. + return 0;
  785. +}
  786. +
  787. +static void sifive_serial_config_port(struct uart_port *port, int flags)
  788. +{
  789. + struct sifive_serial_port *ssp = port_to_sifive_serial_port(port);
  790. +
  791. + ssp->port.type = PORT_SIFIVE_V0;
  792. +}
  793. +
  794. +static int sifive_serial_verify_port(struct uart_port *port,
  795. + struct serial_struct *ser)
  796. +{
  797. + return -EINVAL;
  798. +}
  799. +
  800. +static const char *sifive_serial_type(struct uart_port *port)
  801. +{
  802. + return port->type == PORT_SIFIVE_V0 ? "SiFive UART v0" : NULL;
  803. +}
  804. +
  805. +/*
  806. + * Early console support
  807. + */
  808. +
  809. +#ifdef CONFIG_SERIAL_EARLYCON
  810. +static void early_sifive_serial_putc(struct uart_port *port, int c)
  811. +{
  812. + while (__ssp_early_readl(port, SIFIVE_SERIAL_TXDATA_OFFS) &
  813. + SIFIVE_SERIAL_TXDATA_FULL_MASK)
  814. + cpu_relax();
  815. +
  816. + __ssp_early_writel(c, SIFIVE_SERIAL_TXDATA_OFFS, port);
  817. +}
  818. +
  819. +static void early_sifive_serial_write(struct console *con, const char *s,
  820. + unsigned int n)
  821. +{
  822. + struct earlycon_device *dev = con->data;
  823. + struct uart_port *port = &dev->port;
  824. +
  825. + uart_console_write(port, s, n, early_sifive_serial_putc);
  826. +}
  827. +
  828. +static int __init early_sifive_serial_setup(struct earlycon_device *dev,
  829. + const char *options)
  830. +{
  831. + struct uart_port *port = &dev->port;
  832. +
  833. + if (!port->membase)
  834. + return -ENODEV;
  835. +
  836. + dev->con->write = early_sifive_serial_write;
  837. +
  838. + return 0;
  839. +}
  840. +
  841. +OF_EARLYCON_DECLARE(sifive, "sifive,uart0", early_sifive_serial_setup);
  842. +OF_EARLYCON_DECLARE(sifive, "sifive,fu540-c000-uart0",
  843. + early_sifive_serial_setup);
  844. +#endif /* CONFIG_SERIAL_EARLYCON */
  845. +
  846. +/*
  847. + * Linux console interface
  848. + */
  849. +
  850. +#ifdef CONFIG_SERIAL_SIFIVE_CONSOLE
  851. +
  852. +static struct sifive_serial_port *sifive_serial_console_ports[SIFIVE_SERIAL_MAX_PORTS];
  853. +
  854. +static void sifive_serial_console_putchar(struct uart_port *port, int ch)
  855. +{
  856. + struct sifive_serial_port *ssp = port_to_sifive_serial_port(port);
  857. +
  858. + __ssp_wait_for_xmitr(ssp);
  859. + __ssp_transmit_char(ssp, ch);
  860. +}
  861. +
  862. +static void sifive_serial_console_write(struct console *co, const char *s,
  863. + unsigned int count)
  864. +{
  865. + struct sifive_serial_port *ssp = sifive_serial_console_ports[co->index];
  866. + unsigned long flags;
  867. + unsigned int ier;
  868. + int locked = 1;
  869. +
  870. + if (!ssp)
  871. + return;
  872. +
  873. + local_irq_save(flags);
  874. + if (ssp->port.sysrq)
  875. + locked = 0;
  876. + else if (oops_in_progress)
  877. + locked = spin_trylock(&ssp->port.lock);
  878. + else
  879. + spin_lock(&ssp->port.lock);
  880. +
  881. + ier = __ssp_readl(ssp, SIFIVE_SERIAL_IE_OFFS);
  882. + __ssp_writel(0, SIFIVE_SERIAL_IE_OFFS, ssp);
  883. +
  884. + uart_console_write(&ssp->port, s, count, sifive_serial_console_putchar);
  885. +
  886. + __ssp_writel(ier, SIFIVE_SERIAL_IE_OFFS, ssp);
  887. +
  888. + if (locked)
  889. + spin_unlock(&ssp->port.lock);
  890. + local_irq_restore(flags);
  891. +}
  892. +
  893. +static int __init sifive_serial_console_setup(struct console *co, char *options)
  894. +{
  895. + struct sifive_serial_port *ssp;
  896. + int baud = SIFIVE_DEFAULT_BAUD_RATE;
  897. + int bits = 8;
  898. + int parity = 'n';
  899. + int flow = 'n';
  900. +
  901. + if (co->index < 0 || co->index >= SIFIVE_SERIAL_MAX_PORTS)
  902. + return -ENODEV;
  903. +
  904. + ssp = sifive_serial_console_ports[co->index];
  905. + if (!ssp)
  906. + return -ENODEV;
  907. +
  908. + if (options)
  909. + uart_parse_options(options, &baud, &parity, &bits, &flow);
  910. +
  911. + return uart_set_options(&ssp->port, co, baud, parity, bits, flow);
  912. +}
  913. +
  914. +static struct uart_driver sifive_serial_uart_driver;
  915. +
  916. +static struct console sifive_serial_console = {
  917. + .name = SIFIVE_TTY_PREFIX,
  918. + .write = sifive_serial_console_write,
  919. + .device = uart_console_device,
  920. + .setup = sifive_serial_console_setup,
  921. + .flags = CON_PRINTBUFFER,
  922. + .index = -1,
  923. + .data = &sifive_serial_uart_driver,
  924. +};
  925. +
  926. +static int __init sifive_console_init(void)
  927. +{
  928. + register_console(&sifive_serial_console);
  929. + return 0;
  930. +}
  931. +
  932. +console_initcall(sifive_console_init);
  933. +
  934. +static void __ssp_add_console_port(struct sifive_serial_port *ssp)
  935. +{
  936. + sifive_serial_console_ports[ssp->port.line] = ssp;
  937. +}
  938. +
  939. +static void __ssp_remove_console_port(struct sifive_serial_port *ssp)
  940. +{
  941. + sifive_serial_console_ports[ssp->port.line] = 0;
  942. +}
  943. +
  944. +#define SIFIVE_SERIAL_CONSOLE (&sifive_serial_console)
  945. +
  946. +#else
  947. +
  948. +#define SIFIVE_SERIAL_CONSOLE NULL
  949. +
  950. +static inline void __ssp_add_console_port(struct sifive_serial_port *ssp)
  951. +{}
  952. +static void __ssp_remove_console_port(struct sifive_serial_port *ssp)
  953. +{}
  954. +
  955. +#endif
  956. +
  957. +static const struct uart_ops sifive_serial_uops = {
  958. + .tx_empty = sifive_serial_tx_empty,
  959. + .set_mctrl = sifive_serial_set_mctrl,
  960. + .get_mctrl = sifive_serial_get_mctrl,
  961. + .stop_tx = sifive_serial_stop_tx,
  962. + .start_tx = sifive_serial_start_tx,
  963. + .stop_rx = sifive_serial_stop_rx,
  964. + .break_ctl = sifive_serial_break_ctl,
  965. + .startup = sifive_serial_startup,
  966. + .shutdown = sifive_serial_shutdown,
  967. + .set_termios = sifive_serial_set_termios,
  968. + .type = sifive_serial_type,
  969. + .release_port = sifive_serial_release_port,
  970. + .request_port = sifive_serial_request_port,
  971. + .config_port = sifive_serial_config_port,
  972. + .verify_port = sifive_serial_verify_port,
  973. +};
  974. +
  975. +static struct uart_driver sifive_serial_uart_driver = {
  976. + .owner = THIS_MODULE,
  977. + .driver_name = SIFIVE_SERIAL_NAME,
  978. + .dev_name = SIFIVE_TTY_PREFIX,
  979. + .nr = SIFIVE_SERIAL_MAX_PORTS,
  980. + .cons = SIFIVE_SERIAL_CONSOLE,
  981. +};
  982. +
  983. +static int sifive_serial_probe(struct platform_device *pdev)
  984. +{
  985. + struct sifive_serial_port *ssp;
  986. + struct resource *mem;
  987. + struct clk *clk;
  988. + void __iomem *base;
  989. + int irq, id, r;
  990. +
  991. + irq = platform_get_irq(pdev, 0);
  992. + if (irq < 0) {
  993. + dev_err(&pdev->dev, "could not acquire interrupt\n");
  994. + return -EPROBE_DEFER;
  995. + }
  996. +
  997. + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  998. + base = devm_ioremap_resource(&pdev->dev, mem);
  999. + if (IS_ERR(base)) {
  1000. + dev_err(&pdev->dev, "could not acquire device memory\n");
  1001. + return PTR_ERR(base);
  1002. + }
  1003. +
  1004. + clk = devm_clk_get(&pdev->dev, NULL);
  1005. + if (IS_ERR(clk)) {
  1006. + dev_err(&pdev->dev, "unable to find controller clock\n");
  1007. + return PTR_ERR(clk);
  1008. + }
  1009. +
  1010. + id = of_alias_get_id(pdev->dev.of_node, "serial");
  1011. + if (id < 0) {
  1012. + dev_err(&pdev->dev, "missing aliases entry\n");
  1013. + return id;
  1014. + }
  1015. +
  1016. +#ifdef CONFIG_SERIAL_SIFIVE_CONSOLE
  1017. + if (id > SIFIVE_SERIAL_MAX_PORTS) {
  1018. + dev_err(&pdev->dev, "too many UARTs (%d)\n", id);
  1019. + return -EINVAL;
  1020. + }
  1021. +#endif
  1022. +
  1023. + ssp = devm_kzalloc(&pdev->dev, sizeof(*ssp), GFP_KERNEL);
  1024. + if (!ssp)
  1025. + return -ENOMEM;
  1026. +
  1027. + ssp->port.dev = &pdev->dev;
  1028. + ssp->port.type = PORT_SIFIVE_V0;
  1029. + ssp->port.iotype = UPIO_MEM;
  1030. + ssp->port.irq = irq;
  1031. + ssp->port.fifosize = SIFIVE_TX_FIFO_DEPTH;
  1032. + ssp->port.ops = &sifive_serial_uops;
  1033. + ssp->port.line = id;
  1034. + ssp->port.mapbase = mem->start;
  1035. + ssp->port.membase = base;
  1036. + ssp->dev = &pdev->dev;
  1037. + ssp->clk = clk;
  1038. + ssp->clk_notifier.notifier_call = sifive_serial_clk_notifier;
  1039. +
  1040. + r = clk_notifier_register(ssp->clk, &ssp->clk_notifier);
  1041. + if (r) {
  1042. + dev_err(&pdev->dev, "could not register clock notifier: %d\n",
  1043. + r);
  1044. + goto probe_out1;
  1045. + }
  1046. +
  1047. + /* Set up clock divider */
  1048. + ssp->clkin_rate = clk_get_rate(ssp->clk);
  1049. + ssp->baud_rate = SIFIVE_DEFAULT_BAUD_RATE;
  1050. + __ssp_update_div(ssp);
  1051. +
  1052. + platform_set_drvdata(pdev, ssp);
  1053. +
  1054. + /* Enable transmits and set the watermark level to 1 */
  1055. + __ssp_writel((1 << SIFIVE_SERIAL_TXCTRL_TXCNT_SHIFT) |
  1056. + SIFIVE_SERIAL_TXCTRL_TXEN_MASK,
  1057. + SIFIVE_SERIAL_TXCTRL_OFFS, ssp);
  1058. +
  1059. + /* Enable receives and set the watermark level to 0 */
  1060. + __ssp_writel((0 << SIFIVE_SERIAL_RXCTRL_RXCNT_SHIFT) |
  1061. + SIFIVE_SERIAL_RXCTRL_RXEN_MASK,
  1062. + SIFIVE_SERIAL_RXCTRL_OFFS, ssp);
  1063. +
  1064. + r = request_irq(ssp->port.irq, sifive_serial_irq, ssp->port.irqflags,
  1065. + dev_name(&pdev->dev), ssp);
  1066. + if (r) {
  1067. + dev_err(&pdev->dev, "could not attach interrupt: %d\n", r);
  1068. + goto probe_out2;
  1069. + }
  1070. +
  1071. + __ssp_add_console_port(ssp);
  1072. +
  1073. + r = uart_add_one_port(&sifive_serial_uart_driver, &ssp->port);
  1074. + if (r != 0) {
  1075. + dev_err(&pdev->dev, "could not add uart: %d\n", r);
  1076. + goto probe_out3;
  1077. + }
  1078. +
  1079. + return 0;
  1080. +
  1081. +probe_out3:
  1082. + __ssp_remove_console_port(ssp);
  1083. + free_irq(ssp->port.irq, ssp);
  1084. +probe_out2:
  1085. + clk_notifier_unregister(ssp->clk, &ssp->clk_notifier);
  1086. +probe_out1:
  1087. + return r;
  1088. +}
  1089. +
  1090. +static int sifive_serial_remove(struct platform_device *dev)
  1091. +{
  1092. + struct sifive_serial_port *ssp = platform_get_drvdata(dev);
  1093. +
  1094. + __ssp_remove_console_port(ssp);
  1095. + uart_remove_one_port(&sifive_serial_uart_driver, &ssp->port);
  1096. + free_irq(ssp->port.irq, ssp);
  1097. + clk_notifier_unregister(ssp->clk, &ssp->clk_notifier);
  1098. +
  1099. + return 0;
  1100. +}
  1101. +
  1102. +static const struct of_device_id sifive_serial_of_match[] = {
  1103. + { .compatible = "sifive,fu540-c000-uart0" },
  1104. + { .compatible = "sifive,uart0" },
  1105. + {},
  1106. +};
  1107. +MODULE_DEVICE_TABLE(of, sifive_serial_of_match);
  1108. +
  1109. +static struct platform_driver sifive_serial_platform_driver = {
  1110. + .probe = sifive_serial_probe,
  1111. + .remove = sifive_serial_remove,
  1112. + .driver = {
  1113. + .name = SIFIVE_SERIAL_NAME,
  1114. + .of_match_table = of_match_ptr(sifive_serial_of_match),
  1115. + },
  1116. +};
  1117. +
  1118. +static int __init sifive_serial_init(void)
  1119. +{
  1120. + int r;
  1121. +
  1122. + r = uart_register_driver(&sifive_serial_uart_driver);
  1123. + if (r)
  1124. + goto init_out1;
  1125. +
  1126. + r = platform_driver_register(&sifive_serial_platform_driver);
  1127. + if (r)
  1128. + goto init_out2;
  1129. +
  1130. + return 0;
  1131. +
  1132. +init_out2:
  1133. + uart_unregister_driver(&sifive_serial_uart_driver);
  1134. +init_out1:
  1135. + return r;
  1136. +}
  1137. +
  1138. +static void __exit sifive_serial_exit(void)
  1139. +{
  1140. + platform_driver_unregister(&sifive_serial_platform_driver);
  1141. + uart_unregister_driver(&sifive_serial_uart_driver);
  1142. +}
  1143. +
  1144. +module_init(sifive_serial_init);
  1145. +module_exit(sifive_serial_exit);
  1146. +
  1147. +MODULE_DESCRIPTION("SiFive UART serial driver");
  1148. +MODULE_LICENSE("GPL");
  1149. +MODULE_AUTHOR("Paul Walmsley <paul@pwsan.com>");
  1150. diff --git a/include/uapi/linux/serial_core.h b/include/uapi/linux/serial_core.h
  1151. index 6009ee2c2e99..d3bb0d447c0b 100644
  1152. --- a/include/uapi/linux/serial_core.h
  1153. +++ b/include/uapi/linux/serial_core.h
  1154. @@ -287,4 +287,7 @@
  1155. /* RDA UART */
  1156. #define PORT_RDA 118
  1157. +/* SiFive UART */
  1158. +#define PORT_SIFIVE_V0 118
  1159. +
  1160. #endif /* _UAPILINUX_SERIAL_CORE_H */
  1161. --
  1162. 2.21.0