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- From b1103ea299e49c03555f12f080a1607969fd7e66 Mon Sep 17 00:00:00 2001
- From: Atish Patra <atish.patra@wdc.com>
- Date: Fri, 21 Jun 2019 12:36:21 -0700
- Subject: [PATCH 2/4] Microsemi PCIe expansion board DT entry.
- Signed-off-by: Atish Patra <atish.patra@wdc.com>
- Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
- Upstream-Status: Inappropriate [enable feature]
- ---
- .../sifive/hifive-unleashed-a00-microsemi.dts | 28 +++++++++++++++++++
- 1 file changed, 28 insertions(+)
- create mode 100644 arch/riscv/boot/dts/sifive/hifive-unleashed-a00-microsemi.dts
- diff --git a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00-microsemi.dts b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00-microsemi.dts
- new file mode 100644
- index 000000000000..4d25606f4e0c
- --- /dev/null
- +++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00-microsemi.dts
- @@ -0,0 +1,28 @@
- +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
- +
- +#include "hifive-unleashed-a00.dts"
- +
- +/ {
- + soc {
- + pcie: pcie@2030000000 {
- + #address-cells = <0x3>;
- + #interrupt-cells = <0x1>;
- + #size-cells = <0x2>;
- + compatible = "microsemi,ms-pf-axi-pcie-host";
- + device_type = "pci";
- + bus-range = <0x01 0x7f>;
- + interrupt-map = <0 0 0 1 &ms_pcie_intc 0 0 0 0 2 &ms_pcie_intc 1 0 0 0 3 &ms_pcie_intc 2 0 0 0 4 &ms_pcie_intc 3>;
- + interrupt-map-mask = <0 0 0 7>;
- + interrupt-parent = <&plic0>;
- + interrupts = <32>;
- + ranges = <0x3000000 0x0 0x40000000 0x0 0x40000000 0x0 0x20000000>;
- + reg = <0x20 0x30000000 0x0 0x4000000 0x20 0x0 0x0 0x100000>;
- + reg-names = "control", "apb";
- + ms_pcie_intc: interrupt-controller {
- + #address-cells = <0>;
- + #interrupt-cells = <1>;
- + interrupt-controller;
- + };
- + };
- + };
- +};
- --
- 2.22.0
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