0001-macb-bindings-doc-add-sifive-fu540-c000-binding.patch 1.7 KB

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  1. From a4a5f99e31e85a6f159c62f224e826ed38f027e9 Mon Sep 17 00:00:00 2001
  2. From: Yash Shah <yash.shah@sifive.com>
  3. Date: Tue, 18 Jun 2019 13:26:07 +0530
  4. Subject: [PATCH 1/6] macb: bindings doc: add sifive fu540-c000 binding
  5. Add the compatibility string documentation for SiFive FU540-C0000
  6. interface.
  7. On the FU540, this driver also needs to read and write registers in a
  8. management IP block that monitors or drives boundary signals for the
  9. GEMGXL IP block that are not directly mapped to GEMGXL registers.
  10. Therefore, add additional range to "reg" property for SiFive GEMGXL
  11. management IP registers.
  12. Signed-off-by: Yash Shah <yash.shah@sifive.com>
  13. Reviewed-by: Paul Walmsley <paul.walmsley@sifive.com>
  14. Upstream-Status: Accepted [5.3]
  15. ---
  16. Documentation/devicetree/bindings/net/macb.txt | 3 +++
  17. 1 file changed, 3 insertions(+)
  18. diff --git a/Documentation/devicetree/bindings/net/macb.txt b/Documentation/devicetree/bindings/net/macb.txt
  19. index 9c5e94482b5f..63c73fafe26d 100644
  20. --- a/Documentation/devicetree/bindings/net/macb.txt
  21. +++ b/Documentation/devicetree/bindings/net/macb.txt
  22. @@ -15,8 +15,11 @@ Required properties:
  23. Use "atmel,sama5d4-gem" for the GEM IP (10/100) available on Atmel sama5d4 SoCs.
  24. Use "cdns,zynq-gem" Xilinx Zynq-7xxx SoC.
  25. Use "cdns,zynqmp-gem" for Zynq Ultrascale+ MPSoC.
  26. + Use "sifive,fu540-macb" for SiFive FU540-C000 SoC.
  27. Or the generic form: "cdns,emac".
  28. - reg: Address and length of the register set for the device
  29. + For "sifive,fu540-macb", second range is required to specify the
  30. + address and length of the registers for GEMGXL Management block.
  31. - interrupts: Should contain macb interrupt
  32. - phy-mode: See ethernet.txt file in the same directory.
  33. - clock-names: Tuple listing input clock names.
  34. --
  35. 2.22.0