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- From a4a5f99e31e85a6f159c62f224e826ed38f027e9 Mon Sep 17 00:00:00 2001
- From: Yash Shah <yash.shah@sifive.com>
- Date: Tue, 18 Jun 2019 13:26:07 +0530
- Subject: [PATCH 1/6] macb: bindings doc: add sifive fu540-c000 binding
- Add the compatibility string documentation for SiFive FU540-C0000
- interface.
- On the FU540, this driver also needs to read and write registers in a
- management IP block that monitors or drives boundary signals for the
- GEMGXL IP block that are not directly mapped to GEMGXL registers.
- Therefore, add additional range to "reg" property for SiFive GEMGXL
- management IP registers.
- Signed-off-by: Yash Shah <yash.shah@sifive.com>
- Reviewed-by: Paul Walmsley <paul.walmsley@sifive.com>
- Upstream-Status: Accepted [5.3]
- ---
- Documentation/devicetree/bindings/net/macb.txt | 3 +++
- 1 file changed, 3 insertions(+)
- diff --git a/Documentation/devicetree/bindings/net/macb.txt b/Documentation/devicetree/bindings/net/macb.txt
- index 9c5e94482b5f..63c73fafe26d 100644
- --- a/Documentation/devicetree/bindings/net/macb.txt
- +++ b/Documentation/devicetree/bindings/net/macb.txt
- @@ -15,8 +15,11 @@ Required properties:
- Use "atmel,sama5d4-gem" for the GEM IP (10/100) available on Atmel sama5d4 SoCs.
- Use "cdns,zynq-gem" Xilinx Zynq-7xxx SoC.
- Use "cdns,zynqmp-gem" for Zynq Ultrascale+ MPSoC.
- + Use "sifive,fu540-macb" for SiFive FU540-C000 SoC.
- Or the generic form: "cdns,emac".
- - reg: Address and length of the register set for the device
- + For "sifive,fu540-macb", second range is required to specify the
- + address and length of the registers for GEMGXL Management block.
- - interrupts: Should contain macb interrupt
- - phy-mode: See ethernet.txt file in the same directory.
- - clock-names: Tuple listing input clock names.
- --
- 2.22.0
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