0008-clk-sifive-Factor-out-PLL-library-as-separate-module.patch 4.8 KB

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  1. From f1ec984fea3ce53fc0c6e9a98eb8ba3fa9d3b3ac Mon Sep 17 00:00:00 2001
  2. From: Anup Patel <anup.patel@wdc.com>
  3. Date: Tue, 18 Jun 2019 11:42:49 +0530
  4. Subject: [PATCH 08/21] clk: sifive: Factor-out PLL library as separate module
  5. To match SiFive clock driver with latest Linux, we factor-out PLL
  6. library as separate module under drivers/clk/analogbits.
  7. Signed-off-by: Anup Patel <anup.patel@wdc.com>
  8. Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
  9. Upstream-Status: Submitted
  10. ---
  11. drivers/clk/Kconfig | 1 +
  12. drivers/clk/Makefile | 1 +
  13. drivers/clk/analogbits/Kconfig | 4 ++++
  14. drivers/clk/analogbits/Makefile | 3 +++
  15. drivers/clk/{sifive => analogbits}/wrpll-cln28hpc.c | 3 +--
  16. drivers/clk/sifive/Kconfig | 3 ---
  17. drivers/clk/sifive/Makefile | 2 --
  18. drivers/clk/sifive/fu540-prci.c | 3 +--
  19. .../sifive => include/linux/clk}/analogbits-wrpll-cln28hpc.h | 0
  20. 9 files changed, 11 insertions(+), 9 deletions(-)
  21. create mode 100644 drivers/clk/analogbits/Kconfig
  22. create mode 100644 drivers/clk/analogbits/Makefile
  23. rename drivers/clk/{sifive => analogbits}/wrpll-cln28hpc.c (99%)
  24. rename {drivers/clk/sifive => include/linux/clk}/analogbits-wrpll-cln28hpc.h (100%)
  25. diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
  26. index 96969b9e30..7b81eacf50 100644
  27. --- a/drivers/clk/Kconfig
  28. +++ b/drivers/clk/Kconfig
  29. @@ -98,6 +98,7 @@ config CLK_STM32MP1
  30. Enable the STM32 clock (RCC) driver. Enable support for
  31. manipulating STM32MP1's on-SoC clocks.
  32. +source "drivers/clk/analogbits/Kconfig"
  33. source "drivers/clk/at91/Kconfig"
  34. source "drivers/clk/exynos/Kconfig"
  35. source "drivers/clk/imx/Kconfig"
  36. diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
  37. index 719b9b8e02..f0ced49e5a 100644
  38. --- a/drivers/clk/Makefile
  39. +++ b/drivers/clk/Makefile
  40. @@ -8,6 +8,7 @@ obj-$(CONFIG_$(SPL_TPL_)CLK) += clk-uclass.o
  41. obj-$(CONFIG_$(SPL_TPL_)CLK) += clk_fixed_rate.o
  42. obj-$(CONFIG_$(SPL_TPL_)CLK) += clk_fixed_factor.o
  43. +obj-y += analogbits/
  44. obj-y += imx/
  45. obj-y += tegra/
  46. obj-$(CONFIG_ARCH_ASPEED) += aspeed/
  47. diff --git a/drivers/clk/analogbits/Kconfig b/drivers/clk/analogbits/Kconfig
  48. new file mode 100644
  49. index 0000000000..1d25e6f124
  50. --- /dev/null
  51. +++ b/drivers/clk/analogbits/Kconfig
  52. @@ -0,0 +1,4 @@
  53. +# SPDX-License-Identifier: GPL-2.0
  54. +
  55. +config CLK_ANALOGBITS_WRPLL_CLN28HPC
  56. + bool
  57. diff --git a/drivers/clk/analogbits/Makefile b/drivers/clk/analogbits/Makefile
  58. new file mode 100644
  59. index 0000000000..ec1bb4092b
  60. --- /dev/null
  61. +++ b/drivers/clk/analogbits/Makefile
  62. @@ -0,0 +1,3 @@
  63. +# SPDX-License-Identifier: GPL-2.0+
  64. +
  65. +obj-$(CONFIG_CLK_ANALOGBITS_WRPLL_CLN28HPC) += wrpll-cln28hpc.o
  66. diff --git a/drivers/clk/sifive/wrpll-cln28hpc.c b/drivers/clk/analogbits/wrpll-cln28hpc.c
  67. similarity index 99%
  68. rename from drivers/clk/sifive/wrpll-cln28hpc.c
  69. rename to drivers/clk/analogbits/wrpll-cln28hpc.c
  70. index d377849693..68eb1148b9 100644
  71. --- a/drivers/clk/sifive/wrpll-cln28hpc.c
  72. +++ b/drivers/clk/analogbits/wrpll-cln28hpc.c
  73. @@ -35,8 +35,7 @@
  74. #include <linux/err.h>
  75. #include <linux/log2.h>
  76. #include <linux/math64.h>
  77. -
  78. -#include "analogbits-wrpll-cln28hpc.h"
  79. +#include <linux/clk/analogbits-wrpll-cln28hpc.h>
  80. /* MIN_INPUT_FREQ: minimum input clock frequency, in Hz (Fref_min) */
  81. #define MIN_INPUT_FREQ 7000000
  82. diff --git a/drivers/clk/sifive/Kconfig b/drivers/clk/sifive/Kconfig
  83. index 644881b948..d90be1943f 100644
  84. --- a/drivers/clk/sifive/Kconfig
  85. +++ b/drivers/clk/sifive/Kconfig
  86. @@ -1,8 +1,5 @@
  87. # SPDX-License-Identifier: GPL-2.0
  88. -config CLK_ANALOGBITS_WRPLL_CLN28HPC
  89. - bool
  90. -
  91. config CLK_SIFIVE
  92. bool "SiFive SoC driver support"
  93. depends on CLK
  94. diff --git a/drivers/clk/sifive/Makefile b/drivers/clk/sifive/Makefile
  95. index f8263e79b7..0813360ca7 100644
  96. --- a/drivers/clk/sifive/Makefile
  97. +++ b/drivers/clk/sifive/Makefile
  98. @@ -1,7 +1,5 @@
  99. # SPDX-License-Identifier: GPL-2.0+
  100. -obj-$(CONFIG_CLK_ANALOGBITS_WRPLL_CLN28HPC) += wrpll-cln28hpc.o
  101. -
  102. obj-$(CONFIG_CLK_SIFIVE_FU540_PRCI) += fu540-prci.o
  103. obj-$(CONFIG_CLK_SIFIVE_GEMGXL_MGMT) += gemgxl-mgmt.o
  104. diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c
  105. index 2d47ebc6b1..56084db2e6 100644
  106. --- a/drivers/clk/sifive/fu540-prci.c
  107. +++ b/drivers/clk/sifive/fu540-prci.c
  108. @@ -37,10 +37,9 @@
  109. #include <errno.h>
  110. #include <linux/math64.h>
  111. +#include <linux/clk/analogbits-wrpll-cln28hpc.h>
  112. #include <dt-bindings/clk/sifive-fu540-prci.h>
  113. -#include "analogbits-wrpll-cln28hpc.h"
  114. -
  115. /*
  116. * EXPECTED_CLK_PARENT_COUNT: how many parent clocks this driver expects:
  117. * hfclk and rtcclk
  118. diff --git a/drivers/clk/sifive/analogbits-wrpll-cln28hpc.h b/include/linux/clk/analogbits-wrpll-cln28hpc.h
  119. similarity index 100%
  120. rename from drivers/clk/sifive/analogbits-wrpll-cln28hpc.h
  121. rename to include/linux/clk/analogbits-wrpll-cln28hpc.h
  122. --
  123. 2.22.0