From aebd1722fcf2f9e7071ceeca5995a308ca099959 Mon Sep 17 00:00:00 2001
From: "Wesley W. Terpstra" <wesley@sifive.com>
Date: Tue, 13 Feb 2018 19:39:41 -0800
Subject: [PATCH 03/10] u54-prci: driver for core U54 clocks

---
 .../bindings/clock/sifive,u54-prci.txt        | 44 +++++++++++++++++++
 1 file changed, 44 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/sifive,u54-prci.txt

diff --git a/Documentation/devicetree/bindings/clock/sifive,u54-prci.txt b/Documentation/devicetree/bindings/clock/sifive,u54-prci.txt
new file mode 100644
index 000000000000..88682c5eaebc
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/sifive,u54-prci.txt
@@ -0,0 +1,44 @@
+SiFive U54 SoC clocks
+
+This binding uses the common clock binding:
+    Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+The U54 PRCI controller generates clocks for the U54 SoC. There is
+a core PLL that sets the processor frequency and PLLs for ethernet
+and DDR. It takes an input clock from the board, typically an oscillator
+or crystal.
+
+Required properties:
+- compatible:	Should be "sifive,aloeprci0"
+- #clock-cells:	Should be <1>
+- reg:		Specifies base physical address and size of the registers
+- clocks:	phandles to the parent clock used as input
+
+Example:
+
+	refclk: refclk {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <33333333>;
+		clock-output-names = "xtal";
+	};
+
+	u54: prci@10000000 {
+		compatible = "sifive,aloeprci0";
+		reg = <0x0 0x10000000 0x0 0x1000>;
+		clocks = <&refclk>;
+		#clock-cells = <1>;
+	};
+
+	tlclk: tlclk {
+		compatible = "fixed-factor-clock";
+		clocks = <&u54 0>; /* Core frequency */
+		#clock-cells = <0>;
+		clock-div = <2>;
+		clock-mult = <1>;
+	};
+
+	ethernet@10090000 {
+		...
+		clocks = <&prci 1>; /* TX clock */
+	};
-- 
2.21.0

