ice-c910_defconfig 9.7 KB

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  1. diff -Nur linux-5.4.36/arch/riscv/boot/dts/thead/Makefile kernel/arch/riscv/boot/dts/thead/Makefile
  2. --- /dev/null
  3. +++ kernel/arch/riscv/boot/dts/thead/Makefile
  4. @@ -0,0 +1,2 @@
  5. +# SPDX-License-Identifier: GPL-2.0
  6. +dtb-$(CONFIG_SOC_LIGHT) += k210.dtb
  7. diff -Nur linux-5.4.36/arch/riscv/boot/dts/thead/light-c910.dts kernel/arch/riscv/boot/dts/thead/light-c910.dts
  8. --- /dev/null
  9. +++ kernel/arch/riscv/boot/dts/thead/light-c910.dts
  10. @@ -0,0 +1,401 @@
  11. +/dts-v1/;
  12. +/ {
  13. + model = "T-HEAD ICE soc";
  14. + compatible = "thead,ice_c910";
  15. + #address-cells = <2>;
  16. + #size-cells = <2>;
  17. +
  18. + memory@0 {
  19. + device_type = "memory";
  20. + /*
  21. + * Total memory size: 2GB (0x00000000 0x80000000)
  22. + * 0x00200000 - 0x40000000: 1022MB for Linux system
  23. + * 0x40000000 - 0x60000000: 512MB for NPU: IAS0
  24. + * 0x60000000 - 0x80000000: 512MB for GPU
  25. + */
  26. + reg = <0x0 0x200000 0x0 0x3fe00000>;
  27. + };
  28. +
  29. + cpus {
  30. + #address-cells = <1>;
  31. + #size-cells = <0>;
  32. + timebase-frequency = <3000000>;
  33. + cpu@0 {
  34. + device_type = "cpu";
  35. + reg = <0>;
  36. + status = "okay";
  37. + compatible = "riscv";
  38. + riscv,isa = "rv64imafdcsu";
  39. + mmu-type = "riscv,sv39";
  40. + cpu0_intc: interrupt-controller {
  41. + #interrupt-cells = <1>;
  42. + compatible = "riscv,cpu-intc";
  43. + interrupt-controller;
  44. + };
  45. + };
  46. + cpu@1 {
  47. + device_type = "cpu";
  48. + reg = <1>;
  49. + status = "okay";
  50. + compatible = "riscv";
  51. + riscv,isa = "rv64imafdcsu";
  52. + mmu-type = "riscv,sv39";
  53. + cpu1_intc: interrupt-controller {
  54. + #interrupt-cells = <1>;
  55. + compatible = "riscv,cpu-intc";
  56. + interrupt-controller;
  57. + };
  58. + };
  59. + cpu@2 {
  60. + device_type = "cpu";
  61. + reg = <2>;
  62. + status = "fail";
  63. + compatible = "riscv";
  64. + riscv,isa = "rv64imafdcsu";
  65. + mmu-type = "riscv,sv39";
  66. + cpu2_intc: interrupt-controller {
  67. + #interrupt-cells = <1>;
  68. + compatible = "riscv,cpu-intc";
  69. + interrupt-controller;
  70. + };
  71. + };
  72. + };
  73. +
  74. + aliases {
  75. + ethernet0 = &gmac;
  76. + };
  77. +
  78. + soc {
  79. + #address-cells = <2>;
  80. + #size-cells = <2>;
  81. + compatible = "simple-bus";
  82. + ranges;
  83. +
  84. + intc: interrupt-controller@3f0000000 {
  85. + #interrupt-cells = <1>;
  86. + compatible = "riscv,plic0";
  87. + interrupt-controller;
  88. + interrupts-extended = <
  89. + &cpu0_intc 0xffffffff &cpu0_intc 9
  90. + &cpu1_intc 0xffffffff &cpu1_intc 9
  91. + &cpu2_intc 0xffffffff &cpu2_intc 9
  92. + >;
  93. + reg = <0x3 0xf0000000 0x0 0x04000000>;
  94. + reg-names = "control";
  95. + riscv,max-priority = <7>;
  96. + riscv,ndev = <80>;
  97. + };
  98. +
  99. + dummy_apb: apb-clock {
  100. + compatible = "fixed-clock";
  101. + clock-frequency = <62500000>;
  102. + clock-output-names = "dummy_apb";
  103. + #clock-cells = <0>;
  104. + };
  105. +
  106. + dummy_ahb: ahb-clock {
  107. + compatible = "fixed-clock";
  108. + clock-frequency = <250000000>;
  109. + clock-output-names = "dummy_ahb";
  110. + #clock-cells = <0>;
  111. + };
  112. +
  113. + dummy_axi: axi-clock {
  114. + compatible = "fixed-clock";
  115. + clock-frequency = <500000000>;
  116. + clock-output-names = "dummy_axi";
  117. + #clock-cells = <0>;
  118. + };
  119. +
  120. + dummy_gmac: gmac-clock {
  121. + compatible = "fixed-clock";
  122. + clock-frequency = <1000000000>;
  123. + clock-output-names = "dummy_gmac";
  124. + #clock-cells = <0>;
  125. + };
  126. +
  127. + dummy_clk_sdio: dummy-clk-sdio {
  128. + compatible = "fixed-clock";
  129. + clock-frequency = <150000000>;
  130. + clock-output-names = "dummy_sdio";
  131. + #clock-cells = <0>;
  132. + };
  133. +
  134. + dummy_clk_dpu: dummy-clk-dpu {
  135. + compatible = "fixed-clock";
  136. + clock-frequency = <297000000>;
  137. + clock-output-names = "dummy_dpu";
  138. + #clock-cells = <0>;
  139. + };
  140. +
  141. + gpio0: gpio@3fff71000 {
  142. + compatible = "snps,dw-apb-gpio";
  143. + reg = <0x3 0xfff71000 0x0 0x1000>;
  144. + #address-cells = <2>;
  145. + #size-cells = <2>;
  146. +
  147. + /* GPIO0[0-31] */
  148. + gpio0_porta: gpio0-controller@0 {
  149. + compatible = "snps,dw-apb-gpio-port";
  150. + gpio-controller;
  151. + #gpio-cells = <2>;
  152. + snps,nr-gpios = <32>;
  153. + reg = <0>;
  154. +
  155. + interrupt-controller;
  156. + #interrupt-cells = <2>;
  157. + interrupt-parent = <&intc>;
  158. + interrupts = <27>;
  159. + };
  160. +
  161. + /* GPIO0[32-63] */
  162. + gpio0_portb: gpio0-controller@1 {
  163. + compatible = "snps,dw-apb-gpio-port";
  164. + gpio-controller;
  165. + #gpio-cells = <2>;
  166. + snps,nr-gpios = <32>;
  167. + reg = <1>;
  168. + };
  169. + };
  170. +
  171. + gpio1: gpio@3fff72000 {
  172. + compatible = "snps,dw-apb-gpio";
  173. + reg = <0x3 0xfff72000 0x0 0x1000>;
  174. + #address-cells = <2>;
  175. + #size-cells = <2>;
  176. +
  177. + /* GPIO1[0-31] */
  178. + gpio1_porta: gpio1-controller@0 {
  179. + compatible = "snps,dw-apb-gpio-port";
  180. + gpio-controller;
  181. + #gpio-cells = <2>;
  182. + snps,nr-gpios = <32>;
  183. + reg = <0>;
  184. + };
  185. +
  186. + /* GPIO1[32-63] */
  187. + gpio1_portb: gpio1-controller@1 {
  188. + compatible = "snps,dw-apb-gpio-port";
  189. + gpio-controller;
  190. + #gpio-cells = <2>;
  191. + snps,nr-gpios = <32>;
  192. + reg = <1>;
  193. + };
  194. +
  195. + /* GPIO1[64-95] */
  196. + gpio1_portc: gpio1-controller@2 {
  197. + compatible = "snps,dw-apb-gpio-port";
  198. + gpio-controller;
  199. + #gpio-cells = <2>;
  200. + snps,nr-gpios = <32>;
  201. + reg = <2>;
  202. + };
  203. + };
  204. +
  205. + gpio-leds {
  206. + compatible = "gpio-leds";
  207. +
  208. + led0 { /* GPIO0[11] - UART2_TXD */
  209. + label = "led0";
  210. + gpios = <&gpio0_porta 11 1>;
  211. + default-state = "off";
  212. + };
  213. + };
  214. +
  215. + gpio-keys {
  216. + compatible = "gpio-keys";
  217. + /* autorepeat; */
  218. +
  219. + key_0 { /* GPIO0[10] - UART2_RXD */
  220. + gpios = <&gpio0_porta 10 1>;
  221. + linux,code = <59>;
  222. + label = "key_0";
  223. + };
  224. + };
  225. +
  226. + serial0@3fff73000 {
  227. + compatible = "snps,dw-apb-uart";
  228. + reg = <0x3 0xfff73000 0x0 0x400>;
  229. + interrupt-parent = <&intc>;
  230. + interrupts = <23>;
  231. + clocks = <&dummy_apb>;
  232. + clock-names = "baudclk";
  233. + reg-shift = <2>;
  234. + reg-io-width = <4>;
  235. + fifo-size = <16>;
  236. + /*
  237. + * rx-trigger-level:
  238. + * 0 - 1 character
  239. + * 1 - 1/4 full
  240. + * 2 - 1/2 full
  241. + * 3 - (fifo size - 2)
  242. + */
  243. + rx-trigger-level = <2>;
  244. + };
  245. +
  246. + /* serial1@3fff73400, interrupt=24 is occupied by CK810 system */
  247. +
  248. + serial2@3fff73800 {
  249. + compatible = "snps,dw-apb-uart";
  250. + reg = <0x3 0xfff73800 0x0 0x400>;
  251. + interrupt-parent = <&intc>;
  252. + interrupts = <25>;
  253. + clocks = <&dummy_apb>;
  254. + clock-names = "baudclk";
  255. + reg-shift = <2>;
  256. + reg-io-width = <4>;
  257. + fifo-size = <16>;
  258. + /*
  259. + * rx-trigger-level:
  260. + * 0 - 1 character
  261. + * 1 - 1/4 full
  262. + * 2 - 1/2 full
  263. + * 3 - (fifo size - 2)
  264. + */
  265. + rx-trigger-level = <2>;
  266. + };
  267. +
  268. + i2c@3fff74000 {
  269. + #address-cells = <2>;
  270. + #size-cells = <2>;
  271. + compatible = "dahua,i2c-dw201a";
  272. + reg = <0x3 0xfff74000 0x0 0x1000>;
  273. + interrupts = <21>;
  274. + interrupt-parent = <&intc>;
  275. + clocks = <&dummy_apb>;
  276. + clock-frequency = <400000>;
  277. +
  278. + eeprom@50 {
  279. + compatible = "atmel,24c64";
  280. + reg = <0x50>;
  281. + pagesize = <32>;
  282. + };
  283. + };
  284. +
  285. + pmu: pmu {
  286. + compatible = "riscv,c910_pmu";
  287. + };
  288. +
  289. + dmac0: dmac@3fffd0000 {
  290. + compatible = "snps,axi-dma-1.01a";
  291. + reg = <0x3 0xfffd0000 0x0 0x1000>;
  292. + interrupt-parent = <&intc>;
  293. + interrupts = <65>;
  294. + clocks = <&dummy_axi>, <&dummy_ahb>;
  295. + clock-names = "core-clk", "cfgr-clk";
  296. +
  297. + dma-channels = <8>;
  298. + snps,block-size = <65536 65536 65536 65536 65536 65536 65536 65536>;
  299. + snps,priority = <0 1 2 3 4 5 6 7>;
  300. + snps,dma-masters = <1>;
  301. + snps,data-width = <4>;
  302. + snps,axi-max-burst-len = <16>;
  303. +
  304. + /* status = "disabled"; */
  305. + };
  306. +
  307. + sdhc0: sdhc0@3fffb0000 {
  308. + #address-cells = <1>;
  309. + #size-cells = <0>;
  310. + compatible = "snps,dw-mshc";
  311. + reg = <0x3 0xfffb0000 0x0 0x1000>;
  312. + interrupt-parent = <&intc>;
  313. + interrupts = <37>;
  314. + clocks = <&dummy_clk_sdio>, <&dummy_clk_sdio>;
  315. + clock-names = "ciu", "biu";
  316. + num-slots = <1>;
  317. + card-detect-delay = <200>;
  318. + cap-mmc-highspeed;
  319. + cap-cmd23;
  320. + non-removable;
  321. + bus-width = <8>;
  322. + };
  323. +
  324. + sdhc1: sdhc1@3fffa0000 {
  325. + compatible = "snps,dw-mshc";
  326. + reg = <0x3 0xfffa0000 0x0 0x1000>;
  327. + interrupt-parent = <&intc>;
  328. + interrupts = <38>;
  329. + clocks = <&dummy_clk_sdio>, <&dummy_clk_sdio>;
  330. + clock-names = "ciu", "biu";
  331. + num-slots = <1>;
  332. + card-detect-delay = <200>;
  333. + cap-sd-highspeed;
  334. + bus-width = <4>;
  335. + };
  336. +
  337. + stmmac_axi_setup: stmmac-axi-config {
  338. + snps,wr_osr_lmt = <3>;
  339. + snps,rd_osr_lmt = <3>;
  340. + snps,blen = <16 8 4 0 0 0 0>;
  341. + };
  342. +
  343. + gmac: ethernet@3fffc0000 {
  344. + compatible = "thead,dwmac";
  345. + reg = < 0x3 0xfffc0000 0x0 0x2000
  346. + 0x3 0xfe83025c 0x0 0x4
  347. + 0x3 0xfe83031c 0x0 0x4
  348. + 0x3 0xfff770c0 0x0 0x1c>;
  349. + reg-names = "gmac", "phy_if_reg", "txclk_dir_reg", "clk_mgr_reg";
  350. + interrupt-parent = <&intc>;
  351. + interrupts = <40>;
  352. + interrupt-names = "macirq";
  353. + clocks = <&dummy_ahb>, <&dummy_gmac>;
  354. + clock-names = "stmmaceth", "gmac_pll_clk";
  355. + snps,pbl = <32>;
  356. + snps,fixed-burst;
  357. + snps,axi-config = <&stmmac_axi_setup>;
  358. +
  359. + phy-mode = "rgmii-txid";
  360. + rx-clk-delay = <0x1f>; /* for RGMII */
  361. + tx-clk-delay = <0x1f>; /* for RGMII */
  362. +
  363. + phy-handle = <&eth_phy_0>;
  364. + mdio0 {
  365. + #address-cells = <1>;
  366. + #size-cells = <0>;
  367. + compatible = "snps,dwmac-mdio";
  368. +
  369. + eth_phy_0: ethernet-phy@0 {
  370. + reg = <0>;
  371. + };
  372. + };
  373. + };
  374. +
  375. + npu0: npu@3fff20000 {
  376. + compatible = "verisilicon,vip8000";
  377. + core-id = <0>;
  378. + reg = <0x3 0xfff20000 0x0 0x1000>;
  379. + interrupt-parent = <&intc>;
  380. + interrupts = <66>;
  381. + contiguous-base = <0x0 0x40000000>;
  382. + contiguous-size = <0x0 0x20000000>;
  383. + extsram-base = <0x3 0xfe400000>;
  384. + extsram-size = <0x0 0x40000>;
  385. + };
  386. +
  387. + gpu: gpu@3fff27000 {
  388. + compatible = "verisilicon,gc8000ul";
  389. + reg = <0x3 0xfff27000 0x0 0x1000>;
  390. + interrupt-parent = <&intc>;
  391. + interrupts = <63>;
  392. + contiguous-base = <0x0 0x60000000>;
  393. + contiguous-size = <0x0 0x10000000>;
  394. + };
  395. +
  396. + dpu: dpu@3fff28000 {
  397. + compatible = "verisilicon,dc8000-fb";
  398. + reg = <0x3 0xfff28000 0x0 0x8000>;
  399. + interrupt-parent = <&intc>;
  400. + interrupts = <64>;
  401. + };
  402. +
  403. + };
  404. +
  405. + chosen {
  406. + bootargs = "console=ttyS0,115200 crashkernel=256M-:128M c910_mmu_v1";
  407. + linux,initrd-start = <0x2000000>;
  408. + linux,initrd-end = <0x17000000>;
  409. + stdout-path = "serial0@3fff73000:115200";
  410. + };
  411. +};