intel-pt.c 88 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * intel_pt.c: Intel Processor Trace support
  4. * Copyright (c) 2013-2015, Intel Corporation.
  5. */
  6. #include <inttypes.h>
  7. #include <stdio.h>
  8. #include <stdbool.h>
  9. #include <errno.h>
  10. #include <linux/kernel.h>
  11. #include <linux/string.h>
  12. #include <linux/types.h>
  13. #include <linux/zalloc.h>
  14. #include "session.h"
  15. #include "machine.h"
  16. #include "memswap.h"
  17. #include "sort.h"
  18. #include "tool.h"
  19. #include "event.h"
  20. #include "evlist.h"
  21. #include "evsel.h"
  22. #include "map.h"
  23. #include "color.h"
  24. #include "thread.h"
  25. #include "thread-stack.h"
  26. #include "symbol.h"
  27. #include "callchain.h"
  28. #include "dso.h"
  29. #include "debug.h"
  30. #include "auxtrace.h"
  31. #include "tsc.h"
  32. #include "intel-pt.h"
  33. #include "config.h"
  34. #include "util/perf_api_probe.h"
  35. #include "util/synthetic-events.h"
  36. #include "time-utils.h"
  37. #include "../arch/x86/include/uapi/asm/perf_regs.h"
  38. #include "intel-pt-decoder/intel-pt-log.h"
  39. #include "intel-pt-decoder/intel-pt-decoder.h"
  40. #include "intel-pt-decoder/intel-pt-insn-decoder.h"
  41. #include "intel-pt-decoder/intel-pt-pkt-decoder.h"
  42. #define MAX_TIMESTAMP (~0ULL)
  43. struct range {
  44. u64 start;
  45. u64 end;
  46. };
  47. struct intel_pt {
  48. struct auxtrace auxtrace;
  49. struct auxtrace_queues queues;
  50. struct auxtrace_heap heap;
  51. u32 auxtrace_type;
  52. struct perf_session *session;
  53. struct machine *machine;
  54. struct evsel *switch_evsel;
  55. struct thread *unknown_thread;
  56. bool timeless_decoding;
  57. bool sampling_mode;
  58. bool snapshot_mode;
  59. bool per_cpu_mmaps;
  60. bool have_tsc;
  61. bool data_queued;
  62. bool est_tsc;
  63. bool sync_switch;
  64. bool mispred_all;
  65. bool use_thread_stack;
  66. bool callstack;
  67. unsigned int br_stack_sz;
  68. unsigned int br_stack_sz_plus;
  69. int have_sched_switch;
  70. u32 pmu_type;
  71. u64 kernel_start;
  72. u64 switch_ip;
  73. u64 ptss_ip;
  74. struct perf_tsc_conversion tc;
  75. bool cap_user_time_zero;
  76. struct itrace_synth_opts synth_opts;
  77. bool sample_instructions;
  78. u64 instructions_sample_type;
  79. u64 instructions_id;
  80. bool sample_branches;
  81. u32 branches_filter;
  82. u64 branches_sample_type;
  83. u64 branches_id;
  84. bool sample_transactions;
  85. u64 transactions_sample_type;
  86. u64 transactions_id;
  87. bool sample_ptwrites;
  88. u64 ptwrites_sample_type;
  89. u64 ptwrites_id;
  90. bool sample_pwr_events;
  91. u64 pwr_events_sample_type;
  92. u64 mwait_id;
  93. u64 pwre_id;
  94. u64 exstop_id;
  95. u64 pwrx_id;
  96. u64 cbr_id;
  97. bool sample_pebs;
  98. struct evsel *pebs_evsel;
  99. u64 tsc_bit;
  100. u64 mtc_bit;
  101. u64 mtc_freq_bits;
  102. u32 tsc_ctc_ratio_n;
  103. u32 tsc_ctc_ratio_d;
  104. u64 cyc_bit;
  105. u64 noretcomp_bit;
  106. unsigned max_non_turbo_ratio;
  107. unsigned cbr2khz;
  108. unsigned long num_events;
  109. char *filter;
  110. struct addr_filters filts;
  111. struct range *time_ranges;
  112. unsigned int range_cnt;
  113. struct ip_callchain *chain;
  114. struct branch_stack *br_stack;
  115. };
  116. enum switch_state {
  117. INTEL_PT_SS_NOT_TRACING,
  118. INTEL_PT_SS_UNKNOWN,
  119. INTEL_PT_SS_TRACING,
  120. INTEL_PT_SS_EXPECTING_SWITCH_EVENT,
  121. INTEL_PT_SS_EXPECTING_SWITCH_IP,
  122. };
  123. struct intel_pt_queue {
  124. struct intel_pt *pt;
  125. unsigned int queue_nr;
  126. struct auxtrace_buffer *buffer;
  127. struct auxtrace_buffer *old_buffer;
  128. void *decoder;
  129. const struct intel_pt_state *state;
  130. struct ip_callchain *chain;
  131. struct branch_stack *last_branch;
  132. union perf_event *event_buf;
  133. bool on_heap;
  134. bool stop;
  135. bool step_through_buffers;
  136. bool use_buffer_pid_tid;
  137. bool sync_switch;
  138. pid_t pid, tid;
  139. int cpu;
  140. int switch_state;
  141. pid_t next_tid;
  142. struct thread *thread;
  143. bool exclude_kernel;
  144. bool have_sample;
  145. u64 time;
  146. u64 timestamp;
  147. u64 sel_timestamp;
  148. bool sel_start;
  149. unsigned int sel_idx;
  150. u32 flags;
  151. u16 insn_len;
  152. u64 last_insn_cnt;
  153. u64 ipc_insn_cnt;
  154. u64 ipc_cyc_cnt;
  155. u64 last_in_insn_cnt;
  156. u64 last_in_cyc_cnt;
  157. u64 last_br_insn_cnt;
  158. u64 last_br_cyc_cnt;
  159. unsigned int cbr_seen;
  160. char insn[INTEL_PT_INSN_BUF_SZ];
  161. };
  162. static void intel_pt_dump(struct intel_pt *pt __maybe_unused,
  163. unsigned char *buf, size_t len)
  164. {
  165. struct intel_pt_pkt packet;
  166. size_t pos = 0;
  167. int ret, pkt_len, i;
  168. char desc[INTEL_PT_PKT_DESC_MAX];
  169. const char *color = PERF_COLOR_BLUE;
  170. enum intel_pt_pkt_ctx ctx = INTEL_PT_NO_CTX;
  171. color_fprintf(stdout, color,
  172. ". ... Intel Processor Trace data: size %zu bytes\n",
  173. len);
  174. while (len) {
  175. ret = intel_pt_get_packet(buf, len, &packet, &ctx);
  176. if (ret > 0)
  177. pkt_len = ret;
  178. else
  179. pkt_len = 1;
  180. printf(".");
  181. color_fprintf(stdout, color, " %08x: ", pos);
  182. for (i = 0; i < pkt_len; i++)
  183. color_fprintf(stdout, color, " %02x", buf[i]);
  184. for (; i < 16; i++)
  185. color_fprintf(stdout, color, " ");
  186. if (ret > 0) {
  187. ret = intel_pt_pkt_desc(&packet, desc,
  188. INTEL_PT_PKT_DESC_MAX);
  189. if (ret > 0)
  190. color_fprintf(stdout, color, " %s\n", desc);
  191. } else {
  192. color_fprintf(stdout, color, " Bad packet!\n");
  193. }
  194. pos += pkt_len;
  195. buf += pkt_len;
  196. len -= pkt_len;
  197. }
  198. }
  199. static void intel_pt_dump_event(struct intel_pt *pt, unsigned char *buf,
  200. size_t len)
  201. {
  202. printf(".\n");
  203. intel_pt_dump(pt, buf, len);
  204. }
  205. static void intel_pt_log_event(union perf_event *event)
  206. {
  207. FILE *f = intel_pt_log_fp();
  208. if (!intel_pt_enable_logging || !f)
  209. return;
  210. perf_event__fprintf(event, NULL, f);
  211. }
  212. static void intel_pt_dump_sample(struct perf_session *session,
  213. struct perf_sample *sample)
  214. {
  215. struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
  216. auxtrace);
  217. printf("\n");
  218. intel_pt_dump(pt, sample->aux_sample.data, sample->aux_sample.size);
  219. }
  220. static bool intel_pt_log_events(struct intel_pt *pt, u64 tm)
  221. {
  222. struct perf_time_interval *range = pt->synth_opts.ptime_range;
  223. int n = pt->synth_opts.range_num;
  224. if (pt->synth_opts.log_plus_flags & AUXTRACE_LOG_FLG_ALL_PERF_EVTS)
  225. return true;
  226. if (pt->synth_opts.log_minus_flags & AUXTRACE_LOG_FLG_ALL_PERF_EVTS)
  227. return false;
  228. /* perf_time__ranges_skip_sample does not work if time is zero */
  229. if (!tm)
  230. tm = 1;
  231. return !n || !perf_time__ranges_skip_sample(range, n, tm);
  232. }
  233. static int intel_pt_do_fix_overlap(struct intel_pt *pt, struct auxtrace_buffer *a,
  234. struct auxtrace_buffer *b)
  235. {
  236. bool consecutive = false;
  237. void *start;
  238. start = intel_pt_find_overlap(a->data, a->size, b->data, b->size,
  239. pt->have_tsc, &consecutive);
  240. if (!start)
  241. return -EINVAL;
  242. b->use_size = b->data + b->size - start;
  243. b->use_data = start;
  244. if (b->use_size && consecutive)
  245. b->consecutive = true;
  246. return 0;
  247. }
  248. static int intel_pt_get_buffer(struct intel_pt_queue *ptq,
  249. struct auxtrace_buffer *buffer,
  250. struct auxtrace_buffer *old_buffer,
  251. struct intel_pt_buffer *b)
  252. {
  253. bool might_overlap;
  254. if (!buffer->data) {
  255. int fd = perf_data__fd(ptq->pt->session->data);
  256. buffer->data = auxtrace_buffer__get_data(buffer, fd);
  257. if (!buffer->data)
  258. return -ENOMEM;
  259. }
  260. might_overlap = ptq->pt->snapshot_mode || ptq->pt->sampling_mode;
  261. if (might_overlap && !buffer->consecutive && old_buffer &&
  262. intel_pt_do_fix_overlap(ptq->pt, old_buffer, buffer))
  263. return -ENOMEM;
  264. if (buffer->use_data) {
  265. b->len = buffer->use_size;
  266. b->buf = buffer->use_data;
  267. } else {
  268. b->len = buffer->size;
  269. b->buf = buffer->data;
  270. }
  271. b->ref_timestamp = buffer->reference;
  272. if (!old_buffer || (might_overlap && !buffer->consecutive)) {
  273. b->consecutive = false;
  274. b->trace_nr = buffer->buffer_nr + 1;
  275. } else {
  276. b->consecutive = true;
  277. }
  278. return 0;
  279. }
  280. /* Do not drop buffers with references - refer intel_pt_get_trace() */
  281. static void intel_pt_lookahead_drop_buffer(struct intel_pt_queue *ptq,
  282. struct auxtrace_buffer *buffer)
  283. {
  284. if (!buffer || buffer == ptq->buffer || buffer == ptq->old_buffer)
  285. return;
  286. auxtrace_buffer__drop_data(buffer);
  287. }
  288. /* Must be serialized with respect to intel_pt_get_trace() */
  289. static int intel_pt_lookahead(void *data, intel_pt_lookahead_cb_t cb,
  290. void *cb_data)
  291. {
  292. struct intel_pt_queue *ptq = data;
  293. struct auxtrace_buffer *buffer = ptq->buffer;
  294. struct auxtrace_buffer *old_buffer = ptq->old_buffer;
  295. struct auxtrace_queue *queue;
  296. int err = 0;
  297. queue = &ptq->pt->queues.queue_array[ptq->queue_nr];
  298. while (1) {
  299. struct intel_pt_buffer b = { .len = 0 };
  300. buffer = auxtrace_buffer__next(queue, buffer);
  301. if (!buffer)
  302. break;
  303. err = intel_pt_get_buffer(ptq, buffer, old_buffer, &b);
  304. if (err)
  305. break;
  306. if (b.len) {
  307. intel_pt_lookahead_drop_buffer(ptq, old_buffer);
  308. old_buffer = buffer;
  309. } else {
  310. intel_pt_lookahead_drop_buffer(ptq, buffer);
  311. continue;
  312. }
  313. err = cb(&b, cb_data);
  314. if (err)
  315. break;
  316. }
  317. if (buffer != old_buffer)
  318. intel_pt_lookahead_drop_buffer(ptq, buffer);
  319. intel_pt_lookahead_drop_buffer(ptq, old_buffer);
  320. return err;
  321. }
  322. /*
  323. * This function assumes data is processed sequentially only.
  324. * Must be serialized with respect to intel_pt_lookahead()
  325. */
  326. static int intel_pt_get_trace(struct intel_pt_buffer *b, void *data)
  327. {
  328. struct intel_pt_queue *ptq = data;
  329. struct auxtrace_buffer *buffer = ptq->buffer;
  330. struct auxtrace_buffer *old_buffer = ptq->old_buffer;
  331. struct auxtrace_queue *queue;
  332. int err;
  333. if (ptq->stop) {
  334. b->len = 0;
  335. return 0;
  336. }
  337. queue = &ptq->pt->queues.queue_array[ptq->queue_nr];
  338. buffer = auxtrace_buffer__next(queue, buffer);
  339. if (!buffer) {
  340. if (old_buffer)
  341. auxtrace_buffer__drop_data(old_buffer);
  342. b->len = 0;
  343. return 0;
  344. }
  345. ptq->buffer = buffer;
  346. err = intel_pt_get_buffer(ptq, buffer, old_buffer, b);
  347. if (err)
  348. return err;
  349. if (ptq->step_through_buffers)
  350. ptq->stop = true;
  351. if (b->len) {
  352. if (old_buffer)
  353. auxtrace_buffer__drop_data(old_buffer);
  354. ptq->old_buffer = buffer;
  355. } else {
  356. auxtrace_buffer__drop_data(buffer);
  357. return intel_pt_get_trace(b, data);
  358. }
  359. return 0;
  360. }
  361. struct intel_pt_cache_entry {
  362. struct auxtrace_cache_entry entry;
  363. u64 insn_cnt;
  364. u64 byte_cnt;
  365. enum intel_pt_insn_op op;
  366. enum intel_pt_insn_branch branch;
  367. int length;
  368. int32_t rel;
  369. char insn[INTEL_PT_INSN_BUF_SZ];
  370. };
  371. static int intel_pt_config_div(const char *var, const char *value, void *data)
  372. {
  373. int *d = data;
  374. long val;
  375. if (!strcmp(var, "intel-pt.cache-divisor")) {
  376. val = strtol(value, NULL, 0);
  377. if (val > 0 && val <= INT_MAX)
  378. *d = val;
  379. }
  380. return 0;
  381. }
  382. static int intel_pt_cache_divisor(void)
  383. {
  384. static int d;
  385. if (d)
  386. return d;
  387. perf_config(intel_pt_config_div, &d);
  388. if (!d)
  389. d = 64;
  390. return d;
  391. }
  392. static unsigned int intel_pt_cache_size(struct dso *dso,
  393. struct machine *machine)
  394. {
  395. off_t size;
  396. size = dso__data_size(dso, machine);
  397. size /= intel_pt_cache_divisor();
  398. if (size < 1000)
  399. return 10;
  400. if (size > (1 << 21))
  401. return 21;
  402. return 32 - __builtin_clz(size);
  403. }
  404. static struct auxtrace_cache *intel_pt_cache(struct dso *dso,
  405. struct machine *machine)
  406. {
  407. struct auxtrace_cache *c;
  408. unsigned int bits;
  409. if (dso->auxtrace_cache)
  410. return dso->auxtrace_cache;
  411. bits = intel_pt_cache_size(dso, machine);
  412. /* Ignoring cache creation failure */
  413. c = auxtrace_cache__new(bits, sizeof(struct intel_pt_cache_entry), 200);
  414. dso->auxtrace_cache = c;
  415. return c;
  416. }
  417. static int intel_pt_cache_add(struct dso *dso, struct machine *machine,
  418. u64 offset, u64 insn_cnt, u64 byte_cnt,
  419. struct intel_pt_insn *intel_pt_insn)
  420. {
  421. struct auxtrace_cache *c = intel_pt_cache(dso, machine);
  422. struct intel_pt_cache_entry *e;
  423. int err;
  424. if (!c)
  425. return -ENOMEM;
  426. e = auxtrace_cache__alloc_entry(c);
  427. if (!e)
  428. return -ENOMEM;
  429. e->insn_cnt = insn_cnt;
  430. e->byte_cnt = byte_cnt;
  431. e->op = intel_pt_insn->op;
  432. e->branch = intel_pt_insn->branch;
  433. e->length = intel_pt_insn->length;
  434. e->rel = intel_pt_insn->rel;
  435. memcpy(e->insn, intel_pt_insn->buf, INTEL_PT_INSN_BUF_SZ);
  436. err = auxtrace_cache__add(c, offset, &e->entry);
  437. if (err)
  438. auxtrace_cache__free_entry(c, e);
  439. return err;
  440. }
  441. static struct intel_pt_cache_entry *
  442. intel_pt_cache_lookup(struct dso *dso, struct machine *machine, u64 offset)
  443. {
  444. struct auxtrace_cache *c = intel_pt_cache(dso, machine);
  445. if (!c)
  446. return NULL;
  447. return auxtrace_cache__lookup(dso->auxtrace_cache, offset);
  448. }
  449. static void intel_pt_cache_invalidate(struct dso *dso, struct machine *machine,
  450. u64 offset)
  451. {
  452. struct auxtrace_cache *c = intel_pt_cache(dso, machine);
  453. if (!c)
  454. return;
  455. auxtrace_cache__remove(dso->auxtrace_cache, offset);
  456. }
  457. static inline u8 intel_pt_cpumode(struct intel_pt *pt, uint64_t ip)
  458. {
  459. return ip >= pt->kernel_start ?
  460. PERF_RECORD_MISC_KERNEL :
  461. PERF_RECORD_MISC_USER;
  462. }
  463. static int intel_pt_walk_next_insn(struct intel_pt_insn *intel_pt_insn,
  464. uint64_t *insn_cnt_ptr, uint64_t *ip,
  465. uint64_t to_ip, uint64_t max_insn_cnt,
  466. void *data)
  467. {
  468. struct intel_pt_queue *ptq = data;
  469. struct machine *machine = ptq->pt->machine;
  470. struct thread *thread;
  471. struct addr_location al;
  472. unsigned char buf[INTEL_PT_INSN_BUF_SZ];
  473. ssize_t len;
  474. int x86_64;
  475. u8 cpumode;
  476. u64 offset, start_offset, start_ip;
  477. u64 insn_cnt = 0;
  478. bool one_map = true;
  479. intel_pt_insn->length = 0;
  480. if (to_ip && *ip == to_ip)
  481. goto out_no_cache;
  482. cpumode = intel_pt_cpumode(ptq->pt, *ip);
  483. thread = ptq->thread;
  484. if (!thread) {
  485. if (cpumode != PERF_RECORD_MISC_KERNEL)
  486. return -EINVAL;
  487. thread = ptq->pt->unknown_thread;
  488. }
  489. while (1) {
  490. if (!thread__find_map(thread, cpumode, *ip, &al) || !al.map->dso)
  491. return -EINVAL;
  492. if (al.map->dso->data.status == DSO_DATA_STATUS_ERROR &&
  493. dso__data_status_seen(al.map->dso,
  494. DSO_DATA_STATUS_SEEN_ITRACE))
  495. return -ENOENT;
  496. offset = al.map->map_ip(al.map, *ip);
  497. if (!to_ip && one_map) {
  498. struct intel_pt_cache_entry *e;
  499. e = intel_pt_cache_lookup(al.map->dso, machine, offset);
  500. if (e &&
  501. (!max_insn_cnt || e->insn_cnt <= max_insn_cnt)) {
  502. *insn_cnt_ptr = e->insn_cnt;
  503. *ip += e->byte_cnt;
  504. intel_pt_insn->op = e->op;
  505. intel_pt_insn->branch = e->branch;
  506. intel_pt_insn->length = e->length;
  507. intel_pt_insn->rel = e->rel;
  508. memcpy(intel_pt_insn->buf, e->insn,
  509. INTEL_PT_INSN_BUF_SZ);
  510. intel_pt_log_insn_no_data(intel_pt_insn, *ip);
  511. return 0;
  512. }
  513. }
  514. start_offset = offset;
  515. start_ip = *ip;
  516. /* Load maps to ensure dso->is_64_bit has been updated */
  517. map__load(al.map);
  518. x86_64 = al.map->dso->is_64_bit;
  519. while (1) {
  520. len = dso__data_read_offset(al.map->dso, machine,
  521. offset, buf,
  522. INTEL_PT_INSN_BUF_SZ);
  523. if (len <= 0)
  524. return -EINVAL;
  525. if (intel_pt_get_insn(buf, len, x86_64, intel_pt_insn))
  526. return -EINVAL;
  527. intel_pt_log_insn(intel_pt_insn, *ip);
  528. insn_cnt += 1;
  529. if (intel_pt_insn->branch != INTEL_PT_BR_NO_BRANCH)
  530. goto out;
  531. if (max_insn_cnt && insn_cnt >= max_insn_cnt)
  532. goto out_no_cache;
  533. *ip += intel_pt_insn->length;
  534. if (to_ip && *ip == to_ip) {
  535. intel_pt_insn->length = 0;
  536. goto out_no_cache;
  537. }
  538. if (*ip >= al.map->end)
  539. break;
  540. offset += intel_pt_insn->length;
  541. }
  542. one_map = false;
  543. }
  544. out:
  545. *insn_cnt_ptr = insn_cnt;
  546. if (!one_map)
  547. goto out_no_cache;
  548. /*
  549. * Didn't lookup in the 'to_ip' case, so do it now to prevent duplicate
  550. * entries.
  551. */
  552. if (to_ip) {
  553. struct intel_pt_cache_entry *e;
  554. e = intel_pt_cache_lookup(al.map->dso, machine, start_offset);
  555. if (e)
  556. return 0;
  557. }
  558. /* Ignore cache errors */
  559. intel_pt_cache_add(al.map->dso, machine, start_offset, insn_cnt,
  560. *ip - start_ip, intel_pt_insn);
  561. return 0;
  562. out_no_cache:
  563. *insn_cnt_ptr = insn_cnt;
  564. return 0;
  565. }
  566. static bool intel_pt_match_pgd_ip(struct intel_pt *pt, uint64_t ip,
  567. uint64_t offset, const char *filename)
  568. {
  569. struct addr_filter *filt;
  570. bool have_filter = false;
  571. bool hit_tracestop = false;
  572. bool hit_filter = false;
  573. list_for_each_entry(filt, &pt->filts.head, list) {
  574. if (filt->start)
  575. have_filter = true;
  576. if ((filename && !filt->filename) ||
  577. (!filename && filt->filename) ||
  578. (filename && strcmp(filename, filt->filename)))
  579. continue;
  580. if (!(offset >= filt->addr && offset < filt->addr + filt->size))
  581. continue;
  582. intel_pt_log("TIP.PGD ip %#"PRIx64" offset %#"PRIx64" in %s hit filter: %s offset %#"PRIx64" size %#"PRIx64"\n",
  583. ip, offset, filename ? filename : "[kernel]",
  584. filt->start ? "filter" : "stop",
  585. filt->addr, filt->size);
  586. if (filt->start)
  587. hit_filter = true;
  588. else
  589. hit_tracestop = true;
  590. }
  591. if (!hit_tracestop && !hit_filter)
  592. intel_pt_log("TIP.PGD ip %#"PRIx64" offset %#"PRIx64" in %s is not in a filter region\n",
  593. ip, offset, filename ? filename : "[kernel]");
  594. return hit_tracestop || (have_filter && !hit_filter);
  595. }
  596. static int __intel_pt_pgd_ip(uint64_t ip, void *data)
  597. {
  598. struct intel_pt_queue *ptq = data;
  599. struct thread *thread;
  600. struct addr_location al;
  601. u8 cpumode;
  602. u64 offset;
  603. if (ip >= ptq->pt->kernel_start)
  604. return intel_pt_match_pgd_ip(ptq->pt, ip, ip, NULL);
  605. cpumode = PERF_RECORD_MISC_USER;
  606. thread = ptq->thread;
  607. if (!thread)
  608. return -EINVAL;
  609. if (!thread__find_map(thread, cpumode, ip, &al) || !al.map->dso)
  610. return -EINVAL;
  611. offset = al.map->map_ip(al.map, ip);
  612. return intel_pt_match_pgd_ip(ptq->pt, ip, offset,
  613. al.map->dso->long_name);
  614. }
  615. static bool intel_pt_pgd_ip(uint64_t ip, void *data)
  616. {
  617. return __intel_pt_pgd_ip(ip, data) > 0;
  618. }
  619. static bool intel_pt_get_config(struct intel_pt *pt,
  620. struct perf_event_attr *attr, u64 *config)
  621. {
  622. if (attr->type == pt->pmu_type) {
  623. if (config)
  624. *config = attr->config;
  625. return true;
  626. }
  627. return false;
  628. }
  629. static bool intel_pt_exclude_kernel(struct intel_pt *pt)
  630. {
  631. struct evsel *evsel;
  632. evlist__for_each_entry(pt->session->evlist, evsel) {
  633. if (intel_pt_get_config(pt, &evsel->core.attr, NULL) &&
  634. !evsel->core.attr.exclude_kernel)
  635. return false;
  636. }
  637. return true;
  638. }
  639. static bool intel_pt_return_compression(struct intel_pt *pt)
  640. {
  641. struct evsel *evsel;
  642. u64 config;
  643. if (!pt->noretcomp_bit)
  644. return true;
  645. evlist__for_each_entry(pt->session->evlist, evsel) {
  646. if (intel_pt_get_config(pt, &evsel->core.attr, &config) &&
  647. (config & pt->noretcomp_bit))
  648. return false;
  649. }
  650. return true;
  651. }
  652. static bool intel_pt_branch_enable(struct intel_pt *pt)
  653. {
  654. struct evsel *evsel;
  655. u64 config;
  656. evlist__for_each_entry(pt->session->evlist, evsel) {
  657. if (intel_pt_get_config(pt, &evsel->core.attr, &config) &&
  658. (config & 1) && !(config & 0x2000))
  659. return false;
  660. }
  661. return true;
  662. }
  663. static unsigned int intel_pt_mtc_period(struct intel_pt *pt)
  664. {
  665. struct evsel *evsel;
  666. unsigned int shift;
  667. u64 config;
  668. if (!pt->mtc_freq_bits)
  669. return 0;
  670. for (shift = 0, config = pt->mtc_freq_bits; !(config & 1); shift++)
  671. config >>= 1;
  672. evlist__for_each_entry(pt->session->evlist, evsel) {
  673. if (intel_pt_get_config(pt, &evsel->core.attr, &config))
  674. return (config & pt->mtc_freq_bits) >> shift;
  675. }
  676. return 0;
  677. }
  678. static bool intel_pt_timeless_decoding(struct intel_pt *pt)
  679. {
  680. struct evsel *evsel;
  681. bool timeless_decoding = true;
  682. u64 config;
  683. if (!pt->tsc_bit || !pt->cap_user_time_zero)
  684. return true;
  685. evlist__for_each_entry(pt->session->evlist, evsel) {
  686. if (!(evsel->core.attr.sample_type & PERF_SAMPLE_TIME))
  687. return true;
  688. if (intel_pt_get_config(pt, &evsel->core.attr, &config)) {
  689. if (config & pt->tsc_bit)
  690. timeless_decoding = false;
  691. else
  692. return true;
  693. }
  694. }
  695. return timeless_decoding;
  696. }
  697. static bool intel_pt_tracing_kernel(struct intel_pt *pt)
  698. {
  699. struct evsel *evsel;
  700. evlist__for_each_entry(pt->session->evlist, evsel) {
  701. if (intel_pt_get_config(pt, &evsel->core.attr, NULL) &&
  702. !evsel->core.attr.exclude_kernel)
  703. return true;
  704. }
  705. return false;
  706. }
  707. static bool intel_pt_have_tsc(struct intel_pt *pt)
  708. {
  709. struct evsel *evsel;
  710. bool have_tsc = false;
  711. u64 config;
  712. if (!pt->tsc_bit)
  713. return false;
  714. evlist__for_each_entry(pt->session->evlist, evsel) {
  715. if (intel_pt_get_config(pt, &evsel->core.attr, &config)) {
  716. if (config & pt->tsc_bit)
  717. have_tsc = true;
  718. else
  719. return false;
  720. }
  721. }
  722. return have_tsc;
  723. }
  724. static bool intel_pt_sampling_mode(struct intel_pt *pt)
  725. {
  726. struct evsel *evsel;
  727. evlist__for_each_entry(pt->session->evlist, evsel) {
  728. if ((evsel->core.attr.sample_type & PERF_SAMPLE_AUX) &&
  729. evsel->core.attr.aux_sample_size)
  730. return true;
  731. }
  732. return false;
  733. }
  734. static u64 intel_pt_ctl(struct intel_pt *pt)
  735. {
  736. struct evsel *evsel;
  737. u64 config;
  738. evlist__for_each_entry(pt->session->evlist, evsel) {
  739. if (intel_pt_get_config(pt, &evsel->core.attr, &config))
  740. return config;
  741. }
  742. return 0;
  743. }
  744. static u64 intel_pt_ns_to_ticks(const struct intel_pt *pt, u64 ns)
  745. {
  746. u64 quot, rem;
  747. quot = ns / pt->tc.time_mult;
  748. rem = ns % pt->tc.time_mult;
  749. return (quot << pt->tc.time_shift) + (rem << pt->tc.time_shift) /
  750. pt->tc.time_mult;
  751. }
  752. static struct ip_callchain *intel_pt_alloc_chain(struct intel_pt *pt)
  753. {
  754. size_t sz = sizeof(struct ip_callchain);
  755. /* Add 1 to callchain_sz for callchain context */
  756. sz += (pt->synth_opts.callchain_sz + 1) * sizeof(u64);
  757. return zalloc(sz);
  758. }
  759. static int intel_pt_callchain_init(struct intel_pt *pt)
  760. {
  761. struct evsel *evsel;
  762. evlist__for_each_entry(pt->session->evlist, evsel) {
  763. if (!(evsel->core.attr.sample_type & PERF_SAMPLE_CALLCHAIN))
  764. evsel->synth_sample_type |= PERF_SAMPLE_CALLCHAIN;
  765. }
  766. pt->chain = intel_pt_alloc_chain(pt);
  767. if (!pt->chain)
  768. return -ENOMEM;
  769. return 0;
  770. }
  771. static void intel_pt_add_callchain(struct intel_pt *pt,
  772. struct perf_sample *sample)
  773. {
  774. struct thread *thread = machine__findnew_thread(pt->machine,
  775. sample->pid,
  776. sample->tid);
  777. thread_stack__sample_late(thread, sample->cpu, pt->chain,
  778. pt->synth_opts.callchain_sz + 1, sample->ip,
  779. pt->kernel_start);
  780. sample->callchain = pt->chain;
  781. }
  782. static struct branch_stack *intel_pt_alloc_br_stack(unsigned int entry_cnt)
  783. {
  784. size_t sz = sizeof(struct branch_stack);
  785. sz += entry_cnt * sizeof(struct branch_entry);
  786. return zalloc(sz);
  787. }
  788. static int intel_pt_br_stack_init(struct intel_pt *pt)
  789. {
  790. struct evsel *evsel;
  791. evlist__for_each_entry(pt->session->evlist, evsel) {
  792. if (!(evsel->core.attr.sample_type & PERF_SAMPLE_BRANCH_STACK))
  793. evsel->synth_sample_type |= PERF_SAMPLE_BRANCH_STACK;
  794. }
  795. pt->br_stack = intel_pt_alloc_br_stack(pt->br_stack_sz);
  796. if (!pt->br_stack)
  797. return -ENOMEM;
  798. return 0;
  799. }
  800. static void intel_pt_add_br_stack(struct intel_pt *pt,
  801. struct perf_sample *sample)
  802. {
  803. struct thread *thread = machine__findnew_thread(pt->machine,
  804. sample->pid,
  805. sample->tid);
  806. thread_stack__br_sample_late(thread, sample->cpu, pt->br_stack,
  807. pt->br_stack_sz, sample->ip,
  808. pt->kernel_start);
  809. sample->branch_stack = pt->br_stack;
  810. }
  811. /* INTEL_PT_LBR_0, INTEL_PT_LBR_1 and INTEL_PT_LBR_2 */
  812. #define LBRS_MAX (INTEL_PT_BLK_ITEM_ID_CNT * 3U)
  813. static struct intel_pt_queue *intel_pt_alloc_queue(struct intel_pt *pt,
  814. unsigned int queue_nr)
  815. {
  816. struct intel_pt_params params = { .get_trace = 0, };
  817. struct perf_env *env = pt->machine->env;
  818. struct intel_pt_queue *ptq;
  819. ptq = zalloc(sizeof(struct intel_pt_queue));
  820. if (!ptq)
  821. return NULL;
  822. if (pt->synth_opts.callchain) {
  823. ptq->chain = intel_pt_alloc_chain(pt);
  824. if (!ptq->chain)
  825. goto out_free;
  826. }
  827. if (pt->synth_opts.last_branch || pt->synth_opts.other_events) {
  828. unsigned int entry_cnt = max(LBRS_MAX, pt->br_stack_sz);
  829. ptq->last_branch = intel_pt_alloc_br_stack(entry_cnt);
  830. if (!ptq->last_branch)
  831. goto out_free;
  832. }
  833. ptq->event_buf = malloc(PERF_SAMPLE_MAX_SIZE);
  834. if (!ptq->event_buf)
  835. goto out_free;
  836. ptq->pt = pt;
  837. ptq->queue_nr = queue_nr;
  838. ptq->exclude_kernel = intel_pt_exclude_kernel(pt);
  839. ptq->pid = -1;
  840. ptq->tid = -1;
  841. ptq->cpu = -1;
  842. ptq->next_tid = -1;
  843. params.get_trace = intel_pt_get_trace;
  844. params.walk_insn = intel_pt_walk_next_insn;
  845. params.lookahead = intel_pt_lookahead;
  846. params.data = ptq;
  847. params.return_compression = intel_pt_return_compression(pt);
  848. params.branch_enable = intel_pt_branch_enable(pt);
  849. params.ctl = intel_pt_ctl(pt);
  850. params.max_non_turbo_ratio = pt->max_non_turbo_ratio;
  851. params.mtc_period = intel_pt_mtc_period(pt);
  852. params.tsc_ctc_ratio_n = pt->tsc_ctc_ratio_n;
  853. params.tsc_ctc_ratio_d = pt->tsc_ctc_ratio_d;
  854. params.quick = pt->synth_opts.quick;
  855. if (pt->filts.cnt > 0)
  856. params.pgd_ip = intel_pt_pgd_ip;
  857. if (pt->synth_opts.instructions) {
  858. if (pt->synth_opts.period) {
  859. switch (pt->synth_opts.period_type) {
  860. case PERF_ITRACE_PERIOD_INSTRUCTIONS:
  861. params.period_type =
  862. INTEL_PT_PERIOD_INSTRUCTIONS;
  863. params.period = pt->synth_opts.period;
  864. break;
  865. case PERF_ITRACE_PERIOD_TICKS:
  866. params.period_type = INTEL_PT_PERIOD_TICKS;
  867. params.period = pt->synth_opts.period;
  868. break;
  869. case PERF_ITRACE_PERIOD_NANOSECS:
  870. params.period_type = INTEL_PT_PERIOD_TICKS;
  871. params.period = intel_pt_ns_to_ticks(pt,
  872. pt->synth_opts.period);
  873. break;
  874. default:
  875. break;
  876. }
  877. }
  878. if (!params.period) {
  879. params.period_type = INTEL_PT_PERIOD_INSTRUCTIONS;
  880. params.period = 1;
  881. }
  882. }
  883. if (env->cpuid && !strncmp(env->cpuid, "GenuineIntel,6,92,", 18))
  884. params.flags |= INTEL_PT_FUP_WITH_NLIP;
  885. ptq->decoder = intel_pt_decoder_new(&params);
  886. if (!ptq->decoder)
  887. goto out_free;
  888. return ptq;
  889. out_free:
  890. zfree(&ptq->event_buf);
  891. zfree(&ptq->last_branch);
  892. zfree(&ptq->chain);
  893. free(ptq);
  894. return NULL;
  895. }
  896. static void intel_pt_free_queue(void *priv)
  897. {
  898. struct intel_pt_queue *ptq = priv;
  899. if (!ptq)
  900. return;
  901. thread__zput(ptq->thread);
  902. intel_pt_decoder_free(ptq->decoder);
  903. zfree(&ptq->event_buf);
  904. zfree(&ptq->last_branch);
  905. zfree(&ptq->chain);
  906. free(ptq);
  907. }
  908. static void intel_pt_set_pid_tid_cpu(struct intel_pt *pt,
  909. struct auxtrace_queue *queue)
  910. {
  911. struct intel_pt_queue *ptq = queue->priv;
  912. if (queue->tid == -1 || pt->have_sched_switch) {
  913. ptq->tid = machine__get_current_tid(pt->machine, ptq->cpu);
  914. if (ptq->tid == -1)
  915. ptq->pid = -1;
  916. thread__zput(ptq->thread);
  917. }
  918. if (!ptq->thread && ptq->tid != -1)
  919. ptq->thread = machine__find_thread(pt->machine, -1, ptq->tid);
  920. if (ptq->thread) {
  921. ptq->pid = ptq->thread->pid_;
  922. if (queue->cpu == -1)
  923. ptq->cpu = ptq->thread->cpu;
  924. }
  925. }
  926. static void intel_pt_sample_flags(struct intel_pt_queue *ptq)
  927. {
  928. ptq->insn_len = 0;
  929. if (ptq->state->flags & INTEL_PT_ABORT_TX) {
  930. ptq->flags = PERF_IP_FLAG_BRANCH | PERF_IP_FLAG_TX_ABORT;
  931. } else if (ptq->state->flags & INTEL_PT_ASYNC) {
  932. if (ptq->state->to_ip)
  933. ptq->flags = PERF_IP_FLAG_BRANCH | PERF_IP_FLAG_CALL |
  934. PERF_IP_FLAG_ASYNC |
  935. PERF_IP_FLAG_INTERRUPT;
  936. else
  937. ptq->flags = PERF_IP_FLAG_BRANCH |
  938. PERF_IP_FLAG_TRACE_END;
  939. ptq->insn_len = 0;
  940. } else {
  941. if (ptq->state->from_ip)
  942. ptq->flags = intel_pt_insn_type(ptq->state->insn_op);
  943. else
  944. ptq->flags = PERF_IP_FLAG_BRANCH |
  945. PERF_IP_FLAG_TRACE_BEGIN;
  946. if (ptq->state->flags & INTEL_PT_IN_TX)
  947. ptq->flags |= PERF_IP_FLAG_IN_TX;
  948. ptq->insn_len = ptq->state->insn_len;
  949. memcpy(ptq->insn, ptq->state->insn, INTEL_PT_INSN_BUF_SZ);
  950. }
  951. if (ptq->state->type & INTEL_PT_TRACE_BEGIN)
  952. ptq->flags |= PERF_IP_FLAG_TRACE_BEGIN;
  953. if (ptq->state->type & INTEL_PT_TRACE_END)
  954. ptq->flags |= PERF_IP_FLAG_TRACE_END;
  955. }
  956. static void intel_pt_setup_time_range(struct intel_pt *pt,
  957. struct intel_pt_queue *ptq)
  958. {
  959. if (!pt->range_cnt)
  960. return;
  961. ptq->sel_timestamp = pt->time_ranges[0].start;
  962. ptq->sel_idx = 0;
  963. if (ptq->sel_timestamp) {
  964. ptq->sel_start = true;
  965. } else {
  966. ptq->sel_timestamp = pt->time_ranges[0].end;
  967. ptq->sel_start = false;
  968. }
  969. }
  970. static int intel_pt_setup_queue(struct intel_pt *pt,
  971. struct auxtrace_queue *queue,
  972. unsigned int queue_nr)
  973. {
  974. struct intel_pt_queue *ptq = queue->priv;
  975. if (list_empty(&queue->head))
  976. return 0;
  977. if (!ptq) {
  978. ptq = intel_pt_alloc_queue(pt, queue_nr);
  979. if (!ptq)
  980. return -ENOMEM;
  981. queue->priv = ptq;
  982. if (queue->cpu != -1)
  983. ptq->cpu = queue->cpu;
  984. ptq->tid = queue->tid;
  985. ptq->cbr_seen = UINT_MAX;
  986. if (pt->sampling_mode && !pt->snapshot_mode &&
  987. pt->timeless_decoding)
  988. ptq->step_through_buffers = true;
  989. ptq->sync_switch = pt->sync_switch;
  990. intel_pt_setup_time_range(pt, ptq);
  991. }
  992. if (!ptq->on_heap &&
  993. (!ptq->sync_switch ||
  994. ptq->switch_state != INTEL_PT_SS_EXPECTING_SWITCH_EVENT)) {
  995. const struct intel_pt_state *state;
  996. int ret;
  997. if (pt->timeless_decoding)
  998. return 0;
  999. intel_pt_log("queue %u getting timestamp\n", queue_nr);
  1000. intel_pt_log("queue %u decoding cpu %d pid %d tid %d\n",
  1001. queue_nr, ptq->cpu, ptq->pid, ptq->tid);
  1002. if (ptq->sel_start && ptq->sel_timestamp) {
  1003. ret = intel_pt_fast_forward(ptq->decoder,
  1004. ptq->sel_timestamp);
  1005. if (ret)
  1006. return ret;
  1007. }
  1008. while (1) {
  1009. state = intel_pt_decode(ptq->decoder);
  1010. if (state->err) {
  1011. if (state->err == INTEL_PT_ERR_NODATA) {
  1012. intel_pt_log("queue %u has no timestamp\n",
  1013. queue_nr);
  1014. return 0;
  1015. }
  1016. continue;
  1017. }
  1018. if (state->timestamp)
  1019. break;
  1020. }
  1021. ptq->timestamp = state->timestamp;
  1022. intel_pt_log("queue %u timestamp 0x%" PRIx64 "\n",
  1023. queue_nr, ptq->timestamp);
  1024. ptq->state = state;
  1025. ptq->have_sample = true;
  1026. if (ptq->sel_start && ptq->sel_timestamp &&
  1027. ptq->timestamp < ptq->sel_timestamp)
  1028. ptq->have_sample = false;
  1029. intel_pt_sample_flags(ptq);
  1030. ret = auxtrace_heap__add(&pt->heap, queue_nr, ptq->timestamp);
  1031. if (ret)
  1032. return ret;
  1033. ptq->on_heap = true;
  1034. }
  1035. return 0;
  1036. }
  1037. static int intel_pt_setup_queues(struct intel_pt *pt)
  1038. {
  1039. unsigned int i;
  1040. int ret;
  1041. for (i = 0; i < pt->queues.nr_queues; i++) {
  1042. ret = intel_pt_setup_queue(pt, &pt->queues.queue_array[i], i);
  1043. if (ret)
  1044. return ret;
  1045. }
  1046. return 0;
  1047. }
  1048. static inline bool intel_pt_skip_event(struct intel_pt *pt)
  1049. {
  1050. return pt->synth_opts.initial_skip &&
  1051. pt->num_events++ < pt->synth_opts.initial_skip;
  1052. }
  1053. /*
  1054. * Cannot count CBR as skipped because it won't go away until cbr == cbr_seen.
  1055. * Also ensure CBR is first non-skipped event by allowing for 4 more samples
  1056. * from this decoder state.
  1057. */
  1058. static inline bool intel_pt_skip_cbr_event(struct intel_pt *pt)
  1059. {
  1060. return pt->synth_opts.initial_skip &&
  1061. pt->num_events + 4 < pt->synth_opts.initial_skip;
  1062. }
  1063. static void intel_pt_prep_a_sample(struct intel_pt_queue *ptq,
  1064. union perf_event *event,
  1065. struct perf_sample *sample)
  1066. {
  1067. event->sample.header.type = PERF_RECORD_SAMPLE;
  1068. event->sample.header.size = sizeof(struct perf_event_header);
  1069. sample->pid = ptq->pid;
  1070. sample->tid = ptq->tid;
  1071. sample->cpu = ptq->cpu;
  1072. sample->insn_len = ptq->insn_len;
  1073. memcpy(sample->insn, ptq->insn, INTEL_PT_INSN_BUF_SZ);
  1074. }
  1075. static void intel_pt_prep_b_sample(struct intel_pt *pt,
  1076. struct intel_pt_queue *ptq,
  1077. union perf_event *event,
  1078. struct perf_sample *sample)
  1079. {
  1080. intel_pt_prep_a_sample(ptq, event, sample);
  1081. if (!pt->timeless_decoding)
  1082. sample->time = tsc_to_perf_time(ptq->timestamp, &pt->tc);
  1083. sample->ip = ptq->state->from_ip;
  1084. sample->cpumode = intel_pt_cpumode(pt, sample->ip);
  1085. sample->addr = ptq->state->to_ip;
  1086. sample->period = 1;
  1087. sample->flags = ptq->flags;
  1088. event->sample.header.misc = sample->cpumode;
  1089. }
  1090. static int intel_pt_inject_event(union perf_event *event,
  1091. struct perf_sample *sample, u64 type)
  1092. {
  1093. event->header.size = perf_event__sample_event_size(sample, type, 0);
  1094. return perf_event__synthesize_sample(event, type, 0, sample);
  1095. }
  1096. static inline int intel_pt_opt_inject(struct intel_pt *pt,
  1097. union perf_event *event,
  1098. struct perf_sample *sample, u64 type)
  1099. {
  1100. if (!pt->synth_opts.inject)
  1101. return 0;
  1102. return intel_pt_inject_event(event, sample, type);
  1103. }
  1104. static int intel_pt_deliver_synth_event(struct intel_pt *pt,
  1105. union perf_event *event,
  1106. struct perf_sample *sample, u64 type)
  1107. {
  1108. int ret;
  1109. ret = intel_pt_opt_inject(pt, event, sample, type);
  1110. if (ret)
  1111. return ret;
  1112. ret = perf_session__deliver_synth_event(pt->session, event, sample);
  1113. if (ret)
  1114. pr_err("Intel PT: failed to deliver event, error %d\n", ret);
  1115. return ret;
  1116. }
  1117. static int intel_pt_synth_branch_sample(struct intel_pt_queue *ptq)
  1118. {
  1119. struct intel_pt *pt = ptq->pt;
  1120. union perf_event *event = ptq->event_buf;
  1121. struct perf_sample sample = { .ip = 0, };
  1122. struct dummy_branch_stack {
  1123. u64 nr;
  1124. u64 hw_idx;
  1125. struct branch_entry entries;
  1126. } dummy_bs;
  1127. if (pt->branches_filter && !(pt->branches_filter & ptq->flags))
  1128. return 0;
  1129. if (intel_pt_skip_event(pt))
  1130. return 0;
  1131. intel_pt_prep_b_sample(pt, ptq, event, &sample);
  1132. sample.id = ptq->pt->branches_id;
  1133. sample.stream_id = ptq->pt->branches_id;
  1134. /*
  1135. * perf report cannot handle events without a branch stack when using
  1136. * SORT_MODE__BRANCH so make a dummy one.
  1137. */
  1138. if (pt->synth_opts.last_branch && sort__mode == SORT_MODE__BRANCH) {
  1139. dummy_bs = (struct dummy_branch_stack){
  1140. .nr = 1,
  1141. .hw_idx = -1ULL,
  1142. .entries = {
  1143. .from = sample.ip,
  1144. .to = sample.addr,
  1145. },
  1146. };
  1147. sample.branch_stack = (struct branch_stack *)&dummy_bs;
  1148. }
  1149. if (ptq->state->flags & INTEL_PT_SAMPLE_IPC)
  1150. sample.cyc_cnt = ptq->ipc_cyc_cnt - ptq->last_br_cyc_cnt;
  1151. if (sample.cyc_cnt) {
  1152. sample.insn_cnt = ptq->ipc_insn_cnt - ptq->last_br_insn_cnt;
  1153. ptq->last_br_insn_cnt = ptq->ipc_insn_cnt;
  1154. ptq->last_br_cyc_cnt = ptq->ipc_cyc_cnt;
  1155. }
  1156. return intel_pt_deliver_synth_event(pt, event, &sample,
  1157. pt->branches_sample_type);
  1158. }
  1159. static void intel_pt_prep_sample(struct intel_pt *pt,
  1160. struct intel_pt_queue *ptq,
  1161. union perf_event *event,
  1162. struct perf_sample *sample)
  1163. {
  1164. intel_pt_prep_b_sample(pt, ptq, event, sample);
  1165. if (pt->synth_opts.callchain) {
  1166. thread_stack__sample(ptq->thread, ptq->cpu, ptq->chain,
  1167. pt->synth_opts.callchain_sz + 1,
  1168. sample->ip, pt->kernel_start);
  1169. sample->callchain = ptq->chain;
  1170. }
  1171. if (pt->synth_opts.last_branch) {
  1172. thread_stack__br_sample(ptq->thread, ptq->cpu, ptq->last_branch,
  1173. pt->br_stack_sz);
  1174. sample->branch_stack = ptq->last_branch;
  1175. }
  1176. }
  1177. static int intel_pt_synth_instruction_sample(struct intel_pt_queue *ptq)
  1178. {
  1179. struct intel_pt *pt = ptq->pt;
  1180. union perf_event *event = ptq->event_buf;
  1181. struct perf_sample sample = { .ip = 0, };
  1182. if (intel_pt_skip_event(pt))
  1183. return 0;
  1184. intel_pt_prep_sample(pt, ptq, event, &sample);
  1185. sample.id = ptq->pt->instructions_id;
  1186. sample.stream_id = ptq->pt->instructions_id;
  1187. if (pt->synth_opts.quick)
  1188. sample.period = 1;
  1189. else
  1190. sample.period = ptq->state->tot_insn_cnt - ptq->last_insn_cnt;
  1191. if (ptq->state->flags & INTEL_PT_SAMPLE_IPC)
  1192. sample.cyc_cnt = ptq->ipc_cyc_cnt - ptq->last_in_cyc_cnt;
  1193. if (sample.cyc_cnt) {
  1194. sample.insn_cnt = ptq->ipc_insn_cnt - ptq->last_in_insn_cnt;
  1195. ptq->last_in_insn_cnt = ptq->ipc_insn_cnt;
  1196. ptq->last_in_cyc_cnt = ptq->ipc_cyc_cnt;
  1197. }
  1198. ptq->last_insn_cnt = ptq->state->tot_insn_cnt;
  1199. return intel_pt_deliver_synth_event(pt, event, &sample,
  1200. pt->instructions_sample_type);
  1201. }
  1202. static int intel_pt_synth_transaction_sample(struct intel_pt_queue *ptq)
  1203. {
  1204. struct intel_pt *pt = ptq->pt;
  1205. union perf_event *event = ptq->event_buf;
  1206. struct perf_sample sample = { .ip = 0, };
  1207. if (intel_pt_skip_event(pt))
  1208. return 0;
  1209. intel_pt_prep_sample(pt, ptq, event, &sample);
  1210. sample.id = ptq->pt->transactions_id;
  1211. sample.stream_id = ptq->pt->transactions_id;
  1212. return intel_pt_deliver_synth_event(pt, event, &sample,
  1213. pt->transactions_sample_type);
  1214. }
  1215. static void intel_pt_prep_p_sample(struct intel_pt *pt,
  1216. struct intel_pt_queue *ptq,
  1217. union perf_event *event,
  1218. struct perf_sample *sample)
  1219. {
  1220. intel_pt_prep_sample(pt, ptq, event, sample);
  1221. /*
  1222. * Zero IP is used to mean "trace start" but that is not the case for
  1223. * power or PTWRITE events with no IP, so clear the flags.
  1224. */
  1225. if (!sample->ip)
  1226. sample->flags = 0;
  1227. }
  1228. static int intel_pt_synth_ptwrite_sample(struct intel_pt_queue *ptq)
  1229. {
  1230. struct intel_pt *pt = ptq->pt;
  1231. union perf_event *event = ptq->event_buf;
  1232. struct perf_sample sample = { .ip = 0, };
  1233. struct perf_synth_intel_ptwrite raw;
  1234. if (intel_pt_skip_event(pt))
  1235. return 0;
  1236. intel_pt_prep_p_sample(pt, ptq, event, &sample);
  1237. sample.id = ptq->pt->ptwrites_id;
  1238. sample.stream_id = ptq->pt->ptwrites_id;
  1239. raw.flags = 0;
  1240. raw.ip = !!(ptq->state->flags & INTEL_PT_FUP_IP);
  1241. raw.payload = cpu_to_le64(ptq->state->ptw_payload);
  1242. sample.raw_size = perf_synth__raw_size(raw);
  1243. sample.raw_data = perf_synth__raw_data(&raw);
  1244. return intel_pt_deliver_synth_event(pt, event, &sample,
  1245. pt->ptwrites_sample_type);
  1246. }
  1247. static int intel_pt_synth_cbr_sample(struct intel_pt_queue *ptq)
  1248. {
  1249. struct intel_pt *pt = ptq->pt;
  1250. union perf_event *event = ptq->event_buf;
  1251. struct perf_sample sample = { .ip = 0, };
  1252. struct perf_synth_intel_cbr raw;
  1253. u32 flags;
  1254. if (intel_pt_skip_cbr_event(pt))
  1255. return 0;
  1256. ptq->cbr_seen = ptq->state->cbr;
  1257. intel_pt_prep_p_sample(pt, ptq, event, &sample);
  1258. sample.id = ptq->pt->cbr_id;
  1259. sample.stream_id = ptq->pt->cbr_id;
  1260. flags = (u16)ptq->state->cbr_payload | (pt->max_non_turbo_ratio << 16);
  1261. raw.flags = cpu_to_le32(flags);
  1262. raw.freq = cpu_to_le32(raw.cbr * pt->cbr2khz);
  1263. raw.reserved3 = 0;
  1264. sample.raw_size = perf_synth__raw_size(raw);
  1265. sample.raw_data = perf_synth__raw_data(&raw);
  1266. return intel_pt_deliver_synth_event(pt, event, &sample,
  1267. pt->pwr_events_sample_type);
  1268. }
  1269. static int intel_pt_synth_mwait_sample(struct intel_pt_queue *ptq)
  1270. {
  1271. struct intel_pt *pt = ptq->pt;
  1272. union perf_event *event = ptq->event_buf;
  1273. struct perf_sample sample = { .ip = 0, };
  1274. struct perf_synth_intel_mwait raw;
  1275. if (intel_pt_skip_event(pt))
  1276. return 0;
  1277. intel_pt_prep_p_sample(pt, ptq, event, &sample);
  1278. sample.id = ptq->pt->mwait_id;
  1279. sample.stream_id = ptq->pt->mwait_id;
  1280. raw.reserved = 0;
  1281. raw.payload = cpu_to_le64(ptq->state->mwait_payload);
  1282. sample.raw_size = perf_synth__raw_size(raw);
  1283. sample.raw_data = perf_synth__raw_data(&raw);
  1284. return intel_pt_deliver_synth_event(pt, event, &sample,
  1285. pt->pwr_events_sample_type);
  1286. }
  1287. static int intel_pt_synth_pwre_sample(struct intel_pt_queue *ptq)
  1288. {
  1289. struct intel_pt *pt = ptq->pt;
  1290. union perf_event *event = ptq->event_buf;
  1291. struct perf_sample sample = { .ip = 0, };
  1292. struct perf_synth_intel_pwre raw;
  1293. if (intel_pt_skip_event(pt))
  1294. return 0;
  1295. intel_pt_prep_p_sample(pt, ptq, event, &sample);
  1296. sample.id = ptq->pt->pwre_id;
  1297. sample.stream_id = ptq->pt->pwre_id;
  1298. raw.reserved = 0;
  1299. raw.payload = cpu_to_le64(ptq->state->pwre_payload);
  1300. sample.raw_size = perf_synth__raw_size(raw);
  1301. sample.raw_data = perf_synth__raw_data(&raw);
  1302. return intel_pt_deliver_synth_event(pt, event, &sample,
  1303. pt->pwr_events_sample_type);
  1304. }
  1305. static int intel_pt_synth_exstop_sample(struct intel_pt_queue *ptq)
  1306. {
  1307. struct intel_pt *pt = ptq->pt;
  1308. union perf_event *event = ptq->event_buf;
  1309. struct perf_sample sample = { .ip = 0, };
  1310. struct perf_synth_intel_exstop raw;
  1311. if (intel_pt_skip_event(pt))
  1312. return 0;
  1313. intel_pt_prep_p_sample(pt, ptq, event, &sample);
  1314. sample.id = ptq->pt->exstop_id;
  1315. sample.stream_id = ptq->pt->exstop_id;
  1316. raw.flags = 0;
  1317. raw.ip = !!(ptq->state->flags & INTEL_PT_FUP_IP);
  1318. sample.raw_size = perf_synth__raw_size(raw);
  1319. sample.raw_data = perf_synth__raw_data(&raw);
  1320. return intel_pt_deliver_synth_event(pt, event, &sample,
  1321. pt->pwr_events_sample_type);
  1322. }
  1323. static int intel_pt_synth_pwrx_sample(struct intel_pt_queue *ptq)
  1324. {
  1325. struct intel_pt *pt = ptq->pt;
  1326. union perf_event *event = ptq->event_buf;
  1327. struct perf_sample sample = { .ip = 0, };
  1328. struct perf_synth_intel_pwrx raw;
  1329. if (intel_pt_skip_event(pt))
  1330. return 0;
  1331. intel_pt_prep_p_sample(pt, ptq, event, &sample);
  1332. sample.id = ptq->pt->pwrx_id;
  1333. sample.stream_id = ptq->pt->pwrx_id;
  1334. raw.reserved = 0;
  1335. raw.payload = cpu_to_le64(ptq->state->pwrx_payload);
  1336. sample.raw_size = perf_synth__raw_size(raw);
  1337. sample.raw_data = perf_synth__raw_data(&raw);
  1338. return intel_pt_deliver_synth_event(pt, event, &sample,
  1339. pt->pwr_events_sample_type);
  1340. }
  1341. /*
  1342. * PEBS gp_regs array indexes plus 1 so that 0 means not present. Refer
  1343. * intel_pt_add_gp_regs().
  1344. */
  1345. static const int pebs_gp_regs[] = {
  1346. [PERF_REG_X86_FLAGS] = 1,
  1347. [PERF_REG_X86_IP] = 2,
  1348. [PERF_REG_X86_AX] = 3,
  1349. [PERF_REG_X86_CX] = 4,
  1350. [PERF_REG_X86_DX] = 5,
  1351. [PERF_REG_X86_BX] = 6,
  1352. [PERF_REG_X86_SP] = 7,
  1353. [PERF_REG_X86_BP] = 8,
  1354. [PERF_REG_X86_SI] = 9,
  1355. [PERF_REG_X86_DI] = 10,
  1356. [PERF_REG_X86_R8] = 11,
  1357. [PERF_REG_X86_R9] = 12,
  1358. [PERF_REG_X86_R10] = 13,
  1359. [PERF_REG_X86_R11] = 14,
  1360. [PERF_REG_X86_R12] = 15,
  1361. [PERF_REG_X86_R13] = 16,
  1362. [PERF_REG_X86_R14] = 17,
  1363. [PERF_REG_X86_R15] = 18,
  1364. };
  1365. static u64 *intel_pt_add_gp_regs(struct regs_dump *intr_regs, u64 *pos,
  1366. const struct intel_pt_blk_items *items,
  1367. u64 regs_mask)
  1368. {
  1369. const u64 *gp_regs = items->val[INTEL_PT_GP_REGS_POS];
  1370. u32 mask = items->mask[INTEL_PT_GP_REGS_POS];
  1371. u32 bit;
  1372. int i;
  1373. for (i = 0, bit = 1; i < PERF_REG_X86_64_MAX; i++, bit <<= 1) {
  1374. /* Get the PEBS gp_regs array index */
  1375. int n = pebs_gp_regs[i] - 1;
  1376. if (n < 0)
  1377. continue;
  1378. /*
  1379. * Add only registers that were requested (i.e. 'regs_mask') and
  1380. * that were provided (i.e. 'mask'), and update the resulting
  1381. * mask (i.e. 'intr_regs->mask') accordingly.
  1382. */
  1383. if (mask & 1 << n && regs_mask & bit) {
  1384. intr_regs->mask |= bit;
  1385. *pos++ = gp_regs[n];
  1386. }
  1387. }
  1388. return pos;
  1389. }
  1390. #ifndef PERF_REG_X86_XMM0
  1391. #define PERF_REG_X86_XMM0 32
  1392. #endif
  1393. static void intel_pt_add_xmm(struct regs_dump *intr_regs, u64 *pos,
  1394. const struct intel_pt_blk_items *items,
  1395. u64 regs_mask)
  1396. {
  1397. u32 mask = items->has_xmm & (regs_mask >> PERF_REG_X86_XMM0);
  1398. const u64 *xmm = items->xmm;
  1399. /*
  1400. * If there are any XMM registers, then there should be all of them.
  1401. * Nevertheless, follow the logic to add only registers that were
  1402. * requested (i.e. 'regs_mask') and that were provided (i.e. 'mask'),
  1403. * and update the resulting mask (i.e. 'intr_regs->mask') accordingly.
  1404. */
  1405. intr_regs->mask |= (u64)mask << PERF_REG_X86_XMM0;
  1406. for (; mask; mask >>= 1, xmm++) {
  1407. if (mask & 1)
  1408. *pos++ = *xmm;
  1409. }
  1410. }
  1411. #define LBR_INFO_MISPRED (1ULL << 63)
  1412. #define LBR_INFO_IN_TX (1ULL << 62)
  1413. #define LBR_INFO_ABORT (1ULL << 61)
  1414. #define LBR_INFO_CYCLES 0xffff
  1415. /* Refer kernel's intel_pmu_store_pebs_lbrs() */
  1416. static u64 intel_pt_lbr_flags(u64 info)
  1417. {
  1418. union {
  1419. struct branch_flags flags;
  1420. u64 result;
  1421. } u;
  1422. u.result = 0;
  1423. u.flags.mispred = !!(info & LBR_INFO_MISPRED);
  1424. u.flags.predicted = !(info & LBR_INFO_MISPRED);
  1425. u.flags.in_tx = !!(info & LBR_INFO_IN_TX);
  1426. u.flags.abort = !!(info & LBR_INFO_ABORT);
  1427. u.flags.cycles = info & LBR_INFO_CYCLES;
  1428. return u.result;
  1429. }
  1430. static void intel_pt_add_lbrs(struct branch_stack *br_stack,
  1431. const struct intel_pt_blk_items *items)
  1432. {
  1433. u64 *to;
  1434. int i;
  1435. br_stack->nr = 0;
  1436. to = &br_stack->entries[0].from;
  1437. for (i = INTEL_PT_LBR_0_POS; i <= INTEL_PT_LBR_2_POS; i++) {
  1438. u32 mask = items->mask[i];
  1439. const u64 *from = items->val[i];
  1440. for (; mask; mask >>= 3, from += 3) {
  1441. if ((mask & 7) == 7) {
  1442. *to++ = from[0];
  1443. *to++ = from[1];
  1444. *to++ = intel_pt_lbr_flags(from[2]);
  1445. br_stack->nr += 1;
  1446. }
  1447. }
  1448. }
  1449. }
  1450. static int intel_pt_synth_pebs_sample(struct intel_pt_queue *ptq)
  1451. {
  1452. const struct intel_pt_blk_items *items = &ptq->state->items;
  1453. struct perf_sample sample = { .ip = 0, };
  1454. union perf_event *event = ptq->event_buf;
  1455. struct intel_pt *pt = ptq->pt;
  1456. struct evsel *evsel = pt->pebs_evsel;
  1457. u64 sample_type = evsel->core.attr.sample_type;
  1458. u64 id = evsel->core.id[0];
  1459. u8 cpumode;
  1460. u64 regs[8 * sizeof(sample.intr_regs.mask)];
  1461. if (intel_pt_skip_event(pt))
  1462. return 0;
  1463. intel_pt_prep_a_sample(ptq, event, &sample);
  1464. sample.id = id;
  1465. sample.stream_id = id;
  1466. if (!evsel->core.attr.freq)
  1467. sample.period = evsel->core.attr.sample_period;
  1468. /* No support for non-zero CS base */
  1469. if (items->has_ip)
  1470. sample.ip = items->ip;
  1471. else if (items->has_rip)
  1472. sample.ip = items->rip;
  1473. else
  1474. sample.ip = ptq->state->from_ip;
  1475. /* No support for guest mode at this time */
  1476. cpumode = sample.ip < ptq->pt->kernel_start ?
  1477. PERF_RECORD_MISC_USER :
  1478. PERF_RECORD_MISC_KERNEL;
  1479. event->sample.header.misc = cpumode | PERF_RECORD_MISC_EXACT_IP;
  1480. sample.cpumode = cpumode;
  1481. if (sample_type & PERF_SAMPLE_TIME) {
  1482. u64 timestamp = 0;
  1483. if (items->has_timestamp)
  1484. timestamp = items->timestamp;
  1485. else if (!pt->timeless_decoding)
  1486. timestamp = ptq->timestamp;
  1487. if (timestamp)
  1488. sample.time = tsc_to_perf_time(timestamp, &pt->tc);
  1489. }
  1490. if (sample_type & PERF_SAMPLE_CALLCHAIN &&
  1491. pt->synth_opts.callchain) {
  1492. thread_stack__sample(ptq->thread, ptq->cpu, ptq->chain,
  1493. pt->synth_opts.callchain_sz, sample.ip,
  1494. pt->kernel_start);
  1495. sample.callchain = ptq->chain;
  1496. }
  1497. if (sample_type & PERF_SAMPLE_REGS_INTR &&
  1498. (items->mask[INTEL_PT_GP_REGS_POS] ||
  1499. items->mask[INTEL_PT_XMM_POS])) {
  1500. u64 regs_mask = evsel->core.attr.sample_regs_intr;
  1501. u64 *pos;
  1502. sample.intr_regs.abi = items->is_32_bit ?
  1503. PERF_SAMPLE_REGS_ABI_32 :
  1504. PERF_SAMPLE_REGS_ABI_64;
  1505. sample.intr_regs.regs = regs;
  1506. pos = intel_pt_add_gp_regs(&sample.intr_regs, regs, items, regs_mask);
  1507. intel_pt_add_xmm(&sample.intr_regs, pos, items, regs_mask);
  1508. }
  1509. if (sample_type & PERF_SAMPLE_BRANCH_STACK) {
  1510. if (items->mask[INTEL_PT_LBR_0_POS] ||
  1511. items->mask[INTEL_PT_LBR_1_POS] ||
  1512. items->mask[INTEL_PT_LBR_2_POS]) {
  1513. intel_pt_add_lbrs(ptq->last_branch, items);
  1514. } else if (pt->synth_opts.last_branch) {
  1515. thread_stack__br_sample(ptq->thread, ptq->cpu,
  1516. ptq->last_branch,
  1517. pt->br_stack_sz);
  1518. } else {
  1519. ptq->last_branch->nr = 0;
  1520. }
  1521. sample.branch_stack = ptq->last_branch;
  1522. }
  1523. if (sample_type & PERF_SAMPLE_ADDR && items->has_mem_access_address)
  1524. sample.addr = items->mem_access_address;
  1525. if (sample_type & PERF_SAMPLE_WEIGHT) {
  1526. /*
  1527. * Refer kernel's setup_pebs_adaptive_sample_data() and
  1528. * intel_hsw_weight().
  1529. */
  1530. if (items->has_mem_access_latency)
  1531. sample.weight = items->mem_access_latency;
  1532. if (!sample.weight && items->has_tsx_aux_info) {
  1533. /* Cycles last block */
  1534. sample.weight = (u32)items->tsx_aux_info;
  1535. }
  1536. }
  1537. if (sample_type & PERF_SAMPLE_TRANSACTION && items->has_tsx_aux_info) {
  1538. u64 ax = items->has_rax ? items->rax : 0;
  1539. /* Refer kernel's intel_hsw_transaction() */
  1540. u64 txn = (u8)(items->tsx_aux_info >> 32);
  1541. /* For RTM XABORTs also log the abort code from AX */
  1542. if (txn & PERF_TXN_TRANSACTION && ax & 1)
  1543. txn |= ((ax >> 24) & 0xff) << PERF_TXN_ABORT_SHIFT;
  1544. sample.transaction = txn;
  1545. }
  1546. return intel_pt_deliver_synth_event(pt, event, &sample, sample_type);
  1547. }
  1548. static int intel_pt_synth_error(struct intel_pt *pt, int code, int cpu,
  1549. pid_t pid, pid_t tid, u64 ip, u64 timestamp)
  1550. {
  1551. union perf_event event;
  1552. char msg[MAX_AUXTRACE_ERROR_MSG];
  1553. int err;
  1554. if (pt->synth_opts.error_minus_flags) {
  1555. if (code == INTEL_PT_ERR_OVR &&
  1556. pt->synth_opts.error_minus_flags & AUXTRACE_ERR_FLG_OVERFLOW)
  1557. return 0;
  1558. if (code == INTEL_PT_ERR_LOST &&
  1559. pt->synth_opts.error_minus_flags & AUXTRACE_ERR_FLG_DATA_LOST)
  1560. return 0;
  1561. }
  1562. intel_pt__strerror(code, msg, MAX_AUXTRACE_ERROR_MSG);
  1563. auxtrace_synth_error(&event.auxtrace_error, PERF_AUXTRACE_ERROR_ITRACE,
  1564. code, cpu, pid, tid, ip, msg, timestamp);
  1565. err = perf_session__deliver_synth_event(pt->session, &event, NULL);
  1566. if (err)
  1567. pr_err("Intel Processor Trace: failed to deliver error event, error %d\n",
  1568. err);
  1569. return err;
  1570. }
  1571. static int intel_ptq_synth_error(struct intel_pt_queue *ptq,
  1572. const struct intel_pt_state *state)
  1573. {
  1574. struct intel_pt *pt = ptq->pt;
  1575. u64 tm = ptq->timestamp;
  1576. tm = pt->timeless_decoding ? 0 : tsc_to_perf_time(tm, &pt->tc);
  1577. return intel_pt_synth_error(pt, state->err, ptq->cpu, ptq->pid,
  1578. ptq->tid, state->from_ip, tm);
  1579. }
  1580. static int intel_pt_next_tid(struct intel_pt *pt, struct intel_pt_queue *ptq)
  1581. {
  1582. struct auxtrace_queue *queue;
  1583. pid_t tid = ptq->next_tid;
  1584. int err;
  1585. if (tid == -1)
  1586. return 0;
  1587. intel_pt_log("switch: cpu %d tid %d\n", ptq->cpu, tid);
  1588. err = machine__set_current_tid(pt->machine, ptq->cpu, -1, tid);
  1589. queue = &pt->queues.queue_array[ptq->queue_nr];
  1590. intel_pt_set_pid_tid_cpu(pt, queue);
  1591. ptq->next_tid = -1;
  1592. return err;
  1593. }
  1594. static inline bool intel_pt_is_switch_ip(struct intel_pt_queue *ptq, u64 ip)
  1595. {
  1596. struct intel_pt *pt = ptq->pt;
  1597. return ip == pt->switch_ip &&
  1598. (ptq->flags & PERF_IP_FLAG_BRANCH) &&
  1599. !(ptq->flags & (PERF_IP_FLAG_CONDITIONAL | PERF_IP_FLAG_ASYNC |
  1600. PERF_IP_FLAG_INTERRUPT | PERF_IP_FLAG_TX_ABORT));
  1601. }
  1602. #define INTEL_PT_PWR_EVT (INTEL_PT_MWAIT_OP | INTEL_PT_PWR_ENTRY | \
  1603. INTEL_PT_EX_STOP | INTEL_PT_PWR_EXIT)
  1604. static int intel_pt_sample(struct intel_pt_queue *ptq)
  1605. {
  1606. const struct intel_pt_state *state = ptq->state;
  1607. struct intel_pt *pt = ptq->pt;
  1608. int err;
  1609. if (!ptq->have_sample)
  1610. return 0;
  1611. ptq->have_sample = false;
  1612. ptq->ipc_insn_cnt = ptq->state->tot_insn_cnt;
  1613. ptq->ipc_cyc_cnt = ptq->state->tot_cyc_cnt;
  1614. /*
  1615. * Do PEBS first to allow for the possibility that the PEBS timestamp
  1616. * precedes the current timestamp.
  1617. */
  1618. if (pt->sample_pebs && state->type & INTEL_PT_BLK_ITEMS) {
  1619. err = intel_pt_synth_pebs_sample(ptq);
  1620. if (err)
  1621. return err;
  1622. }
  1623. if (pt->sample_pwr_events) {
  1624. if (ptq->state->cbr != ptq->cbr_seen) {
  1625. err = intel_pt_synth_cbr_sample(ptq);
  1626. if (err)
  1627. return err;
  1628. }
  1629. if (state->type & INTEL_PT_PWR_EVT) {
  1630. if (state->type & INTEL_PT_MWAIT_OP) {
  1631. err = intel_pt_synth_mwait_sample(ptq);
  1632. if (err)
  1633. return err;
  1634. }
  1635. if (state->type & INTEL_PT_PWR_ENTRY) {
  1636. err = intel_pt_synth_pwre_sample(ptq);
  1637. if (err)
  1638. return err;
  1639. }
  1640. if (state->type & INTEL_PT_EX_STOP) {
  1641. err = intel_pt_synth_exstop_sample(ptq);
  1642. if (err)
  1643. return err;
  1644. }
  1645. if (state->type & INTEL_PT_PWR_EXIT) {
  1646. err = intel_pt_synth_pwrx_sample(ptq);
  1647. if (err)
  1648. return err;
  1649. }
  1650. }
  1651. }
  1652. if (pt->sample_instructions && (state->type & INTEL_PT_INSTRUCTION)) {
  1653. err = intel_pt_synth_instruction_sample(ptq);
  1654. if (err)
  1655. return err;
  1656. }
  1657. if (pt->sample_transactions && (state->type & INTEL_PT_TRANSACTION)) {
  1658. err = intel_pt_synth_transaction_sample(ptq);
  1659. if (err)
  1660. return err;
  1661. }
  1662. if (pt->sample_ptwrites && (state->type & INTEL_PT_PTW)) {
  1663. err = intel_pt_synth_ptwrite_sample(ptq);
  1664. if (err)
  1665. return err;
  1666. }
  1667. if (!(state->type & INTEL_PT_BRANCH))
  1668. return 0;
  1669. if (pt->use_thread_stack) {
  1670. thread_stack__event(ptq->thread, ptq->cpu, ptq->flags,
  1671. state->from_ip, state->to_ip, ptq->insn_len,
  1672. state->trace_nr, pt->callstack,
  1673. pt->br_stack_sz_plus,
  1674. pt->mispred_all);
  1675. } else {
  1676. thread_stack__set_trace_nr(ptq->thread, ptq->cpu, state->trace_nr);
  1677. }
  1678. if (pt->sample_branches) {
  1679. err = intel_pt_synth_branch_sample(ptq);
  1680. if (err)
  1681. return err;
  1682. }
  1683. if (!ptq->sync_switch)
  1684. return 0;
  1685. if (intel_pt_is_switch_ip(ptq, state->to_ip)) {
  1686. switch (ptq->switch_state) {
  1687. case INTEL_PT_SS_NOT_TRACING:
  1688. case INTEL_PT_SS_UNKNOWN:
  1689. case INTEL_PT_SS_EXPECTING_SWITCH_IP:
  1690. err = intel_pt_next_tid(pt, ptq);
  1691. if (err)
  1692. return err;
  1693. ptq->switch_state = INTEL_PT_SS_TRACING;
  1694. break;
  1695. default:
  1696. ptq->switch_state = INTEL_PT_SS_EXPECTING_SWITCH_EVENT;
  1697. return 1;
  1698. }
  1699. } else if (!state->to_ip) {
  1700. ptq->switch_state = INTEL_PT_SS_NOT_TRACING;
  1701. } else if (ptq->switch_state == INTEL_PT_SS_NOT_TRACING) {
  1702. ptq->switch_state = INTEL_PT_SS_UNKNOWN;
  1703. } else if (ptq->switch_state == INTEL_PT_SS_UNKNOWN &&
  1704. state->to_ip == pt->ptss_ip &&
  1705. (ptq->flags & PERF_IP_FLAG_CALL)) {
  1706. ptq->switch_state = INTEL_PT_SS_TRACING;
  1707. }
  1708. return 0;
  1709. }
  1710. static u64 intel_pt_switch_ip(struct intel_pt *pt, u64 *ptss_ip)
  1711. {
  1712. struct machine *machine = pt->machine;
  1713. struct map *map;
  1714. struct symbol *sym, *start;
  1715. u64 ip, switch_ip = 0;
  1716. const char *ptss;
  1717. if (ptss_ip)
  1718. *ptss_ip = 0;
  1719. map = machine__kernel_map(machine);
  1720. if (!map)
  1721. return 0;
  1722. if (map__load(map))
  1723. return 0;
  1724. start = dso__first_symbol(map->dso);
  1725. for (sym = start; sym; sym = dso__next_symbol(sym)) {
  1726. if (sym->binding == STB_GLOBAL &&
  1727. !strcmp(sym->name, "__switch_to")) {
  1728. ip = map->unmap_ip(map, sym->start);
  1729. if (ip >= map->start && ip < map->end) {
  1730. switch_ip = ip;
  1731. break;
  1732. }
  1733. }
  1734. }
  1735. if (!switch_ip || !ptss_ip)
  1736. return 0;
  1737. if (pt->have_sched_switch == 1)
  1738. ptss = "perf_trace_sched_switch";
  1739. else
  1740. ptss = "__perf_event_task_sched_out";
  1741. for (sym = start; sym; sym = dso__next_symbol(sym)) {
  1742. if (!strcmp(sym->name, ptss)) {
  1743. ip = map->unmap_ip(map, sym->start);
  1744. if (ip >= map->start && ip < map->end) {
  1745. *ptss_ip = ip;
  1746. break;
  1747. }
  1748. }
  1749. }
  1750. return switch_ip;
  1751. }
  1752. static void intel_pt_enable_sync_switch(struct intel_pt *pt)
  1753. {
  1754. unsigned int i;
  1755. pt->sync_switch = true;
  1756. for (i = 0; i < pt->queues.nr_queues; i++) {
  1757. struct auxtrace_queue *queue = &pt->queues.queue_array[i];
  1758. struct intel_pt_queue *ptq = queue->priv;
  1759. if (ptq)
  1760. ptq->sync_switch = true;
  1761. }
  1762. }
  1763. /*
  1764. * To filter against time ranges, it is only necessary to look at the next start
  1765. * or end time.
  1766. */
  1767. static bool intel_pt_next_time(struct intel_pt_queue *ptq)
  1768. {
  1769. struct intel_pt *pt = ptq->pt;
  1770. if (ptq->sel_start) {
  1771. /* Next time is an end time */
  1772. ptq->sel_start = false;
  1773. ptq->sel_timestamp = pt->time_ranges[ptq->sel_idx].end;
  1774. return true;
  1775. } else if (ptq->sel_idx + 1 < pt->range_cnt) {
  1776. /* Next time is a start time */
  1777. ptq->sel_start = true;
  1778. ptq->sel_idx += 1;
  1779. ptq->sel_timestamp = pt->time_ranges[ptq->sel_idx].start;
  1780. return true;
  1781. }
  1782. /* No next time */
  1783. return false;
  1784. }
  1785. static int intel_pt_time_filter(struct intel_pt_queue *ptq, u64 *ff_timestamp)
  1786. {
  1787. int err;
  1788. while (1) {
  1789. if (ptq->sel_start) {
  1790. if (ptq->timestamp >= ptq->sel_timestamp) {
  1791. /* After start time, so consider next time */
  1792. intel_pt_next_time(ptq);
  1793. if (!ptq->sel_timestamp) {
  1794. /* No end time */
  1795. return 0;
  1796. }
  1797. /* Check against end time */
  1798. continue;
  1799. }
  1800. /* Before start time, so fast forward */
  1801. ptq->have_sample = false;
  1802. if (ptq->sel_timestamp > *ff_timestamp) {
  1803. if (ptq->sync_switch) {
  1804. intel_pt_next_tid(ptq->pt, ptq);
  1805. ptq->switch_state = INTEL_PT_SS_UNKNOWN;
  1806. }
  1807. *ff_timestamp = ptq->sel_timestamp;
  1808. err = intel_pt_fast_forward(ptq->decoder,
  1809. ptq->sel_timestamp);
  1810. if (err)
  1811. return err;
  1812. }
  1813. return 0;
  1814. } else if (ptq->timestamp > ptq->sel_timestamp) {
  1815. /* After end time, so consider next time */
  1816. if (!intel_pt_next_time(ptq)) {
  1817. /* No next time range, so stop decoding */
  1818. ptq->have_sample = false;
  1819. ptq->switch_state = INTEL_PT_SS_NOT_TRACING;
  1820. return 1;
  1821. }
  1822. /* Check against next start time */
  1823. continue;
  1824. } else {
  1825. /* Before end time */
  1826. return 0;
  1827. }
  1828. }
  1829. }
  1830. static int intel_pt_run_decoder(struct intel_pt_queue *ptq, u64 *timestamp)
  1831. {
  1832. const struct intel_pt_state *state = ptq->state;
  1833. struct intel_pt *pt = ptq->pt;
  1834. u64 ff_timestamp = 0;
  1835. int err;
  1836. if (!pt->kernel_start) {
  1837. pt->kernel_start = machine__kernel_start(pt->machine);
  1838. if (pt->per_cpu_mmaps &&
  1839. (pt->have_sched_switch == 1 || pt->have_sched_switch == 3) &&
  1840. !pt->timeless_decoding && intel_pt_tracing_kernel(pt) &&
  1841. !pt->sampling_mode) {
  1842. pt->switch_ip = intel_pt_switch_ip(pt, &pt->ptss_ip);
  1843. if (pt->switch_ip) {
  1844. intel_pt_log("switch_ip: %"PRIx64" ptss_ip: %"PRIx64"\n",
  1845. pt->switch_ip, pt->ptss_ip);
  1846. intel_pt_enable_sync_switch(pt);
  1847. }
  1848. }
  1849. }
  1850. intel_pt_log("queue %u decoding cpu %d pid %d tid %d\n",
  1851. ptq->queue_nr, ptq->cpu, ptq->pid, ptq->tid);
  1852. while (1) {
  1853. err = intel_pt_sample(ptq);
  1854. if (err)
  1855. return err;
  1856. state = intel_pt_decode(ptq->decoder);
  1857. if (state->err) {
  1858. if (state->err == INTEL_PT_ERR_NODATA)
  1859. return 1;
  1860. if (ptq->sync_switch &&
  1861. state->from_ip >= pt->kernel_start) {
  1862. ptq->sync_switch = false;
  1863. intel_pt_next_tid(pt, ptq);
  1864. }
  1865. ptq->timestamp = state->est_timestamp;
  1866. if (pt->synth_opts.errors) {
  1867. err = intel_ptq_synth_error(ptq, state);
  1868. if (err)
  1869. return err;
  1870. }
  1871. continue;
  1872. }
  1873. ptq->state = state;
  1874. ptq->have_sample = true;
  1875. intel_pt_sample_flags(ptq);
  1876. /* Use estimated TSC upon return to user space */
  1877. if (pt->est_tsc &&
  1878. (state->from_ip >= pt->kernel_start || !state->from_ip) &&
  1879. state->to_ip && state->to_ip < pt->kernel_start) {
  1880. intel_pt_log("TSC %"PRIx64" est. TSC %"PRIx64"\n",
  1881. state->timestamp, state->est_timestamp);
  1882. ptq->timestamp = state->est_timestamp;
  1883. /* Use estimated TSC in unknown switch state */
  1884. } else if (ptq->sync_switch &&
  1885. ptq->switch_state == INTEL_PT_SS_UNKNOWN &&
  1886. intel_pt_is_switch_ip(ptq, state->to_ip) &&
  1887. ptq->next_tid == -1) {
  1888. intel_pt_log("TSC %"PRIx64" est. TSC %"PRIx64"\n",
  1889. state->timestamp, state->est_timestamp);
  1890. ptq->timestamp = state->est_timestamp;
  1891. } else if (state->timestamp > ptq->timestamp) {
  1892. ptq->timestamp = state->timestamp;
  1893. }
  1894. if (ptq->sel_timestamp) {
  1895. err = intel_pt_time_filter(ptq, &ff_timestamp);
  1896. if (err)
  1897. return err;
  1898. }
  1899. if (!pt->timeless_decoding && ptq->timestamp >= *timestamp) {
  1900. *timestamp = ptq->timestamp;
  1901. return 0;
  1902. }
  1903. }
  1904. return 0;
  1905. }
  1906. static inline int intel_pt_update_queues(struct intel_pt *pt)
  1907. {
  1908. if (pt->queues.new_data) {
  1909. pt->queues.new_data = false;
  1910. return intel_pt_setup_queues(pt);
  1911. }
  1912. return 0;
  1913. }
  1914. static int intel_pt_process_queues(struct intel_pt *pt, u64 timestamp)
  1915. {
  1916. unsigned int queue_nr;
  1917. u64 ts;
  1918. int ret;
  1919. while (1) {
  1920. struct auxtrace_queue *queue;
  1921. struct intel_pt_queue *ptq;
  1922. if (!pt->heap.heap_cnt)
  1923. return 0;
  1924. if (pt->heap.heap_array[0].ordinal >= timestamp)
  1925. return 0;
  1926. queue_nr = pt->heap.heap_array[0].queue_nr;
  1927. queue = &pt->queues.queue_array[queue_nr];
  1928. ptq = queue->priv;
  1929. intel_pt_log("queue %u processing 0x%" PRIx64 " to 0x%" PRIx64 "\n",
  1930. queue_nr, pt->heap.heap_array[0].ordinal,
  1931. timestamp);
  1932. auxtrace_heap__pop(&pt->heap);
  1933. if (pt->heap.heap_cnt) {
  1934. ts = pt->heap.heap_array[0].ordinal + 1;
  1935. if (ts > timestamp)
  1936. ts = timestamp;
  1937. } else {
  1938. ts = timestamp;
  1939. }
  1940. intel_pt_set_pid_tid_cpu(pt, queue);
  1941. ret = intel_pt_run_decoder(ptq, &ts);
  1942. if (ret < 0) {
  1943. auxtrace_heap__add(&pt->heap, queue_nr, ts);
  1944. return ret;
  1945. }
  1946. if (!ret) {
  1947. ret = auxtrace_heap__add(&pt->heap, queue_nr, ts);
  1948. if (ret < 0)
  1949. return ret;
  1950. } else {
  1951. ptq->on_heap = false;
  1952. }
  1953. }
  1954. return 0;
  1955. }
  1956. static int intel_pt_process_timeless_queues(struct intel_pt *pt, pid_t tid,
  1957. u64 time_)
  1958. {
  1959. struct auxtrace_queues *queues = &pt->queues;
  1960. unsigned int i;
  1961. u64 ts = 0;
  1962. for (i = 0; i < queues->nr_queues; i++) {
  1963. struct auxtrace_queue *queue = &pt->queues.queue_array[i];
  1964. struct intel_pt_queue *ptq = queue->priv;
  1965. if (ptq && (tid == -1 || ptq->tid == tid)) {
  1966. ptq->time = time_;
  1967. intel_pt_set_pid_tid_cpu(pt, queue);
  1968. intel_pt_run_decoder(ptq, &ts);
  1969. }
  1970. }
  1971. return 0;
  1972. }
  1973. static void intel_pt_sample_set_pid_tid_cpu(struct intel_pt_queue *ptq,
  1974. struct auxtrace_queue *queue,
  1975. struct perf_sample *sample)
  1976. {
  1977. struct machine *m = ptq->pt->machine;
  1978. ptq->pid = sample->pid;
  1979. ptq->tid = sample->tid;
  1980. ptq->cpu = queue->cpu;
  1981. intel_pt_log("queue %u cpu %d pid %d tid %d\n",
  1982. ptq->queue_nr, ptq->cpu, ptq->pid, ptq->tid);
  1983. thread__zput(ptq->thread);
  1984. if (ptq->tid == -1)
  1985. return;
  1986. if (ptq->pid == -1) {
  1987. ptq->thread = machine__find_thread(m, -1, ptq->tid);
  1988. if (ptq->thread)
  1989. ptq->pid = ptq->thread->pid_;
  1990. return;
  1991. }
  1992. ptq->thread = machine__findnew_thread(m, ptq->pid, ptq->tid);
  1993. }
  1994. static int intel_pt_process_timeless_sample(struct intel_pt *pt,
  1995. struct perf_sample *sample)
  1996. {
  1997. struct auxtrace_queue *queue;
  1998. struct intel_pt_queue *ptq;
  1999. u64 ts = 0;
  2000. queue = auxtrace_queues__sample_queue(&pt->queues, sample, pt->session);
  2001. if (!queue)
  2002. return -EINVAL;
  2003. ptq = queue->priv;
  2004. if (!ptq)
  2005. return 0;
  2006. ptq->stop = false;
  2007. ptq->time = sample->time;
  2008. intel_pt_sample_set_pid_tid_cpu(ptq, queue, sample);
  2009. intel_pt_run_decoder(ptq, &ts);
  2010. return 0;
  2011. }
  2012. static int intel_pt_lost(struct intel_pt *pt, struct perf_sample *sample)
  2013. {
  2014. return intel_pt_synth_error(pt, INTEL_PT_ERR_LOST, sample->cpu,
  2015. sample->pid, sample->tid, 0, sample->time);
  2016. }
  2017. static struct intel_pt_queue *intel_pt_cpu_to_ptq(struct intel_pt *pt, int cpu)
  2018. {
  2019. unsigned i, j;
  2020. if (cpu < 0 || !pt->queues.nr_queues)
  2021. return NULL;
  2022. if ((unsigned)cpu >= pt->queues.nr_queues)
  2023. i = pt->queues.nr_queues - 1;
  2024. else
  2025. i = cpu;
  2026. if (pt->queues.queue_array[i].cpu == cpu)
  2027. return pt->queues.queue_array[i].priv;
  2028. for (j = 0; i > 0; j++) {
  2029. if (pt->queues.queue_array[--i].cpu == cpu)
  2030. return pt->queues.queue_array[i].priv;
  2031. }
  2032. for (; j < pt->queues.nr_queues; j++) {
  2033. if (pt->queues.queue_array[j].cpu == cpu)
  2034. return pt->queues.queue_array[j].priv;
  2035. }
  2036. return NULL;
  2037. }
  2038. static int intel_pt_sync_switch(struct intel_pt *pt, int cpu, pid_t tid,
  2039. u64 timestamp)
  2040. {
  2041. struct intel_pt_queue *ptq;
  2042. int err;
  2043. if (!pt->sync_switch)
  2044. return 1;
  2045. ptq = intel_pt_cpu_to_ptq(pt, cpu);
  2046. if (!ptq || !ptq->sync_switch)
  2047. return 1;
  2048. switch (ptq->switch_state) {
  2049. case INTEL_PT_SS_NOT_TRACING:
  2050. break;
  2051. case INTEL_PT_SS_UNKNOWN:
  2052. case INTEL_PT_SS_TRACING:
  2053. ptq->next_tid = tid;
  2054. ptq->switch_state = INTEL_PT_SS_EXPECTING_SWITCH_IP;
  2055. return 0;
  2056. case INTEL_PT_SS_EXPECTING_SWITCH_EVENT:
  2057. if (!ptq->on_heap) {
  2058. ptq->timestamp = perf_time_to_tsc(timestamp,
  2059. &pt->tc);
  2060. err = auxtrace_heap__add(&pt->heap, ptq->queue_nr,
  2061. ptq->timestamp);
  2062. if (err)
  2063. return err;
  2064. ptq->on_heap = true;
  2065. }
  2066. ptq->switch_state = INTEL_PT_SS_TRACING;
  2067. break;
  2068. case INTEL_PT_SS_EXPECTING_SWITCH_IP:
  2069. intel_pt_log("ERROR: cpu %d expecting switch ip\n", cpu);
  2070. break;
  2071. default:
  2072. break;
  2073. }
  2074. ptq->next_tid = -1;
  2075. return 1;
  2076. }
  2077. static int intel_pt_process_switch(struct intel_pt *pt,
  2078. struct perf_sample *sample)
  2079. {
  2080. struct evsel *evsel;
  2081. pid_t tid;
  2082. int cpu, ret;
  2083. evsel = perf_evlist__id2evsel(pt->session->evlist, sample->id);
  2084. if (evsel != pt->switch_evsel)
  2085. return 0;
  2086. tid = evsel__intval(evsel, sample, "next_pid");
  2087. cpu = sample->cpu;
  2088. intel_pt_log("sched_switch: cpu %d tid %d time %"PRIu64" tsc %#"PRIx64"\n",
  2089. cpu, tid, sample->time, perf_time_to_tsc(sample->time,
  2090. &pt->tc));
  2091. ret = intel_pt_sync_switch(pt, cpu, tid, sample->time);
  2092. if (ret <= 0)
  2093. return ret;
  2094. return machine__set_current_tid(pt->machine, cpu, -1, tid);
  2095. }
  2096. static int intel_pt_context_switch_in(struct intel_pt *pt,
  2097. struct perf_sample *sample)
  2098. {
  2099. pid_t pid = sample->pid;
  2100. pid_t tid = sample->tid;
  2101. int cpu = sample->cpu;
  2102. if (pt->sync_switch) {
  2103. struct intel_pt_queue *ptq;
  2104. ptq = intel_pt_cpu_to_ptq(pt, cpu);
  2105. if (ptq && ptq->sync_switch) {
  2106. ptq->next_tid = -1;
  2107. switch (ptq->switch_state) {
  2108. case INTEL_PT_SS_NOT_TRACING:
  2109. case INTEL_PT_SS_UNKNOWN:
  2110. case INTEL_PT_SS_TRACING:
  2111. break;
  2112. case INTEL_PT_SS_EXPECTING_SWITCH_EVENT:
  2113. case INTEL_PT_SS_EXPECTING_SWITCH_IP:
  2114. ptq->switch_state = INTEL_PT_SS_TRACING;
  2115. break;
  2116. default:
  2117. break;
  2118. }
  2119. }
  2120. }
  2121. /*
  2122. * If the current tid has not been updated yet, ensure it is now that
  2123. * a "switch in" event has occurred.
  2124. */
  2125. if (machine__get_current_tid(pt->machine, cpu) == tid)
  2126. return 0;
  2127. return machine__set_current_tid(pt->machine, cpu, pid, tid);
  2128. }
  2129. static int intel_pt_context_switch(struct intel_pt *pt, union perf_event *event,
  2130. struct perf_sample *sample)
  2131. {
  2132. bool out = event->header.misc & PERF_RECORD_MISC_SWITCH_OUT;
  2133. pid_t pid, tid;
  2134. int cpu, ret;
  2135. cpu = sample->cpu;
  2136. if (pt->have_sched_switch == 3) {
  2137. if (!out)
  2138. return intel_pt_context_switch_in(pt, sample);
  2139. if (event->header.type != PERF_RECORD_SWITCH_CPU_WIDE) {
  2140. pr_err("Expecting CPU-wide context switch event\n");
  2141. return -EINVAL;
  2142. }
  2143. pid = event->context_switch.next_prev_pid;
  2144. tid = event->context_switch.next_prev_tid;
  2145. } else {
  2146. if (out)
  2147. return 0;
  2148. pid = sample->pid;
  2149. tid = sample->tid;
  2150. }
  2151. if (tid == -1)
  2152. intel_pt_log("context_switch event has no tid\n");
  2153. ret = intel_pt_sync_switch(pt, cpu, tid, sample->time);
  2154. if (ret <= 0)
  2155. return ret;
  2156. return machine__set_current_tid(pt->machine, cpu, pid, tid);
  2157. }
  2158. static int intel_pt_process_itrace_start(struct intel_pt *pt,
  2159. union perf_event *event,
  2160. struct perf_sample *sample)
  2161. {
  2162. if (!pt->per_cpu_mmaps)
  2163. return 0;
  2164. intel_pt_log("itrace_start: cpu %d pid %d tid %d time %"PRIu64" tsc %#"PRIx64"\n",
  2165. sample->cpu, event->itrace_start.pid,
  2166. event->itrace_start.tid, sample->time,
  2167. perf_time_to_tsc(sample->time, &pt->tc));
  2168. return machine__set_current_tid(pt->machine, sample->cpu,
  2169. event->itrace_start.pid,
  2170. event->itrace_start.tid);
  2171. }
  2172. static int intel_pt_find_map(struct thread *thread, u8 cpumode, u64 addr,
  2173. struct addr_location *al)
  2174. {
  2175. if (!al->map || addr < al->map->start || addr >= al->map->end) {
  2176. if (!thread__find_map(thread, cpumode, addr, al))
  2177. return -1;
  2178. }
  2179. return 0;
  2180. }
  2181. /* Invalidate all instruction cache entries that overlap the text poke */
  2182. static int intel_pt_text_poke(struct intel_pt *pt, union perf_event *event)
  2183. {
  2184. u8 cpumode = event->header.misc & PERF_RECORD_MISC_CPUMODE_MASK;
  2185. u64 addr = event->text_poke.addr + event->text_poke.new_len - 1;
  2186. /* Assume text poke begins in a basic block no more than 4096 bytes */
  2187. int cnt = 4096 + event->text_poke.new_len;
  2188. struct thread *thread = pt->unknown_thread;
  2189. struct addr_location al = { .map = NULL };
  2190. struct machine *machine = pt->machine;
  2191. struct intel_pt_cache_entry *e;
  2192. u64 offset;
  2193. if (!event->text_poke.new_len)
  2194. return 0;
  2195. for (; cnt; cnt--, addr--) {
  2196. if (intel_pt_find_map(thread, cpumode, addr, &al)) {
  2197. if (addr < event->text_poke.addr)
  2198. return 0;
  2199. continue;
  2200. }
  2201. if (!al.map->dso || !al.map->dso->auxtrace_cache)
  2202. continue;
  2203. offset = al.map->map_ip(al.map, addr);
  2204. e = intel_pt_cache_lookup(al.map->dso, machine, offset);
  2205. if (!e)
  2206. continue;
  2207. if (addr + e->byte_cnt + e->length <= event->text_poke.addr) {
  2208. /*
  2209. * No overlap. Working backwards there cannot be another
  2210. * basic block that overlaps the text poke if there is a
  2211. * branch instruction before the text poke address.
  2212. */
  2213. if (e->branch != INTEL_PT_BR_NO_BRANCH)
  2214. return 0;
  2215. } else {
  2216. intel_pt_cache_invalidate(al.map->dso, machine, offset);
  2217. intel_pt_log("Invalidated instruction cache for %s at %#"PRIx64"\n",
  2218. al.map->dso->long_name, addr);
  2219. }
  2220. }
  2221. return 0;
  2222. }
  2223. static int intel_pt_process_event(struct perf_session *session,
  2224. union perf_event *event,
  2225. struct perf_sample *sample,
  2226. struct perf_tool *tool)
  2227. {
  2228. struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
  2229. auxtrace);
  2230. u64 timestamp;
  2231. int err = 0;
  2232. if (dump_trace)
  2233. return 0;
  2234. if (!tool->ordered_events) {
  2235. pr_err("Intel Processor Trace requires ordered events\n");
  2236. return -EINVAL;
  2237. }
  2238. if (sample->time && sample->time != (u64)-1)
  2239. timestamp = perf_time_to_tsc(sample->time, &pt->tc);
  2240. else
  2241. timestamp = 0;
  2242. if (timestamp || pt->timeless_decoding) {
  2243. err = intel_pt_update_queues(pt);
  2244. if (err)
  2245. return err;
  2246. }
  2247. if (pt->timeless_decoding) {
  2248. if (pt->sampling_mode) {
  2249. if (sample->aux_sample.size)
  2250. err = intel_pt_process_timeless_sample(pt,
  2251. sample);
  2252. } else if (event->header.type == PERF_RECORD_EXIT) {
  2253. err = intel_pt_process_timeless_queues(pt,
  2254. event->fork.tid,
  2255. sample->time);
  2256. }
  2257. } else if (timestamp) {
  2258. err = intel_pt_process_queues(pt, timestamp);
  2259. }
  2260. if (err)
  2261. return err;
  2262. if (event->header.type == PERF_RECORD_SAMPLE) {
  2263. if (pt->synth_opts.add_callchain && !sample->callchain)
  2264. intel_pt_add_callchain(pt, sample);
  2265. if (pt->synth_opts.add_last_branch && !sample->branch_stack)
  2266. intel_pt_add_br_stack(pt, sample);
  2267. }
  2268. if (event->header.type == PERF_RECORD_AUX &&
  2269. (event->aux.flags & PERF_AUX_FLAG_TRUNCATED) &&
  2270. pt->synth_opts.errors) {
  2271. err = intel_pt_lost(pt, sample);
  2272. if (err)
  2273. return err;
  2274. }
  2275. if (pt->switch_evsel && event->header.type == PERF_RECORD_SAMPLE)
  2276. err = intel_pt_process_switch(pt, sample);
  2277. else if (event->header.type == PERF_RECORD_ITRACE_START)
  2278. err = intel_pt_process_itrace_start(pt, event, sample);
  2279. else if (event->header.type == PERF_RECORD_SWITCH ||
  2280. event->header.type == PERF_RECORD_SWITCH_CPU_WIDE)
  2281. err = intel_pt_context_switch(pt, event, sample);
  2282. if (!err && event->header.type == PERF_RECORD_TEXT_POKE)
  2283. err = intel_pt_text_poke(pt, event);
  2284. if (intel_pt_enable_logging && intel_pt_log_events(pt, sample->time)) {
  2285. intel_pt_log("event %u: cpu %d time %"PRIu64" tsc %#"PRIx64" ",
  2286. event->header.type, sample->cpu, sample->time, timestamp);
  2287. intel_pt_log_event(event);
  2288. }
  2289. return err;
  2290. }
  2291. static int intel_pt_flush(struct perf_session *session, struct perf_tool *tool)
  2292. {
  2293. struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
  2294. auxtrace);
  2295. int ret;
  2296. if (dump_trace)
  2297. return 0;
  2298. if (!tool->ordered_events)
  2299. return -EINVAL;
  2300. ret = intel_pt_update_queues(pt);
  2301. if (ret < 0)
  2302. return ret;
  2303. if (pt->timeless_decoding)
  2304. return intel_pt_process_timeless_queues(pt, -1,
  2305. MAX_TIMESTAMP - 1);
  2306. return intel_pt_process_queues(pt, MAX_TIMESTAMP);
  2307. }
  2308. static void intel_pt_free_events(struct perf_session *session)
  2309. {
  2310. struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
  2311. auxtrace);
  2312. struct auxtrace_queues *queues = &pt->queues;
  2313. unsigned int i;
  2314. for (i = 0; i < queues->nr_queues; i++) {
  2315. intel_pt_free_queue(queues->queue_array[i].priv);
  2316. queues->queue_array[i].priv = NULL;
  2317. }
  2318. intel_pt_log_disable();
  2319. auxtrace_queues__free(queues);
  2320. }
  2321. static void intel_pt_free(struct perf_session *session)
  2322. {
  2323. struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
  2324. auxtrace);
  2325. auxtrace_heap__free(&pt->heap);
  2326. intel_pt_free_events(session);
  2327. session->auxtrace = NULL;
  2328. thread__put(pt->unknown_thread);
  2329. addr_filters__exit(&pt->filts);
  2330. zfree(&pt->chain);
  2331. zfree(&pt->filter);
  2332. zfree(&pt->time_ranges);
  2333. free(pt);
  2334. }
  2335. static bool intel_pt_evsel_is_auxtrace(struct perf_session *session,
  2336. struct evsel *evsel)
  2337. {
  2338. struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
  2339. auxtrace);
  2340. return evsel->core.attr.type == pt->pmu_type;
  2341. }
  2342. static int intel_pt_process_auxtrace_event(struct perf_session *session,
  2343. union perf_event *event,
  2344. struct perf_tool *tool __maybe_unused)
  2345. {
  2346. struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
  2347. auxtrace);
  2348. if (!pt->data_queued) {
  2349. struct auxtrace_buffer *buffer;
  2350. off_t data_offset;
  2351. int fd = perf_data__fd(session->data);
  2352. int err;
  2353. if (perf_data__is_pipe(session->data)) {
  2354. data_offset = 0;
  2355. } else {
  2356. data_offset = lseek(fd, 0, SEEK_CUR);
  2357. if (data_offset == -1)
  2358. return -errno;
  2359. }
  2360. err = auxtrace_queues__add_event(&pt->queues, session, event,
  2361. data_offset, &buffer);
  2362. if (err)
  2363. return err;
  2364. /* Dump here now we have copied a piped trace out of the pipe */
  2365. if (dump_trace) {
  2366. if (auxtrace_buffer__get_data(buffer, fd)) {
  2367. intel_pt_dump_event(pt, buffer->data,
  2368. buffer->size);
  2369. auxtrace_buffer__put_data(buffer);
  2370. }
  2371. }
  2372. }
  2373. return 0;
  2374. }
  2375. static int intel_pt_queue_data(struct perf_session *session,
  2376. struct perf_sample *sample,
  2377. union perf_event *event, u64 data_offset)
  2378. {
  2379. struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
  2380. auxtrace);
  2381. u64 timestamp;
  2382. if (event) {
  2383. return auxtrace_queues__add_event(&pt->queues, session, event,
  2384. data_offset, NULL);
  2385. }
  2386. if (sample->time && sample->time != (u64)-1)
  2387. timestamp = perf_time_to_tsc(sample->time, &pt->tc);
  2388. else
  2389. timestamp = 0;
  2390. return auxtrace_queues__add_sample(&pt->queues, session, sample,
  2391. data_offset, timestamp);
  2392. }
  2393. struct intel_pt_synth {
  2394. struct perf_tool dummy_tool;
  2395. struct perf_session *session;
  2396. };
  2397. static int intel_pt_event_synth(struct perf_tool *tool,
  2398. union perf_event *event,
  2399. struct perf_sample *sample __maybe_unused,
  2400. struct machine *machine __maybe_unused)
  2401. {
  2402. struct intel_pt_synth *intel_pt_synth =
  2403. container_of(tool, struct intel_pt_synth, dummy_tool);
  2404. return perf_session__deliver_synth_event(intel_pt_synth->session, event,
  2405. NULL);
  2406. }
  2407. static int intel_pt_synth_event(struct perf_session *session, const char *name,
  2408. struct perf_event_attr *attr, u64 id)
  2409. {
  2410. struct intel_pt_synth intel_pt_synth;
  2411. int err;
  2412. pr_debug("Synthesizing '%s' event with id %" PRIu64 " sample type %#" PRIx64 "\n",
  2413. name, id, (u64)attr->sample_type);
  2414. memset(&intel_pt_synth, 0, sizeof(struct intel_pt_synth));
  2415. intel_pt_synth.session = session;
  2416. err = perf_event__synthesize_attr(&intel_pt_synth.dummy_tool, attr, 1,
  2417. &id, intel_pt_event_synth);
  2418. if (err)
  2419. pr_err("%s: failed to synthesize '%s' event type\n",
  2420. __func__, name);
  2421. return err;
  2422. }
  2423. static void intel_pt_set_event_name(struct evlist *evlist, u64 id,
  2424. const char *name)
  2425. {
  2426. struct evsel *evsel;
  2427. evlist__for_each_entry(evlist, evsel) {
  2428. if (evsel->core.id && evsel->core.id[0] == id) {
  2429. if (evsel->name)
  2430. zfree(&evsel->name);
  2431. evsel->name = strdup(name);
  2432. break;
  2433. }
  2434. }
  2435. }
  2436. static struct evsel *intel_pt_evsel(struct intel_pt *pt,
  2437. struct evlist *evlist)
  2438. {
  2439. struct evsel *evsel;
  2440. evlist__for_each_entry(evlist, evsel) {
  2441. if (evsel->core.attr.type == pt->pmu_type && evsel->core.ids)
  2442. return evsel;
  2443. }
  2444. return NULL;
  2445. }
  2446. static int intel_pt_synth_events(struct intel_pt *pt,
  2447. struct perf_session *session)
  2448. {
  2449. struct evlist *evlist = session->evlist;
  2450. struct evsel *evsel = intel_pt_evsel(pt, evlist);
  2451. struct perf_event_attr attr;
  2452. u64 id;
  2453. int err;
  2454. if (!evsel) {
  2455. pr_debug("There are no selected events with Intel Processor Trace data\n");
  2456. return 0;
  2457. }
  2458. memset(&attr, 0, sizeof(struct perf_event_attr));
  2459. attr.size = sizeof(struct perf_event_attr);
  2460. attr.type = PERF_TYPE_HARDWARE;
  2461. attr.sample_type = evsel->core.attr.sample_type & PERF_SAMPLE_MASK;
  2462. attr.sample_type |= PERF_SAMPLE_IP | PERF_SAMPLE_TID |
  2463. PERF_SAMPLE_PERIOD;
  2464. if (pt->timeless_decoding)
  2465. attr.sample_type &= ~(u64)PERF_SAMPLE_TIME;
  2466. else
  2467. attr.sample_type |= PERF_SAMPLE_TIME;
  2468. if (!pt->per_cpu_mmaps)
  2469. attr.sample_type &= ~(u64)PERF_SAMPLE_CPU;
  2470. attr.exclude_user = evsel->core.attr.exclude_user;
  2471. attr.exclude_kernel = evsel->core.attr.exclude_kernel;
  2472. attr.exclude_hv = evsel->core.attr.exclude_hv;
  2473. attr.exclude_host = evsel->core.attr.exclude_host;
  2474. attr.exclude_guest = evsel->core.attr.exclude_guest;
  2475. attr.sample_id_all = evsel->core.attr.sample_id_all;
  2476. attr.read_format = evsel->core.attr.read_format;
  2477. id = evsel->core.id[0] + 1000000000;
  2478. if (!id)
  2479. id = 1;
  2480. if (pt->synth_opts.branches) {
  2481. attr.config = PERF_COUNT_HW_BRANCH_INSTRUCTIONS;
  2482. attr.sample_period = 1;
  2483. attr.sample_type |= PERF_SAMPLE_ADDR;
  2484. err = intel_pt_synth_event(session, "branches", &attr, id);
  2485. if (err)
  2486. return err;
  2487. pt->sample_branches = true;
  2488. pt->branches_sample_type = attr.sample_type;
  2489. pt->branches_id = id;
  2490. id += 1;
  2491. attr.sample_type &= ~(u64)PERF_SAMPLE_ADDR;
  2492. }
  2493. if (pt->synth_opts.callchain)
  2494. attr.sample_type |= PERF_SAMPLE_CALLCHAIN;
  2495. if (pt->synth_opts.last_branch) {
  2496. attr.sample_type |= PERF_SAMPLE_BRANCH_STACK;
  2497. /*
  2498. * We don't use the hardware index, but the sample generation
  2499. * code uses the new format branch_stack with this field,
  2500. * so the event attributes must indicate that it's present.
  2501. */
  2502. attr.branch_sample_type |= PERF_SAMPLE_BRANCH_HW_INDEX;
  2503. }
  2504. if (pt->synth_opts.instructions) {
  2505. attr.config = PERF_COUNT_HW_INSTRUCTIONS;
  2506. if (pt->synth_opts.period_type == PERF_ITRACE_PERIOD_NANOSECS)
  2507. attr.sample_period =
  2508. intel_pt_ns_to_ticks(pt, pt->synth_opts.period);
  2509. else
  2510. attr.sample_period = pt->synth_opts.period;
  2511. err = intel_pt_synth_event(session, "instructions", &attr, id);
  2512. if (err)
  2513. return err;
  2514. pt->sample_instructions = true;
  2515. pt->instructions_sample_type = attr.sample_type;
  2516. pt->instructions_id = id;
  2517. id += 1;
  2518. }
  2519. attr.sample_type &= ~(u64)PERF_SAMPLE_PERIOD;
  2520. attr.sample_period = 1;
  2521. if (pt->synth_opts.transactions) {
  2522. attr.config = PERF_COUNT_HW_INSTRUCTIONS;
  2523. err = intel_pt_synth_event(session, "transactions", &attr, id);
  2524. if (err)
  2525. return err;
  2526. pt->sample_transactions = true;
  2527. pt->transactions_sample_type = attr.sample_type;
  2528. pt->transactions_id = id;
  2529. intel_pt_set_event_name(evlist, id, "transactions");
  2530. id += 1;
  2531. }
  2532. attr.type = PERF_TYPE_SYNTH;
  2533. attr.sample_type |= PERF_SAMPLE_RAW;
  2534. if (pt->synth_opts.ptwrites) {
  2535. attr.config = PERF_SYNTH_INTEL_PTWRITE;
  2536. err = intel_pt_synth_event(session, "ptwrite", &attr, id);
  2537. if (err)
  2538. return err;
  2539. pt->sample_ptwrites = true;
  2540. pt->ptwrites_sample_type = attr.sample_type;
  2541. pt->ptwrites_id = id;
  2542. intel_pt_set_event_name(evlist, id, "ptwrite");
  2543. id += 1;
  2544. }
  2545. if (pt->synth_opts.pwr_events) {
  2546. pt->sample_pwr_events = true;
  2547. pt->pwr_events_sample_type = attr.sample_type;
  2548. attr.config = PERF_SYNTH_INTEL_CBR;
  2549. err = intel_pt_synth_event(session, "cbr", &attr, id);
  2550. if (err)
  2551. return err;
  2552. pt->cbr_id = id;
  2553. intel_pt_set_event_name(evlist, id, "cbr");
  2554. id += 1;
  2555. }
  2556. if (pt->synth_opts.pwr_events && (evsel->core.attr.config & 0x10)) {
  2557. attr.config = PERF_SYNTH_INTEL_MWAIT;
  2558. err = intel_pt_synth_event(session, "mwait", &attr, id);
  2559. if (err)
  2560. return err;
  2561. pt->mwait_id = id;
  2562. intel_pt_set_event_name(evlist, id, "mwait");
  2563. id += 1;
  2564. attr.config = PERF_SYNTH_INTEL_PWRE;
  2565. err = intel_pt_synth_event(session, "pwre", &attr, id);
  2566. if (err)
  2567. return err;
  2568. pt->pwre_id = id;
  2569. intel_pt_set_event_name(evlist, id, "pwre");
  2570. id += 1;
  2571. attr.config = PERF_SYNTH_INTEL_EXSTOP;
  2572. err = intel_pt_synth_event(session, "exstop", &attr, id);
  2573. if (err)
  2574. return err;
  2575. pt->exstop_id = id;
  2576. intel_pt_set_event_name(evlist, id, "exstop");
  2577. id += 1;
  2578. attr.config = PERF_SYNTH_INTEL_PWRX;
  2579. err = intel_pt_synth_event(session, "pwrx", &attr, id);
  2580. if (err)
  2581. return err;
  2582. pt->pwrx_id = id;
  2583. intel_pt_set_event_name(evlist, id, "pwrx");
  2584. id += 1;
  2585. }
  2586. return 0;
  2587. }
  2588. static void intel_pt_setup_pebs_events(struct intel_pt *pt)
  2589. {
  2590. struct evsel *evsel;
  2591. if (!pt->synth_opts.other_events)
  2592. return;
  2593. evlist__for_each_entry(pt->session->evlist, evsel) {
  2594. if (evsel->core.attr.aux_output && evsel->core.id) {
  2595. pt->sample_pebs = true;
  2596. pt->pebs_evsel = evsel;
  2597. return;
  2598. }
  2599. }
  2600. }
  2601. static struct evsel *intel_pt_find_sched_switch(struct evlist *evlist)
  2602. {
  2603. struct evsel *evsel;
  2604. evlist__for_each_entry_reverse(evlist, evsel) {
  2605. const char *name = evsel__name(evsel);
  2606. if (!strcmp(name, "sched:sched_switch"))
  2607. return evsel;
  2608. }
  2609. return NULL;
  2610. }
  2611. static bool intel_pt_find_switch(struct evlist *evlist)
  2612. {
  2613. struct evsel *evsel;
  2614. evlist__for_each_entry(evlist, evsel) {
  2615. if (evsel->core.attr.context_switch)
  2616. return true;
  2617. }
  2618. return false;
  2619. }
  2620. static int intel_pt_perf_config(const char *var, const char *value, void *data)
  2621. {
  2622. struct intel_pt *pt = data;
  2623. if (!strcmp(var, "intel-pt.mispred-all"))
  2624. pt->mispred_all = perf_config_bool(var, value);
  2625. return 0;
  2626. }
  2627. /* Find least TSC which converts to ns or later */
  2628. static u64 intel_pt_tsc_start(u64 ns, struct intel_pt *pt)
  2629. {
  2630. u64 tsc, tm;
  2631. tsc = perf_time_to_tsc(ns, &pt->tc);
  2632. while (1) {
  2633. tm = tsc_to_perf_time(tsc, &pt->tc);
  2634. if (tm < ns)
  2635. break;
  2636. tsc -= 1;
  2637. }
  2638. while (tm < ns)
  2639. tm = tsc_to_perf_time(++tsc, &pt->tc);
  2640. return tsc;
  2641. }
  2642. /* Find greatest TSC which converts to ns or earlier */
  2643. static u64 intel_pt_tsc_end(u64 ns, struct intel_pt *pt)
  2644. {
  2645. u64 tsc, tm;
  2646. tsc = perf_time_to_tsc(ns, &pt->tc);
  2647. while (1) {
  2648. tm = tsc_to_perf_time(tsc, &pt->tc);
  2649. if (tm > ns)
  2650. break;
  2651. tsc += 1;
  2652. }
  2653. while (tm > ns)
  2654. tm = tsc_to_perf_time(--tsc, &pt->tc);
  2655. return tsc;
  2656. }
  2657. static int intel_pt_setup_time_ranges(struct intel_pt *pt,
  2658. struct itrace_synth_opts *opts)
  2659. {
  2660. struct perf_time_interval *p = opts->ptime_range;
  2661. int n = opts->range_num;
  2662. int i;
  2663. if (!n || !p || pt->timeless_decoding)
  2664. return 0;
  2665. pt->time_ranges = calloc(n, sizeof(struct range));
  2666. if (!pt->time_ranges)
  2667. return -ENOMEM;
  2668. pt->range_cnt = n;
  2669. intel_pt_log("%s: %u range(s)\n", __func__, n);
  2670. for (i = 0; i < n; i++) {
  2671. struct range *r = &pt->time_ranges[i];
  2672. u64 ts = p[i].start;
  2673. u64 te = p[i].end;
  2674. /*
  2675. * Take care to ensure the TSC range matches the perf-time range
  2676. * when converted back to perf-time.
  2677. */
  2678. r->start = ts ? intel_pt_tsc_start(ts, pt) : 0;
  2679. r->end = te ? intel_pt_tsc_end(te, pt) : 0;
  2680. intel_pt_log("range %d: perf time interval: %"PRIu64" to %"PRIu64"\n",
  2681. i, ts, te);
  2682. intel_pt_log("range %d: TSC time interval: %#"PRIx64" to %#"PRIx64"\n",
  2683. i, r->start, r->end);
  2684. }
  2685. return 0;
  2686. }
  2687. static const char * const intel_pt_info_fmts[] = {
  2688. [INTEL_PT_PMU_TYPE] = " PMU Type %"PRId64"\n",
  2689. [INTEL_PT_TIME_SHIFT] = " Time Shift %"PRIu64"\n",
  2690. [INTEL_PT_TIME_MULT] = " Time Muliplier %"PRIu64"\n",
  2691. [INTEL_PT_TIME_ZERO] = " Time Zero %"PRIu64"\n",
  2692. [INTEL_PT_CAP_USER_TIME_ZERO] = " Cap Time Zero %"PRId64"\n",
  2693. [INTEL_PT_TSC_BIT] = " TSC bit %#"PRIx64"\n",
  2694. [INTEL_PT_NORETCOMP_BIT] = " NoRETComp bit %#"PRIx64"\n",
  2695. [INTEL_PT_HAVE_SCHED_SWITCH] = " Have sched_switch %"PRId64"\n",
  2696. [INTEL_PT_SNAPSHOT_MODE] = " Snapshot mode %"PRId64"\n",
  2697. [INTEL_PT_PER_CPU_MMAPS] = " Per-cpu maps %"PRId64"\n",
  2698. [INTEL_PT_MTC_BIT] = " MTC bit %#"PRIx64"\n",
  2699. [INTEL_PT_TSC_CTC_N] = " TSC:CTC numerator %"PRIu64"\n",
  2700. [INTEL_PT_TSC_CTC_D] = " TSC:CTC denominator %"PRIu64"\n",
  2701. [INTEL_PT_CYC_BIT] = " CYC bit %#"PRIx64"\n",
  2702. [INTEL_PT_MAX_NONTURBO_RATIO] = " Max non-turbo ratio %"PRIu64"\n",
  2703. [INTEL_PT_FILTER_STR_LEN] = " Filter string len. %"PRIu64"\n",
  2704. };
  2705. static void intel_pt_print_info(__u64 *arr, int start, int finish)
  2706. {
  2707. int i;
  2708. if (!dump_trace)
  2709. return;
  2710. for (i = start; i <= finish; i++)
  2711. fprintf(stdout, intel_pt_info_fmts[i], arr[i]);
  2712. }
  2713. static void intel_pt_print_info_str(const char *name, const char *str)
  2714. {
  2715. if (!dump_trace)
  2716. return;
  2717. fprintf(stdout, " %-20s%s\n", name, str ? str : "");
  2718. }
  2719. static bool intel_pt_has(struct perf_record_auxtrace_info *auxtrace_info, int pos)
  2720. {
  2721. return auxtrace_info->header.size >=
  2722. sizeof(struct perf_record_auxtrace_info) + (sizeof(u64) * (pos + 1));
  2723. }
  2724. int intel_pt_process_auxtrace_info(union perf_event *event,
  2725. struct perf_session *session)
  2726. {
  2727. struct perf_record_auxtrace_info *auxtrace_info = &event->auxtrace_info;
  2728. size_t min_sz = sizeof(u64) * INTEL_PT_PER_CPU_MMAPS;
  2729. struct intel_pt *pt;
  2730. void *info_end;
  2731. __u64 *info;
  2732. int err;
  2733. if (auxtrace_info->header.size < sizeof(struct perf_record_auxtrace_info) +
  2734. min_sz)
  2735. return -EINVAL;
  2736. pt = zalloc(sizeof(struct intel_pt));
  2737. if (!pt)
  2738. return -ENOMEM;
  2739. addr_filters__init(&pt->filts);
  2740. err = perf_config(intel_pt_perf_config, pt);
  2741. if (err)
  2742. goto err_free;
  2743. err = auxtrace_queues__init(&pt->queues);
  2744. if (err)
  2745. goto err_free;
  2746. intel_pt_log_set_name(INTEL_PT_PMU_NAME);
  2747. pt->session = session;
  2748. pt->machine = &session->machines.host; /* No kvm support */
  2749. pt->auxtrace_type = auxtrace_info->type;
  2750. pt->pmu_type = auxtrace_info->priv[INTEL_PT_PMU_TYPE];
  2751. pt->tc.time_shift = auxtrace_info->priv[INTEL_PT_TIME_SHIFT];
  2752. pt->tc.time_mult = auxtrace_info->priv[INTEL_PT_TIME_MULT];
  2753. pt->tc.time_zero = auxtrace_info->priv[INTEL_PT_TIME_ZERO];
  2754. pt->cap_user_time_zero = auxtrace_info->priv[INTEL_PT_CAP_USER_TIME_ZERO];
  2755. pt->tsc_bit = auxtrace_info->priv[INTEL_PT_TSC_BIT];
  2756. pt->noretcomp_bit = auxtrace_info->priv[INTEL_PT_NORETCOMP_BIT];
  2757. pt->have_sched_switch = auxtrace_info->priv[INTEL_PT_HAVE_SCHED_SWITCH];
  2758. pt->snapshot_mode = auxtrace_info->priv[INTEL_PT_SNAPSHOT_MODE];
  2759. pt->per_cpu_mmaps = auxtrace_info->priv[INTEL_PT_PER_CPU_MMAPS];
  2760. intel_pt_print_info(&auxtrace_info->priv[0], INTEL_PT_PMU_TYPE,
  2761. INTEL_PT_PER_CPU_MMAPS);
  2762. if (intel_pt_has(auxtrace_info, INTEL_PT_CYC_BIT)) {
  2763. pt->mtc_bit = auxtrace_info->priv[INTEL_PT_MTC_BIT];
  2764. pt->mtc_freq_bits = auxtrace_info->priv[INTEL_PT_MTC_FREQ_BITS];
  2765. pt->tsc_ctc_ratio_n = auxtrace_info->priv[INTEL_PT_TSC_CTC_N];
  2766. pt->tsc_ctc_ratio_d = auxtrace_info->priv[INTEL_PT_TSC_CTC_D];
  2767. pt->cyc_bit = auxtrace_info->priv[INTEL_PT_CYC_BIT];
  2768. intel_pt_print_info(&auxtrace_info->priv[0], INTEL_PT_MTC_BIT,
  2769. INTEL_PT_CYC_BIT);
  2770. }
  2771. if (intel_pt_has(auxtrace_info, INTEL_PT_MAX_NONTURBO_RATIO)) {
  2772. pt->max_non_turbo_ratio =
  2773. auxtrace_info->priv[INTEL_PT_MAX_NONTURBO_RATIO];
  2774. intel_pt_print_info(&auxtrace_info->priv[0],
  2775. INTEL_PT_MAX_NONTURBO_RATIO,
  2776. INTEL_PT_MAX_NONTURBO_RATIO);
  2777. }
  2778. info = &auxtrace_info->priv[INTEL_PT_FILTER_STR_LEN] + 1;
  2779. info_end = (void *)info + auxtrace_info->header.size;
  2780. if (intel_pt_has(auxtrace_info, INTEL_PT_FILTER_STR_LEN)) {
  2781. size_t len;
  2782. len = auxtrace_info->priv[INTEL_PT_FILTER_STR_LEN];
  2783. intel_pt_print_info(&auxtrace_info->priv[0],
  2784. INTEL_PT_FILTER_STR_LEN,
  2785. INTEL_PT_FILTER_STR_LEN);
  2786. if (len) {
  2787. const char *filter = (const char *)info;
  2788. len = roundup(len + 1, 8);
  2789. info += len >> 3;
  2790. if ((void *)info > info_end) {
  2791. pr_err("%s: bad filter string length\n", __func__);
  2792. err = -EINVAL;
  2793. goto err_free_queues;
  2794. }
  2795. pt->filter = memdup(filter, len);
  2796. if (!pt->filter) {
  2797. err = -ENOMEM;
  2798. goto err_free_queues;
  2799. }
  2800. if (session->header.needs_swap)
  2801. mem_bswap_64(pt->filter, len);
  2802. if (pt->filter[len - 1]) {
  2803. pr_err("%s: filter string not null terminated\n", __func__);
  2804. err = -EINVAL;
  2805. goto err_free_queues;
  2806. }
  2807. err = addr_filters__parse_bare_filter(&pt->filts,
  2808. filter);
  2809. if (err)
  2810. goto err_free_queues;
  2811. }
  2812. intel_pt_print_info_str("Filter string", pt->filter);
  2813. }
  2814. pt->timeless_decoding = intel_pt_timeless_decoding(pt);
  2815. if (pt->timeless_decoding && !pt->tc.time_mult)
  2816. pt->tc.time_mult = 1;
  2817. pt->have_tsc = intel_pt_have_tsc(pt);
  2818. pt->sampling_mode = intel_pt_sampling_mode(pt);
  2819. pt->est_tsc = !pt->timeless_decoding;
  2820. pt->unknown_thread = thread__new(999999999, 999999999);
  2821. if (!pt->unknown_thread) {
  2822. err = -ENOMEM;
  2823. goto err_free_queues;
  2824. }
  2825. /*
  2826. * Since this thread will not be kept in any rbtree not in a
  2827. * list, initialize its list node so that at thread__put() the
  2828. * current thread lifetime assuption is kept and we don't segfault
  2829. * at list_del_init().
  2830. */
  2831. INIT_LIST_HEAD(&pt->unknown_thread->node);
  2832. err = thread__set_comm(pt->unknown_thread, "unknown", 0);
  2833. if (err)
  2834. goto err_delete_thread;
  2835. if (thread__init_maps(pt->unknown_thread, pt->machine)) {
  2836. err = -ENOMEM;
  2837. goto err_delete_thread;
  2838. }
  2839. pt->auxtrace.process_event = intel_pt_process_event;
  2840. pt->auxtrace.process_auxtrace_event = intel_pt_process_auxtrace_event;
  2841. pt->auxtrace.queue_data = intel_pt_queue_data;
  2842. pt->auxtrace.dump_auxtrace_sample = intel_pt_dump_sample;
  2843. pt->auxtrace.flush_events = intel_pt_flush;
  2844. pt->auxtrace.free_events = intel_pt_free_events;
  2845. pt->auxtrace.free = intel_pt_free;
  2846. pt->auxtrace.evsel_is_auxtrace = intel_pt_evsel_is_auxtrace;
  2847. session->auxtrace = &pt->auxtrace;
  2848. if (dump_trace)
  2849. return 0;
  2850. if (pt->have_sched_switch == 1) {
  2851. pt->switch_evsel = intel_pt_find_sched_switch(session->evlist);
  2852. if (!pt->switch_evsel) {
  2853. pr_err("%s: missing sched_switch event\n", __func__);
  2854. err = -EINVAL;
  2855. goto err_delete_thread;
  2856. }
  2857. } else if (pt->have_sched_switch == 2 &&
  2858. !intel_pt_find_switch(session->evlist)) {
  2859. pr_err("%s: missing context_switch attribute flag\n", __func__);
  2860. err = -EINVAL;
  2861. goto err_delete_thread;
  2862. }
  2863. if (session->itrace_synth_opts->set) {
  2864. pt->synth_opts = *session->itrace_synth_opts;
  2865. } else {
  2866. itrace_synth_opts__set_default(&pt->synth_opts,
  2867. session->itrace_synth_opts->default_no_sample);
  2868. if (!session->itrace_synth_opts->default_no_sample &&
  2869. !session->itrace_synth_opts->inject) {
  2870. pt->synth_opts.branches = false;
  2871. pt->synth_opts.callchain = true;
  2872. pt->synth_opts.add_callchain = true;
  2873. }
  2874. pt->synth_opts.thread_stack =
  2875. session->itrace_synth_opts->thread_stack;
  2876. }
  2877. if (pt->synth_opts.log)
  2878. intel_pt_log_enable();
  2879. /* Maximum non-turbo ratio is TSC freq / 100 MHz */
  2880. if (pt->tc.time_mult) {
  2881. u64 tsc_freq = intel_pt_ns_to_ticks(pt, 1000000000);
  2882. if (!pt->max_non_turbo_ratio)
  2883. pt->max_non_turbo_ratio =
  2884. (tsc_freq + 50000000) / 100000000;
  2885. intel_pt_log("TSC frequency %"PRIu64"\n", tsc_freq);
  2886. intel_pt_log("Maximum non-turbo ratio %u\n",
  2887. pt->max_non_turbo_ratio);
  2888. pt->cbr2khz = tsc_freq / pt->max_non_turbo_ratio / 1000;
  2889. }
  2890. err = intel_pt_setup_time_ranges(pt, session->itrace_synth_opts);
  2891. if (err)
  2892. goto err_delete_thread;
  2893. if (pt->synth_opts.calls)
  2894. pt->branches_filter |= PERF_IP_FLAG_CALL | PERF_IP_FLAG_ASYNC |
  2895. PERF_IP_FLAG_TRACE_END;
  2896. if (pt->synth_opts.returns)
  2897. pt->branches_filter |= PERF_IP_FLAG_RETURN |
  2898. PERF_IP_FLAG_TRACE_BEGIN;
  2899. if ((pt->synth_opts.callchain || pt->synth_opts.add_callchain) &&
  2900. !symbol_conf.use_callchain) {
  2901. symbol_conf.use_callchain = true;
  2902. if (callchain_register_param(&callchain_param) < 0) {
  2903. symbol_conf.use_callchain = false;
  2904. pt->synth_opts.callchain = false;
  2905. pt->synth_opts.add_callchain = false;
  2906. }
  2907. }
  2908. if (pt->synth_opts.add_callchain) {
  2909. err = intel_pt_callchain_init(pt);
  2910. if (err)
  2911. goto err_delete_thread;
  2912. }
  2913. if (pt->synth_opts.last_branch || pt->synth_opts.add_last_branch) {
  2914. pt->br_stack_sz = pt->synth_opts.last_branch_sz;
  2915. pt->br_stack_sz_plus = pt->br_stack_sz;
  2916. }
  2917. if (pt->synth_opts.add_last_branch) {
  2918. err = intel_pt_br_stack_init(pt);
  2919. if (err)
  2920. goto err_delete_thread;
  2921. /*
  2922. * Additional branch stack size to cater for tracing from the
  2923. * actual sample ip to where the sample time is recorded.
  2924. * Measured at about 200 branches, but generously set to 1024.
  2925. * If kernel space is not being traced, then add just 1 for the
  2926. * branch to kernel space.
  2927. */
  2928. if (intel_pt_tracing_kernel(pt))
  2929. pt->br_stack_sz_plus += 1024;
  2930. else
  2931. pt->br_stack_sz_plus += 1;
  2932. }
  2933. pt->use_thread_stack = pt->synth_opts.callchain ||
  2934. pt->synth_opts.add_callchain ||
  2935. pt->synth_opts.thread_stack ||
  2936. pt->synth_opts.last_branch ||
  2937. pt->synth_opts.add_last_branch;
  2938. pt->callstack = pt->synth_opts.callchain ||
  2939. pt->synth_opts.add_callchain ||
  2940. pt->synth_opts.thread_stack;
  2941. err = intel_pt_synth_events(pt, session);
  2942. if (err)
  2943. goto err_delete_thread;
  2944. intel_pt_setup_pebs_events(pt);
  2945. if (pt->sampling_mode || list_empty(&session->auxtrace_index))
  2946. err = auxtrace_queue_data(session, true, true);
  2947. else
  2948. err = auxtrace_queues__process_index(&pt->queues, session);
  2949. if (err)
  2950. goto err_delete_thread;
  2951. if (pt->queues.populated)
  2952. pt->data_queued = true;
  2953. if (pt->timeless_decoding)
  2954. pr_debug2("Intel PT decoding without timestamps\n");
  2955. return 0;
  2956. err_delete_thread:
  2957. zfree(&pt->chain);
  2958. thread__zput(pt->unknown_thread);
  2959. err_free_queues:
  2960. intel_pt_log_disable();
  2961. auxtrace_queues__free(&pt->queues);
  2962. session->auxtrace = NULL;
  2963. err_free:
  2964. addr_filters__exit(&pt->filts);
  2965. zfree(&pt->filter);
  2966. zfree(&pt->time_ranges);
  2967. free(pt);
  2968. return err;
  2969. }