perf-list.txt 10 KB

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  1. perf-list(1)
  2. ============
  3. NAME
  4. ----
  5. perf-list - List all symbolic event types
  6. SYNOPSIS
  7. --------
  8. [verse]
  9. 'perf list' [--no-desc] [--long-desc]
  10. [hw|sw|cache|tracepoint|pmu|sdt|metric|metricgroup|event_glob]
  11. DESCRIPTION
  12. -----------
  13. This command displays the symbolic event types which can be selected in the
  14. various perf commands with the -e option.
  15. OPTIONS
  16. -------
  17. -d::
  18. --desc::
  19. Print extra event descriptions. (default)
  20. --no-desc::
  21. Don't print descriptions.
  22. -v::
  23. --long-desc::
  24. Print longer event descriptions.
  25. --debug::
  26. Enable debugging output.
  27. --details::
  28. Print how named events are resolved internally into perf events, and also
  29. any extra expressions computed by perf stat.
  30. --deprecated::
  31. Print deprecated events. By default the deprecated events are hidden.
  32. [[EVENT_MODIFIERS]]
  33. EVENT MODIFIERS
  34. ---------------
  35. Events can optionally have a modifier by appending a colon and one or
  36. more modifiers. Modifiers allow the user to restrict the events to be
  37. counted. The following modifiers exist:
  38. u - user-space counting
  39. k - kernel counting
  40. h - hypervisor counting
  41. I - non idle counting
  42. G - guest counting (in KVM guests)
  43. H - host counting (not in KVM guests)
  44. p - precise level
  45. P - use maximum detected precise level
  46. S - read sample value (PERF_SAMPLE_READ)
  47. D - pin the event to the PMU
  48. W - group is weak and will fallback to non-group if not schedulable,
  49. e - group or event are exclusive and do not share the PMU
  50. The 'p' modifier can be used for specifying how precise the instruction
  51. address should be. The 'p' modifier can be specified multiple times:
  52. 0 - SAMPLE_IP can have arbitrary skid
  53. 1 - SAMPLE_IP must have constant skid
  54. 2 - SAMPLE_IP requested to have 0 skid
  55. 3 - SAMPLE_IP must have 0 skid, or uses randomization to avoid
  56. sample shadowing effects.
  57. For Intel systems precise event sampling is implemented with PEBS
  58. which supports up to precise-level 2, and precise level 3 for
  59. some special cases
  60. On AMD systems it is implemented using IBS (up to precise-level 2).
  61. The precise modifier works with event types 0x76 (cpu-cycles, CPU
  62. clocks not halted) and 0xC1 (micro-ops retired). Both events map to
  63. IBS execution sampling (IBS op) with the IBS Op Counter Control bit
  64. (IbsOpCntCtl) set respectively (see AMD64 Architecture Programmer’s
  65. Manual Volume 2: System Programming, 13.3 Instruction-Based
  66. Sampling). Examples to use IBS:
  67. perf record -a -e cpu-cycles:p ... # use ibs op counting cycles
  68. perf record -a -e r076:p ... # same as -e cpu-cycles:p
  69. perf record -a -e r0C1:p ... # use ibs op counting micro-ops
  70. RAW HARDWARE EVENT DESCRIPTOR
  71. -----------------------------
  72. Even when an event is not available in a symbolic form within perf right now,
  73. it can be encoded in a per processor specific way.
  74. For instance For x86 CPUs NNN represents the raw register encoding with the
  75. layout of IA32_PERFEVTSELx MSRs (see [Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide] Figure 30-1 Layout
  76. of IA32_PERFEVTSELx MSRs) or AMD's PerfEvtSeln (see [AMD64 Architecture Programmer’s Manual Volume 2: System Programming], Page 344,
  77. Figure 13-7 Performance Event-Select Register (PerfEvtSeln)).
  78. Note: Only the following bit fields can be set in x86 counter
  79. registers: event, umask, edge, inv, cmask. Esp. guest/host only and
  80. OS/user mode flags must be setup using <<EVENT_MODIFIERS, EVENT
  81. MODIFIERS>>.
  82. Example:
  83. If the Intel docs for a QM720 Core i7 describe an event as:
  84. Event Umask Event Mask
  85. Num. Value Mnemonic Description Comment
  86. A8H 01H LSD.UOPS Counts the number of micro-ops Use cmask=1 and
  87. delivered by loop stream detector invert to count
  88. cycles
  89. raw encoding of 0x1A8 can be used:
  90. perf stat -e r1a8 -a sleep 1
  91. perf record -e r1a8 ...
  92. It's also possible to use pmu syntax:
  93. perf record -e r1a8 -a sleep 1
  94. perf record -e cpu/r1a8/ ...
  95. perf record -e cpu/r0x1a8/ ...
  96. You should refer to the processor specific documentation for getting these
  97. details. Some of them are referenced in the SEE ALSO section below.
  98. ARBITRARY PMUS
  99. --------------
  100. perf also supports an extended syntax for specifying raw parameters
  101. to PMUs. Using this typically requires looking up the specific event
  102. in the CPU vendor specific documentation.
  103. The available PMUs and their raw parameters can be listed with
  104. ls /sys/devices/*/format
  105. For example the raw event "LSD.UOPS" core pmu event above could
  106. be specified as
  107. perf stat -e cpu/event=0xa8,umask=0x1,name=LSD.UOPS_CYCLES,cmask=0x1/ ...
  108. or using extended name syntax
  109. perf stat -e cpu/event=0xa8,umask=0x1,cmask=0x1,name=\'LSD.UOPS_CYCLES:cmask=0x1\'/ ...
  110. PER SOCKET PMUS
  111. ---------------
  112. Some PMUs are not associated with a core, but with a whole CPU socket.
  113. Events on these PMUs generally cannot be sampled, but only counted globally
  114. with perf stat -a. They can be bound to one logical CPU, but will measure
  115. all the CPUs in the same socket.
  116. This example measures memory bandwidth every second
  117. on the first memory controller on socket 0 of a Intel Xeon system
  118. perf stat -C 0 -a uncore_imc_0/cas_count_read/,uncore_imc_0/cas_count_write/ -I 1000 ...
  119. Each memory controller has its own PMU. Measuring the complete system
  120. bandwidth would require specifying all imc PMUs (see perf list output),
  121. and adding the values together. To simplify creation of multiple events,
  122. prefix and glob matching is supported in the PMU name, and the prefix
  123. 'uncore_' is also ignored when performing the match. So the command above
  124. can be expanded to all memory controllers by using the syntaxes:
  125. perf stat -C 0 -a imc/cas_count_read/,imc/cas_count_write/ -I 1000 ...
  126. perf stat -C 0 -a *imc*/cas_count_read/,*imc*/cas_count_write/ -I 1000 ...
  127. This example measures the combined core power every second
  128. perf stat -I 1000 -e power/energy-cores/ -a
  129. ACCESS RESTRICTIONS
  130. -------------------
  131. For non root users generally only context switched PMU events are available.
  132. This is normally only the events in the cpu PMU, the predefined events
  133. like cycles and instructions and some software events.
  134. Other PMUs and global measurements are normally root only.
  135. Some event qualifiers, such as "any", are also root only.
  136. This can be overridden by setting the kernel.perf_event_paranoid
  137. sysctl to -1, which allows non root to use these events.
  138. For accessing trace point events perf needs to have read access to
  139. /sys/kernel/debug/tracing, even when perf_event_paranoid is in a relaxed
  140. setting.
  141. TRACING
  142. -------
  143. Some PMUs control advanced hardware tracing capabilities, such as Intel PT,
  144. that allows low overhead execution tracing. These are described in a separate
  145. intel-pt.txt document.
  146. PARAMETERIZED EVENTS
  147. --------------------
  148. Some pmu events listed by 'perf-list' will be displayed with '?' in them. For
  149. example:
  150. hv_gpci/dtbp_ptitc,phys_processor_idx=?/
  151. This means that when provided as an event, a value for '?' must
  152. also be supplied. For example:
  153. perf stat -C 0 -e 'hv_gpci/dtbp_ptitc,phys_processor_idx=0x2/' ...
  154. EVENT QUALIFIERS:
  155. It is also possible to add extra qualifiers to an event:
  156. percore:
  157. Sums up the event counts for all hardware threads in a core, e.g.:
  158. perf stat -e cpu/event=0,umask=0x3,percore=1/
  159. EVENT GROUPS
  160. ------------
  161. Perf supports time based multiplexing of events, when the number of events
  162. active exceeds the number of hardware performance counters. Multiplexing
  163. can cause measurement errors when the workload changes its execution
  164. profile.
  165. When metrics are computed using formulas from event counts, it is useful to
  166. ensure some events are always measured together as a group to minimize multiplexing
  167. errors. Event groups can be specified using { }.
  168. perf stat -e '{instructions,cycles}' ...
  169. The number of available performance counters depend on the CPU. A group
  170. cannot contain more events than available counters.
  171. For example Intel Core CPUs typically have four generic performance counters
  172. for the core, plus three fixed counters for instructions, cycles and
  173. ref-cycles. Some special events have restrictions on which counter they
  174. can schedule, and may not support multiple instances in a single group.
  175. When too many events are specified in the group some of them will not
  176. be measured.
  177. Globally pinned events can limit the number of counters available for
  178. other groups. On x86 systems, the NMI watchdog pins a counter by default.
  179. The nmi watchdog can be disabled as root with
  180. echo 0 > /proc/sys/kernel/nmi_watchdog
  181. Events from multiple different PMUs cannot be mixed in a group, with
  182. some exceptions for software events.
  183. LEADER SAMPLING
  184. ---------------
  185. perf also supports group leader sampling using the :S specifier.
  186. perf record -e '{cycles,instructions}:S' ...
  187. perf report --group
  188. Normally all events in an event group sample, but with :S only
  189. the first event (the leader) samples, and it only reads the values of the
  190. other events in the group.
  191. However, in the case AUX area events (e.g. Intel PT or CoreSight), the AUX
  192. area event must be the leader, so then the second event samples, not the first.
  193. OPTIONS
  194. -------
  195. Without options all known events will be listed.
  196. To limit the list use:
  197. . 'hw' or 'hardware' to list hardware events such as cache-misses, etc.
  198. . 'sw' or 'software' to list software events such as context switches, etc.
  199. . 'cache' or 'hwcache' to list hardware cache events such as L1-dcache-loads, etc.
  200. . 'tracepoint' to list all tracepoint events, alternatively use
  201. 'subsys_glob:event_glob' to filter by tracepoint subsystems such as sched,
  202. block, etc.
  203. . 'pmu' to print the kernel supplied PMU events.
  204. . 'sdt' to list all Statically Defined Tracepoint events.
  205. . 'metric' to list metrics
  206. . 'metricgroup' to list metricgroups with metrics.
  207. . If none of the above is matched, it will apply the supplied glob to all
  208. events, printing the ones that match.
  209. . As a last resort, it will do a substring search in all event names.
  210. One or more types can be used at the same time, listing the events for the
  211. types specified.
  212. Support raw format:
  213. . '--raw-dump', shows the raw-dump of all the events.
  214. . '--raw-dump [hw|sw|cache|tracepoint|pmu|event_glob]', shows the raw-dump of
  215. a certain kind of events.
  216. SEE ALSO
  217. --------
  218. linkperf:perf-stat[1], linkperf:perf-top[1],
  219. linkperf:perf-record[1],
  220. http://www.intel.com/sdm/[Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide],
  221. http://support.amd.com/us/Processor_TechDocs/24593_APM_v2.pdf[AMD64 Architecture Programmer’s Manual Volume 2: System Programming]