perf-c2c.txt 7.8 KB

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  1. perf-c2c(1)
  2. ===========
  3. NAME
  4. ----
  5. perf-c2c - Shared Data C2C/HITM Analyzer.
  6. SYNOPSIS
  7. --------
  8. [verse]
  9. 'perf c2c record' [<options>] <command>
  10. 'perf c2c record' [<options>] -- [<record command options>] <command>
  11. 'perf c2c report' [<options>]
  12. DESCRIPTION
  13. -----------
  14. C2C stands for Cache To Cache.
  15. The perf c2c tool provides means for Shared Data C2C/HITM analysis. It allows
  16. you to track down the cacheline contentions.
  17. On x86, the tool is based on load latency and precise store facility events
  18. provided by Intel CPUs. On PowerPC, the tool uses random instruction sampling
  19. with thresholding feature.
  20. These events provide:
  21. - memory address of the access
  22. - type of the access (load and store details)
  23. - latency (in cycles) of the load access
  24. The c2c tool provide means to record this data and report back access details
  25. for cachelines with highest contention - highest number of HITM accesses.
  26. The basic workflow with this tool follows the standard record/report phase.
  27. User uses the record command to record events data and report command to
  28. display it.
  29. RECORD OPTIONS
  30. --------------
  31. -e::
  32. --event=::
  33. Select the PMU event. Use 'perf c2c record -e list'
  34. to list available events.
  35. -v::
  36. --verbose::
  37. Be more verbose (show counter open errors, etc).
  38. -l::
  39. --ldlat::
  40. Configure mem-loads latency. (x86 only)
  41. -k::
  42. --all-kernel::
  43. Configure all used events to run in kernel space.
  44. -u::
  45. --all-user::
  46. Configure all used events to run in user space.
  47. REPORT OPTIONS
  48. --------------
  49. -k::
  50. --vmlinux=<file>::
  51. vmlinux pathname
  52. -v::
  53. --verbose::
  54. Be more verbose (show counter open errors, etc).
  55. -i::
  56. --input::
  57. Specify the input file to process.
  58. -N::
  59. --node-info::
  60. Show extra node info in report (see NODE INFO section)
  61. -c::
  62. --coalesce::
  63. Specify sorting fields for single cacheline display.
  64. Following fields are available: tid,pid,iaddr,dso
  65. (see COALESCE)
  66. -g::
  67. --call-graph::
  68. Setup callchains parameters.
  69. Please refer to perf-report man page for details.
  70. --stdio::
  71. Force the stdio output (see STDIO OUTPUT)
  72. --stats::
  73. Display only statistic tables and force stdio mode.
  74. --full-symbols::
  75. Display full length of symbols.
  76. --no-source::
  77. Do not display Source:Line column.
  78. --show-all::
  79. Show all captured HITM lines, with no regard to HITM % 0.0005 limit.
  80. -f::
  81. --force::
  82. Don't do ownership validation.
  83. -d::
  84. --display::
  85. Switch to HITM type (rmt, lcl) to display and sort on. Total HITMs as default.
  86. --stitch-lbr::
  87. Show callgraph with stitched LBRs, which may have more complete
  88. callgraph. The perf.data file must have been obtained using
  89. perf c2c record --call-graph lbr.
  90. Disabled by default. In common cases with call stack overflows,
  91. it can recreate better call stacks than the default lbr call stack
  92. output. But this approach is not full proof. There can be cases
  93. where it creates incorrect call stacks from incorrect matches.
  94. The known limitations include exception handing such as
  95. setjmp/longjmp will have calls/returns not match.
  96. C2C RECORD
  97. ----------
  98. The perf c2c record command setup options related to HITM cacheline analysis
  99. and calls standard perf record command.
  100. Following perf record options are configured by default:
  101. (check perf record man page for details)
  102. -W,-d,--phys-data,--sample-cpu
  103. Unless specified otherwise with '-e' option, following events are monitored by
  104. default on x86:
  105. cpu/mem-loads,ldlat=30/P
  106. cpu/mem-stores/P
  107. and following on PowerPC:
  108. cpu/mem-loads/
  109. cpu/mem-stores/
  110. User can pass any 'perf record' option behind '--' mark, like (to enable
  111. callchains and system wide monitoring):
  112. $ perf c2c record -- -g -a
  113. Please check RECORD OPTIONS section for specific c2c record options.
  114. C2C REPORT
  115. ----------
  116. The perf c2c report command displays shared data analysis. It comes in two
  117. display modes: stdio and tui (default).
  118. The report command workflow is following:
  119. - sort all the data based on the cacheline address
  120. - store access details for each cacheline
  121. - sort all cachelines based on user settings
  122. - display data
  123. In general perf report output consist of 2 basic views:
  124. 1) most expensive cachelines list
  125. 2) offsets details for each cacheline
  126. For each cacheline in the 1) list we display following data:
  127. (Both stdio and TUI modes follow the same fields output)
  128. Index
  129. - zero based index to identify the cacheline
  130. Cacheline
  131. - cacheline address (hex number)
  132. Rmt/Lcl Hitm
  133. - cacheline percentage of all Remote/Local HITM accesses
  134. LLC Load Hitm - Total, LclHitm, RmtHitm
  135. - count of Total/Local/Remote load HITMs
  136. Total records
  137. - sum of all cachelines accesses
  138. Total loads
  139. - sum of all load accesses
  140. Total stores
  141. - sum of all store accesses
  142. Store Reference - L1Hit, L1Miss
  143. L1Hit - store accesses that hit L1
  144. L1Miss - store accesses that missed L1
  145. Core Load Hit - FB, L1, L2
  146. - count of load hits in FB (Fill Buffer), L1 and L2 cache
  147. LLC Load Hit - LlcHit, LclHitm
  148. - count of LLC load accesses, includes LLC hits and LLC HITMs
  149. RMT Load Hit - RmtHit, RmtHitm
  150. - count of remote load accesses, includes remote hits and remote HITMs
  151. Load Dram - Lcl, Rmt
  152. - count of local and remote DRAM accesses
  153. For each offset in the 2) list we display following data:
  154. HITM - Rmt, Lcl
  155. - % of Remote/Local HITM accesses for given offset within cacheline
  156. Store Refs - L1 Hit, L1 Miss
  157. - % of store accesses that hit/missed L1 for given offset within cacheline
  158. Data address - Offset
  159. - offset address
  160. Pid
  161. - pid of the process responsible for the accesses
  162. Tid
  163. - tid of the process responsible for the accesses
  164. Code address
  165. - code address responsible for the accesses
  166. cycles - rmt hitm, lcl hitm, load
  167. - sum of cycles for given accesses - Remote/Local HITM and generic load
  168. cpu cnt
  169. - number of cpus that participated on the access
  170. Symbol
  171. - code symbol related to the 'Code address' value
  172. Shared Object
  173. - shared object name related to the 'Code address' value
  174. Source:Line
  175. - source information related to the 'Code address' value
  176. Node
  177. - nodes participating on the access (see NODE INFO section)
  178. NODE INFO
  179. ---------
  180. The 'Node' field displays nodes that accesses given cacheline
  181. offset. Its output comes in 3 flavors:
  182. - node IDs separated by ','
  183. - node IDs with stats for each ID, in following format:
  184. Node{cpus %hitms %stores}
  185. - node IDs with list of affected CPUs in following format:
  186. Node{cpu list}
  187. User can switch between above flavors with -N option or
  188. use 'n' key to interactively switch in TUI mode.
  189. COALESCE
  190. --------
  191. User can specify how to sort offsets for cacheline.
  192. Following fields are available and governs the final
  193. output fields set for caheline offsets output:
  194. tid - coalesced by process TIDs
  195. pid - coalesced by process PIDs
  196. iaddr - coalesced by code address, following fields are displayed:
  197. Code address, Code symbol, Shared Object, Source line
  198. dso - coalesced by shared object
  199. By default the coalescing is setup with 'pid,iaddr'.
  200. STDIO OUTPUT
  201. ------------
  202. The stdio output displays data on standard output.
  203. Following tables are displayed:
  204. Trace Event Information
  205. - overall statistics of memory accesses
  206. Global Shared Cache Line Event Information
  207. - overall statistics on shared cachelines
  208. Shared Data Cache Line Table
  209. - list of most expensive cachelines
  210. Shared Cache Line Distribution Pareto
  211. - list of all accessed offsets for each cacheline
  212. TUI OUTPUT
  213. ----------
  214. The TUI output provides interactive interface to navigate
  215. through cachelines list and to display offset details.
  216. For details please refer to the help window by pressing '?' key.
  217. CREDITS
  218. -------
  219. Although Don Zickus, Dick Fowles and Joe Mario worked together
  220. to get this implemented, we got lots of early help from Arnaldo
  221. Carvalho de Melo, Stephane Eranian, Jiri Olsa and Andi Kleen.
  222. C2C BLOG
  223. --------
  224. Check Joe's blog on c2c tool for detailed use case explanation:
  225. https://joemario.github.io/blog/2016/09/01/c2c-blog/
  226. SEE ALSO
  227. --------
  228. linkperf:perf-record[1], linkperf:perf-mem[1]