mtty.c 33 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Mediated virtual PCI serial host device driver
  4. *
  5. * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
  6. * Author: Neo Jia <cjia@nvidia.com>
  7. * Kirti Wankhede <kwankhede@nvidia.com>
  8. *
  9. * Sample driver that creates mdev device that simulates serial port over PCI
  10. * card.
  11. */
  12. #include <linux/init.h>
  13. #include <linux/module.h>
  14. #include <linux/device.h>
  15. #include <linux/kernel.h>
  16. #include <linux/fs.h>
  17. #include <linux/poll.h>
  18. #include <linux/slab.h>
  19. #include <linux/cdev.h>
  20. #include <linux/sched.h>
  21. #include <linux/wait.h>
  22. #include <linux/uuid.h>
  23. #include <linux/vfio.h>
  24. #include <linux/iommu.h>
  25. #include <linux/sysfs.h>
  26. #include <linux/ctype.h>
  27. #include <linux/file.h>
  28. #include <linux/mdev.h>
  29. #include <linux/pci.h>
  30. #include <linux/serial.h>
  31. #include <uapi/linux/serial_reg.h>
  32. #include <linux/eventfd.h>
  33. /*
  34. * #defines
  35. */
  36. #define VERSION_STRING "0.1"
  37. #define DRIVER_AUTHOR "NVIDIA Corporation"
  38. #define MTTY_CLASS_NAME "mtty"
  39. #define MTTY_NAME "mtty"
  40. #define MTTY_STRING_LEN 16
  41. #define MTTY_CONFIG_SPACE_SIZE 0xff
  42. #define MTTY_IO_BAR_SIZE 0x8
  43. #define MTTY_MMIO_BAR_SIZE 0x100000
  44. #define STORE_LE16(addr, val) (*(u16 *)addr = val)
  45. #define STORE_LE32(addr, val) (*(u32 *)addr = val)
  46. #define MAX_FIFO_SIZE 16
  47. #define CIRCULAR_BUF_INC_IDX(idx) (idx = (idx + 1) & (MAX_FIFO_SIZE - 1))
  48. #define MTTY_VFIO_PCI_OFFSET_SHIFT 40
  49. #define MTTY_VFIO_PCI_OFFSET_TO_INDEX(off) (off >> MTTY_VFIO_PCI_OFFSET_SHIFT)
  50. #define MTTY_VFIO_PCI_INDEX_TO_OFFSET(index) \
  51. ((u64)(index) << MTTY_VFIO_PCI_OFFSET_SHIFT)
  52. #define MTTY_VFIO_PCI_OFFSET_MASK \
  53. (((u64)(1) << MTTY_VFIO_PCI_OFFSET_SHIFT) - 1)
  54. #define MAX_MTTYS 24
  55. /*
  56. * Global Structures
  57. */
  58. static struct mtty_dev {
  59. dev_t vd_devt;
  60. struct class *vd_class;
  61. struct cdev vd_cdev;
  62. struct idr vd_idr;
  63. struct device dev;
  64. } mtty_dev;
  65. struct mdev_region_info {
  66. u64 start;
  67. u64 phys_start;
  68. u32 size;
  69. u64 vfio_offset;
  70. };
  71. #if defined(DEBUG_REGS)
  72. static const char *wr_reg[] = {
  73. "TX",
  74. "IER",
  75. "FCR",
  76. "LCR",
  77. "MCR",
  78. "LSR",
  79. "MSR",
  80. "SCR"
  81. };
  82. static const char *rd_reg[] = {
  83. "RX",
  84. "IER",
  85. "IIR",
  86. "LCR",
  87. "MCR",
  88. "LSR",
  89. "MSR",
  90. "SCR"
  91. };
  92. #endif
  93. /* loop back buffer */
  94. struct rxtx {
  95. u8 fifo[MAX_FIFO_SIZE];
  96. u8 head, tail;
  97. u8 count;
  98. };
  99. struct serial_port {
  100. u8 uart_reg[8]; /* 8 registers */
  101. struct rxtx rxtx; /* loop back buffer */
  102. bool dlab;
  103. bool overrun;
  104. u16 divisor;
  105. u8 fcr; /* FIFO control register */
  106. u8 max_fifo_size;
  107. u8 intr_trigger_level; /* interrupt trigger level */
  108. };
  109. /* State of each mdev device */
  110. struct mdev_state {
  111. int irq_fd;
  112. struct eventfd_ctx *intx_evtfd;
  113. struct eventfd_ctx *msi_evtfd;
  114. int irq_index;
  115. u8 *vconfig;
  116. struct mutex ops_lock;
  117. struct mdev_device *mdev;
  118. struct mdev_region_info region_info[VFIO_PCI_NUM_REGIONS];
  119. u32 bar_mask[VFIO_PCI_NUM_REGIONS];
  120. struct list_head next;
  121. struct serial_port s[2];
  122. struct mutex rxtx_lock;
  123. struct vfio_device_info dev_info;
  124. int nr_ports;
  125. };
  126. static struct mutex mdev_list_lock;
  127. static struct list_head mdev_devices_list;
  128. static const struct file_operations vd_fops = {
  129. .owner = THIS_MODULE,
  130. };
  131. /* function prototypes */
  132. static int mtty_trigger_interrupt(struct mdev_state *mdev_state);
  133. /* Helper functions */
  134. static void dump_buffer(u8 *buf, uint32_t count)
  135. {
  136. #if defined(DEBUG)
  137. int i;
  138. pr_info("Buffer:\n");
  139. for (i = 0; i < count; i++) {
  140. pr_info("%2x ", *(buf + i));
  141. if ((i + 1) % 16 == 0)
  142. pr_info("\n");
  143. }
  144. #endif
  145. }
  146. static void mtty_create_config_space(struct mdev_state *mdev_state)
  147. {
  148. /* PCI dev ID */
  149. STORE_LE32((u32 *) &mdev_state->vconfig[0x0], 0x32534348);
  150. /* Control: I/O+, Mem-, BusMaster- */
  151. STORE_LE16((u16 *) &mdev_state->vconfig[0x4], 0x0001);
  152. /* Status: capabilities list absent */
  153. STORE_LE16((u16 *) &mdev_state->vconfig[0x6], 0x0200);
  154. /* Rev ID */
  155. mdev_state->vconfig[0x8] = 0x10;
  156. /* programming interface class : 16550-compatible serial controller */
  157. mdev_state->vconfig[0x9] = 0x02;
  158. /* Sub class : 00 */
  159. mdev_state->vconfig[0xa] = 0x00;
  160. /* Base class : Simple Communication controllers */
  161. mdev_state->vconfig[0xb] = 0x07;
  162. /* base address registers */
  163. /* BAR0: IO space */
  164. STORE_LE32((u32 *) &mdev_state->vconfig[0x10], 0x000001);
  165. mdev_state->bar_mask[0] = ~(MTTY_IO_BAR_SIZE) + 1;
  166. if (mdev_state->nr_ports == 2) {
  167. /* BAR1: IO space */
  168. STORE_LE32((u32 *) &mdev_state->vconfig[0x14], 0x000001);
  169. mdev_state->bar_mask[1] = ~(MTTY_IO_BAR_SIZE) + 1;
  170. }
  171. /* Subsystem ID */
  172. STORE_LE32((u32 *) &mdev_state->vconfig[0x2c], 0x32534348);
  173. mdev_state->vconfig[0x34] = 0x00; /* Cap Ptr */
  174. mdev_state->vconfig[0x3d] = 0x01; /* interrupt pin (INTA#) */
  175. /* Vendor specific data */
  176. mdev_state->vconfig[0x40] = 0x23;
  177. mdev_state->vconfig[0x43] = 0x80;
  178. mdev_state->vconfig[0x44] = 0x23;
  179. mdev_state->vconfig[0x48] = 0x23;
  180. mdev_state->vconfig[0x4c] = 0x23;
  181. mdev_state->vconfig[0x60] = 0x50;
  182. mdev_state->vconfig[0x61] = 0x43;
  183. mdev_state->vconfig[0x62] = 0x49;
  184. mdev_state->vconfig[0x63] = 0x20;
  185. mdev_state->vconfig[0x64] = 0x53;
  186. mdev_state->vconfig[0x65] = 0x65;
  187. mdev_state->vconfig[0x66] = 0x72;
  188. mdev_state->vconfig[0x67] = 0x69;
  189. mdev_state->vconfig[0x68] = 0x61;
  190. mdev_state->vconfig[0x69] = 0x6c;
  191. mdev_state->vconfig[0x6a] = 0x2f;
  192. mdev_state->vconfig[0x6b] = 0x55;
  193. mdev_state->vconfig[0x6c] = 0x41;
  194. mdev_state->vconfig[0x6d] = 0x52;
  195. mdev_state->vconfig[0x6e] = 0x54;
  196. }
  197. static void handle_pci_cfg_write(struct mdev_state *mdev_state, u16 offset,
  198. u8 *buf, u32 count)
  199. {
  200. u32 cfg_addr, bar_mask, bar_index = 0;
  201. switch (offset) {
  202. case 0x04: /* device control */
  203. case 0x06: /* device status */
  204. /* do nothing */
  205. break;
  206. case 0x3c: /* interrupt line */
  207. mdev_state->vconfig[0x3c] = buf[0];
  208. break;
  209. case 0x3d:
  210. /*
  211. * Interrupt Pin is hardwired to INTA.
  212. * This field is write protected by hardware
  213. */
  214. break;
  215. case 0x10: /* BAR0 */
  216. case 0x14: /* BAR1 */
  217. if (offset == 0x10)
  218. bar_index = 0;
  219. else if (offset == 0x14)
  220. bar_index = 1;
  221. if ((mdev_state->nr_ports == 1) && (bar_index == 1)) {
  222. STORE_LE32(&mdev_state->vconfig[offset], 0);
  223. break;
  224. }
  225. cfg_addr = *(u32 *)buf;
  226. pr_info("BAR%d addr 0x%x\n", bar_index, cfg_addr);
  227. if (cfg_addr == 0xffffffff) {
  228. bar_mask = mdev_state->bar_mask[bar_index];
  229. cfg_addr = (cfg_addr & bar_mask);
  230. }
  231. cfg_addr |= (mdev_state->vconfig[offset] & 0x3ul);
  232. STORE_LE32(&mdev_state->vconfig[offset], cfg_addr);
  233. break;
  234. case 0x18: /* BAR2 */
  235. case 0x1c: /* BAR3 */
  236. case 0x20: /* BAR4 */
  237. STORE_LE32(&mdev_state->vconfig[offset], 0);
  238. break;
  239. default:
  240. pr_info("PCI config write @0x%x of %d bytes not handled\n",
  241. offset, count);
  242. break;
  243. }
  244. }
  245. static void handle_bar_write(unsigned int index, struct mdev_state *mdev_state,
  246. u16 offset, u8 *buf, u32 count)
  247. {
  248. u8 data = *buf;
  249. /* Handle data written by guest */
  250. switch (offset) {
  251. case UART_TX:
  252. /* if DLAB set, data is LSB of divisor */
  253. if (mdev_state->s[index].dlab) {
  254. mdev_state->s[index].divisor |= data;
  255. break;
  256. }
  257. mutex_lock(&mdev_state->rxtx_lock);
  258. /* save in TX buffer */
  259. if (mdev_state->s[index].rxtx.count <
  260. mdev_state->s[index].max_fifo_size) {
  261. mdev_state->s[index].rxtx.fifo[
  262. mdev_state->s[index].rxtx.head] = data;
  263. mdev_state->s[index].rxtx.count++;
  264. CIRCULAR_BUF_INC_IDX(mdev_state->s[index].rxtx.head);
  265. mdev_state->s[index].overrun = false;
  266. /*
  267. * Trigger interrupt if receive data interrupt is
  268. * enabled and fifo reached trigger level
  269. */
  270. if ((mdev_state->s[index].uart_reg[UART_IER] &
  271. UART_IER_RDI) &&
  272. (mdev_state->s[index].rxtx.count ==
  273. mdev_state->s[index].intr_trigger_level)) {
  274. /* trigger interrupt */
  275. #if defined(DEBUG_INTR)
  276. pr_err("Serial port %d: Fifo level trigger\n",
  277. index);
  278. #endif
  279. mtty_trigger_interrupt(mdev_state);
  280. }
  281. } else {
  282. #if defined(DEBUG_INTR)
  283. pr_err("Serial port %d: Buffer Overflow\n", index);
  284. #endif
  285. mdev_state->s[index].overrun = true;
  286. /*
  287. * Trigger interrupt if receiver line status interrupt
  288. * is enabled
  289. */
  290. if (mdev_state->s[index].uart_reg[UART_IER] &
  291. UART_IER_RLSI)
  292. mtty_trigger_interrupt(mdev_state);
  293. }
  294. mutex_unlock(&mdev_state->rxtx_lock);
  295. break;
  296. case UART_IER:
  297. /* if DLAB set, data is MSB of divisor */
  298. if (mdev_state->s[index].dlab)
  299. mdev_state->s[index].divisor |= (u16)data << 8;
  300. else {
  301. mdev_state->s[index].uart_reg[offset] = data;
  302. mutex_lock(&mdev_state->rxtx_lock);
  303. if ((data & UART_IER_THRI) &&
  304. (mdev_state->s[index].rxtx.head ==
  305. mdev_state->s[index].rxtx.tail)) {
  306. #if defined(DEBUG_INTR)
  307. pr_err("Serial port %d: IER_THRI write\n",
  308. index);
  309. #endif
  310. mtty_trigger_interrupt(mdev_state);
  311. }
  312. mutex_unlock(&mdev_state->rxtx_lock);
  313. }
  314. break;
  315. case UART_FCR:
  316. mdev_state->s[index].fcr = data;
  317. mutex_lock(&mdev_state->rxtx_lock);
  318. if (data & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT)) {
  319. /* clear loop back FIFO */
  320. mdev_state->s[index].rxtx.count = 0;
  321. mdev_state->s[index].rxtx.head = 0;
  322. mdev_state->s[index].rxtx.tail = 0;
  323. }
  324. mutex_unlock(&mdev_state->rxtx_lock);
  325. switch (data & UART_FCR_TRIGGER_MASK) {
  326. case UART_FCR_TRIGGER_1:
  327. mdev_state->s[index].intr_trigger_level = 1;
  328. break;
  329. case UART_FCR_TRIGGER_4:
  330. mdev_state->s[index].intr_trigger_level = 4;
  331. break;
  332. case UART_FCR_TRIGGER_8:
  333. mdev_state->s[index].intr_trigger_level = 8;
  334. break;
  335. case UART_FCR_TRIGGER_14:
  336. mdev_state->s[index].intr_trigger_level = 14;
  337. break;
  338. }
  339. /*
  340. * Set trigger level to 1 otherwise or implement timer with
  341. * timeout of 4 characters and on expiring that timer set
  342. * Recevice data timeout in IIR register
  343. */
  344. mdev_state->s[index].intr_trigger_level = 1;
  345. if (data & UART_FCR_ENABLE_FIFO)
  346. mdev_state->s[index].max_fifo_size = MAX_FIFO_SIZE;
  347. else {
  348. mdev_state->s[index].max_fifo_size = 1;
  349. mdev_state->s[index].intr_trigger_level = 1;
  350. }
  351. break;
  352. case UART_LCR:
  353. if (data & UART_LCR_DLAB) {
  354. mdev_state->s[index].dlab = true;
  355. mdev_state->s[index].divisor = 0;
  356. } else
  357. mdev_state->s[index].dlab = false;
  358. mdev_state->s[index].uart_reg[offset] = data;
  359. break;
  360. case UART_MCR:
  361. mdev_state->s[index].uart_reg[offset] = data;
  362. if ((mdev_state->s[index].uart_reg[UART_IER] & UART_IER_MSI) &&
  363. (data & UART_MCR_OUT2)) {
  364. #if defined(DEBUG_INTR)
  365. pr_err("Serial port %d: MCR_OUT2 write\n", index);
  366. #endif
  367. mtty_trigger_interrupt(mdev_state);
  368. }
  369. if ((mdev_state->s[index].uart_reg[UART_IER] & UART_IER_MSI) &&
  370. (data & (UART_MCR_RTS | UART_MCR_DTR))) {
  371. #if defined(DEBUG_INTR)
  372. pr_err("Serial port %d: MCR RTS/DTR write\n", index);
  373. #endif
  374. mtty_trigger_interrupt(mdev_state);
  375. }
  376. break;
  377. case UART_LSR:
  378. case UART_MSR:
  379. /* do nothing */
  380. break;
  381. case UART_SCR:
  382. mdev_state->s[index].uart_reg[offset] = data;
  383. break;
  384. default:
  385. break;
  386. }
  387. }
  388. static void handle_bar_read(unsigned int index, struct mdev_state *mdev_state,
  389. u16 offset, u8 *buf, u32 count)
  390. {
  391. /* Handle read requests by guest */
  392. switch (offset) {
  393. case UART_RX:
  394. /* if DLAB set, data is LSB of divisor */
  395. if (mdev_state->s[index].dlab) {
  396. *buf = (u8)mdev_state->s[index].divisor;
  397. break;
  398. }
  399. mutex_lock(&mdev_state->rxtx_lock);
  400. /* return data in tx buffer */
  401. if (mdev_state->s[index].rxtx.head !=
  402. mdev_state->s[index].rxtx.tail) {
  403. *buf = mdev_state->s[index].rxtx.fifo[
  404. mdev_state->s[index].rxtx.tail];
  405. mdev_state->s[index].rxtx.count--;
  406. CIRCULAR_BUF_INC_IDX(mdev_state->s[index].rxtx.tail);
  407. }
  408. if (mdev_state->s[index].rxtx.head ==
  409. mdev_state->s[index].rxtx.tail) {
  410. /*
  411. * Trigger interrupt if tx buffer empty interrupt is
  412. * enabled and fifo is empty
  413. */
  414. #if defined(DEBUG_INTR)
  415. pr_err("Serial port %d: Buffer Empty\n", index);
  416. #endif
  417. if (mdev_state->s[index].uart_reg[UART_IER] &
  418. UART_IER_THRI)
  419. mtty_trigger_interrupt(mdev_state);
  420. }
  421. mutex_unlock(&mdev_state->rxtx_lock);
  422. break;
  423. case UART_IER:
  424. if (mdev_state->s[index].dlab) {
  425. *buf = (u8)(mdev_state->s[index].divisor >> 8);
  426. break;
  427. }
  428. *buf = mdev_state->s[index].uart_reg[offset] & 0x0f;
  429. break;
  430. case UART_IIR:
  431. {
  432. u8 ier = mdev_state->s[index].uart_reg[UART_IER];
  433. *buf = 0;
  434. mutex_lock(&mdev_state->rxtx_lock);
  435. /* Interrupt priority 1: Parity, overrun, framing or break */
  436. if ((ier & UART_IER_RLSI) && mdev_state->s[index].overrun)
  437. *buf |= UART_IIR_RLSI;
  438. /* Interrupt priority 2: Fifo trigger level reached */
  439. if ((ier & UART_IER_RDI) &&
  440. (mdev_state->s[index].rxtx.count >=
  441. mdev_state->s[index].intr_trigger_level))
  442. *buf |= UART_IIR_RDI;
  443. /* Interrupt priotiry 3: transmitter holding register empty */
  444. if ((ier & UART_IER_THRI) &&
  445. (mdev_state->s[index].rxtx.head ==
  446. mdev_state->s[index].rxtx.tail))
  447. *buf |= UART_IIR_THRI;
  448. /* Interrupt priotiry 4: Modem status: CTS, DSR, RI or DCD */
  449. if ((ier & UART_IER_MSI) &&
  450. (mdev_state->s[index].uart_reg[UART_MCR] &
  451. (UART_MCR_RTS | UART_MCR_DTR)))
  452. *buf |= UART_IIR_MSI;
  453. /* bit0: 0=> interrupt pending, 1=> no interrupt is pending */
  454. if (*buf == 0)
  455. *buf = UART_IIR_NO_INT;
  456. /* set bit 6 & 7 to be 16550 compatible */
  457. *buf |= 0xC0;
  458. mutex_unlock(&mdev_state->rxtx_lock);
  459. }
  460. break;
  461. case UART_LCR:
  462. case UART_MCR:
  463. *buf = mdev_state->s[index].uart_reg[offset];
  464. break;
  465. case UART_LSR:
  466. {
  467. u8 lsr = 0;
  468. mutex_lock(&mdev_state->rxtx_lock);
  469. /* atleast one char in FIFO */
  470. if (mdev_state->s[index].rxtx.head !=
  471. mdev_state->s[index].rxtx.tail)
  472. lsr |= UART_LSR_DR;
  473. /* if FIFO overrun */
  474. if (mdev_state->s[index].overrun)
  475. lsr |= UART_LSR_OE;
  476. /* transmit FIFO empty and tramsitter empty */
  477. if (mdev_state->s[index].rxtx.head ==
  478. mdev_state->s[index].rxtx.tail)
  479. lsr |= UART_LSR_TEMT | UART_LSR_THRE;
  480. mutex_unlock(&mdev_state->rxtx_lock);
  481. *buf = lsr;
  482. break;
  483. }
  484. case UART_MSR:
  485. *buf = UART_MSR_DSR | UART_MSR_DDSR | UART_MSR_DCD;
  486. mutex_lock(&mdev_state->rxtx_lock);
  487. /* if AFE is 1 and FIFO have space, set CTS bit */
  488. if (mdev_state->s[index].uart_reg[UART_MCR] &
  489. UART_MCR_AFE) {
  490. if (mdev_state->s[index].rxtx.count <
  491. mdev_state->s[index].max_fifo_size)
  492. *buf |= UART_MSR_CTS | UART_MSR_DCTS;
  493. } else
  494. *buf |= UART_MSR_CTS | UART_MSR_DCTS;
  495. mutex_unlock(&mdev_state->rxtx_lock);
  496. break;
  497. case UART_SCR:
  498. *buf = mdev_state->s[index].uart_reg[offset];
  499. break;
  500. default:
  501. break;
  502. }
  503. }
  504. static void mdev_read_base(struct mdev_state *mdev_state)
  505. {
  506. int index, pos;
  507. u32 start_lo, start_hi;
  508. u32 mem_type;
  509. pos = PCI_BASE_ADDRESS_0;
  510. for (index = 0; index <= VFIO_PCI_BAR5_REGION_INDEX; index++) {
  511. if (!mdev_state->region_info[index].size)
  512. continue;
  513. start_lo = (*(u32 *)(mdev_state->vconfig + pos)) &
  514. PCI_BASE_ADDRESS_MEM_MASK;
  515. mem_type = (*(u32 *)(mdev_state->vconfig + pos)) &
  516. PCI_BASE_ADDRESS_MEM_TYPE_MASK;
  517. switch (mem_type) {
  518. case PCI_BASE_ADDRESS_MEM_TYPE_64:
  519. start_hi = (*(u32 *)(mdev_state->vconfig + pos + 4));
  520. pos += 4;
  521. break;
  522. case PCI_BASE_ADDRESS_MEM_TYPE_32:
  523. case PCI_BASE_ADDRESS_MEM_TYPE_1M:
  524. /* 1M mem BAR treated as 32-bit BAR */
  525. default:
  526. /* mem unknown type treated as 32-bit BAR */
  527. start_hi = 0;
  528. break;
  529. }
  530. pos += 4;
  531. mdev_state->region_info[index].start = ((u64)start_hi << 32) |
  532. start_lo;
  533. }
  534. }
  535. static ssize_t mdev_access(struct mdev_device *mdev, u8 *buf, size_t count,
  536. loff_t pos, bool is_write)
  537. {
  538. struct mdev_state *mdev_state;
  539. unsigned int index;
  540. loff_t offset;
  541. int ret = 0;
  542. if (!mdev || !buf)
  543. return -EINVAL;
  544. mdev_state = mdev_get_drvdata(mdev);
  545. if (!mdev_state) {
  546. pr_err("%s mdev_state not found\n", __func__);
  547. return -EINVAL;
  548. }
  549. mutex_lock(&mdev_state->ops_lock);
  550. index = MTTY_VFIO_PCI_OFFSET_TO_INDEX(pos);
  551. offset = pos & MTTY_VFIO_PCI_OFFSET_MASK;
  552. switch (index) {
  553. case VFIO_PCI_CONFIG_REGION_INDEX:
  554. #if defined(DEBUG)
  555. pr_info("%s: PCI config space %s at offset 0x%llx\n",
  556. __func__, is_write ? "write" : "read", offset);
  557. #endif
  558. if (is_write) {
  559. dump_buffer(buf, count);
  560. handle_pci_cfg_write(mdev_state, offset, buf, count);
  561. } else {
  562. memcpy(buf, (mdev_state->vconfig + offset), count);
  563. dump_buffer(buf, count);
  564. }
  565. break;
  566. case VFIO_PCI_BAR0_REGION_INDEX ... VFIO_PCI_BAR5_REGION_INDEX:
  567. if (!mdev_state->region_info[index].start)
  568. mdev_read_base(mdev_state);
  569. if (is_write) {
  570. dump_buffer(buf, count);
  571. #if defined(DEBUG_REGS)
  572. pr_info("%s: BAR%d WR @0x%llx %s val:0x%02x dlab:%d\n",
  573. __func__, index, offset, wr_reg[offset],
  574. *buf, mdev_state->s[index].dlab);
  575. #endif
  576. handle_bar_write(index, mdev_state, offset, buf, count);
  577. } else {
  578. handle_bar_read(index, mdev_state, offset, buf, count);
  579. dump_buffer(buf, count);
  580. #if defined(DEBUG_REGS)
  581. pr_info("%s: BAR%d RD @0x%llx %s val:0x%02x dlab:%d\n",
  582. __func__, index, offset, rd_reg[offset],
  583. *buf, mdev_state->s[index].dlab);
  584. #endif
  585. }
  586. break;
  587. default:
  588. ret = -1;
  589. goto accessfailed;
  590. }
  591. ret = count;
  592. accessfailed:
  593. mutex_unlock(&mdev_state->ops_lock);
  594. return ret;
  595. }
  596. static int mtty_create(struct kobject *kobj, struct mdev_device *mdev)
  597. {
  598. struct mdev_state *mdev_state;
  599. char name[MTTY_STRING_LEN];
  600. int nr_ports = 0, i;
  601. if (!mdev)
  602. return -EINVAL;
  603. for (i = 0; i < 2; i++) {
  604. snprintf(name, MTTY_STRING_LEN, "%s-%d",
  605. dev_driver_string(mdev_parent_dev(mdev)), i + 1);
  606. if (!strcmp(kobj->name, name)) {
  607. nr_ports = i + 1;
  608. break;
  609. }
  610. }
  611. if (!nr_ports)
  612. return -EINVAL;
  613. mdev_state = kzalloc(sizeof(struct mdev_state), GFP_KERNEL);
  614. if (mdev_state == NULL)
  615. return -ENOMEM;
  616. mdev_state->nr_ports = nr_ports;
  617. mdev_state->irq_index = -1;
  618. mdev_state->s[0].max_fifo_size = MAX_FIFO_SIZE;
  619. mdev_state->s[1].max_fifo_size = MAX_FIFO_SIZE;
  620. mutex_init(&mdev_state->rxtx_lock);
  621. mdev_state->vconfig = kzalloc(MTTY_CONFIG_SPACE_SIZE, GFP_KERNEL);
  622. if (mdev_state->vconfig == NULL) {
  623. kfree(mdev_state);
  624. return -ENOMEM;
  625. }
  626. mutex_init(&mdev_state->ops_lock);
  627. mdev_state->mdev = mdev;
  628. mdev_set_drvdata(mdev, mdev_state);
  629. mtty_create_config_space(mdev_state);
  630. mutex_lock(&mdev_list_lock);
  631. list_add(&mdev_state->next, &mdev_devices_list);
  632. mutex_unlock(&mdev_list_lock);
  633. return 0;
  634. }
  635. static int mtty_remove(struct mdev_device *mdev)
  636. {
  637. struct mdev_state *mds, *tmp_mds;
  638. struct mdev_state *mdev_state = mdev_get_drvdata(mdev);
  639. int ret = -EINVAL;
  640. mutex_lock(&mdev_list_lock);
  641. list_for_each_entry_safe(mds, tmp_mds, &mdev_devices_list, next) {
  642. if (mdev_state == mds) {
  643. list_del(&mdev_state->next);
  644. mdev_set_drvdata(mdev, NULL);
  645. kfree(mdev_state->vconfig);
  646. kfree(mdev_state);
  647. ret = 0;
  648. break;
  649. }
  650. }
  651. mutex_unlock(&mdev_list_lock);
  652. return ret;
  653. }
  654. static int mtty_reset(struct mdev_device *mdev)
  655. {
  656. struct mdev_state *mdev_state;
  657. if (!mdev)
  658. return -EINVAL;
  659. mdev_state = mdev_get_drvdata(mdev);
  660. if (!mdev_state)
  661. return -EINVAL;
  662. pr_info("%s: called\n", __func__);
  663. return 0;
  664. }
  665. static ssize_t mtty_read(struct mdev_device *mdev, char __user *buf,
  666. size_t count, loff_t *ppos)
  667. {
  668. unsigned int done = 0;
  669. int ret;
  670. while (count) {
  671. size_t filled;
  672. if (count >= 4 && !(*ppos % 4)) {
  673. u32 val;
  674. ret = mdev_access(mdev, (u8 *)&val, sizeof(val),
  675. *ppos, false);
  676. if (ret <= 0)
  677. goto read_err;
  678. if (copy_to_user(buf, &val, sizeof(val)))
  679. goto read_err;
  680. filled = 4;
  681. } else if (count >= 2 && !(*ppos % 2)) {
  682. u16 val;
  683. ret = mdev_access(mdev, (u8 *)&val, sizeof(val),
  684. *ppos, false);
  685. if (ret <= 0)
  686. goto read_err;
  687. if (copy_to_user(buf, &val, sizeof(val)))
  688. goto read_err;
  689. filled = 2;
  690. } else {
  691. u8 val;
  692. ret = mdev_access(mdev, (u8 *)&val, sizeof(val),
  693. *ppos, false);
  694. if (ret <= 0)
  695. goto read_err;
  696. if (copy_to_user(buf, &val, sizeof(val)))
  697. goto read_err;
  698. filled = 1;
  699. }
  700. count -= filled;
  701. done += filled;
  702. *ppos += filled;
  703. buf += filled;
  704. }
  705. return done;
  706. read_err:
  707. return -EFAULT;
  708. }
  709. static ssize_t mtty_write(struct mdev_device *mdev, const char __user *buf,
  710. size_t count, loff_t *ppos)
  711. {
  712. unsigned int done = 0;
  713. int ret;
  714. while (count) {
  715. size_t filled;
  716. if (count >= 4 && !(*ppos % 4)) {
  717. u32 val;
  718. if (copy_from_user(&val, buf, sizeof(val)))
  719. goto write_err;
  720. ret = mdev_access(mdev, (u8 *)&val, sizeof(val),
  721. *ppos, true);
  722. if (ret <= 0)
  723. goto write_err;
  724. filled = 4;
  725. } else if (count >= 2 && !(*ppos % 2)) {
  726. u16 val;
  727. if (copy_from_user(&val, buf, sizeof(val)))
  728. goto write_err;
  729. ret = mdev_access(mdev, (u8 *)&val, sizeof(val),
  730. *ppos, true);
  731. if (ret <= 0)
  732. goto write_err;
  733. filled = 2;
  734. } else {
  735. u8 val;
  736. if (copy_from_user(&val, buf, sizeof(val)))
  737. goto write_err;
  738. ret = mdev_access(mdev, (u8 *)&val, sizeof(val),
  739. *ppos, true);
  740. if (ret <= 0)
  741. goto write_err;
  742. filled = 1;
  743. }
  744. count -= filled;
  745. done += filled;
  746. *ppos += filled;
  747. buf += filled;
  748. }
  749. return done;
  750. write_err:
  751. return -EFAULT;
  752. }
  753. static int mtty_set_irqs(struct mdev_device *mdev, uint32_t flags,
  754. unsigned int index, unsigned int start,
  755. unsigned int count, void *data)
  756. {
  757. int ret = 0;
  758. struct mdev_state *mdev_state;
  759. if (!mdev)
  760. return -EINVAL;
  761. mdev_state = mdev_get_drvdata(mdev);
  762. if (!mdev_state)
  763. return -EINVAL;
  764. mutex_lock(&mdev_state->ops_lock);
  765. switch (index) {
  766. case VFIO_PCI_INTX_IRQ_INDEX:
  767. switch (flags & VFIO_IRQ_SET_ACTION_TYPE_MASK) {
  768. case VFIO_IRQ_SET_ACTION_MASK:
  769. case VFIO_IRQ_SET_ACTION_UNMASK:
  770. break;
  771. case VFIO_IRQ_SET_ACTION_TRIGGER:
  772. {
  773. if (flags & VFIO_IRQ_SET_DATA_NONE) {
  774. pr_info("%s: disable INTx\n", __func__);
  775. if (mdev_state->intx_evtfd)
  776. eventfd_ctx_put(mdev_state->intx_evtfd);
  777. break;
  778. }
  779. if (flags & VFIO_IRQ_SET_DATA_EVENTFD) {
  780. int fd = *(int *)data;
  781. if (fd > 0) {
  782. struct eventfd_ctx *evt;
  783. evt = eventfd_ctx_fdget(fd);
  784. if (IS_ERR(evt)) {
  785. ret = PTR_ERR(evt);
  786. break;
  787. }
  788. mdev_state->intx_evtfd = evt;
  789. mdev_state->irq_fd = fd;
  790. mdev_state->irq_index = index;
  791. break;
  792. }
  793. }
  794. break;
  795. }
  796. }
  797. break;
  798. case VFIO_PCI_MSI_IRQ_INDEX:
  799. switch (flags & VFIO_IRQ_SET_ACTION_TYPE_MASK) {
  800. case VFIO_IRQ_SET_ACTION_MASK:
  801. case VFIO_IRQ_SET_ACTION_UNMASK:
  802. break;
  803. case VFIO_IRQ_SET_ACTION_TRIGGER:
  804. if (flags & VFIO_IRQ_SET_DATA_NONE) {
  805. if (mdev_state->msi_evtfd)
  806. eventfd_ctx_put(mdev_state->msi_evtfd);
  807. pr_info("%s: disable MSI\n", __func__);
  808. mdev_state->irq_index = VFIO_PCI_INTX_IRQ_INDEX;
  809. break;
  810. }
  811. if (flags & VFIO_IRQ_SET_DATA_EVENTFD) {
  812. int fd = *(int *)data;
  813. struct eventfd_ctx *evt;
  814. if (fd <= 0)
  815. break;
  816. if (mdev_state->msi_evtfd)
  817. break;
  818. evt = eventfd_ctx_fdget(fd);
  819. if (IS_ERR(evt)) {
  820. ret = PTR_ERR(evt);
  821. break;
  822. }
  823. mdev_state->msi_evtfd = evt;
  824. mdev_state->irq_fd = fd;
  825. mdev_state->irq_index = index;
  826. }
  827. break;
  828. }
  829. break;
  830. case VFIO_PCI_MSIX_IRQ_INDEX:
  831. pr_info("%s: MSIX_IRQ\n", __func__);
  832. break;
  833. case VFIO_PCI_ERR_IRQ_INDEX:
  834. pr_info("%s: ERR_IRQ\n", __func__);
  835. break;
  836. case VFIO_PCI_REQ_IRQ_INDEX:
  837. pr_info("%s: REQ_IRQ\n", __func__);
  838. break;
  839. }
  840. mutex_unlock(&mdev_state->ops_lock);
  841. return ret;
  842. }
  843. static int mtty_trigger_interrupt(struct mdev_state *mdev_state)
  844. {
  845. int ret = -1;
  846. if ((mdev_state->irq_index == VFIO_PCI_MSI_IRQ_INDEX) &&
  847. (!mdev_state->msi_evtfd))
  848. return -EINVAL;
  849. else if ((mdev_state->irq_index == VFIO_PCI_INTX_IRQ_INDEX) &&
  850. (!mdev_state->intx_evtfd)) {
  851. pr_info("%s: Intr eventfd not found\n", __func__);
  852. return -EINVAL;
  853. }
  854. if (mdev_state->irq_index == VFIO_PCI_MSI_IRQ_INDEX)
  855. ret = eventfd_signal(mdev_state->msi_evtfd, 1);
  856. else
  857. ret = eventfd_signal(mdev_state->intx_evtfd, 1);
  858. #if defined(DEBUG_INTR)
  859. pr_info("Intx triggered\n");
  860. #endif
  861. if (ret != 1)
  862. pr_err("%s: eventfd signal failed (%d)\n", __func__, ret);
  863. return ret;
  864. }
  865. static int mtty_get_region_info(struct mdev_device *mdev,
  866. struct vfio_region_info *region_info,
  867. u16 *cap_type_id, void **cap_type)
  868. {
  869. unsigned int size = 0;
  870. struct mdev_state *mdev_state;
  871. u32 bar_index;
  872. if (!mdev)
  873. return -EINVAL;
  874. mdev_state = mdev_get_drvdata(mdev);
  875. if (!mdev_state)
  876. return -EINVAL;
  877. bar_index = region_info->index;
  878. if (bar_index >= VFIO_PCI_NUM_REGIONS)
  879. return -EINVAL;
  880. mutex_lock(&mdev_state->ops_lock);
  881. switch (bar_index) {
  882. case VFIO_PCI_CONFIG_REGION_INDEX:
  883. size = MTTY_CONFIG_SPACE_SIZE;
  884. break;
  885. case VFIO_PCI_BAR0_REGION_INDEX:
  886. size = MTTY_IO_BAR_SIZE;
  887. break;
  888. case VFIO_PCI_BAR1_REGION_INDEX:
  889. if (mdev_state->nr_ports == 2)
  890. size = MTTY_IO_BAR_SIZE;
  891. break;
  892. default:
  893. size = 0;
  894. break;
  895. }
  896. mdev_state->region_info[bar_index].size = size;
  897. mdev_state->region_info[bar_index].vfio_offset =
  898. MTTY_VFIO_PCI_INDEX_TO_OFFSET(bar_index);
  899. region_info->size = size;
  900. region_info->offset = MTTY_VFIO_PCI_INDEX_TO_OFFSET(bar_index);
  901. region_info->flags = VFIO_REGION_INFO_FLAG_READ |
  902. VFIO_REGION_INFO_FLAG_WRITE;
  903. mutex_unlock(&mdev_state->ops_lock);
  904. return 0;
  905. }
  906. static int mtty_get_irq_info(struct mdev_device *mdev,
  907. struct vfio_irq_info *irq_info)
  908. {
  909. switch (irq_info->index) {
  910. case VFIO_PCI_INTX_IRQ_INDEX:
  911. case VFIO_PCI_MSI_IRQ_INDEX:
  912. case VFIO_PCI_REQ_IRQ_INDEX:
  913. break;
  914. default:
  915. return -EINVAL;
  916. }
  917. irq_info->flags = VFIO_IRQ_INFO_EVENTFD;
  918. irq_info->count = 1;
  919. if (irq_info->index == VFIO_PCI_INTX_IRQ_INDEX)
  920. irq_info->flags |= (VFIO_IRQ_INFO_MASKABLE |
  921. VFIO_IRQ_INFO_AUTOMASKED);
  922. else
  923. irq_info->flags |= VFIO_IRQ_INFO_NORESIZE;
  924. return 0;
  925. }
  926. static int mtty_get_device_info(struct mdev_device *mdev,
  927. struct vfio_device_info *dev_info)
  928. {
  929. dev_info->flags = VFIO_DEVICE_FLAGS_PCI;
  930. dev_info->num_regions = VFIO_PCI_NUM_REGIONS;
  931. dev_info->num_irqs = VFIO_PCI_NUM_IRQS;
  932. return 0;
  933. }
  934. static long mtty_ioctl(struct mdev_device *mdev, unsigned int cmd,
  935. unsigned long arg)
  936. {
  937. int ret = 0;
  938. unsigned long minsz;
  939. struct mdev_state *mdev_state;
  940. if (!mdev)
  941. return -EINVAL;
  942. mdev_state = mdev_get_drvdata(mdev);
  943. if (!mdev_state)
  944. return -ENODEV;
  945. switch (cmd) {
  946. case VFIO_DEVICE_GET_INFO:
  947. {
  948. struct vfio_device_info info;
  949. minsz = offsetofend(struct vfio_device_info, num_irqs);
  950. if (copy_from_user(&info, (void __user *)arg, minsz))
  951. return -EFAULT;
  952. if (info.argsz < minsz)
  953. return -EINVAL;
  954. ret = mtty_get_device_info(mdev, &info);
  955. if (ret)
  956. return ret;
  957. memcpy(&mdev_state->dev_info, &info, sizeof(info));
  958. if (copy_to_user((void __user *)arg, &info, minsz))
  959. return -EFAULT;
  960. return 0;
  961. }
  962. case VFIO_DEVICE_GET_REGION_INFO:
  963. {
  964. struct vfio_region_info info;
  965. u16 cap_type_id = 0;
  966. void *cap_type = NULL;
  967. minsz = offsetofend(struct vfio_region_info, offset);
  968. if (copy_from_user(&info, (void __user *)arg, minsz))
  969. return -EFAULT;
  970. if (info.argsz < minsz)
  971. return -EINVAL;
  972. ret = mtty_get_region_info(mdev, &info, &cap_type_id,
  973. &cap_type);
  974. if (ret)
  975. return ret;
  976. if (copy_to_user((void __user *)arg, &info, minsz))
  977. return -EFAULT;
  978. return 0;
  979. }
  980. case VFIO_DEVICE_GET_IRQ_INFO:
  981. {
  982. struct vfio_irq_info info;
  983. minsz = offsetofend(struct vfio_irq_info, count);
  984. if (copy_from_user(&info, (void __user *)arg, minsz))
  985. return -EFAULT;
  986. if ((info.argsz < minsz) ||
  987. (info.index >= mdev_state->dev_info.num_irqs))
  988. return -EINVAL;
  989. ret = mtty_get_irq_info(mdev, &info);
  990. if (ret)
  991. return ret;
  992. if (copy_to_user((void __user *)arg, &info, minsz))
  993. return -EFAULT;
  994. return 0;
  995. }
  996. case VFIO_DEVICE_SET_IRQS:
  997. {
  998. struct vfio_irq_set hdr;
  999. u8 *data = NULL, *ptr = NULL;
  1000. size_t data_size = 0;
  1001. minsz = offsetofend(struct vfio_irq_set, count);
  1002. if (copy_from_user(&hdr, (void __user *)arg, minsz))
  1003. return -EFAULT;
  1004. ret = vfio_set_irqs_validate_and_prepare(&hdr,
  1005. mdev_state->dev_info.num_irqs,
  1006. VFIO_PCI_NUM_IRQS,
  1007. &data_size);
  1008. if (ret)
  1009. return ret;
  1010. if (data_size) {
  1011. ptr = data = memdup_user((void __user *)(arg + minsz),
  1012. data_size);
  1013. if (IS_ERR(data))
  1014. return PTR_ERR(data);
  1015. }
  1016. ret = mtty_set_irqs(mdev, hdr.flags, hdr.index, hdr.start,
  1017. hdr.count, data);
  1018. kfree(ptr);
  1019. return ret;
  1020. }
  1021. case VFIO_DEVICE_RESET:
  1022. return mtty_reset(mdev);
  1023. }
  1024. return -ENOTTY;
  1025. }
  1026. static int mtty_open(struct mdev_device *mdev)
  1027. {
  1028. pr_info("%s\n", __func__);
  1029. return 0;
  1030. }
  1031. static void mtty_close(struct mdev_device *mdev)
  1032. {
  1033. pr_info("%s\n", __func__);
  1034. }
  1035. static ssize_t
  1036. sample_mtty_dev_show(struct device *dev, struct device_attribute *attr,
  1037. char *buf)
  1038. {
  1039. return sprintf(buf, "This is phy device\n");
  1040. }
  1041. static DEVICE_ATTR_RO(sample_mtty_dev);
  1042. static struct attribute *mtty_dev_attrs[] = {
  1043. &dev_attr_sample_mtty_dev.attr,
  1044. NULL,
  1045. };
  1046. static const struct attribute_group mtty_dev_group = {
  1047. .name = "mtty_dev",
  1048. .attrs = mtty_dev_attrs,
  1049. };
  1050. static const struct attribute_group *mtty_dev_groups[] = {
  1051. &mtty_dev_group,
  1052. NULL,
  1053. };
  1054. static ssize_t
  1055. sample_mdev_dev_show(struct device *dev, struct device_attribute *attr,
  1056. char *buf)
  1057. {
  1058. if (mdev_from_dev(dev))
  1059. return sprintf(buf, "This is MDEV %s\n", dev_name(dev));
  1060. return sprintf(buf, "\n");
  1061. }
  1062. static DEVICE_ATTR_RO(sample_mdev_dev);
  1063. static struct attribute *mdev_dev_attrs[] = {
  1064. &dev_attr_sample_mdev_dev.attr,
  1065. NULL,
  1066. };
  1067. static const struct attribute_group mdev_dev_group = {
  1068. .name = "vendor",
  1069. .attrs = mdev_dev_attrs,
  1070. };
  1071. static const struct attribute_group *mdev_dev_groups[] = {
  1072. &mdev_dev_group,
  1073. NULL,
  1074. };
  1075. static ssize_t
  1076. name_show(struct kobject *kobj, struct device *dev, char *buf)
  1077. {
  1078. char name[MTTY_STRING_LEN];
  1079. int i;
  1080. const char *name_str[2] = {"Single port serial", "Dual port serial"};
  1081. for (i = 0; i < 2; i++) {
  1082. snprintf(name, MTTY_STRING_LEN, "%s-%d",
  1083. dev_driver_string(dev), i + 1);
  1084. if (!strcmp(kobj->name, name))
  1085. return sprintf(buf, "%s\n", name_str[i]);
  1086. }
  1087. return -EINVAL;
  1088. }
  1089. static MDEV_TYPE_ATTR_RO(name);
  1090. static ssize_t
  1091. available_instances_show(struct kobject *kobj, struct device *dev, char *buf)
  1092. {
  1093. char name[MTTY_STRING_LEN];
  1094. int i;
  1095. struct mdev_state *mds;
  1096. int ports = 0, used = 0;
  1097. for (i = 0; i < 2; i++) {
  1098. snprintf(name, MTTY_STRING_LEN, "%s-%d",
  1099. dev_driver_string(dev), i + 1);
  1100. if (!strcmp(kobj->name, name)) {
  1101. ports = i + 1;
  1102. break;
  1103. }
  1104. }
  1105. if (!ports)
  1106. return -EINVAL;
  1107. list_for_each_entry(mds, &mdev_devices_list, next)
  1108. used += mds->nr_ports;
  1109. return sprintf(buf, "%d\n", (MAX_MTTYS - used)/ports);
  1110. }
  1111. static MDEV_TYPE_ATTR_RO(available_instances);
  1112. static ssize_t device_api_show(struct kobject *kobj, struct device *dev,
  1113. char *buf)
  1114. {
  1115. return sprintf(buf, "%s\n", VFIO_DEVICE_API_PCI_STRING);
  1116. }
  1117. static MDEV_TYPE_ATTR_RO(device_api);
  1118. static struct attribute *mdev_types_attrs[] = {
  1119. &mdev_type_attr_name.attr,
  1120. &mdev_type_attr_device_api.attr,
  1121. &mdev_type_attr_available_instances.attr,
  1122. NULL,
  1123. };
  1124. static struct attribute_group mdev_type_group1 = {
  1125. .name = "1",
  1126. .attrs = mdev_types_attrs,
  1127. };
  1128. static struct attribute_group mdev_type_group2 = {
  1129. .name = "2",
  1130. .attrs = mdev_types_attrs,
  1131. };
  1132. static struct attribute_group *mdev_type_groups[] = {
  1133. &mdev_type_group1,
  1134. &mdev_type_group2,
  1135. NULL,
  1136. };
  1137. static const struct mdev_parent_ops mdev_fops = {
  1138. .owner = THIS_MODULE,
  1139. .dev_attr_groups = mtty_dev_groups,
  1140. .mdev_attr_groups = mdev_dev_groups,
  1141. .supported_type_groups = mdev_type_groups,
  1142. .create = mtty_create,
  1143. .remove = mtty_remove,
  1144. .open = mtty_open,
  1145. .release = mtty_close,
  1146. .read = mtty_read,
  1147. .write = mtty_write,
  1148. .ioctl = mtty_ioctl,
  1149. };
  1150. static void mtty_device_release(struct device *dev)
  1151. {
  1152. dev_dbg(dev, "mtty: released\n");
  1153. }
  1154. static int __init mtty_dev_init(void)
  1155. {
  1156. int ret = 0;
  1157. pr_info("mtty_dev: %s\n", __func__);
  1158. memset(&mtty_dev, 0, sizeof(mtty_dev));
  1159. idr_init(&mtty_dev.vd_idr);
  1160. ret = alloc_chrdev_region(&mtty_dev.vd_devt, 0, MINORMASK + 1,
  1161. MTTY_NAME);
  1162. if (ret < 0) {
  1163. pr_err("Error: failed to register mtty_dev, err:%d\n", ret);
  1164. return ret;
  1165. }
  1166. cdev_init(&mtty_dev.vd_cdev, &vd_fops);
  1167. cdev_add(&mtty_dev.vd_cdev, mtty_dev.vd_devt, MINORMASK + 1);
  1168. pr_info("major_number:%d\n", MAJOR(mtty_dev.vd_devt));
  1169. mtty_dev.vd_class = class_create(THIS_MODULE, MTTY_CLASS_NAME);
  1170. if (IS_ERR(mtty_dev.vd_class)) {
  1171. pr_err("Error: failed to register mtty_dev class\n");
  1172. ret = PTR_ERR(mtty_dev.vd_class);
  1173. goto failed1;
  1174. }
  1175. mtty_dev.dev.class = mtty_dev.vd_class;
  1176. mtty_dev.dev.release = mtty_device_release;
  1177. dev_set_name(&mtty_dev.dev, "%s", MTTY_NAME);
  1178. ret = device_register(&mtty_dev.dev);
  1179. if (ret)
  1180. goto failed2;
  1181. ret = mdev_register_device(&mtty_dev.dev, &mdev_fops);
  1182. if (ret)
  1183. goto failed3;
  1184. mutex_init(&mdev_list_lock);
  1185. INIT_LIST_HEAD(&mdev_devices_list);
  1186. goto all_done;
  1187. failed3:
  1188. device_unregister(&mtty_dev.dev);
  1189. failed2:
  1190. class_destroy(mtty_dev.vd_class);
  1191. failed1:
  1192. cdev_del(&mtty_dev.vd_cdev);
  1193. unregister_chrdev_region(mtty_dev.vd_devt, MINORMASK + 1);
  1194. all_done:
  1195. return ret;
  1196. }
  1197. static void __exit mtty_dev_exit(void)
  1198. {
  1199. mtty_dev.dev.bus = NULL;
  1200. mdev_unregister_device(&mtty_dev.dev);
  1201. device_unregister(&mtty_dev.dev);
  1202. idr_destroy(&mtty_dev.vd_idr);
  1203. cdev_del(&mtty_dev.vd_cdev);
  1204. unregister_chrdev_region(mtty_dev.vd_devt, MINORMASK + 1);
  1205. class_destroy(mtty_dev.vd_class);
  1206. mtty_dev.vd_class = NULL;
  1207. pr_info("mtty_dev: Unloaded!\n");
  1208. }
  1209. module_init(mtty_dev_init)
  1210. module_exit(mtty_dev_exit)
  1211. MODULE_LICENSE("GPL v2");
  1212. MODULE_INFO(supported, "Test driver that simulate serial port over PCI");
  1213. MODULE_VERSION(VERSION_STRING);
  1214. MODULE_AUTHOR(DRIVER_AUTHOR);