direct.c 15 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2018-2020 Christoph Hellwig.
  4. *
  5. * DMA operations that map physical memory directly without using an IOMMU.
  6. */
  7. #include <linux/memblock.h> /* for max_pfn */
  8. #include <linux/export.h>
  9. #include <linux/mm.h>
  10. #include <linux/dma-map-ops.h>
  11. #include <linux/scatterlist.h>
  12. #include <linux/pfn.h>
  13. #include <linux/vmalloc.h>
  14. #include <linux/set_memory.h>
  15. #include <linux/slab.h>
  16. #include "direct.h"
  17. /*
  18. * Most architectures use ZONE_DMA for the first 16 Megabytes, but some use
  19. * it for entirely different regions. In that case the arch code needs to
  20. * override the variable below for dma-direct to work properly.
  21. */
  22. unsigned int zone_dma_bits __ro_after_init = 24;
  23. static inline dma_addr_t phys_to_dma_direct(struct device *dev,
  24. phys_addr_t phys)
  25. {
  26. if (force_dma_unencrypted(dev))
  27. return phys_to_dma_unencrypted(dev, phys);
  28. return phys_to_dma(dev, phys);
  29. }
  30. static inline struct page *dma_direct_to_page(struct device *dev,
  31. dma_addr_t dma_addr)
  32. {
  33. return pfn_to_page(PHYS_PFN(dma_to_phys(dev, dma_addr)));
  34. }
  35. u64 dma_direct_get_required_mask(struct device *dev)
  36. {
  37. phys_addr_t phys = (phys_addr_t)(max_pfn - 1) << PAGE_SHIFT;
  38. u64 max_dma = phys_to_dma_direct(dev, phys);
  39. return (1ULL << (fls64(max_dma) - 1)) * 2 - 1;
  40. }
  41. EXPORT_SYMBOL_GPL(dma_direct_get_required_mask);
  42. static gfp_t dma_direct_optimal_gfp_mask(struct device *dev, u64 dma_mask,
  43. u64 *phys_limit)
  44. {
  45. u64 dma_limit = min_not_zero(dma_mask, dev->bus_dma_limit);
  46. /*
  47. * Optimistically try the zone that the physical address mask falls
  48. * into first. If that returns memory that isn't actually addressable
  49. * we will fallback to the next lower zone and try again.
  50. *
  51. * Note that GFP_DMA32 and GFP_DMA are no ops without the corresponding
  52. * zones.
  53. */
  54. *phys_limit = dma_to_phys(dev, dma_limit);
  55. if (*phys_limit <= DMA_BIT_MASK(zone_dma_bits))
  56. return GFP_DMA;
  57. if (*phys_limit <= DMA_BIT_MASK(32) &&
  58. !zone_dma32_are_empty())
  59. return GFP_DMA32;
  60. return 0;
  61. }
  62. static bool dma_coherent_ok(struct device *dev, phys_addr_t phys, size_t size)
  63. {
  64. dma_addr_t dma_addr = phys_to_dma_direct(dev, phys);
  65. if (dma_addr == DMA_MAPPING_ERROR)
  66. return false;
  67. return dma_addr + size - 1 <=
  68. min_not_zero(dev->coherent_dma_mask, dev->bus_dma_limit);
  69. }
  70. static struct page *__dma_direct_alloc_pages(struct device *dev, size_t size,
  71. gfp_t gfp)
  72. {
  73. int node = dev_to_node(dev);
  74. struct page *page = NULL;
  75. u64 phys_limit;
  76. WARN_ON_ONCE(!PAGE_ALIGNED(size));
  77. gfp |= dma_direct_optimal_gfp_mask(dev, dev->coherent_dma_mask,
  78. &phys_limit);
  79. page = dma_alloc_contiguous(dev, size, gfp);
  80. if (page && !dma_coherent_ok(dev, page_to_phys(page), size)) {
  81. dma_free_contiguous(dev, page, size);
  82. page = NULL;
  83. }
  84. again:
  85. if (!page)
  86. page = alloc_pages_node(node, gfp, get_order(size));
  87. if (page && !dma_coherent_ok(dev, page_to_phys(page), size)) {
  88. dma_free_contiguous(dev, page, size);
  89. page = NULL;
  90. if (IS_ENABLED(CONFIG_ZONE_DMA32) &&
  91. phys_limit < DMA_BIT_MASK(64) &&
  92. !(gfp & (GFP_DMA32 | GFP_DMA)) &&
  93. !zone_dma32_are_empty()) {
  94. gfp |= GFP_DMA32;
  95. goto again;
  96. }
  97. if (IS_ENABLED(CONFIG_ZONE_DMA) && !(gfp & GFP_DMA)) {
  98. gfp = (gfp & ~GFP_DMA32) | GFP_DMA;
  99. goto again;
  100. }
  101. }
  102. return page;
  103. }
  104. static void *dma_direct_alloc_from_pool(struct device *dev, size_t size,
  105. dma_addr_t *dma_handle, gfp_t gfp)
  106. {
  107. struct page *page;
  108. u64 phys_mask;
  109. void *ret;
  110. gfp |= dma_direct_optimal_gfp_mask(dev, dev->coherent_dma_mask,
  111. &phys_mask);
  112. page = dma_alloc_from_pool(dev, size, &ret, gfp, dma_coherent_ok);
  113. if (!page)
  114. return NULL;
  115. *dma_handle = phys_to_dma_direct(dev, page_to_phys(page));
  116. return ret;
  117. }
  118. void *dma_direct_alloc(struct device *dev, size_t size,
  119. dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs)
  120. {
  121. struct page *page;
  122. void *ret;
  123. int err;
  124. size = PAGE_ALIGN(size);
  125. if (attrs & DMA_ATTR_NO_WARN)
  126. gfp |= __GFP_NOWARN;
  127. if ((attrs & DMA_ATTR_NO_KERNEL_MAPPING) &&
  128. !force_dma_unencrypted(dev)) {
  129. page = __dma_direct_alloc_pages(dev, size, gfp & ~__GFP_ZERO);
  130. if (!page)
  131. return NULL;
  132. /* remove any dirty cache lines on the kernel alias */
  133. if (!PageHighMem(page))
  134. arch_dma_prep_coherent(page, size);
  135. *dma_handle = phys_to_dma_direct(dev, page_to_phys(page));
  136. /* return the page pointer as the opaque cookie */
  137. return page;
  138. }
  139. if (!IS_ENABLED(CONFIG_ARCH_HAS_DMA_SET_UNCACHED) &&
  140. !IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) &&
  141. !dev_is_dma_coherent(dev))
  142. return arch_dma_alloc(dev, size, dma_handle, gfp, attrs);
  143. /*
  144. * Remapping or decrypting memory may block. If either is required and
  145. * we can't block, allocate the memory from the atomic pools.
  146. */
  147. if (IS_ENABLED(CONFIG_DMA_COHERENT_POOL) &&
  148. !gfpflags_allow_blocking(gfp) &&
  149. (force_dma_unencrypted(dev) ||
  150. (IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) && !dev_is_dma_coherent(dev))))
  151. return dma_direct_alloc_from_pool(dev, size, dma_handle, gfp);
  152. /* we always manually zero the memory once we are done */
  153. page = __dma_direct_alloc_pages(dev, size, gfp & ~__GFP_ZERO);
  154. if (!page)
  155. return NULL;
  156. if ((IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) &&
  157. !dev_is_dma_coherent(dev)) ||
  158. (IS_ENABLED(CONFIG_DMA_REMAP) && PageHighMem(page))) {
  159. /* remove any dirty cache lines on the kernel alias */
  160. arch_dma_prep_coherent(page, size);
  161. /* create a coherent mapping */
  162. ret = dma_common_contiguous_remap(page, size,
  163. dma_pgprot(dev, PAGE_KERNEL, attrs),
  164. __builtin_return_address(0));
  165. if (!ret)
  166. goto out_free_pages;
  167. if (force_dma_unencrypted(dev)) {
  168. err = set_memory_decrypted((unsigned long)ret,
  169. 1 << get_order(size));
  170. if (err)
  171. goto out_free_pages;
  172. }
  173. memset(ret, 0, size);
  174. goto done;
  175. }
  176. if (PageHighMem(page)) {
  177. /*
  178. * Depending on the cma= arguments and per-arch setup
  179. * dma_alloc_contiguous could return highmem pages.
  180. * Without remapping there is no way to return them here,
  181. * so log an error and fail.
  182. */
  183. dev_info(dev, "Rejecting highmem page from CMA.\n");
  184. goto out_free_pages;
  185. }
  186. ret = page_address(page);
  187. if (force_dma_unencrypted(dev)) {
  188. err = set_memory_decrypted((unsigned long)ret,
  189. 1 << get_order(size));
  190. if (err)
  191. goto out_free_pages;
  192. }
  193. memset(ret, 0, size);
  194. if (IS_ENABLED(CONFIG_ARCH_HAS_DMA_SET_UNCACHED) &&
  195. !dev_is_dma_coherent(dev)) {
  196. arch_dma_prep_coherent(page, size);
  197. ret = arch_dma_set_uncached(ret, size);
  198. if (IS_ERR(ret))
  199. goto out_encrypt_pages;
  200. }
  201. done:
  202. *dma_handle = phys_to_dma_direct(dev, page_to_phys(page));
  203. return ret;
  204. out_encrypt_pages:
  205. if (force_dma_unencrypted(dev)) {
  206. err = set_memory_encrypted((unsigned long)page_address(page),
  207. 1 << get_order(size));
  208. /* If memory cannot be re-encrypted, it must be leaked */
  209. if (err)
  210. return NULL;
  211. }
  212. out_free_pages:
  213. dma_free_contiguous(dev, page, size);
  214. return NULL;
  215. }
  216. void dma_direct_free(struct device *dev, size_t size,
  217. void *cpu_addr, dma_addr_t dma_addr, unsigned long attrs)
  218. {
  219. unsigned int page_order = get_order(size);
  220. if ((attrs & DMA_ATTR_NO_KERNEL_MAPPING) &&
  221. !force_dma_unencrypted(dev)) {
  222. /* cpu_addr is a struct page cookie, not a kernel address */
  223. dma_free_contiguous(dev, cpu_addr, size);
  224. return;
  225. }
  226. if (!IS_ENABLED(CONFIG_ARCH_HAS_DMA_SET_UNCACHED) &&
  227. !IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) &&
  228. !dev_is_dma_coherent(dev)) {
  229. arch_dma_free(dev, size, cpu_addr, dma_addr, attrs);
  230. return;
  231. }
  232. /* If cpu_addr is not from an atomic pool, dma_free_from_pool() fails */
  233. if (IS_ENABLED(CONFIG_DMA_COHERENT_POOL) &&
  234. dma_free_from_pool(dev, cpu_addr, PAGE_ALIGN(size)))
  235. return;
  236. if (force_dma_unencrypted(dev))
  237. set_memory_encrypted((unsigned long)cpu_addr, 1 << page_order);
  238. if (IS_ENABLED(CONFIG_DMA_REMAP) && is_vmalloc_addr(cpu_addr))
  239. vunmap(cpu_addr);
  240. else if (IS_ENABLED(CONFIG_ARCH_HAS_DMA_CLEAR_UNCACHED))
  241. arch_dma_clear_uncached(cpu_addr, size);
  242. dma_free_contiguous(dev, dma_direct_to_page(dev, dma_addr), size);
  243. }
  244. struct page *dma_direct_alloc_pages(struct device *dev, size_t size,
  245. dma_addr_t *dma_handle, enum dma_data_direction dir, gfp_t gfp)
  246. {
  247. struct page *page;
  248. void *ret;
  249. if (IS_ENABLED(CONFIG_DMA_COHERENT_POOL) &&
  250. force_dma_unencrypted(dev) && !gfpflags_allow_blocking(gfp))
  251. return dma_direct_alloc_from_pool(dev, size, dma_handle, gfp);
  252. page = __dma_direct_alloc_pages(dev, size, gfp);
  253. if (!page)
  254. return NULL;
  255. if (PageHighMem(page)) {
  256. /*
  257. * Depending on the cma= arguments and per-arch setup
  258. * dma_alloc_contiguous could return highmem pages.
  259. * Without remapping there is no way to return them here,
  260. * so log an error and fail.
  261. */
  262. dev_info(dev, "Rejecting highmem page from CMA.\n");
  263. goto out_free_pages;
  264. }
  265. ret = page_address(page);
  266. if (force_dma_unencrypted(dev)) {
  267. if (set_memory_decrypted((unsigned long)ret,
  268. 1 << get_order(size)))
  269. goto out_free_pages;
  270. }
  271. memset(ret, 0, size);
  272. *dma_handle = phys_to_dma_direct(dev, page_to_phys(page));
  273. return page;
  274. out_free_pages:
  275. dma_free_contiguous(dev, page, size);
  276. return NULL;
  277. }
  278. EXPORT_SYMBOL_GPL(dma_direct_alloc);
  279. void dma_direct_free_pages(struct device *dev, size_t size,
  280. struct page *page, dma_addr_t dma_addr,
  281. enum dma_data_direction dir)
  282. {
  283. unsigned int page_order = get_order(size);
  284. void *vaddr = page_address(page);
  285. /* If cpu_addr is not from an atomic pool, dma_free_from_pool() fails */
  286. if (IS_ENABLED(CONFIG_DMA_COHERENT_POOL) &&
  287. dma_free_from_pool(dev, vaddr, size))
  288. return;
  289. if (force_dma_unencrypted(dev))
  290. set_memory_encrypted((unsigned long)vaddr, 1 << page_order);
  291. dma_free_contiguous(dev, page, size);
  292. }
  293. EXPORT_SYMBOL_GPL(dma_direct_free);
  294. #if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \
  295. defined(CONFIG_SWIOTLB)
  296. void dma_direct_sync_sg_for_device(struct device *dev,
  297. struct scatterlist *sgl, int nents, enum dma_data_direction dir)
  298. {
  299. struct scatterlist *sg;
  300. int i;
  301. for_each_sg(sgl, sg, nents, i) {
  302. phys_addr_t paddr = dma_to_phys(dev, sg_dma_address(sg));
  303. if (unlikely(is_swiotlb_buffer(paddr)))
  304. swiotlb_tbl_sync_single(dev, paddr, sg->length,
  305. dir, SYNC_FOR_DEVICE);
  306. if (!dev_is_dma_coherent(dev))
  307. arch_sync_dma_for_device(paddr, sg->length,
  308. dir);
  309. }
  310. }
  311. #endif
  312. #if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \
  313. defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL) || \
  314. defined(CONFIG_SWIOTLB)
  315. void dma_direct_sync_sg_for_cpu(struct device *dev,
  316. struct scatterlist *sgl, int nents, enum dma_data_direction dir)
  317. {
  318. struct scatterlist *sg;
  319. int i;
  320. for_each_sg(sgl, sg, nents, i) {
  321. phys_addr_t paddr = dma_to_phys(dev, sg_dma_address(sg));
  322. if (!dev_is_dma_coherent(dev))
  323. arch_sync_dma_for_cpu(paddr, sg->length, dir);
  324. if (unlikely(is_swiotlb_buffer(paddr)))
  325. swiotlb_tbl_sync_single(dev, paddr, sg->length, dir,
  326. SYNC_FOR_CPU);
  327. if (dir == DMA_FROM_DEVICE)
  328. arch_dma_mark_clean(paddr, sg->length);
  329. }
  330. if (!dev_is_dma_coherent(dev))
  331. arch_sync_dma_for_cpu_all();
  332. }
  333. void dma_direct_unmap_sg(struct device *dev, struct scatterlist *sgl,
  334. int nents, enum dma_data_direction dir, unsigned long attrs)
  335. {
  336. struct scatterlist *sg;
  337. int i;
  338. for_each_sg(sgl, sg, nents, i)
  339. dma_direct_unmap_page(dev, sg->dma_address, sg_dma_len(sg), dir,
  340. attrs);
  341. }
  342. #endif
  343. int dma_direct_map_sg(struct device *dev, struct scatterlist *sgl, int nents,
  344. enum dma_data_direction dir, unsigned long attrs)
  345. {
  346. int i;
  347. struct scatterlist *sg;
  348. for_each_sg(sgl, sg, nents, i) {
  349. sg->dma_address = dma_direct_map_page(dev, sg_page(sg),
  350. sg->offset, sg->length, dir, attrs);
  351. if (sg->dma_address == DMA_MAPPING_ERROR)
  352. goto out_unmap;
  353. sg_dma_len(sg) = sg->length;
  354. }
  355. return nents;
  356. out_unmap:
  357. dma_direct_unmap_sg(dev, sgl, i, dir, attrs | DMA_ATTR_SKIP_CPU_SYNC);
  358. return 0;
  359. }
  360. dma_addr_t dma_direct_map_resource(struct device *dev, phys_addr_t paddr,
  361. size_t size, enum dma_data_direction dir, unsigned long attrs)
  362. {
  363. dma_addr_t dma_addr = paddr;
  364. if (unlikely(!dma_capable(dev, dma_addr, size, false))) {
  365. dev_err_once(dev,
  366. "DMA addr %pad+%zu overflow (mask %llx, bus limit %llx).\n",
  367. &dma_addr, size, *dev->dma_mask, dev->bus_dma_limit);
  368. WARN_ON_ONCE(1);
  369. return DMA_MAPPING_ERROR;
  370. }
  371. return dma_addr;
  372. }
  373. int dma_direct_get_sgtable(struct device *dev, struct sg_table *sgt,
  374. void *cpu_addr, dma_addr_t dma_addr, size_t size,
  375. unsigned long attrs)
  376. {
  377. struct page *page = dma_direct_to_page(dev, dma_addr);
  378. int ret;
  379. ret = sg_alloc_table(sgt, 1, GFP_KERNEL);
  380. if (!ret)
  381. sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0);
  382. return ret;
  383. }
  384. bool dma_direct_can_mmap(struct device *dev)
  385. {
  386. return dev_is_dma_coherent(dev) ||
  387. IS_ENABLED(CONFIG_DMA_NONCOHERENT_MMAP);
  388. }
  389. int dma_direct_mmap(struct device *dev, struct vm_area_struct *vma,
  390. void *cpu_addr, dma_addr_t dma_addr, size_t size,
  391. unsigned long attrs)
  392. {
  393. unsigned long user_count = vma_pages(vma);
  394. unsigned long count = PAGE_ALIGN(size) >> PAGE_SHIFT;
  395. unsigned long pfn = PHYS_PFN(dma_to_phys(dev, dma_addr));
  396. int ret = -ENXIO;
  397. vma->vm_page_prot = dma_pgprot(dev, vma->vm_page_prot, attrs);
  398. if (dma_mmap_from_dev_coherent(dev, vma, cpu_addr, size, &ret))
  399. return ret;
  400. if (vma->vm_pgoff >= count || user_count > count - vma->vm_pgoff)
  401. return -ENXIO;
  402. return remap_pfn_range(vma, vma->vm_start, pfn + vma->vm_pgoff,
  403. user_count << PAGE_SHIFT, vma->vm_page_prot);
  404. }
  405. int dma_direct_supported(struct device *dev, u64 mask)
  406. {
  407. u64 min_mask = (max_pfn - 1) << PAGE_SHIFT;
  408. /*
  409. * Because 32-bit DMA masks are so common we expect every architecture
  410. * to be able to satisfy them - either by not supporting more physical
  411. * memory, or by providing a ZONE_DMA32. If neither is the case, the
  412. * architecture needs to use an IOMMU instead of the direct mapping.
  413. */
  414. if (mask >= DMA_BIT_MASK(32))
  415. return 1;
  416. /*
  417. * This check needs to be against the actual bit mask value, so use
  418. * phys_to_dma_unencrypted() here so that the SME encryption mask isn't
  419. * part of the check.
  420. */
  421. if (IS_ENABLED(CONFIG_ZONE_DMA))
  422. min_mask = min_t(u64, min_mask, DMA_BIT_MASK(zone_dma_bits));
  423. return mask >= phys_to_dma_unencrypted(dev, min_mask);
  424. }
  425. size_t dma_direct_max_mapping_size(struct device *dev)
  426. {
  427. /* If SWIOTLB is active, use its maximum mapping size */
  428. if (is_swiotlb_active() &&
  429. (dma_addressing_limited(dev) || swiotlb_force == SWIOTLB_FORCE))
  430. return swiotlb_max_mapping_size(dev);
  431. return SIZE_MAX;
  432. }
  433. bool dma_direct_need_sync(struct device *dev, dma_addr_t dma_addr)
  434. {
  435. return !dev_is_dma_coherent(dev) ||
  436. is_swiotlb_buffer(dma_to_phys(dev, dma_addr));
  437. }
  438. /**
  439. * dma_direct_set_offset - Assign scalar offset for a single DMA range.
  440. * @dev: device pointer; needed to "own" the alloced memory.
  441. * @cpu_start: beginning of memory region covered by this offset.
  442. * @dma_start: beginning of DMA/PCI region covered by this offset.
  443. * @size: size of the region.
  444. *
  445. * This is for the simple case of a uniform offset which cannot
  446. * be discovered by "dma-ranges".
  447. *
  448. * It returns -ENOMEM if out of memory, -EINVAL if a map
  449. * already exists, 0 otherwise.
  450. *
  451. * Note: any call to this from a driver is a bug. The mapping needs
  452. * to be described by the device tree or other firmware interfaces.
  453. */
  454. int dma_direct_set_offset(struct device *dev, phys_addr_t cpu_start,
  455. dma_addr_t dma_start, u64 size)
  456. {
  457. struct bus_dma_region *map;
  458. u64 offset = (u64)cpu_start - (u64)dma_start;
  459. if (dev->dma_range_map) {
  460. dev_err(dev, "attempt to add DMA range to existing map\n");
  461. return -EINVAL;
  462. }
  463. if (!offset)
  464. return 0;
  465. map = kcalloc(2, sizeof(*map), GFP_KERNEL);
  466. if (!map)
  467. return -ENOMEM;
  468. map[0].cpu_start = cpu_start;
  469. map[0].dma_start = dma_start;
  470. map[0].offset = offset;
  471. map[0].size = size;
  472. dev->dma_range_map = map;
  473. return 0;
  474. }
  475. EXPORT_SYMBOL_GPL(dma_direct_set_offset);