tegra_wdt.c 7.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
  4. */
  5. #include <linux/kernel.h>
  6. #include <linux/module.h>
  7. #include <linux/interrupt.h>
  8. #include <linux/io.h>
  9. #include <linux/of.h>
  10. #include <linux/platform_device.h>
  11. #include <linux/watchdog.h>
  12. /* minimum and maximum watchdog trigger timeout, in seconds */
  13. #define MIN_WDT_TIMEOUT 1
  14. #define MAX_WDT_TIMEOUT 255
  15. /*
  16. * Base of the WDT registers, from the timer base address. There are
  17. * actually 5 watchdogs that can be configured (by pairing with an available
  18. * timer), at bases 0x100 + (WDT ID) * 0x20, where WDT ID is 0 through 4.
  19. * This driver only configures the first watchdog (WDT ID 0).
  20. */
  21. #define WDT_BASE 0x100
  22. #define WDT_ID 0
  23. /*
  24. * Register base of the timer that's selected for pairing with the watchdog.
  25. * This driver arbitrarily uses timer 5, which is currently unused by
  26. * other drivers (in particular, the Tegra clocksource driver). If this
  27. * needs to change, take care that the new timer is not used by the
  28. * clocksource driver.
  29. */
  30. #define WDT_TIMER_BASE 0x60
  31. #define WDT_TIMER_ID 5
  32. /* WDT registers */
  33. #define WDT_CFG 0x0
  34. #define WDT_CFG_PERIOD_SHIFT 4
  35. #define WDT_CFG_PERIOD_MASK 0xff
  36. #define WDT_CFG_INT_EN (1 << 12)
  37. #define WDT_CFG_PMC2CAR_RST_EN (1 << 15)
  38. #define WDT_STS 0x4
  39. #define WDT_STS_COUNT_SHIFT 4
  40. #define WDT_STS_COUNT_MASK 0xff
  41. #define WDT_STS_EXP_SHIFT 12
  42. #define WDT_STS_EXP_MASK 0x3
  43. #define WDT_CMD 0x8
  44. #define WDT_CMD_START_COUNTER (1 << 0)
  45. #define WDT_CMD_DISABLE_COUNTER (1 << 1)
  46. #define WDT_UNLOCK (0xc)
  47. #define WDT_UNLOCK_PATTERN (0xc45a << 0)
  48. /* Timer registers */
  49. #define TIMER_PTV 0x0
  50. #define TIMER_EN (1 << 31)
  51. #define TIMER_PERIODIC (1 << 30)
  52. struct tegra_wdt {
  53. struct watchdog_device wdd;
  54. void __iomem *wdt_regs;
  55. void __iomem *tmr_regs;
  56. };
  57. #define WDT_HEARTBEAT 120
  58. static int heartbeat = WDT_HEARTBEAT;
  59. module_param(heartbeat, int, 0);
  60. MODULE_PARM_DESC(heartbeat,
  61. "Watchdog heartbeats in seconds. (default = "
  62. __MODULE_STRING(WDT_HEARTBEAT) ")");
  63. static bool nowayout = WATCHDOG_NOWAYOUT;
  64. module_param(nowayout, bool, 0);
  65. MODULE_PARM_DESC(nowayout,
  66. "Watchdog cannot be stopped once started (default="
  67. __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  68. static int tegra_wdt_start(struct watchdog_device *wdd)
  69. {
  70. struct tegra_wdt *wdt = watchdog_get_drvdata(wdd);
  71. u32 val;
  72. /*
  73. * This thing has a fixed 1MHz clock. Normally, we would set the
  74. * period to 1 second by writing 1000000ul, but the watchdog system
  75. * reset actually occurs on the 4th expiration of this counter,
  76. * so we set the period to 1/4 of this amount.
  77. */
  78. val = 1000000ul / 4;
  79. val |= (TIMER_EN | TIMER_PERIODIC);
  80. writel(val, wdt->tmr_regs + TIMER_PTV);
  81. /*
  82. * Set number of periods and start counter.
  83. *
  84. * Interrupt handler is not required for user space
  85. * WDT accesses, since the caller is responsible to ping the
  86. * WDT to reset the counter before expiration, through ioctls.
  87. */
  88. val = WDT_TIMER_ID |
  89. (wdd->timeout << WDT_CFG_PERIOD_SHIFT) |
  90. WDT_CFG_PMC2CAR_RST_EN;
  91. writel(val, wdt->wdt_regs + WDT_CFG);
  92. writel(WDT_CMD_START_COUNTER, wdt->wdt_regs + WDT_CMD);
  93. return 0;
  94. }
  95. static int tegra_wdt_stop(struct watchdog_device *wdd)
  96. {
  97. struct tegra_wdt *wdt = watchdog_get_drvdata(wdd);
  98. writel(WDT_UNLOCK_PATTERN, wdt->wdt_regs + WDT_UNLOCK);
  99. writel(WDT_CMD_DISABLE_COUNTER, wdt->wdt_regs + WDT_CMD);
  100. writel(0, wdt->tmr_regs + TIMER_PTV);
  101. return 0;
  102. }
  103. static int tegra_wdt_ping(struct watchdog_device *wdd)
  104. {
  105. struct tegra_wdt *wdt = watchdog_get_drvdata(wdd);
  106. writel(WDT_CMD_START_COUNTER, wdt->wdt_regs + WDT_CMD);
  107. return 0;
  108. }
  109. static int tegra_wdt_set_timeout(struct watchdog_device *wdd,
  110. unsigned int timeout)
  111. {
  112. wdd->timeout = timeout;
  113. if (watchdog_active(wdd)) {
  114. tegra_wdt_stop(wdd);
  115. return tegra_wdt_start(wdd);
  116. }
  117. return 0;
  118. }
  119. static unsigned int tegra_wdt_get_timeleft(struct watchdog_device *wdd)
  120. {
  121. struct tegra_wdt *wdt = watchdog_get_drvdata(wdd);
  122. u32 val;
  123. int count;
  124. int exp;
  125. val = readl(wdt->wdt_regs + WDT_STS);
  126. /* Current countdown (from timeout) */
  127. count = (val >> WDT_STS_COUNT_SHIFT) & WDT_STS_COUNT_MASK;
  128. /* Number of expirations (we are waiting for the 4th expiration) */
  129. exp = (val >> WDT_STS_EXP_SHIFT) & WDT_STS_EXP_MASK;
  130. /*
  131. * The entire thing is divided by 4 because we are ticking down 4 times
  132. * faster due to needing to wait for the 4th expiration.
  133. */
  134. return (((3 - exp) * wdd->timeout) + count) / 4;
  135. }
  136. static const struct watchdog_info tegra_wdt_info = {
  137. .options = WDIOF_SETTIMEOUT |
  138. WDIOF_MAGICCLOSE |
  139. WDIOF_KEEPALIVEPING,
  140. .firmware_version = 0,
  141. .identity = "Tegra Watchdog",
  142. };
  143. static const struct watchdog_ops tegra_wdt_ops = {
  144. .owner = THIS_MODULE,
  145. .start = tegra_wdt_start,
  146. .stop = tegra_wdt_stop,
  147. .ping = tegra_wdt_ping,
  148. .set_timeout = tegra_wdt_set_timeout,
  149. .get_timeleft = tegra_wdt_get_timeleft,
  150. };
  151. static int tegra_wdt_probe(struct platform_device *pdev)
  152. {
  153. struct device *dev = &pdev->dev;
  154. struct watchdog_device *wdd;
  155. struct tegra_wdt *wdt;
  156. void __iomem *regs;
  157. int ret;
  158. /* This is the timer base. */
  159. regs = devm_platform_ioremap_resource(pdev, 0);
  160. if (IS_ERR(regs))
  161. return PTR_ERR(regs);
  162. /*
  163. * Allocate our watchdog driver data, which has the
  164. * struct watchdog_device nested within it.
  165. */
  166. wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
  167. if (!wdt)
  168. return -ENOMEM;
  169. /* Initialize struct tegra_wdt. */
  170. wdt->wdt_regs = regs + WDT_BASE;
  171. wdt->tmr_regs = regs + WDT_TIMER_BASE;
  172. /* Initialize struct watchdog_device. */
  173. wdd = &wdt->wdd;
  174. wdd->timeout = heartbeat;
  175. wdd->info = &tegra_wdt_info;
  176. wdd->ops = &tegra_wdt_ops;
  177. wdd->min_timeout = MIN_WDT_TIMEOUT;
  178. wdd->max_timeout = MAX_WDT_TIMEOUT;
  179. wdd->parent = dev;
  180. watchdog_set_drvdata(wdd, wdt);
  181. watchdog_set_nowayout(wdd, nowayout);
  182. watchdog_stop_on_unregister(wdd);
  183. ret = devm_watchdog_register_device(dev, wdd);
  184. if (ret)
  185. return ret;
  186. platform_set_drvdata(pdev, wdt);
  187. dev_info(dev, "initialized (heartbeat = %d sec, nowayout = %d)\n",
  188. heartbeat, nowayout);
  189. return 0;
  190. }
  191. #ifdef CONFIG_PM_SLEEP
  192. static int tegra_wdt_runtime_suspend(struct device *dev)
  193. {
  194. struct tegra_wdt *wdt = dev_get_drvdata(dev);
  195. if (watchdog_active(&wdt->wdd))
  196. tegra_wdt_stop(&wdt->wdd);
  197. return 0;
  198. }
  199. static int tegra_wdt_runtime_resume(struct device *dev)
  200. {
  201. struct tegra_wdt *wdt = dev_get_drvdata(dev);
  202. if (watchdog_active(&wdt->wdd))
  203. tegra_wdt_start(&wdt->wdd);
  204. return 0;
  205. }
  206. #endif
  207. static const struct of_device_id tegra_wdt_of_match[] = {
  208. { .compatible = "nvidia,tegra30-timer", },
  209. { },
  210. };
  211. MODULE_DEVICE_TABLE(of, tegra_wdt_of_match);
  212. static const struct dev_pm_ops tegra_wdt_pm_ops = {
  213. SET_SYSTEM_SLEEP_PM_OPS(tegra_wdt_runtime_suspend,
  214. tegra_wdt_runtime_resume)
  215. };
  216. static struct platform_driver tegra_wdt_driver = {
  217. .probe = tegra_wdt_probe,
  218. .driver = {
  219. .name = "tegra-wdt",
  220. .pm = &tegra_wdt_pm_ops,
  221. .of_match_table = tegra_wdt_of_match,
  222. },
  223. };
  224. module_platform_driver(tegra_wdt_driver);
  225. MODULE_AUTHOR("NVIDIA Corporation");
  226. MODULE_DESCRIPTION("Tegra Watchdog Driver");
  227. MODULE_LICENSE("GPL v2");