stm32_iwdg.c 7.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Driver for STM32 Independent Watchdog
  4. *
  5. * Copyright (C) STMicroelectronics 2017
  6. * Author: Yannick Fertre <yannick.fertre@st.com> for STMicroelectronics.
  7. *
  8. * This driver is based on tegra_wdt.c
  9. *
  10. */
  11. #include <linux/clk.h>
  12. #include <linux/delay.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/io.h>
  15. #include <linux/iopoll.h>
  16. #include <linux/kernel.h>
  17. #include <linux/module.h>
  18. #include <linux/of.h>
  19. #include <linux/of_device.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/watchdog.h>
  22. /* IWDG registers */
  23. #define IWDG_KR 0x00 /* Key register */
  24. #define IWDG_PR 0x04 /* Prescaler Register */
  25. #define IWDG_RLR 0x08 /* ReLoad Register */
  26. #define IWDG_SR 0x0C /* Status Register */
  27. #define IWDG_WINR 0x10 /* Windows Register */
  28. /* IWDG_KR register bit mask */
  29. #define KR_KEY_RELOAD 0xAAAA /* reload counter enable */
  30. #define KR_KEY_ENABLE 0xCCCC /* peripheral enable */
  31. #define KR_KEY_EWA 0x5555 /* write access enable */
  32. #define KR_KEY_DWA 0x0000 /* write access disable */
  33. /* IWDG_PR register */
  34. #define PR_SHIFT 2
  35. #define PR_MIN BIT(PR_SHIFT)
  36. /* IWDG_RLR register values */
  37. #define RLR_MIN 0x2 /* min value recommended */
  38. #define RLR_MAX GENMASK(11, 0) /* max value of reload register */
  39. /* IWDG_SR register bit mask */
  40. #define SR_PVU BIT(0) /* Watchdog prescaler value update */
  41. #define SR_RVU BIT(1) /* Watchdog counter reload value update */
  42. /* set timeout to 100000 us */
  43. #define TIMEOUT_US 100000
  44. #define SLEEP_US 1000
  45. struct stm32_iwdg_data {
  46. bool has_pclk;
  47. u32 max_prescaler;
  48. };
  49. static const struct stm32_iwdg_data stm32_iwdg_data = {
  50. .has_pclk = false,
  51. .max_prescaler = 256,
  52. };
  53. static const struct stm32_iwdg_data stm32mp1_iwdg_data = {
  54. .has_pclk = true,
  55. .max_prescaler = 1024,
  56. };
  57. struct stm32_iwdg {
  58. struct watchdog_device wdd;
  59. const struct stm32_iwdg_data *data;
  60. void __iomem *regs;
  61. struct clk *clk_lsi;
  62. struct clk *clk_pclk;
  63. unsigned int rate;
  64. };
  65. static inline u32 reg_read(void __iomem *base, u32 reg)
  66. {
  67. return readl_relaxed(base + reg);
  68. }
  69. static inline void reg_write(void __iomem *base, u32 reg, u32 val)
  70. {
  71. writel_relaxed(val, base + reg);
  72. }
  73. static int stm32_iwdg_start(struct watchdog_device *wdd)
  74. {
  75. struct stm32_iwdg *wdt = watchdog_get_drvdata(wdd);
  76. u32 tout, presc, iwdg_rlr, iwdg_pr, iwdg_sr;
  77. int ret;
  78. dev_dbg(wdd->parent, "%s\n", __func__);
  79. tout = clamp_t(unsigned int, wdd->timeout,
  80. wdd->min_timeout, wdd->max_hw_heartbeat_ms / 1000);
  81. presc = DIV_ROUND_UP(tout * wdt->rate, RLR_MAX + 1);
  82. /* The prescaler is align on power of 2 and start at 2 ^ PR_SHIFT. */
  83. presc = roundup_pow_of_two(presc);
  84. iwdg_pr = presc <= 1 << PR_SHIFT ? 0 : ilog2(presc) - PR_SHIFT;
  85. iwdg_rlr = ((tout * wdt->rate) / presc) - 1;
  86. /* enable write access */
  87. reg_write(wdt->regs, IWDG_KR, KR_KEY_EWA);
  88. /* set prescaler & reload registers */
  89. reg_write(wdt->regs, IWDG_PR, iwdg_pr);
  90. reg_write(wdt->regs, IWDG_RLR, iwdg_rlr);
  91. reg_write(wdt->regs, IWDG_KR, KR_KEY_ENABLE);
  92. /* wait for the registers to be updated (max 100ms) */
  93. ret = readl_relaxed_poll_timeout(wdt->regs + IWDG_SR, iwdg_sr,
  94. !(iwdg_sr & (SR_PVU | SR_RVU)),
  95. SLEEP_US, TIMEOUT_US);
  96. if (ret) {
  97. dev_err(wdd->parent, "Fail to set prescaler, reload regs\n");
  98. return ret;
  99. }
  100. /* reload watchdog */
  101. reg_write(wdt->regs, IWDG_KR, KR_KEY_RELOAD);
  102. return 0;
  103. }
  104. static int stm32_iwdg_ping(struct watchdog_device *wdd)
  105. {
  106. struct stm32_iwdg *wdt = watchdog_get_drvdata(wdd);
  107. dev_dbg(wdd->parent, "%s\n", __func__);
  108. /* reload watchdog */
  109. reg_write(wdt->regs, IWDG_KR, KR_KEY_RELOAD);
  110. return 0;
  111. }
  112. static int stm32_iwdg_set_timeout(struct watchdog_device *wdd,
  113. unsigned int timeout)
  114. {
  115. dev_dbg(wdd->parent, "%s timeout: %d sec\n", __func__, timeout);
  116. wdd->timeout = timeout;
  117. if (watchdog_active(wdd))
  118. return stm32_iwdg_start(wdd);
  119. return 0;
  120. }
  121. static void stm32_clk_disable_unprepare(void *data)
  122. {
  123. clk_disable_unprepare(data);
  124. }
  125. static int stm32_iwdg_clk_init(struct platform_device *pdev,
  126. struct stm32_iwdg *wdt)
  127. {
  128. struct device *dev = &pdev->dev;
  129. u32 ret;
  130. wdt->clk_lsi = devm_clk_get(dev, "lsi");
  131. if (IS_ERR(wdt->clk_lsi)) {
  132. dev_err(dev, "Unable to get lsi clock\n");
  133. return PTR_ERR(wdt->clk_lsi);
  134. }
  135. /* optional peripheral clock */
  136. if (wdt->data->has_pclk) {
  137. wdt->clk_pclk = devm_clk_get(dev, "pclk");
  138. if (IS_ERR(wdt->clk_pclk)) {
  139. dev_err(dev, "Unable to get pclk clock\n");
  140. return PTR_ERR(wdt->clk_pclk);
  141. }
  142. ret = clk_prepare_enable(wdt->clk_pclk);
  143. if (ret) {
  144. dev_err(dev, "Unable to prepare pclk clock\n");
  145. return ret;
  146. }
  147. ret = devm_add_action_or_reset(dev,
  148. stm32_clk_disable_unprepare,
  149. wdt->clk_pclk);
  150. if (ret)
  151. return ret;
  152. }
  153. ret = clk_prepare_enable(wdt->clk_lsi);
  154. if (ret) {
  155. dev_err(dev, "Unable to prepare lsi clock\n");
  156. return ret;
  157. }
  158. ret = devm_add_action_or_reset(dev, stm32_clk_disable_unprepare,
  159. wdt->clk_lsi);
  160. if (ret)
  161. return ret;
  162. wdt->rate = clk_get_rate(wdt->clk_lsi);
  163. return 0;
  164. }
  165. static const struct watchdog_info stm32_iwdg_info = {
  166. .options = WDIOF_SETTIMEOUT |
  167. WDIOF_MAGICCLOSE |
  168. WDIOF_KEEPALIVEPING,
  169. .identity = "STM32 Independent Watchdog",
  170. };
  171. static const struct watchdog_ops stm32_iwdg_ops = {
  172. .owner = THIS_MODULE,
  173. .start = stm32_iwdg_start,
  174. .ping = stm32_iwdg_ping,
  175. .set_timeout = stm32_iwdg_set_timeout,
  176. };
  177. static const struct of_device_id stm32_iwdg_of_match[] = {
  178. { .compatible = "st,stm32-iwdg", .data = &stm32_iwdg_data },
  179. { .compatible = "st,stm32mp1-iwdg", .data = &stm32mp1_iwdg_data },
  180. { /* end node */ }
  181. };
  182. MODULE_DEVICE_TABLE(of, stm32_iwdg_of_match);
  183. static int stm32_iwdg_probe(struct platform_device *pdev)
  184. {
  185. struct device *dev = &pdev->dev;
  186. struct watchdog_device *wdd;
  187. struct stm32_iwdg *wdt;
  188. int ret;
  189. wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
  190. if (!wdt)
  191. return -ENOMEM;
  192. wdt->data = of_device_get_match_data(&pdev->dev);
  193. if (!wdt->data)
  194. return -ENODEV;
  195. /* This is the timer base. */
  196. wdt->regs = devm_platform_ioremap_resource(pdev, 0);
  197. if (IS_ERR(wdt->regs)) {
  198. dev_err(dev, "Could not get resource\n");
  199. return PTR_ERR(wdt->regs);
  200. }
  201. ret = stm32_iwdg_clk_init(pdev, wdt);
  202. if (ret)
  203. return ret;
  204. /* Initialize struct watchdog_device. */
  205. wdd = &wdt->wdd;
  206. wdd->parent = dev;
  207. wdd->info = &stm32_iwdg_info;
  208. wdd->ops = &stm32_iwdg_ops;
  209. wdd->min_timeout = DIV_ROUND_UP((RLR_MIN + 1) * PR_MIN, wdt->rate);
  210. wdd->max_hw_heartbeat_ms = ((RLR_MAX + 1) * wdt->data->max_prescaler *
  211. 1000) / wdt->rate;
  212. watchdog_set_drvdata(wdd, wdt);
  213. watchdog_set_nowayout(wdd, WATCHDOG_NOWAYOUT);
  214. watchdog_init_timeout(wdd, 0, dev);
  215. /*
  216. * In case of CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED is set
  217. * (Means U-Boot/bootloaders leaves the watchdog running)
  218. * When we get here we should make a decision to prevent
  219. * any side effects before user space daemon will take care of it.
  220. * The best option, taking into consideration that there is no
  221. * way to read values back from hardware, is to enforce watchdog
  222. * being run with deterministic values.
  223. */
  224. if (IS_ENABLED(CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED)) {
  225. ret = stm32_iwdg_start(wdd);
  226. if (ret)
  227. return ret;
  228. /* Make sure the watchdog is serviced */
  229. set_bit(WDOG_HW_RUNNING, &wdd->status);
  230. }
  231. ret = devm_watchdog_register_device(dev, wdd);
  232. if (ret)
  233. return ret;
  234. platform_set_drvdata(pdev, wdt);
  235. return 0;
  236. }
  237. static struct platform_driver stm32_iwdg_driver = {
  238. .probe = stm32_iwdg_probe,
  239. .driver = {
  240. .name = "iwdg",
  241. .of_match_table = of_match_ptr(stm32_iwdg_of_match),
  242. },
  243. };
  244. module_platform_driver(stm32_iwdg_driver);
  245. MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>");
  246. MODULE_DESCRIPTION("STMicroelectronics STM32 Independent Watchdog Driver");
  247. MODULE_LICENSE("GPL v2");