sp5100_tco.c 13 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506
  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * sp5100_tco : TCO timer driver for sp5100 chipsets
  4. *
  5. * (c) Copyright 2009 Google Inc., All Rights Reserved.
  6. *
  7. * Based on i8xx_tco.c:
  8. * (c) Copyright 2000 kernel concepts <nils@kernelconcepts.de>, All Rights
  9. * Reserved.
  10. * https://www.kernelconcepts.de
  11. *
  12. * See AMD Publication 43009 "AMD SB700/710/750 Register Reference Guide",
  13. * AMD Publication 45482 "AMD SB800-Series Southbridges Register
  14. * Reference Guide"
  15. * AMD Publication 48751 "BIOS and Kernel Developer’s Guide (BKDG)
  16. * for AMD Family 16h Models 00h-0Fh Processors"
  17. * AMD Publication 51192 "AMD Bolton FCH Register Reference Guide"
  18. * AMD Publication 52740 "BIOS and Kernel Developer’s Guide (BKDG)
  19. * for AMD Family 16h Models 30h-3Fh Processors"
  20. * AMD Publication 55570-B1-PUB "Processor Programming Reference (PPR)
  21. * for AMD Family 17h Model 18h, Revision B1
  22. * Processors (PUB)
  23. * AMD Publication 55772-A1-PUB "Processor Programming Reference (PPR)
  24. * for AMD Family 17h Model 20h, Revision A1
  25. * Processors (PUB)
  26. */
  27. /*
  28. * Includes, defines, variables, module parameters, ...
  29. */
  30. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  31. #include <linux/init.h>
  32. #include <linux/io.h>
  33. #include <linux/ioport.h>
  34. #include <linux/module.h>
  35. #include <linux/moduleparam.h>
  36. #include <linux/pci.h>
  37. #include <linux/platform_device.h>
  38. #include <linux/types.h>
  39. #include <linux/watchdog.h>
  40. #include "sp5100_tco.h"
  41. #define TCO_DRIVER_NAME "sp5100-tco"
  42. /* internal variables */
  43. enum tco_reg_layout {
  44. sp5100, sb800, efch
  45. };
  46. struct sp5100_tco {
  47. struct watchdog_device wdd;
  48. void __iomem *tcobase;
  49. enum tco_reg_layout tco_reg_layout;
  50. };
  51. /* the watchdog platform device */
  52. static struct platform_device *sp5100_tco_platform_device;
  53. /* the associated PCI device */
  54. static struct pci_dev *sp5100_tco_pci;
  55. /* module parameters */
  56. #define WATCHDOG_HEARTBEAT 60 /* 60 sec default heartbeat. */
  57. static int heartbeat = WATCHDOG_HEARTBEAT; /* in seconds */
  58. module_param(heartbeat, int, 0);
  59. MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds. (default="
  60. __MODULE_STRING(WATCHDOG_HEARTBEAT) ")");
  61. static bool nowayout = WATCHDOG_NOWAYOUT;
  62. module_param(nowayout, bool, 0);
  63. MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started."
  64. " (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  65. /*
  66. * Some TCO specific functions
  67. */
  68. static enum tco_reg_layout tco_reg_layout(struct pci_dev *dev)
  69. {
  70. if (dev->vendor == PCI_VENDOR_ID_ATI &&
  71. dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS &&
  72. dev->revision < 0x40) {
  73. return sp5100;
  74. } else if (dev->vendor == PCI_VENDOR_ID_AMD &&
  75. ((dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS &&
  76. dev->revision >= 0x41) ||
  77. (dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS &&
  78. dev->revision >= 0x49))) {
  79. return efch;
  80. }
  81. return sb800;
  82. }
  83. static int tco_timer_start(struct watchdog_device *wdd)
  84. {
  85. struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
  86. u32 val;
  87. val = readl(SP5100_WDT_CONTROL(tco->tcobase));
  88. val |= SP5100_WDT_START_STOP_BIT;
  89. writel(val, SP5100_WDT_CONTROL(tco->tcobase));
  90. return 0;
  91. }
  92. static int tco_timer_stop(struct watchdog_device *wdd)
  93. {
  94. struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
  95. u32 val;
  96. val = readl(SP5100_WDT_CONTROL(tco->tcobase));
  97. val &= ~SP5100_WDT_START_STOP_BIT;
  98. writel(val, SP5100_WDT_CONTROL(tco->tcobase));
  99. return 0;
  100. }
  101. static int tco_timer_ping(struct watchdog_device *wdd)
  102. {
  103. struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
  104. u32 val;
  105. val = readl(SP5100_WDT_CONTROL(tco->tcobase));
  106. val |= SP5100_WDT_TRIGGER_BIT;
  107. writel(val, SP5100_WDT_CONTROL(tco->tcobase));
  108. return 0;
  109. }
  110. static int tco_timer_set_timeout(struct watchdog_device *wdd,
  111. unsigned int t)
  112. {
  113. struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
  114. /* Write new heartbeat to watchdog */
  115. writel(t, SP5100_WDT_COUNT(tco->tcobase));
  116. wdd->timeout = t;
  117. return 0;
  118. }
  119. static u8 sp5100_tco_read_pm_reg8(u8 index)
  120. {
  121. outb(index, SP5100_IO_PM_INDEX_REG);
  122. return inb(SP5100_IO_PM_DATA_REG);
  123. }
  124. static void sp5100_tco_update_pm_reg8(u8 index, u8 reset, u8 set)
  125. {
  126. u8 val;
  127. outb(index, SP5100_IO_PM_INDEX_REG);
  128. val = inb(SP5100_IO_PM_DATA_REG);
  129. val &= reset;
  130. val |= set;
  131. outb(val, SP5100_IO_PM_DATA_REG);
  132. }
  133. static void tco_timer_enable(struct sp5100_tco *tco)
  134. {
  135. u32 val;
  136. switch (tco->tco_reg_layout) {
  137. case sb800:
  138. /* For SB800 or later */
  139. /* Set the Watchdog timer resolution to 1 sec */
  140. sp5100_tco_update_pm_reg8(SB800_PM_WATCHDOG_CONFIG,
  141. 0xff, SB800_PM_WATCHDOG_SECOND_RES);
  142. /* Enable watchdog decode bit and watchdog timer */
  143. sp5100_tco_update_pm_reg8(SB800_PM_WATCHDOG_CONTROL,
  144. ~SB800_PM_WATCHDOG_DISABLE,
  145. SB800_PCI_WATCHDOG_DECODE_EN);
  146. break;
  147. case sp5100:
  148. /* For SP5100 or SB7x0 */
  149. /* Enable watchdog decode bit */
  150. pci_read_config_dword(sp5100_tco_pci,
  151. SP5100_PCI_WATCHDOG_MISC_REG,
  152. &val);
  153. val |= SP5100_PCI_WATCHDOG_DECODE_EN;
  154. pci_write_config_dword(sp5100_tco_pci,
  155. SP5100_PCI_WATCHDOG_MISC_REG,
  156. val);
  157. /* Enable Watchdog timer and set the resolution to 1 sec */
  158. sp5100_tco_update_pm_reg8(SP5100_PM_WATCHDOG_CONTROL,
  159. ~SP5100_PM_WATCHDOG_DISABLE,
  160. SP5100_PM_WATCHDOG_SECOND_RES);
  161. break;
  162. case efch:
  163. /* Set the Watchdog timer resolution to 1 sec and enable */
  164. sp5100_tco_update_pm_reg8(EFCH_PM_DECODEEN3,
  165. ~EFCH_PM_WATCHDOG_DISABLE,
  166. EFCH_PM_DECODEEN_SECOND_RES);
  167. break;
  168. }
  169. }
  170. static u32 sp5100_tco_read_pm_reg32(u8 index)
  171. {
  172. u32 val = 0;
  173. int i;
  174. for (i = 3; i >= 0; i--)
  175. val = (val << 8) + sp5100_tco_read_pm_reg8(index + i);
  176. return val;
  177. }
  178. static int sp5100_tco_setupdevice(struct device *dev,
  179. struct watchdog_device *wdd)
  180. {
  181. struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
  182. const char *dev_name;
  183. u32 mmio_addr = 0, val;
  184. int ret;
  185. /* Request the IO ports used by this driver */
  186. if (!request_muxed_region(SP5100_IO_PM_INDEX_REG,
  187. SP5100_PM_IOPORTS_SIZE, "sp5100_tco")) {
  188. dev_err(dev, "I/O address 0x%04x already in use\n",
  189. SP5100_IO_PM_INDEX_REG);
  190. return -EBUSY;
  191. }
  192. /*
  193. * Determine type of southbridge chipset.
  194. */
  195. switch (tco->tco_reg_layout) {
  196. case sp5100:
  197. dev_name = SP5100_DEVNAME;
  198. mmio_addr = sp5100_tco_read_pm_reg32(SP5100_PM_WATCHDOG_BASE) &
  199. 0xfffffff8;
  200. break;
  201. case sb800:
  202. dev_name = SB800_DEVNAME;
  203. mmio_addr = sp5100_tco_read_pm_reg32(SB800_PM_WATCHDOG_BASE) &
  204. 0xfffffff8;
  205. break;
  206. case efch:
  207. dev_name = SB800_DEVNAME;
  208. /*
  209. * On Family 17h devices, the EFCH_PM_DECODEEN_WDT_TMREN bit of
  210. * EFCH_PM_DECODEEN not only enables the EFCH_PM_WDT_ADDR memory
  211. * region, it also enables the watchdog itself.
  212. */
  213. if (boot_cpu_data.x86 == 0x17) {
  214. val = sp5100_tco_read_pm_reg8(EFCH_PM_DECODEEN);
  215. if (!(val & EFCH_PM_DECODEEN_WDT_TMREN)) {
  216. sp5100_tco_update_pm_reg8(EFCH_PM_DECODEEN, 0xff,
  217. EFCH_PM_DECODEEN_WDT_TMREN);
  218. }
  219. }
  220. val = sp5100_tco_read_pm_reg8(EFCH_PM_DECODEEN);
  221. if (val & EFCH_PM_DECODEEN_WDT_TMREN)
  222. mmio_addr = EFCH_PM_WDT_ADDR;
  223. break;
  224. default:
  225. return -ENODEV;
  226. }
  227. /* Check MMIO address conflict */
  228. if (!mmio_addr ||
  229. !devm_request_mem_region(dev, mmio_addr, SP5100_WDT_MEM_MAP_SIZE,
  230. dev_name)) {
  231. if (mmio_addr)
  232. dev_dbg(dev, "MMIO address 0x%08x already in use\n",
  233. mmio_addr);
  234. switch (tco->tco_reg_layout) {
  235. case sp5100:
  236. /*
  237. * Secondly, Find the watchdog timer MMIO address
  238. * from SBResource_MMIO register.
  239. */
  240. /* Read SBResource_MMIO from PCI config(PCI_Reg: 9Ch) */
  241. pci_read_config_dword(sp5100_tco_pci,
  242. SP5100_SB_RESOURCE_MMIO_BASE,
  243. &mmio_addr);
  244. if ((mmio_addr & (SB800_ACPI_MMIO_DECODE_EN |
  245. SB800_ACPI_MMIO_SEL)) !=
  246. SB800_ACPI_MMIO_DECODE_EN) {
  247. ret = -ENODEV;
  248. goto unreg_region;
  249. }
  250. mmio_addr &= ~0xFFF;
  251. mmio_addr += SB800_PM_WDT_MMIO_OFFSET;
  252. break;
  253. case sb800:
  254. /* Read SBResource_MMIO from AcpiMmioEn(PM_Reg: 24h) */
  255. mmio_addr =
  256. sp5100_tco_read_pm_reg32(SB800_PM_ACPI_MMIO_EN);
  257. if ((mmio_addr & (SB800_ACPI_MMIO_DECODE_EN |
  258. SB800_ACPI_MMIO_SEL)) !=
  259. SB800_ACPI_MMIO_DECODE_EN) {
  260. ret = -ENODEV;
  261. goto unreg_region;
  262. }
  263. mmio_addr &= ~0xFFF;
  264. mmio_addr += SB800_PM_WDT_MMIO_OFFSET;
  265. break;
  266. case efch:
  267. val = sp5100_tco_read_pm_reg8(EFCH_PM_ISACONTROL);
  268. if (!(val & EFCH_PM_ISACONTROL_MMIOEN)) {
  269. ret = -ENODEV;
  270. goto unreg_region;
  271. }
  272. mmio_addr = EFCH_PM_ACPI_MMIO_ADDR +
  273. EFCH_PM_ACPI_MMIO_WDT_OFFSET;
  274. break;
  275. }
  276. dev_dbg(dev, "Got 0x%08x from SBResource_MMIO register\n",
  277. mmio_addr);
  278. if (!devm_request_mem_region(dev, mmio_addr,
  279. SP5100_WDT_MEM_MAP_SIZE,
  280. dev_name)) {
  281. dev_dbg(dev, "MMIO address 0x%08x already in use\n",
  282. mmio_addr);
  283. ret = -EBUSY;
  284. goto unreg_region;
  285. }
  286. }
  287. tco->tcobase = devm_ioremap(dev, mmio_addr, SP5100_WDT_MEM_MAP_SIZE);
  288. if (!tco->tcobase) {
  289. dev_err(dev, "failed to get tcobase address\n");
  290. ret = -ENOMEM;
  291. goto unreg_region;
  292. }
  293. dev_info(dev, "Using 0x%08x for watchdog MMIO address\n", mmio_addr);
  294. /* Setup the watchdog timer */
  295. tco_timer_enable(tco);
  296. val = readl(SP5100_WDT_CONTROL(tco->tcobase));
  297. if (val & SP5100_WDT_DISABLED) {
  298. dev_err(dev, "Watchdog hardware is disabled\n");
  299. ret = -ENODEV;
  300. goto unreg_region;
  301. }
  302. /*
  303. * Save WatchDogFired status, because WatchDogFired flag is
  304. * cleared here.
  305. */
  306. if (val & SP5100_WDT_FIRED)
  307. wdd->bootstatus = WDIOF_CARDRESET;
  308. /* Set watchdog action to reset the system */
  309. val &= ~SP5100_WDT_ACTION_RESET;
  310. writel(val, SP5100_WDT_CONTROL(tco->tcobase));
  311. /* Set a reasonable heartbeat before we stop the timer */
  312. tco_timer_set_timeout(wdd, wdd->timeout);
  313. /*
  314. * Stop the TCO before we change anything so we don't race with
  315. * a zeroed timer.
  316. */
  317. tco_timer_stop(wdd);
  318. release_region(SP5100_IO_PM_INDEX_REG, SP5100_PM_IOPORTS_SIZE);
  319. return 0;
  320. unreg_region:
  321. release_region(SP5100_IO_PM_INDEX_REG, SP5100_PM_IOPORTS_SIZE);
  322. return ret;
  323. }
  324. static struct watchdog_info sp5100_tco_wdt_info = {
  325. .identity = "SP5100 TCO timer",
  326. .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
  327. };
  328. static const struct watchdog_ops sp5100_tco_wdt_ops = {
  329. .owner = THIS_MODULE,
  330. .start = tco_timer_start,
  331. .stop = tco_timer_stop,
  332. .ping = tco_timer_ping,
  333. .set_timeout = tco_timer_set_timeout,
  334. };
  335. static int sp5100_tco_probe(struct platform_device *pdev)
  336. {
  337. struct device *dev = &pdev->dev;
  338. struct watchdog_device *wdd;
  339. struct sp5100_tco *tco;
  340. int ret;
  341. tco = devm_kzalloc(dev, sizeof(*tco), GFP_KERNEL);
  342. if (!tco)
  343. return -ENOMEM;
  344. tco->tco_reg_layout = tco_reg_layout(sp5100_tco_pci);
  345. wdd = &tco->wdd;
  346. wdd->parent = dev;
  347. wdd->info = &sp5100_tco_wdt_info;
  348. wdd->ops = &sp5100_tco_wdt_ops;
  349. wdd->timeout = WATCHDOG_HEARTBEAT;
  350. wdd->min_timeout = 1;
  351. wdd->max_timeout = 0xffff;
  352. watchdog_init_timeout(wdd, heartbeat, NULL);
  353. watchdog_set_nowayout(wdd, nowayout);
  354. watchdog_stop_on_reboot(wdd);
  355. watchdog_stop_on_unregister(wdd);
  356. watchdog_set_drvdata(wdd, tco);
  357. ret = sp5100_tco_setupdevice(dev, wdd);
  358. if (ret)
  359. return ret;
  360. ret = devm_watchdog_register_device(dev, wdd);
  361. if (ret)
  362. return ret;
  363. /* Show module parameters */
  364. dev_info(dev, "initialized. heartbeat=%d sec (nowayout=%d)\n",
  365. wdd->timeout, nowayout);
  366. return 0;
  367. }
  368. static struct platform_driver sp5100_tco_driver = {
  369. .probe = sp5100_tco_probe,
  370. .driver = {
  371. .name = TCO_DRIVER_NAME,
  372. },
  373. };
  374. /*
  375. * Data for PCI driver interface
  376. *
  377. * This data only exists for exporting the supported
  378. * PCI ids via MODULE_DEVICE_TABLE. We do not actually
  379. * register a pci_driver, because someone else might
  380. * want to register another driver on the same PCI id.
  381. */
  382. static const struct pci_device_id sp5100_tco_pci_tbl[] = {
  383. { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, PCI_ANY_ID,
  384. PCI_ANY_ID, },
  385. { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, PCI_ANY_ID,
  386. PCI_ANY_ID, },
  387. { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, PCI_ANY_ID,
  388. PCI_ANY_ID, },
  389. { 0, }, /* End of list */
  390. };
  391. MODULE_DEVICE_TABLE(pci, sp5100_tco_pci_tbl);
  392. static int __init sp5100_tco_init(void)
  393. {
  394. struct pci_dev *dev = NULL;
  395. int err;
  396. /* Match the PCI device */
  397. for_each_pci_dev(dev) {
  398. if (pci_match_id(sp5100_tco_pci_tbl, dev) != NULL) {
  399. sp5100_tco_pci = dev;
  400. break;
  401. }
  402. }
  403. if (!sp5100_tco_pci)
  404. return -ENODEV;
  405. pr_info("SP5100/SB800 TCO WatchDog Timer Driver\n");
  406. err = platform_driver_register(&sp5100_tco_driver);
  407. if (err)
  408. return err;
  409. sp5100_tco_platform_device =
  410. platform_device_register_simple(TCO_DRIVER_NAME, -1, NULL, 0);
  411. if (IS_ERR(sp5100_tco_platform_device)) {
  412. err = PTR_ERR(sp5100_tco_platform_device);
  413. goto unreg_platform_driver;
  414. }
  415. return 0;
  416. unreg_platform_driver:
  417. platform_driver_unregister(&sp5100_tco_driver);
  418. return err;
  419. }
  420. static void __exit sp5100_tco_exit(void)
  421. {
  422. platform_device_unregister(sp5100_tco_platform_device);
  423. platform_driver_unregister(&sp5100_tco_driver);
  424. }
  425. module_init(sp5100_tco_init);
  426. module_exit(sp5100_tco_exit);
  427. MODULE_AUTHOR("Priyanka Gupta");
  428. MODULE_DESCRIPTION("TCO timer driver for SP5100/SB800 chipset");
  429. MODULE_LICENSE("GPL");