s3c2410_wdt.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (c) 2004 Simtec Electronics
  4. * Ben Dooks <ben@simtec.co.uk>
  5. *
  6. * S3C2410 Watchdog Timer Support
  7. *
  8. * Based on, softdog.c by Alan Cox,
  9. * (c) Copyright 1996 Alan Cox <alan@lxorguk.ukuu.org.uk>
  10. */
  11. #include <linux/module.h>
  12. #include <linux/moduleparam.h>
  13. #include <linux/types.h>
  14. #include <linux/timer.h>
  15. #include <linux/watchdog.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/interrupt.h>
  18. #include <linux/clk.h>
  19. #include <linux/uaccess.h>
  20. #include <linux/io.h>
  21. #include <linux/cpufreq.h>
  22. #include <linux/slab.h>
  23. #include <linux/err.h>
  24. #include <linux/of.h>
  25. #include <linux/of_device.h>
  26. #include <linux/mfd/syscon.h>
  27. #include <linux/regmap.h>
  28. #include <linux/delay.h>
  29. #define S3C2410_WTCON 0x00
  30. #define S3C2410_WTDAT 0x04
  31. #define S3C2410_WTCNT 0x08
  32. #define S3C2410_WTCLRINT 0x0c
  33. #define S3C2410_WTCNT_MAXCNT 0xffff
  34. #define S3C2410_WTCON_RSTEN (1 << 0)
  35. #define S3C2410_WTCON_INTEN (1 << 2)
  36. #define S3C2410_WTCON_ENABLE (1 << 5)
  37. #define S3C2410_WTCON_DIV16 (0 << 3)
  38. #define S3C2410_WTCON_DIV32 (1 << 3)
  39. #define S3C2410_WTCON_DIV64 (2 << 3)
  40. #define S3C2410_WTCON_DIV128 (3 << 3)
  41. #define S3C2410_WTCON_MAXDIV 0x80
  42. #define S3C2410_WTCON_PRESCALE(x) ((x) << 8)
  43. #define S3C2410_WTCON_PRESCALE_MASK (0xff << 8)
  44. #define S3C2410_WTCON_PRESCALE_MAX 0xff
  45. #define S3C2410_WATCHDOG_ATBOOT (0)
  46. #define S3C2410_WATCHDOG_DEFAULT_TIME (15)
  47. #define EXYNOS5_RST_STAT_REG_OFFSET 0x0404
  48. #define EXYNOS5_WDT_DISABLE_REG_OFFSET 0x0408
  49. #define EXYNOS5_WDT_MASK_RESET_REG_OFFSET 0x040c
  50. #define QUIRK_HAS_PMU_CONFIG (1 << 0)
  51. #define QUIRK_HAS_RST_STAT (1 << 1)
  52. #define QUIRK_HAS_WTCLRINT_REG (1 << 2)
  53. /* These quirks require that we have a PMU register map */
  54. #define QUIRKS_HAVE_PMUREG (QUIRK_HAS_PMU_CONFIG | \
  55. QUIRK_HAS_RST_STAT)
  56. static bool nowayout = WATCHDOG_NOWAYOUT;
  57. static int tmr_margin;
  58. static int tmr_atboot = S3C2410_WATCHDOG_ATBOOT;
  59. static int soft_noboot;
  60. module_param(tmr_margin, int, 0);
  61. module_param(tmr_atboot, int, 0);
  62. module_param(nowayout, bool, 0);
  63. module_param(soft_noboot, int, 0);
  64. MODULE_PARM_DESC(tmr_margin, "Watchdog tmr_margin in seconds. (default="
  65. __MODULE_STRING(S3C2410_WATCHDOG_DEFAULT_TIME) ")");
  66. MODULE_PARM_DESC(tmr_atboot,
  67. "Watchdog is started at boot time if set to 1, default="
  68. __MODULE_STRING(S3C2410_WATCHDOG_ATBOOT));
  69. MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
  70. __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  71. MODULE_PARM_DESC(soft_noboot, "Watchdog action, set to 1 to ignore reboots, 0 to reboot (default 0)");
  72. /**
  73. * struct s3c2410_wdt_variant - Per-variant config data
  74. *
  75. * @disable_reg: Offset in pmureg for the register that disables the watchdog
  76. * timer reset functionality.
  77. * @mask_reset_reg: Offset in pmureg for the register that masks the watchdog
  78. * timer reset functionality.
  79. * @mask_bit: Bit number for the watchdog timer in the disable register and the
  80. * mask reset register.
  81. * @rst_stat_reg: Offset in pmureg for the register that has the reset status.
  82. * @rst_stat_bit: Bit number in the rst_stat register indicating a watchdog
  83. * reset.
  84. * @quirks: A bitfield of quirks.
  85. */
  86. struct s3c2410_wdt_variant {
  87. int disable_reg;
  88. int mask_reset_reg;
  89. int mask_bit;
  90. int rst_stat_reg;
  91. int rst_stat_bit;
  92. u32 quirks;
  93. };
  94. struct s3c2410_wdt {
  95. struct device *dev;
  96. struct clk *clock;
  97. void __iomem *reg_base;
  98. unsigned int count;
  99. spinlock_t lock;
  100. unsigned long wtcon_save;
  101. unsigned long wtdat_save;
  102. struct watchdog_device wdt_device;
  103. struct notifier_block freq_transition;
  104. const struct s3c2410_wdt_variant *drv_data;
  105. struct regmap *pmureg;
  106. };
  107. static const struct s3c2410_wdt_variant drv_data_s3c2410 = {
  108. .quirks = 0
  109. };
  110. #ifdef CONFIG_OF
  111. static const struct s3c2410_wdt_variant drv_data_s3c6410 = {
  112. .quirks = QUIRK_HAS_WTCLRINT_REG,
  113. };
  114. static const struct s3c2410_wdt_variant drv_data_exynos5250 = {
  115. .disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET,
  116. .mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET,
  117. .mask_bit = 20,
  118. .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
  119. .rst_stat_bit = 20,
  120. .quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT \
  121. | QUIRK_HAS_WTCLRINT_REG,
  122. };
  123. static const struct s3c2410_wdt_variant drv_data_exynos5420 = {
  124. .disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET,
  125. .mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET,
  126. .mask_bit = 0,
  127. .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
  128. .rst_stat_bit = 9,
  129. .quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT \
  130. | QUIRK_HAS_WTCLRINT_REG,
  131. };
  132. static const struct s3c2410_wdt_variant drv_data_exynos7 = {
  133. .disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET,
  134. .mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET,
  135. .mask_bit = 23,
  136. .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
  137. .rst_stat_bit = 23, /* A57 WDTRESET */
  138. .quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT \
  139. | QUIRK_HAS_WTCLRINT_REG,
  140. };
  141. static const struct of_device_id s3c2410_wdt_match[] = {
  142. { .compatible = "samsung,s3c2410-wdt",
  143. .data = &drv_data_s3c2410 },
  144. { .compatible = "samsung,s3c6410-wdt",
  145. .data = &drv_data_s3c6410 },
  146. { .compatible = "samsung,exynos5250-wdt",
  147. .data = &drv_data_exynos5250 },
  148. { .compatible = "samsung,exynos5420-wdt",
  149. .data = &drv_data_exynos5420 },
  150. { .compatible = "samsung,exynos7-wdt",
  151. .data = &drv_data_exynos7 },
  152. {},
  153. };
  154. MODULE_DEVICE_TABLE(of, s3c2410_wdt_match);
  155. #endif
  156. static const struct platform_device_id s3c2410_wdt_ids[] = {
  157. {
  158. .name = "s3c2410-wdt",
  159. .driver_data = (unsigned long)&drv_data_s3c2410,
  160. },
  161. {}
  162. };
  163. MODULE_DEVICE_TABLE(platform, s3c2410_wdt_ids);
  164. /* functions */
  165. static inline unsigned int s3c2410wdt_max_timeout(struct clk *clock)
  166. {
  167. unsigned long freq = clk_get_rate(clock);
  168. return S3C2410_WTCNT_MAXCNT / (freq / (S3C2410_WTCON_PRESCALE_MAX + 1)
  169. / S3C2410_WTCON_MAXDIV);
  170. }
  171. static inline struct s3c2410_wdt *freq_to_wdt(struct notifier_block *nb)
  172. {
  173. return container_of(nb, struct s3c2410_wdt, freq_transition);
  174. }
  175. static int s3c2410wdt_mask_and_disable_reset(struct s3c2410_wdt *wdt, bool mask)
  176. {
  177. int ret;
  178. u32 mask_val = 1 << wdt->drv_data->mask_bit;
  179. u32 val = 0;
  180. /* No need to do anything if no PMU CONFIG needed */
  181. if (!(wdt->drv_data->quirks & QUIRK_HAS_PMU_CONFIG))
  182. return 0;
  183. if (mask)
  184. val = mask_val;
  185. ret = regmap_update_bits(wdt->pmureg,
  186. wdt->drv_data->disable_reg,
  187. mask_val, val);
  188. if (ret < 0)
  189. goto error;
  190. ret = regmap_update_bits(wdt->pmureg,
  191. wdt->drv_data->mask_reset_reg,
  192. mask_val, val);
  193. error:
  194. if (ret < 0)
  195. dev_err(wdt->dev, "failed to update reg(%d)\n", ret);
  196. return ret;
  197. }
  198. static int s3c2410wdt_keepalive(struct watchdog_device *wdd)
  199. {
  200. struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
  201. spin_lock(&wdt->lock);
  202. writel(wdt->count, wdt->reg_base + S3C2410_WTCNT);
  203. spin_unlock(&wdt->lock);
  204. return 0;
  205. }
  206. static void __s3c2410wdt_stop(struct s3c2410_wdt *wdt)
  207. {
  208. unsigned long wtcon;
  209. wtcon = readl(wdt->reg_base + S3C2410_WTCON);
  210. wtcon &= ~(S3C2410_WTCON_ENABLE | S3C2410_WTCON_RSTEN);
  211. writel(wtcon, wdt->reg_base + S3C2410_WTCON);
  212. }
  213. static int s3c2410wdt_stop(struct watchdog_device *wdd)
  214. {
  215. struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
  216. spin_lock(&wdt->lock);
  217. __s3c2410wdt_stop(wdt);
  218. spin_unlock(&wdt->lock);
  219. return 0;
  220. }
  221. static int s3c2410wdt_start(struct watchdog_device *wdd)
  222. {
  223. unsigned long wtcon;
  224. struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
  225. spin_lock(&wdt->lock);
  226. __s3c2410wdt_stop(wdt);
  227. wtcon = readl(wdt->reg_base + S3C2410_WTCON);
  228. wtcon |= S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128;
  229. if (soft_noboot) {
  230. wtcon |= S3C2410_WTCON_INTEN;
  231. wtcon &= ~S3C2410_WTCON_RSTEN;
  232. } else {
  233. wtcon &= ~S3C2410_WTCON_INTEN;
  234. wtcon |= S3C2410_WTCON_RSTEN;
  235. }
  236. dev_dbg(wdt->dev, "Starting watchdog: count=0x%08x, wtcon=%08lx\n",
  237. wdt->count, wtcon);
  238. writel(wdt->count, wdt->reg_base + S3C2410_WTDAT);
  239. writel(wdt->count, wdt->reg_base + S3C2410_WTCNT);
  240. writel(wtcon, wdt->reg_base + S3C2410_WTCON);
  241. spin_unlock(&wdt->lock);
  242. return 0;
  243. }
  244. static inline int s3c2410wdt_is_running(struct s3c2410_wdt *wdt)
  245. {
  246. return readl(wdt->reg_base + S3C2410_WTCON) & S3C2410_WTCON_ENABLE;
  247. }
  248. static int s3c2410wdt_set_heartbeat(struct watchdog_device *wdd,
  249. unsigned int timeout)
  250. {
  251. struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
  252. unsigned long freq = clk_get_rate(wdt->clock);
  253. unsigned int count;
  254. unsigned int divisor = 1;
  255. unsigned long wtcon;
  256. if (timeout < 1)
  257. return -EINVAL;
  258. freq = DIV_ROUND_UP(freq, 128);
  259. count = timeout * freq;
  260. dev_dbg(wdt->dev, "Heartbeat: count=%d, timeout=%d, freq=%lu\n",
  261. count, timeout, freq);
  262. /* if the count is bigger than the watchdog register,
  263. then work out what we need to do (and if) we can
  264. actually make this value
  265. */
  266. if (count >= 0x10000) {
  267. divisor = DIV_ROUND_UP(count, 0xffff);
  268. if (divisor > 0x100) {
  269. dev_err(wdt->dev, "timeout %d too big\n", timeout);
  270. return -EINVAL;
  271. }
  272. }
  273. dev_dbg(wdt->dev, "Heartbeat: timeout=%d, divisor=%d, count=%d (%08x)\n",
  274. timeout, divisor, count, DIV_ROUND_UP(count, divisor));
  275. count = DIV_ROUND_UP(count, divisor);
  276. wdt->count = count;
  277. /* update the pre-scaler */
  278. wtcon = readl(wdt->reg_base + S3C2410_WTCON);
  279. wtcon &= ~S3C2410_WTCON_PRESCALE_MASK;
  280. wtcon |= S3C2410_WTCON_PRESCALE(divisor-1);
  281. writel(count, wdt->reg_base + S3C2410_WTDAT);
  282. writel(wtcon, wdt->reg_base + S3C2410_WTCON);
  283. wdd->timeout = (count * divisor) / freq;
  284. return 0;
  285. }
  286. static int s3c2410wdt_restart(struct watchdog_device *wdd, unsigned long action,
  287. void *data)
  288. {
  289. struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
  290. void __iomem *wdt_base = wdt->reg_base;
  291. /* disable watchdog, to be safe */
  292. writel(0, wdt_base + S3C2410_WTCON);
  293. /* put initial values into count and data */
  294. writel(0x80, wdt_base + S3C2410_WTCNT);
  295. writel(0x80, wdt_base + S3C2410_WTDAT);
  296. /* set the watchdog to go and reset... */
  297. writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV16 |
  298. S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x20),
  299. wdt_base + S3C2410_WTCON);
  300. /* wait for reset to assert... */
  301. mdelay(500);
  302. return 0;
  303. }
  304. #define OPTIONS (WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE)
  305. static const struct watchdog_info s3c2410_wdt_ident = {
  306. .options = OPTIONS,
  307. .firmware_version = 0,
  308. .identity = "S3C2410 Watchdog",
  309. };
  310. static const struct watchdog_ops s3c2410wdt_ops = {
  311. .owner = THIS_MODULE,
  312. .start = s3c2410wdt_start,
  313. .stop = s3c2410wdt_stop,
  314. .ping = s3c2410wdt_keepalive,
  315. .set_timeout = s3c2410wdt_set_heartbeat,
  316. .restart = s3c2410wdt_restart,
  317. };
  318. static const struct watchdog_device s3c2410_wdd = {
  319. .info = &s3c2410_wdt_ident,
  320. .ops = &s3c2410wdt_ops,
  321. .timeout = S3C2410_WATCHDOG_DEFAULT_TIME,
  322. };
  323. /* interrupt handler code */
  324. static irqreturn_t s3c2410wdt_irq(int irqno, void *param)
  325. {
  326. struct s3c2410_wdt *wdt = platform_get_drvdata(param);
  327. dev_info(wdt->dev, "watchdog timer expired (irq)\n");
  328. s3c2410wdt_keepalive(&wdt->wdt_device);
  329. if (wdt->drv_data->quirks & QUIRK_HAS_WTCLRINT_REG)
  330. writel(0x1, wdt->reg_base + S3C2410_WTCLRINT);
  331. return IRQ_HANDLED;
  332. }
  333. #ifdef CONFIG_ARM_S3C24XX_CPUFREQ
  334. static int s3c2410wdt_cpufreq_transition(struct notifier_block *nb,
  335. unsigned long val, void *data)
  336. {
  337. int ret;
  338. struct s3c2410_wdt *wdt = freq_to_wdt(nb);
  339. if (!s3c2410wdt_is_running(wdt))
  340. goto done;
  341. if (val == CPUFREQ_PRECHANGE) {
  342. /* To ensure that over the change we don't cause the
  343. * watchdog to trigger, we perform an keep-alive if
  344. * the watchdog is running.
  345. */
  346. s3c2410wdt_keepalive(&wdt->wdt_device);
  347. } else if (val == CPUFREQ_POSTCHANGE) {
  348. s3c2410wdt_stop(&wdt->wdt_device);
  349. ret = s3c2410wdt_set_heartbeat(&wdt->wdt_device,
  350. wdt->wdt_device.timeout);
  351. if (ret >= 0)
  352. s3c2410wdt_start(&wdt->wdt_device);
  353. else
  354. goto err;
  355. }
  356. done:
  357. return 0;
  358. err:
  359. dev_err(wdt->dev, "cannot set new value for timeout %d\n",
  360. wdt->wdt_device.timeout);
  361. return ret;
  362. }
  363. static inline int s3c2410wdt_cpufreq_register(struct s3c2410_wdt *wdt)
  364. {
  365. wdt->freq_transition.notifier_call = s3c2410wdt_cpufreq_transition;
  366. return cpufreq_register_notifier(&wdt->freq_transition,
  367. CPUFREQ_TRANSITION_NOTIFIER);
  368. }
  369. static inline void s3c2410wdt_cpufreq_deregister(struct s3c2410_wdt *wdt)
  370. {
  371. wdt->freq_transition.notifier_call = s3c2410wdt_cpufreq_transition;
  372. cpufreq_unregister_notifier(&wdt->freq_transition,
  373. CPUFREQ_TRANSITION_NOTIFIER);
  374. }
  375. #else
  376. static inline int s3c2410wdt_cpufreq_register(struct s3c2410_wdt *wdt)
  377. {
  378. return 0;
  379. }
  380. static inline void s3c2410wdt_cpufreq_deregister(struct s3c2410_wdt *wdt)
  381. {
  382. }
  383. #endif
  384. static inline unsigned int s3c2410wdt_get_bootstatus(struct s3c2410_wdt *wdt)
  385. {
  386. unsigned int rst_stat;
  387. int ret;
  388. if (!(wdt->drv_data->quirks & QUIRK_HAS_RST_STAT))
  389. return 0;
  390. ret = regmap_read(wdt->pmureg, wdt->drv_data->rst_stat_reg, &rst_stat);
  391. if (ret)
  392. dev_warn(wdt->dev, "Couldn't get RST_STAT register\n");
  393. else if (rst_stat & BIT(wdt->drv_data->rst_stat_bit))
  394. return WDIOF_CARDRESET;
  395. return 0;
  396. }
  397. static inline const struct s3c2410_wdt_variant *
  398. s3c2410_get_wdt_drv_data(struct platform_device *pdev)
  399. {
  400. const struct s3c2410_wdt_variant *variant;
  401. variant = of_device_get_match_data(&pdev->dev);
  402. if (!variant) {
  403. /* Device matched by platform_device_id */
  404. variant = (struct s3c2410_wdt_variant *)
  405. platform_get_device_id(pdev)->driver_data;
  406. }
  407. return variant;
  408. }
  409. static int s3c2410wdt_probe(struct platform_device *pdev)
  410. {
  411. struct device *dev = &pdev->dev;
  412. struct s3c2410_wdt *wdt;
  413. struct resource *wdt_irq;
  414. unsigned int wtcon;
  415. int started = 0;
  416. int ret;
  417. wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
  418. if (!wdt)
  419. return -ENOMEM;
  420. wdt->dev = dev;
  421. spin_lock_init(&wdt->lock);
  422. wdt->wdt_device = s3c2410_wdd;
  423. wdt->drv_data = s3c2410_get_wdt_drv_data(pdev);
  424. if (wdt->drv_data->quirks & QUIRKS_HAVE_PMUREG) {
  425. wdt->pmureg = syscon_regmap_lookup_by_phandle(dev->of_node,
  426. "samsung,syscon-phandle");
  427. if (IS_ERR(wdt->pmureg)) {
  428. dev_err(dev, "syscon regmap lookup failed.\n");
  429. return PTR_ERR(wdt->pmureg);
  430. }
  431. }
  432. wdt_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  433. if (wdt_irq == NULL) {
  434. dev_err(dev, "no irq resource specified\n");
  435. ret = -ENOENT;
  436. goto err;
  437. }
  438. /* get the memory region for the watchdog timer */
  439. wdt->reg_base = devm_platform_ioremap_resource(pdev, 0);
  440. if (IS_ERR(wdt->reg_base)) {
  441. ret = PTR_ERR(wdt->reg_base);
  442. goto err;
  443. }
  444. wdt->clock = devm_clk_get(dev, "watchdog");
  445. if (IS_ERR(wdt->clock)) {
  446. dev_err(dev, "failed to find watchdog clock source\n");
  447. ret = PTR_ERR(wdt->clock);
  448. goto err;
  449. }
  450. ret = clk_prepare_enable(wdt->clock);
  451. if (ret < 0) {
  452. dev_err(dev, "failed to enable clock\n");
  453. return ret;
  454. }
  455. wdt->wdt_device.min_timeout = 1;
  456. wdt->wdt_device.max_timeout = s3c2410wdt_max_timeout(wdt->clock);
  457. ret = s3c2410wdt_cpufreq_register(wdt);
  458. if (ret < 0) {
  459. dev_err(dev, "failed to register cpufreq\n");
  460. goto err_clk;
  461. }
  462. watchdog_set_drvdata(&wdt->wdt_device, wdt);
  463. /* see if we can actually set the requested timer margin, and if
  464. * not, try the default value */
  465. watchdog_init_timeout(&wdt->wdt_device, tmr_margin, dev);
  466. ret = s3c2410wdt_set_heartbeat(&wdt->wdt_device,
  467. wdt->wdt_device.timeout);
  468. if (ret) {
  469. started = s3c2410wdt_set_heartbeat(&wdt->wdt_device,
  470. S3C2410_WATCHDOG_DEFAULT_TIME);
  471. if (started == 0)
  472. dev_info(dev,
  473. "tmr_margin value out of range, default %d used\n",
  474. S3C2410_WATCHDOG_DEFAULT_TIME);
  475. else
  476. dev_info(dev, "default timer value is out of range, cannot start\n");
  477. }
  478. ret = devm_request_irq(dev, wdt_irq->start, s3c2410wdt_irq, 0,
  479. pdev->name, pdev);
  480. if (ret != 0) {
  481. dev_err(dev, "failed to install irq (%d)\n", ret);
  482. goto err_cpufreq;
  483. }
  484. watchdog_set_nowayout(&wdt->wdt_device, nowayout);
  485. watchdog_set_restart_priority(&wdt->wdt_device, 128);
  486. wdt->wdt_device.bootstatus = s3c2410wdt_get_bootstatus(wdt);
  487. wdt->wdt_device.parent = dev;
  488. ret = watchdog_register_device(&wdt->wdt_device);
  489. if (ret)
  490. goto err_cpufreq;
  491. ret = s3c2410wdt_mask_and_disable_reset(wdt, false);
  492. if (ret < 0)
  493. goto err_unregister;
  494. if (tmr_atboot && started == 0) {
  495. dev_info(dev, "starting watchdog timer\n");
  496. s3c2410wdt_start(&wdt->wdt_device);
  497. } else if (!tmr_atboot) {
  498. /* if we're not enabling the watchdog, then ensure it is
  499. * disabled if it has been left running from the bootloader
  500. * or other source */
  501. s3c2410wdt_stop(&wdt->wdt_device);
  502. }
  503. platform_set_drvdata(pdev, wdt);
  504. /* print out a statement of readiness */
  505. wtcon = readl(wdt->reg_base + S3C2410_WTCON);
  506. dev_info(dev, "watchdog %sactive, reset %sabled, irq %sabled\n",
  507. (wtcon & S3C2410_WTCON_ENABLE) ? "" : "in",
  508. (wtcon & S3C2410_WTCON_RSTEN) ? "en" : "dis",
  509. (wtcon & S3C2410_WTCON_INTEN) ? "en" : "dis");
  510. return 0;
  511. err_unregister:
  512. watchdog_unregister_device(&wdt->wdt_device);
  513. err_cpufreq:
  514. s3c2410wdt_cpufreq_deregister(wdt);
  515. err_clk:
  516. clk_disable_unprepare(wdt->clock);
  517. err:
  518. return ret;
  519. }
  520. static int s3c2410wdt_remove(struct platform_device *dev)
  521. {
  522. int ret;
  523. struct s3c2410_wdt *wdt = platform_get_drvdata(dev);
  524. ret = s3c2410wdt_mask_and_disable_reset(wdt, true);
  525. if (ret < 0)
  526. return ret;
  527. watchdog_unregister_device(&wdt->wdt_device);
  528. s3c2410wdt_cpufreq_deregister(wdt);
  529. clk_disable_unprepare(wdt->clock);
  530. return 0;
  531. }
  532. static void s3c2410wdt_shutdown(struct platform_device *dev)
  533. {
  534. struct s3c2410_wdt *wdt = platform_get_drvdata(dev);
  535. s3c2410wdt_mask_and_disable_reset(wdt, true);
  536. s3c2410wdt_stop(&wdt->wdt_device);
  537. }
  538. #ifdef CONFIG_PM_SLEEP
  539. static int s3c2410wdt_suspend(struct device *dev)
  540. {
  541. int ret;
  542. struct s3c2410_wdt *wdt = dev_get_drvdata(dev);
  543. /* Save watchdog state, and turn it off. */
  544. wdt->wtcon_save = readl(wdt->reg_base + S3C2410_WTCON);
  545. wdt->wtdat_save = readl(wdt->reg_base + S3C2410_WTDAT);
  546. ret = s3c2410wdt_mask_and_disable_reset(wdt, true);
  547. if (ret < 0)
  548. return ret;
  549. /* Note that WTCNT doesn't need to be saved. */
  550. s3c2410wdt_stop(&wdt->wdt_device);
  551. return 0;
  552. }
  553. static int s3c2410wdt_resume(struct device *dev)
  554. {
  555. int ret;
  556. struct s3c2410_wdt *wdt = dev_get_drvdata(dev);
  557. /* Restore watchdog state. */
  558. writel(wdt->wtdat_save, wdt->reg_base + S3C2410_WTDAT);
  559. writel(wdt->wtdat_save, wdt->reg_base + S3C2410_WTCNT);/* Reset count */
  560. writel(wdt->wtcon_save, wdt->reg_base + S3C2410_WTCON);
  561. ret = s3c2410wdt_mask_and_disable_reset(wdt, false);
  562. if (ret < 0)
  563. return ret;
  564. dev_info(dev, "watchdog %sabled\n",
  565. (wdt->wtcon_save & S3C2410_WTCON_ENABLE) ? "en" : "dis");
  566. return 0;
  567. }
  568. #endif
  569. static SIMPLE_DEV_PM_OPS(s3c2410wdt_pm_ops, s3c2410wdt_suspend,
  570. s3c2410wdt_resume);
  571. static struct platform_driver s3c2410wdt_driver = {
  572. .probe = s3c2410wdt_probe,
  573. .remove = s3c2410wdt_remove,
  574. .shutdown = s3c2410wdt_shutdown,
  575. .id_table = s3c2410_wdt_ids,
  576. .driver = {
  577. .name = "s3c2410-wdt",
  578. .pm = &s3c2410wdt_pm_ops,
  579. .of_match_table = of_match_ptr(s3c2410_wdt_match),
  580. },
  581. };
  582. module_platform_driver(s3c2410wdt_driver);
  583. MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, Dimitry Andric <dimitry.andric@tomtom.com>");
  584. MODULE_DESCRIPTION("S3C2410 Watchdog Device Driver");
  585. MODULE_LICENSE("GPL");