rza_wdt.c 6.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Renesas RZ/A Series WDT Driver
  4. *
  5. * Copyright (C) 2017 Renesas Electronics America, Inc.
  6. * Copyright (C) 2017 Chris Brandt
  7. */
  8. #include <linux/bitops.h>
  9. #include <linux/clk.h>
  10. #include <linux/delay.h>
  11. #include <linux/module.h>
  12. #include <linux/of_address.h>
  13. #include <linux/of_device.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/watchdog.h>
  16. #define DEFAULT_TIMEOUT 30
  17. /* Watchdog Timer Registers */
  18. #define WTCSR 0
  19. #define WTCSR_MAGIC 0xA500
  20. #define WTSCR_WT BIT(6)
  21. #define WTSCR_TME BIT(5)
  22. #define WTSCR_CKS(i) (i)
  23. #define WTCNT 2
  24. #define WTCNT_MAGIC 0x5A00
  25. #define WRCSR 4
  26. #define WRCSR_MAGIC 0x5A00
  27. #define WRCSR_RSTE BIT(6)
  28. #define WRCSR_CLEAR_WOVF 0xA500 /* special value */
  29. /* The maximum CKS register setting value to get the longest timeout */
  30. #define CKS_3BIT 0x7
  31. #define CKS_4BIT 0xF
  32. #define DIVIDER_3BIT 16384 /* Clock divider when CKS = 0x7 */
  33. #define DIVIDER_4BIT 4194304 /* Clock divider when CKS = 0xF */
  34. struct rza_wdt {
  35. struct watchdog_device wdev;
  36. void __iomem *base;
  37. struct clk *clk;
  38. u8 count;
  39. u8 cks;
  40. };
  41. static void rza_wdt_calc_timeout(struct rza_wdt *priv, int timeout)
  42. {
  43. unsigned long rate = clk_get_rate(priv->clk);
  44. unsigned int ticks;
  45. if (priv->cks == CKS_4BIT) {
  46. ticks = DIV_ROUND_UP(timeout * rate, DIVIDER_4BIT);
  47. /*
  48. * Since max_timeout was set in probe, we know that the timeout
  49. * value passed will never calculate to a tick value greater
  50. * than 256.
  51. */
  52. priv->count = 256 - ticks;
  53. } else {
  54. /* Start timer with longest timeout */
  55. priv->count = 0;
  56. }
  57. pr_debug("%s: timeout set to %u (WTCNT=%d)\n", __func__,
  58. timeout, priv->count);
  59. }
  60. static int rza_wdt_start(struct watchdog_device *wdev)
  61. {
  62. struct rza_wdt *priv = watchdog_get_drvdata(wdev);
  63. /* Stop timer */
  64. writew(WTCSR_MAGIC | 0, priv->base + WTCSR);
  65. /* Must dummy read WRCSR:WOVF at least once before clearing */
  66. readb(priv->base + WRCSR);
  67. writew(WRCSR_CLEAR_WOVF, priv->base + WRCSR);
  68. rza_wdt_calc_timeout(priv, wdev->timeout);
  69. writew(WRCSR_MAGIC | WRCSR_RSTE, priv->base + WRCSR);
  70. writew(WTCNT_MAGIC | priv->count, priv->base + WTCNT);
  71. writew(WTCSR_MAGIC | WTSCR_WT | WTSCR_TME |
  72. WTSCR_CKS(priv->cks), priv->base + WTCSR);
  73. return 0;
  74. }
  75. static int rza_wdt_stop(struct watchdog_device *wdev)
  76. {
  77. struct rza_wdt *priv = watchdog_get_drvdata(wdev);
  78. writew(WTCSR_MAGIC | 0, priv->base + WTCSR);
  79. return 0;
  80. }
  81. static int rza_wdt_ping(struct watchdog_device *wdev)
  82. {
  83. struct rza_wdt *priv = watchdog_get_drvdata(wdev);
  84. writew(WTCNT_MAGIC | priv->count, priv->base + WTCNT);
  85. pr_debug("%s: timeout = %u\n", __func__, wdev->timeout);
  86. return 0;
  87. }
  88. static int rza_set_timeout(struct watchdog_device *wdev, unsigned int timeout)
  89. {
  90. wdev->timeout = timeout;
  91. rza_wdt_start(wdev);
  92. return 0;
  93. }
  94. static int rza_wdt_restart(struct watchdog_device *wdev, unsigned long action,
  95. void *data)
  96. {
  97. struct rza_wdt *priv = watchdog_get_drvdata(wdev);
  98. /* Stop timer */
  99. writew(WTCSR_MAGIC | 0, priv->base + WTCSR);
  100. /* Must dummy read WRCSR:WOVF at least once before clearing */
  101. readb(priv->base + WRCSR);
  102. writew(WRCSR_CLEAR_WOVF, priv->base + WRCSR);
  103. /*
  104. * Start timer with fastest clock source and only 1 clock left before
  105. * overflow with reset option enabled.
  106. */
  107. writew(WRCSR_MAGIC | WRCSR_RSTE, priv->base + WRCSR);
  108. writew(WTCNT_MAGIC | 255, priv->base + WTCNT);
  109. writew(WTCSR_MAGIC | WTSCR_WT | WTSCR_TME, priv->base + WTCSR);
  110. /*
  111. * Actually make sure the above sequence hits hardware before sleeping.
  112. */
  113. wmb();
  114. /* Wait for WDT overflow (reset) */
  115. udelay(20);
  116. return 0;
  117. }
  118. static const struct watchdog_info rza_wdt_ident = {
  119. .options = WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT,
  120. .identity = "Renesas RZ/A WDT Watchdog",
  121. };
  122. static const struct watchdog_ops rza_wdt_ops = {
  123. .owner = THIS_MODULE,
  124. .start = rza_wdt_start,
  125. .stop = rza_wdt_stop,
  126. .ping = rza_wdt_ping,
  127. .set_timeout = rza_set_timeout,
  128. .restart = rza_wdt_restart,
  129. };
  130. static int rza_wdt_probe(struct platform_device *pdev)
  131. {
  132. struct device *dev = &pdev->dev;
  133. struct rza_wdt *priv;
  134. unsigned long rate;
  135. int ret;
  136. priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  137. if (!priv)
  138. return -ENOMEM;
  139. priv->base = devm_platform_ioremap_resource(pdev, 0);
  140. if (IS_ERR(priv->base))
  141. return PTR_ERR(priv->base);
  142. priv->clk = devm_clk_get(dev, NULL);
  143. if (IS_ERR(priv->clk))
  144. return PTR_ERR(priv->clk);
  145. rate = clk_get_rate(priv->clk);
  146. if (rate < 16384) {
  147. dev_err(dev, "invalid clock rate (%ld)\n", rate);
  148. return -ENOENT;
  149. }
  150. priv->wdev.info = &rza_wdt_ident,
  151. priv->wdev.ops = &rza_wdt_ops,
  152. priv->wdev.parent = dev;
  153. priv->cks = (u8)(uintptr_t) of_device_get_match_data(dev);
  154. if (priv->cks == CKS_4BIT) {
  155. /* Assume slowest clock rate possible (CKS=0xF) */
  156. priv->wdev.max_timeout = (DIVIDER_4BIT * U8_MAX) / rate;
  157. } else if (priv->cks == CKS_3BIT) {
  158. /* Assume slowest clock rate possible (CKS=7) */
  159. rate /= DIVIDER_3BIT;
  160. /*
  161. * Since the max possible timeout of our 8-bit count
  162. * register is less than a second, we must use
  163. * max_hw_heartbeat_ms.
  164. */
  165. priv->wdev.max_hw_heartbeat_ms = (1000 * U8_MAX) / rate;
  166. dev_dbg(dev, "max hw timeout of %dms\n",
  167. priv->wdev.max_hw_heartbeat_ms);
  168. }
  169. priv->wdev.min_timeout = 1;
  170. priv->wdev.timeout = DEFAULT_TIMEOUT;
  171. watchdog_init_timeout(&priv->wdev, 0, dev);
  172. watchdog_set_drvdata(&priv->wdev, priv);
  173. ret = devm_watchdog_register_device(dev, &priv->wdev);
  174. if (ret)
  175. dev_err(dev, "Cannot register watchdog device\n");
  176. return ret;
  177. }
  178. static const struct of_device_id rza_wdt_of_match[] = {
  179. { .compatible = "renesas,r7s9210-wdt", .data = (void *)CKS_4BIT, },
  180. { .compatible = "renesas,rza-wdt", .data = (void *)CKS_3BIT, },
  181. { /* sentinel */ }
  182. };
  183. MODULE_DEVICE_TABLE(of, rza_wdt_of_match);
  184. static struct platform_driver rza_wdt_driver = {
  185. .probe = rza_wdt_probe,
  186. .driver = {
  187. .name = "rza_wdt",
  188. .of_match_table = rza_wdt_of_match,
  189. },
  190. };
  191. module_platform_driver(rza_wdt_driver);
  192. MODULE_DESCRIPTION("Renesas RZ/A WDT Driver");
  193. MODULE_AUTHOR("Chris Brandt <chris.brandt@renesas.com>");
  194. MODULE_LICENSE("GPL v2");