renesas_wdt.c 7.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Watchdog driver for Renesas WDT watchdog
  4. *
  5. * Copyright (C) 2015-17 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
  6. * Copyright (C) 2015-17 Renesas Electronics Corporation
  7. */
  8. #include <linux/bitops.h>
  9. #include <linux/clk.h>
  10. #include <linux/delay.h>
  11. #include <linux/io.h>
  12. #include <linux/kernel.h>
  13. #include <linux/module.h>
  14. #include <linux/of.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/pm_runtime.h>
  17. #include <linux/smp.h>
  18. #include <linux/sys_soc.h>
  19. #include <linux/watchdog.h>
  20. #define RWTCNT 0
  21. #define RWTCSRA 4
  22. #define RWTCSRA_WOVF BIT(4)
  23. #define RWTCSRA_WRFLG BIT(5)
  24. #define RWTCSRA_TME BIT(7)
  25. #define RWTCSRB 8
  26. #define RWDT_DEFAULT_TIMEOUT 60U
  27. /*
  28. * In probe, clk_rate is checked to be not more than 16 bit * biggest clock
  29. * divider (12 bits). d is only a factor to fully utilize the WDT counter and
  30. * will not exceed its 16 bits. Thus, no overflow, we stay below 32 bits.
  31. */
  32. #define MUL_BY_CLKS_PER_SEC(p, d) \
  33. DIV_ROUND_UP((d) * (p)->clk_rate, clk_divs[(p)->cks])
  34. /* d is 16 bit, clk_divs 12 bit -> no 32 bit overflow */
  35. #define DIV_BY_CLKS_PER_SEC(p, d) ((d) * clk_divs[(p)->cks] / (p)->clk_rate)
  36. static const unsigned int clk_divs[] = { 1, 4, 16, 32, 64, 128, 1024, 4096 };
  37. static bool nowayout = WATCHDOG_NOWAYOUT;
  38. module_param(nowayout, bool, 0);
  39. MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
  40. __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  41. struct rwdt_priv {
  42. void __iomem *base;
  43. struct watchdog_device wdev;
  44. unsigned long clk_rate;
  45. u8 cks;
  46. };
  47. static void rwdt_write(struct rwdt_priv *priv, u32 val, unsigned int reg)
  48. {
  49. if (reg == RWTCNT)
  50. val |= 0x5a5a0000;
  51. else
  52. val |= 0xa5a5a500;
  53. writel_relaxed(val, priv->base + reg);
  54. }
  55. static int rwdt_init_timeout(struct watchdog_device *wdev)
  56. {
  57. struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
  58. rwdt_write(priv, 65536 - MUL_BY_CLKS_PER_SEC(priv, wdev->timeout), RWTCNT);
  59. return 0;
  60. }
  61. static void rwdt_wait_cycles(struct rwdt_priv *priv, unsigned int cycles)
  62. {
  63. unsigned int delay;
  64. delay = DIV_ROUND_UP(cycles * 1000000, priv->clk_rate);
  65. usleep_range(delay, 2 * delay);
  66. }
  67. static int rwdt_start(struct watchdog_device *wdev)
  68. {
  69. struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
  70. u8 val;
  71. pm_runtime_get_sync(wdev->parent);
  72. /* Stop the timer before we modify any register */
  73. val = readb_relaxed(priv->base + RWTCSRA) & ~RWTCSRA_TME;
  74. rwdt_write(priv, val, RWTCSRA);
  75. /* Delay 2 cycles before setting watchdog counter */
  76. rwdt_wait_cycles(priv, 2);
  77. rwdt_init_timeout(wdev);
  78. rwdt_write(priv, priv->cks, RWTCSRA);
  79. rwdt_write(priv, 0, RWTCSRB);
  80. while (readb_relaxed(priv->base + RWTCSRA) & RWTCSRA_WRFLG)
  81. cpu_relax();
  82. rwdt_write(priv, priv->cks | RWTCSRA_TME, RWTCSRA);
  83. return 0;
  84. }
  85. static int rwdt_stop(struct watchdog_device *wdev)
  86. {
  87. struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
  88. rwdt_write(priv, priv->cks, RWTCSRA);
  89. /* Delay 3 cycles before disabling module clock */
  90. rwdt_wait_cycles(priv, 3);
  91. pm_runtime_put(wdev->parent);
  92. return 0;
  93. }
  94. static unsigned int rwdt_get_timeleft(struct watchdog_device *wdev)
  95. {
  96. struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
  97. u16 val = readw_relaxed(priv->base + RWTCNT);
  98. return DIV_BY_CLKS_PER_SEC(priv, 65536 - val);
  99. }
  100. static int rwdt_restart(struct watchdog_device *wdev, unsigned long action,
  101. void *data)
  102. {
  103. struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
  104. rwdt_start(wdev);
  105. rwdt_write(priv, 0xffff, RWTCNT);
  106. return 0;
  107. }
  108. static const struct watchdog_info rwdt_ident = {
  109. .options = WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT |
  110. WDIOF_CARDRESET,
  111. .identity = "Renesas WDT Watchdog",
  112. };
  113. static const struct watchdog_ops rwdt_ops = {
  114. .owner = THIS_MODULE,
  115. .start = rwdt_start,
  116. .stop = rwdt_stop,
  117. .ping = rwdt_init_timeout,
  118. .get_timeleft = rwdt_get_timeleft,
  119. .restart = rwdt_restart,
  120. };
  121. #if defined(CONFIG_ARCH_RCAR_GEN2) && defined(CONFIG_SMP)
  122. /*
  123. * Watchdog-reset integration is broken on early revisions of R-Car Gen2 SoCs
  124. */
  125. static const struct soc_device_attribute rwdt_quirks_match[] = {
  126. {
  127. .soc_id = "r8a7790",
  128. .revision = "ES1.*",
  129. .data = (void *)1, /* needs single CPU */
  130. }, {
  131. .soc_id = "r8a7791",
  132. .revision = "ES1.*",
  133. .data = (void *)1, /* needs single CPU */
  134. }, {
  135. .soc_id = "r8a7792",
  136. .data = (void *)0, /* needs SMP disabled */
  137. },
  138. { /* sentinel */ }
  139. };
  140. static bool rwdt_blacklisted(struct device *dev)
  141. {
  142. const struct soc_device_attribute *attr;
  143. attr = soc_device_match(rwdt_quirks_match);
  144. if (attr && setup_max_cpus > (uintptr_t)attr->data) {
  145. dev_info(dev, "Watchdog blacklisted on %s %s\n", attr->soc_id,
  146. attr->revision);
  147. return true;
  148. }
  149. return false;
  150. }
  151. #else /* !CONFIG_ARCH_RCAR_GEN2 || !CONFIG_SMP */
  152. static inline bool rwdt_blacklisted(struct device *dev) { return false; }
  153. #endif /* !CONFIG_ARCH_RCAR_GEN2 || !CONFIG_SMP */
  154. static int rwdt_probe(struct platform_device *pdev)
  155. {
  156. struct device *dev = &pdev->dev;
  157. struct rwdt_priv *priv;
  158. struct clk *clk;
  159. unsigned long clks_per_sec;
  160. int ret, i;
  161. u8 csra;
  162. if (rwdt_blacklisted(dev))
  163. return -ENODEV;
  164. priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  165. if (!priv)
  166. return -ENOMEM;
  167. priv->base = devm_platform_ioremap_resource(pdev, 0);
  168. if (IS_ERR(priv->base))
  169. return PTR_ERR(priv->base);
  170. clk = devm_clk_get(dev, NULL);
  171. if (IS_ERR(clk))
  172. return PTR_ERR(clk);
  173. pm_runtime_enable(dev);
  174. pm_runtime_get_sync(dev);
  175. priv->clk_rate = clk_get_rate(clk);
  176. csra = readb_relaxed(priv->base + RWTCSRA);
  177. priv->wdev.bootstatus = csra & RWTCSRA_WOVF ? WDIOF_CARDRESET : 0;
  178. pm_runtime_put(dev);
  179. if (!priv->clk_rate) {
  180. ret = -ENOENT;
  181. goto out_pm_disable;
  182. }
  183. for (i = ARRAY_SIZE(clk_divs) - 1; i >= 0; i--) {
  184. clks_per_sec = priv->clk_rate / clk_divs[i];
  185. if (clks_per_sec && clks_per_sec < 65536) {
  186. priv->cks = i;
  187. break;
  188. }
  189. }
  190. if (i < 0) {
  191. dev_err(dev, "Can't find suitable clock divider\n");
  192. ret = -ERANGE;
  193. goto out_pm_disable;
  194. }
  195. priv->wdev.info = &rwdt_ident;
  196. priv->wdev.ops = &rwdt_ops;
  197. priv->wdev.parent = dev;
  198. priv->wdev.min_timeout = 1;
  199. priv->wdev.max_timeout = DIV_BY_CLKS_PER_SEC(priv, 65536);
  200. priv->wdev.timeout = min(priv->wdev.max_timeout, RWDT_DEFAULT_TIMEOUT);
  201. platform_set_drvdata(pdev, priv);
  202. watchdog_set_drvdata(&priv->wdev, priv);
  203. watchdog_set_nowayout(&priv->wdev, nowayout);
  204. watchdog_set_restart_priority(&priv->wdev, 0);
  205. watchdog_stop_on_unregister(&priv->wdev);
  206. /* This overrides the default timeout only if DT configuration was found */
  207. watchdog_init_timeout(&priv->wdev, 0, dev);
  208. /* Check if FW enabled the watchdog */
  209. if (csra & RWTCSRA_TME) {
  210. /* Ensure properly initialized dividers */
  211. rwdt_start(&priv->wdev);
  212. set_bit(WDOG_HW_RUNNING, &priv->wdev.status);
  213. }
  214. ret = watchdog_register_device(&priv->wdev);
  215. if (ret < 0)
  216. goto out_pm_disable;
  217. return 0;
  218. out_pm_disable:
  219. pm_runtime_disable(dev);
  220. return ret;
  221. }
  222. static int rwdt_remove(struct platform_device *pdev)
  223. {
  224. struct rwdt_priv *priv = platform_get_drvdata(pdev);
  225. watchdog_unregister_device(&priv->wdev);
  226. pm_runtime_disable(&pdev->dev);
  227. return 0;
  228. }
  229. static int __maybe_unused rwdt_suspend(struct device *dev)
  230. {
  231. struct rwdt_priv *priv = dev_get_drvdata(dev);
  232. if (watchdog_active(&priv->wdev))
  233. rwdt_stop(&priv->wdev);
  234. return 0;
  235. }
  236. static int __maybe_unused rwdt_resume(struct device *dev)
  237. {
  238. struct rwdt_priv *priv = dev_get_drvdata(dev);
  239. if (watchdog_active(&priv->wdev))
  240. rwdt_start(&priv->wdev);
  241. return 0;
  242. }
  243. static SIMPLE_DEV_PM_OPS(rwdt_pm_ops, rwdt_suspend, rwdt_resume);
  244. static const struct of_device_id rwdt_ids[] = {
  245. { .compatible = "renesas,rcar-gen2-wdt", },
  246. { .compatible = "renesas,rcar-gen3-wdt", },
  247. { /* sentinel */ }
  248. };
  249. MODULE_DEVICE_TABLE(of, rwdt_ids);
  250. static struct platform_driver rwdt_driver = {
  251. .driver = {
  252. .name = "renesas_wdt",
  253. .of_match_table = rwdt_ids,
  254. .pm = &rwdt_pm_ops,
  255. },
  256. .probe = rwdt_probe,
  257. .remove = rwdt_remove,
  258. };
  259. module_platform_driver(rwdt_driver);
  260. MODULE_DESCRIPTION("Renesas WDT Watchdog Driver");
  261. MODULE_LICENSE("GPL v2");
  262. MODULE_AUTHOR("Wolfram Sang <wsa@sang-engineering.com>");