qcom-wdt.c 7.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /* Copyright (c) 2014, The Linux Foundation. All rights reserved.
  3. */
  4. #include <linux/bits.h>
  5. #include <linux/clk.h>
  6. #include <linux/delay.h>
  7. #include <linux/interrupt.h>
  8. #include <linux/io.h>
  9. #include <linux/kernel.h>
  10. #include <linux/module.h>
  11. #include <linux/of.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/watchdog.h>
  14. #include <linux/of_device.h>
  15. enum wdt_reg {
  16. WDT_RST,
  17. WDT_EN,
  18. WDT_STS,
  19. WDT_BARK_TIME,
  20. WDT_BITE_TIME,
  21. };
  22. #define QCOM_WDT_ENABLE BIT(0)
  23. static const u32 reg_offset_data_apcs_tmr[] = {
  24. [WDT_RST] = 0x38,
  25. [WDT_EN] = 0x40,
  26. [WDT_STS] = 0x44,
  27. [WDT_BARK_TIME] = 0x4C,
  28. [WDT_BITE_TIME] = 0x5C,
  29. };
  30. static const u32 reg_offset_data_kpss[] = {
  31. [WDT_RST] = 0x4,
  32. [WDT_EN] = 0x8,
  33. [WDT_STS] = 0xC,
  34. [WDT_BARK_TIME] = 0x10,
  35. [WDT_BITE_TIME] = 0x14,
  36. };
  37. struct qcom_wdt_match_data {
  38. const u32 *offset;
  39. bool pretimeout;
  40. };
  41. struct qcom_wdt {
  42. struct watchdog_device wdd;
  43. unsigned long rate;
  44. void __iomem *base;
  45. const u32 *layout;
  46. };
  47. static void __iomem *wdt_addr(struct qcom_wdt *wdt, enum wdt_reg reg)
  48. {
  49. return wdt->base + wdt->layout[reg];
  50. }
  51. static inline
  52. struct qcom_wdt *to_qcom_wdt(struct watchdog_device *wdd)
  53. {
  54. return container_of(wdd, struct qcom_wdt, wdd);
  55. }
  56. static irqreturn_t qcom_wdt_isr(int irq, void *arg)
  57. {
  58. struct watchdog_device *wdd = arg;
  59. watchdog_notify_pretimeout(wdd);
  60. return IRQ_HANDLED;
  61. }
  62. static int qcom_wdt_start(struct watchdog_device *wdd)
  63. {
  64. struct qcom_wdt *wdt = to_qcom_wdt(wdd);
  65. unsigned int bark = wdd->timeout - wdd->pretimeout;
  66. writel(0, wdt_addr(wdt, WDT_EN));
  67. writel(1, wdt_addr(wdt, WDT_RST));
  68. writel(bark * wdt->rate, wdt_addr(wdt, WDT_BARK_TIME));
  69. writel(wdd->timeout * wdt->rate, wdt_addr(wdt, WDT_BITE_TIME));
  70. writel(QCOM_WDT_ENABLE, wdt_addr(wdt, WDT_EN));
  71. return 0;
  72. }
  73. static int qcom_wdt_stop(struct watchdog_device *wdd)
  74. {
  75. struct qcom_wdt *wdt = to_qcom_wdt(wdd);
  76. writel(0, wdt_addr(wdt, WDT_EN));
  77. return 0;
  78. }
  79. static int qcom_wdt_ping(struct watchdog_device *wdd)
  80. {
  81. struct qcom_wdt *wdt = to_qcom_wdt(wdd);
  82. writel(1, wdt_addr(wdt, WDT_RST));
  83. return 0;
  84. }
  85. static int qcom_wdt_set_timeout(struct watchdog_device *wdd,
  86. unsigned int timeout)
  87. {
  88. wdd->timeout = timeout;
  89. return qcom_wdt_start(wdd);
  90. }
  91. static int qcom_wdt_set_pretimeout(struct watchdog_device *wdd,
  92. unsigned int timeout)
  93. {
  94. wdd->pretimeout = timeout;
  95. return qcom_wdt_start(wdd);
  96. }
  97. static int qcom_wdt_restart(struct watchdog_device *wdd, unsigned long action,
  98. void *data)
  99. {
  100. struct qcom_wdt *wdt = to_qcom_wdt(wdd);
  101. u32 timeout;
  102. /*
  103. * Trigger watchdog bite:
  104. * Setup BITE_TIME to be 128ms, and enable WDT.
  105. */
  106. timeout = 128 * wdt->rate / 1000;
  107. writel(0, wdt_addr(wdt, WDT_EN));
  108. writel(1, wdt_addr(wdt, WDT_RST));
  109. writel(timeout, wdt_addr(wdt, WDT_BARK_TIME));
  110. writel(timeout, wdt_addr(wdt, WDT_BITE_TIME));
  111. writel(QCOM_WDT_ENABLE, wdt_addr(wdt, WDT_EN));
  112. /*
  113. * Actually make sure the above sequence hits hardware before sleeping.
  114. */
  115. wmb();
  116. mdelay(150);
  117. return 0;
  118. }
  119. static const struct watchdog_ops qcom_wdt_ops = {
  120. .start = qcom_wdt_start,
  121. .stop = qcom_wdt_stop,
  122. .ping = qcom_wdt_ping,
  123. .set_timeout = qcom_wdt_set_timeout,
  124. .set_pretimeout = qcom_wdt_set_pretimeout,
  125. .restart = qcom_wdt_restart,
  126. .owner = THIS_MODULE,
  127. };
  128. static const struct watchdog_info qcom_wdt_info = {
  129. .options = WDIOF_KEEPALIVEPING
  130. | WDIOF_MAGICCLOSE
  131. | WDIOF_SETTIMEOUT
  132. | WDIOF_CARDRESET,
  133. .identity = KBUILD_MODNAME,
  134. };
  135. static const struct watchdog_info qcom_wdt_pt_info = {
  136. .options = WDIOF_KEEPALIVEPING
  137. | WDIOF_MAGICCLOSE
  138. | WDIOF_SETTIMEOUT
  139. | WDIOF_PRETIMEOUT
  140. | WDIOF_CARDRESET,
  141. .identity = KBUILD_MODNAME,
  142. };
  143. static void qcom_clk_disable_unprepare(void *data)
  144. {
  145. clk_disable_unprepare(data);
  146. }
  147. static const struct qcom_wdt_match_data match_data_apcs_tmr = {
  148. .offset = reg_offset_data_apcs_tmr,
  149. .pretimeout = false,
  150. };
  151. static const struct qcom_wdt_match_data match_data_kpss = {
  152. .offset = reg_offset_data_kpss,
  153. .pretimeout = true,
  154. };
  155. static int qcom_wdt_probe(struct platform_device *pdev)
  156. {
  157. struct device *dev = &pdev->dev;
  158. struct qcom_wdt *wdt;
  159. struct resource *res;
  160. struct device_node *np = dev->of_node;
  161. const struct qcom_wdt_match_data *data;
  162. u32 percpu_offset;
  163. int irq, ret;
  164. struct clk *clk;
  165. data = of_device_get_match_data(dev);
  166. if (!data) {
  167. dev_err(dev, "Unsupported QCOM WDT module\n");
  168. return -ENODEV;
  169. }
  170. wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
  171. if (!wdt)
  172. return -ENOMEM;
  173. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  174. if (!res)
  175. return -ENOMEM;
  176. /* We use CPU0's DGT for the watchdog */
  177. if (of_property_read_u32(np, "cpu-offset", &percpu_offset))
  178. percpu_offset = 0;
  179. res->start += percpu_offset;
  180. res->end += percpu_offset;
  181. wdt->base = devm_ioremap_resource(dev, res);
  182. if (IS_ERR(wdt->base))
  183. return PTR_ERR(wdt->base);
  184. clk = devm_clk_get(dev, NULL);
  185. if (IS_ERR(clk)) {
  186. dev_err(dev, "failed to get input clock\n");
  187. return PTR_ERR(clk);
  188. }
  189. ret = clk_prepare_enable(clk);
  190. if (ret) {
  191. dev_err(dev, "failed to setup clock\n");
  192. return ret;
  193. }
  194. ret = devm_add_action_or_reset(dev, qcom_clk_disable_unprepare, clk);
  195. if (ret)
  196. return ret;
  197. /*
  198. * We use the clock rate to calculate the max timeout, so ensure it's
  199. * not zero to avoid a divide-by-zero exception.
  200. *
  201. * WATCHDOG_CORE assumes units of seconds, if the WDT is clocked such
  202. * that it would bite before a second elapses it's usefulness is
  203. * limited. Bail if this is the case.
  204. */
  205. wdt->rate = clk_get_rate(clk);
  206. if (wdt->rate == 0 ||
  207. wdt->rate > 0x10000000U) {
  208. dev_err(dev, "invalid clock rate\n");
  209. return -EINVAL;
  210. }
  211. /* check if there is pretimeout support */
  212. irq = platform_get_irq_optional(pdev, 0);
  213. if (data->pretimeout && irq > 0) {
  214. ret = devm_request_irq(dev, irq, qcom_wdt_isr, 0,
  215. "wdt_bark", &wdt->wdd);
  216. if (ret)
  217. return ret;
  218. wdt->wdd.info = &qcom_wdt_pt_info;
  219. wdt->wdd.pretimeout = 1;
  220. } else {
  221. if (irq == -EPROBE_DEFER)
  222. return -EPROBE_DEFER;
  223. wdt->wdd.info = &qcom_wdt_info;
  224. }
  225. wdt->wdd.ops = &qcom_wdt_ops;
  226. wdt->wdd.min_timeout = 1;
  227. wdt->wdd.max_timeout = 0x10000000U / wdt->rate;
  228. wdt->wdd.parent = dev;
  229. wdt->layout = data->offset;
  230. if (readl(wdt_addr(wdt, WDT_STS)) & 1)
  231. wdt->wdd.bootstatus = WDIOF_CARDRESET;
  232. /*
  233. * If 'timeout-sec' unspecified in devicetree, assume a 30 second
  234. * default, unless the max timeout is less than 30 seconds, then use
  235. * the max instead.
  236. */
  237. wdt->wdd.timeout = min(wdt->wdd.max_timeout, 30U);
  238. watchdog_init_timeout(&wdt->wdd, 0, dev);
  239. ret = devm_watchdog_register_device(dev, &wdt->wdd);
  240. if (ret)
  241. return ret;
  242. platform_set_drvdata(pdev, wdt);
  243. return 0;
  244. }
  245. static int __maybe_unused qcom_wdt_suspend(struct device *dev)
  246. {
  247. struct qcom_wdt *wdt = dev_get_drvdata(dev);
  248. if (watchdog_active(&wdt->wdd))
  249. qcom_wdt_stop(&wdt->wdd);
  250. return 0;
  251. }
  252. static int __maybe_unused qcom_wdt_resume(struct device *dev)
  253. {
  254. struct qcom_wdt *wdt = dev_get_drvdata(dev);
  255. if (watchdog_active(&wdt->wdd))
  256. qcom_wdt_start(&wdt->wdd);
  257. return 0;
  258. }
  259. static SIMPLE_DEV_PM_OPS(qcom_wdt_pm_ops, qcom_wdt_suspend, qcom_wdt_resume);
  260. static const struct of_device_id qcom_wdt_of_table[] = {
  261. { .compatible = "qcom,kpss-timer", .data = &match_data_apcs_tmr },
  262. { .compatible = "qcom,scss-timer", .data = &match_data_apcs_tmr },
  263. { .compatible = "qcom,kpss-wdt", .data = &match_data_kpss },
  264. { },
  265. };
  266. MODULE_DEVICE_TABLE(of, qcom_wdt_of_table);
  267. static struct platform_driver qcom_watchdog_driver = {
  268. .probe = qcom_wdt_probe,
  269. .driver = {
  270. .name = KBUILD_MODNAME,
  271. .of_match_table = qcom_wdt_of_table,
  272. .pm = &qcom_wdt_pm_ops,
  273. },
  274. };
  275. module_platform_driver(qcom_watchdog_driver);
  276. MODULE_DESCRIPTION("QCOM KPSS Watchdog Driver");
  277. MODULE_LICENSE("GPL v2");