pnx4008_wdt.c 6.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * drivers/char/watchdog/pnx4008_wdt.c
  4. *
  5. * Watchdog driver for PNX4008 board
  6. *
  7. * Authors: Dmitry Chigirev <source@mvista.com>,
  8. * Vitaly Wool <vitalywool@gmail.com>
  9. * Based on sa1100 driver,
  10. * Copyright (C) 2000 Oleg Drokin <green@crimea.edu>
  11. *
  12. * 2005-2006 (c) MontaVista Software, Inc.
  13. *
  14. * (C) 2012 Wolfram Sang, Pengutronix
  15. */
  16. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  17. #include <linux/module.h>
  18. #include <linux/moduleparam.h>
  19. #include <linux/types.h>
  20. #include <linux/kernel.h>
  21. #include <linux/watchdog.h>
  22. #include <linux/platform_device.h>
  23. #include <linux/clk.h>
  24. #include <linux/spinlock.h>
  25. #include <linux/io.h>
  26. #include <linux/slab.h>
  27. #include <linux/err.h>
  28. #include <linux/of.h>
  29. #include <linux/delay.h>
  30. #include <linux/reboot.h>
  31. /* WatchDog Timer - Chapter 23 Page 207 */
  32. #define DEFAULT_HEARTBEAT 19
  33. #define MAX_HEARTBEAT 60
  34. /* Watchdog timer register set definition */
  35. #define WDTIM_INT(p) ((p) + 0x0)
  36. #define WDTIM_CTRL(p) ((p) + 0x4)
  37. #define WDTIM_COUNTER(p) ((p) + 0x8)
  38. #define WDTIM_MCTRL(p) ((p) + 0xC)
  39. #define WDTIM_MATCH0(p) ((p) + 0x10)
  40. #define WDTIM_EMR(p) ((p) + 0x14)
  41. #define WDTIM_PULSE(p) ((p) + 0x18)
  42. #define WDTIM_RES(p) ((p) + 0x1C)
  43. /* WDTIM_INT bit definitions */
  44. #define MATCH_INT 1
  45. /* WDTIM_CTRL bit definitions */
  46. #define COUNT_ENAB 1
  47. #define RESET_COUNT (1 << 1)
  48. #define DEBUG_EN (1 << 2)
  49. /* WDTIM_MCTRL bit definitions */
  50. #define MR0_INT 1
  51. #undef RESET_COUNT0
  52. #define RESET_COUNT0 (1 << 2)
  53. #define STOP_COUNT0 (1 << 2)
  54. #define M_RES1 (1 << 3)
  55. #define M_RES2 (1 << 4)
  56. #define RESFRC1 (1 << 5)
  57. #define RESFRC2 (1 << 6)
  58. /* WDTIM_EMR bit definitions */
  59. #define EXT_MATCH0 1
  60. #define MATCH_OUTPUT_HIGH (2 << 4) /*a MATCH_CTRL setting */
  61. /* WDTIM_RES bit definitions */
  62. #define WDOG_RESET 1 /* read only */
  63. #define WDOG_COUNTER_RATE 13000000 /*the counter clock is 13 MHz fixed */
  64. static bool nowayout = WATCHDOG_NOWAYOUT;
  65. static unsigned int heartbeat;
  66. static DEFINE_SPINLOCK(io_lock);
  67. static void __iomem *wdt_base;
  68. static struct clk *wdt_clk;
  69. static int pnx4008_wdt_start(struct watchdog_device *wdd)
  70. {
  71. spin_lock(&io_lock);
  72. /* stop counter, initiate counter reset */
  73. writel(RESET_COUNT, WDTIM_CTRL(wdt_base));
  74. /*wait for reset to complete. 100% guarantee event */
  75. while (readl(WDTIM_COUNTER(wdt_base)))
  76. cpu_relax();
  77. /* internal and external reset, stop after that */
  78. writel(M_RES2 | STOP_COUNT0 | RESET_COUNT0, WDTIM_MCTRL(wdt_base));
  79. /* configure match output */
  80. writel(MATCH_OUTPUT_HIGH, WDTIM_EMR(wdt_base));
  81. /* clear interrupt, just in case */
  82. writel(MATCH_INT, WDTIM_INT(wdt_base));
  83. /* the longest pulse period 65541/(13*10^6) seconds ~ 5 ms. */
  84. writel(0xFFFF, WDTIM_PULSE(wdt_base));
  85. writel(wdd->timeout * WDOG_COUNTER_RATE, WDTIM_MATCH0(wdt_base));
  86. /*enable counter, stop when debugger active */
  87. writel(COUNT_ENAB | DEBUG_EN, WDTIM_CTRL(wdt_base));
  88. spin_unlock(&io_lock);
  89. return 0;
  90. }
  91. static int pnx4008_wdt_stop(struct watchdog_device *wdd)
  92. {
  93. spin_lock(&io_lock);
  94. writel(0, WDTIM_CTRL(wdt_base)); /*stop counter */
  95. spin_unlock(&io_lock);
  96. return 0;
  97. }
  98. static int pnx4008_wdt_set_timeout(struct watchdog_device *wdd,
  99. unsigned int new_timeout)
  100. {
  101. wdd->timeout = new_timeout;
  102. return 0;
  103. }
  104. static int pnx4008_restart_handler(struct watchdog_device *wdd,
  105. unsigned long mode, void *cmd)
  106. {
  107. const char *boot_cmd = cmd;
  108. /*
  109. * Verify if a "cmd" passed from the userspace program rebooting
  110. * the system; if available, handle it.
  111. * - For details, see the 'reboot' syscall in kernel/reboot.c
  112. * - If the received "cmd" is not supported, use the default mode.
  113. */
  114. if (boot_cmd) {
  115. if (boot_cmd[0] == 'h')
  116. mode = REBOOT_HARD;
  117. else if (boot_cmd[0] == 's')
  118. mode = REBOOT_SOFT;
  119. }
  120. if (mode == REBOOT_SOFT) {
  121. /* Force match output active */
  122. writel(EXT_MATCH0, WDTIM_EMR(wdt_base));
  123. /* Internal reset on match output (RESOUT_N not asserted) */
  124. writel(M_RES1, WDTIM_MCTRL(wdt_base));
  125. } else {
  126. /* Instant assert of RESETOUT_N with pulse length 1mS */
  127. writel(13000, WDTIM_PULSE(wdt_base));
  128. writel(M_RES2 | RESFRC1 | RESFRC2, WDTIM_MCTRL(wdt_base));
  129. }
  130. /* Wait for watchdog to reset system */
  131. mdelay(1000);
  132. return NOTIFY_DONE;
  133. }
  134. static const struct watchdog_info pnx4008_wdt_ident = {
  135. .options = WDIOF_CARDRESET | WDIOF_MAGICCLOSE |
  136. WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
  137. .identity = "PNX4008 Watchdog",
  138. };
  139. static const struct watchdog_ops pnx4008_wdt_ops = {
  140. .owner = THIS_MODULE,
  141. .start = pnx4008_wdt_start,
  142. .stop = pnx4008_wdt_stop,
  143. .set_timeout = pnx4008_wdt_set_timeout,
  144. .restart = pnx4008_restart_handler,
  145. };
  146. static struct watchdog_device pnx4008_wdd = {
  147. .info = &pnx4008_wdt_ident,
  148. .ops = &pnx4008_wdt_ops,
  149. .timeout = DEFAULT_HEARTBEAT,
  150. .min_timeout = 1,
  151. .max_timeout = MAX_HEARTBEAT,
  152. };
  153. static void pnx4008_clk_disable_unprepare(void *data)
  154. {
  155. clk_disable_unprepare(data);
  156. }
  157. static int pnx4008_wdt_probe(struct platform_device *pdev)
  158. {
  159. struct device *dev = &pdev->dev;
  160. int ret = 0;
  161. watchdog_init_timeout(&pnx4008_wdd, heartbeat, dev);
  162. wdt_base = devm_platform_ioremap_resource(pdev, 0);
  163. if (IS_ERR(wdt_base))
  164. return PTR_ERR(wdt_base);
  165. wdt_clk = devm_clk_get(dev, NULL);
  166. if (IS_ERR(wdt_clk))
  167. return PTR_ERR(wdt_clk);
  168. ret = clk_prepare_enable(wdt_clk);
  169. if (ret)
  170. return ret;
  171. ret = devm_add_action_or_reset(dev, pnx4008_clk_disable_unprepare,
  172. wdt_clk);
  173. if (ret)
  174. return ret;
  175. pnx4008_wdd.bootstatus = (readl(WDTIM_RES(wdt_base)) & WDOG_RESET) ?
  176. WDIOF_CARDRESET : 0;
  177. pnx4008_wdd.parent = dev;
  178. watchdog_set_nowayout(&pnx4008_wdd, nowayout);
  179. watchdog_set_restart_priority(&pnx4008_wdd, 128);
  180. if (readl(WDTIM_CTRL(wdt_base)) & COUNT_ENAB)
  181. set_bit(WDOG_HW_RUNNING, &pnx4008_wdd.status);
  182. ret = devm_watchdog_register_device(dev, &pnx4008_wdd);
  183. if (ret < 0)
  184. return ret;
  185. dev_info(dev, "heartbeat %d sec\n", pnx4008_wdd.timeout);
  186. return 0;
  187. }
  188. #ifdef CONFIG_OF
  189. static const struct of_device_id pnx4008_wdt_match[] = {
  190. { .compatible = "nxp,pnx4008-wdt" },
  191. { }
  192. };
  193. MODULE_DEVICE_TABLE(of, pnx4008_wdt_match);
  194. #endif
  195. static struct platform_driver platform_wdt_driver = {
  196. .driver = {
  197. .name = "pnx4008-watchdog",
  198. .of_match_table = of_match_ptr(pnx4008_wdt_match),
  199. },
  200. .probe = pnx4008_wdt_probe,
  201. };
  202. module_platform_driver(platform_wdt_driver);
  203. MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
  204. MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>");
  205. MODULE_DESCRIPTION("PNX4008 Watchdog Driver");
  206. module_param(heartbeat, uint, 0);
  207. MODULE_PARM_DESC(heartbeat,
  208. "Watchdog heartbeat period in seconds from 1 to "
  209. __MODULE_STRING(MAX_HEARTBEAT) ", default "
  210. __MODULE_STRING(DEFAULT_HEARTBEAT));
  211. module_param(nowayout, bool, 0);
  212. MODULE_PARM_DESC(nowayout,
  213. "Set to 1 to keep watchdog running after device release");
  214. MODULE_LICENSE("GPL");
  215. MODULE_ALIAS("platform:pnx4008-watchdog");