omap_wdt.c 9.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * omap_wdt.c
  4. *
  5. * Watchdog driver for the TI OMAP 16xx & 24xx/34xx 32KHz (non-secure) watchdog
  6. *
  7. * Author: MontaVista Software, Inc.
  8. * <gdavis@mvista.com> or <source@mvista.com>
  9. *
  10. * 2003 (c) MontaVista Software, Inc.
  11. *
  12. * History:
  13. *
  14. * 20030527: George G. Davis <gdavis@mvista.com>
  15. * Initially based on linux-2.4.19-rmk7-pxa1/drivers/char/sa1100_wdt.c
  16. * (c) Copyright 2000 Oleg Drokin <green@crimea.edu>
  17. * Based on SoftDog driver by Alan Cox <alan@lxorguk.ukuu.org.uk>
  18. *
  19. * Copyright (c) 2004 Texas Instruments.
  20. * 1. Modified to support OMAP1610 32-KHz watchdog timer
  21. * 2. Ported to 2.6 kernel
  22. *
  23. * Copyright (c) 2005 David Brownell
  24. * Use the driver model and standard identifiers; handle bigger timeouts.
  25. */
  26. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  27. #include <linux/module.h>
  28. #include <linux/mod_devicetable.h>
  29. #include <linux/types.h>
  30. #include <linux/kernel.h>
  31. #include <linux/mm.h>
  32. #include <linux/watchdog.h>
  33. #include <linux/reboot.h>
  34. #include <linux/err.h>
  35. #include <linux/platform_device.h>
  36. #include <linux/moduleparam.h>
  37. #include <linux/io.h>
  38. #include <linux/slab.h>
  39. #include <linux/pm_runtime.h>
  40. #include <linux/platform_data/omap-wd-timer.h>
  41. #include "omap_wdt.h"
  42. static bool nowayout = WATCHDOG_NOWAYOUT;
  43. module_param(nowayout, bool, 0);
  44. MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
  45. "(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  46. static unsigned timer_margin;
  47. module_param(timer_margin, uint, 0);
  48. MODULE_PARM_DESC(timer_margin, "initial watchdog timeout (in seconds)");
  49. #define to_omap_wdt_dev(_wdog) container_of(_wdog, struct omap_wdt_dev, wdog)
  50. static bool early_enable;
  51. module_param(early_enable, bool, 0);
  52. MODULE_PARM_DESC(early_enable,
  53. "Watchdog is started on module insertion (default=0)");
  54. struct omap_wdt_dev {
  55. struct watchdog_device wdog;
  56. void __iomem *base; /* physical */
  57. struct device *dev;
  58. bool omap_wdt_users;
  59. int wdt_trgr_pattern;
  60. struct mutex lock; /* to avoid races with PM */
  61. };
  62. static void omap_wdt_reload(struct omap_wdt_dev *wdev)
  63. {
  64. void __iomem *base = wdev->base;
  65. /* wait for posted write to complete */
  66. while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x08)
  67. cpu_relax();
  68. wdev->wdt_trgr_pattern = ~wdev->wdt_trgr_pattern;
  69. writel_relaxed(wdev->wdt_trgr_pattern, (base + OMAP_WATCHDOG_TGR));
  70. /* wait for posted write to complete */
  71. while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x08)
  72. cpu_relax();
  73. /* reloaded WCRR from WLDR */
  74. }
  75. static void omap_wdt_enable(struct omap_wdt_dev *wdev)
  76. {
  77. void __iomem *base = wdev->base;
  78. /* Sequence to enable the watchdog */
  79. writel_relaxed(0xBBBB, base + OMAP_WATCHDOG_SPR);
  80. while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x10)
  81. cpu_relax();
  82. writel_relaxed(0x4444, base + OMAP_WATCHDOG_SPR);
  83. while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x10)
  84. cpu_relax();
  85. }
  86. static void omap_wdt_disable(struct omap_wdt_dev *wdev)
  87. {
  88. void __iomem *base = wdev->base;
  89. /* sequence required to disable watchdog */
  90. writel_relaxed(0xAAAA, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */
  91. while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x10)
  92. cpu_relax();
  93. writel_relaxed(0x5555, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */
  94. while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x10)
  95. cpu_relax();
  96. }
  97. static void omap_wdt_set_timer(struct omap_wdt_dev *wdev,
  98. unsigned int timeout)
  99. {
  100. u32 pre_margin = GET_WLDR_VAL(timeout);
  101. void __iomem *base = wdev->base;
  102. /* just count up at 32 KHz */
  103. while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x04)
  104. cpu_relax();
  105. writel_relaxed(pre_margin, base + OMAP_WATCHDOG_LDR);
  106. while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x04)
  107. cpu_relax();
  108. }
  109. static int omap_wdt_start(struct watchdog_device *wdog)
  110. {
  111. struct omap_wdt_dev *wdev = to_omap_wdt_dev(wdog);
  112. void __iomem *base = wdev->base;
  113. mutex_lock(&wdev->lock);
  114. wdev->omap_wdt_users = true;
  115. pm_runtime_get_sync(wdev->dev);
  116. /*
  117. * Make sure the watchdog is disabled. This is unfortunately required
  118. * because writing to various registers with the watchdog running has no
  119. * effect.
  120. */
  121. omap_wdt_disable(wdev);
  122. /* initialize prescaler */
  123. while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x01)
  124. cpu_relax();
  125. writel_relaxed((1 << 5) | (PTV << 2), base + OMAP_WATCHDOG_CNTRL);
  126. while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x01)
  127. cpu_relax();
  128. omap_wdt_set_timer(wdev, wdog->timeout);
  129. omap_wdt_reload(wdev); /* trigger loading of new timeout value */
  130. omap_wdt_enable(wdev);
  131. mutex_unlock(&wdev->lock);
  132. return 0;
  133. }
  134. static int omap_wdt_stop(struct watchdog_device *wdog)
  135. {
  136. struct omap_wdt_dev *wdev = to_omap_wdt_dev(wdog);
  137. mutex_lock(&wdev->lock);
  138. omap_wdt_disable(wdev);
  139. pm_runtime_put_sync(wdev->dev);
  140. wdev->omap_wdt_users = false;
  141. mutex_unlock(&wdev->lock);
  142. return 0;
  143. }
  144. static int omap_wdt_ping(struct watchdog_device *wdog)
  145. {
  146. struct omap_wdt_dev *wdev = to_omap_wdt_dev(wdog);
  147. mutex_lock(&wdev->lock);
  148. omap_wdt_reload(wdev);
  149. mutex_unlock(&wdev->lock);
  150. return 0;
  151. }
  152. static int omap_wdt_set_timeout(struct watchdog_device *wdog,
  153. unsigned int timeout)
  154. {
  155. struct omap_wdt_dev *wdev = to_omap_wdt_dev(wdog);
  156. mutex_lock(&wdev->lock);
  157. omap_wdt_disable(wdev);
  158. omap_wdt_set_timer(wdev, timeout);
  159. omap_wdt_enable(wdev);
  160. omap_wdt_reload(wdev);
  161. wdog->timeout = timeout;
  162. mutex_unlock(&wdev->lock);
  163. return 0;
  164. }
  165. static unsigned int omap_wdt_get_timeleft(struct watchdog_device *wdog)
  166. {
  167. struct omap_wdt_dev *wdev = to_omap_wdt_dev(wdog);
  168. void __iomem *base = wdev->base;
  169. u32 value;
  170. value = readl_relaxed(base + OMAP_WATCHDOG_CRR);
  171. return GET_WCCR_SECS(value);
  172. }
  173. static const struct watchdog_info omap_wdt_info = {
  174. .options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING,
  175. .identity = "OMAP Watchdog",
  176. };
  177. static const struct watchdog_ops omap_wdt_ops = {
  178. .owner = THIS_MODULE,
  179. .start = omap_wdt_start,
  180. .stop = omap_wdt_stop,
  181. .ping = omap_wdt_ping,
  182. .set_timeout = omap_wdt_set_timeout,
  183. .get_timeleft = omap_wdt_get_timeleft,
  184. };
  185. static int omap_wdt_probe(struct platform_device *pdev)
  186. {
  187. struct omap_wd_timer_platform_data *pdata = dev_get_platdata(&pdev->dev);
  188. struct omap_wdt_dev *wdev;
  189. int ret;
  190. wdev = devm_kzalloc(&pdev->dev, sizeof(*wdev), GFP_KERNEL);
  191. if (!wdev)
  192. return -ENOMEM;
  193. wdev->omap_wdt_users = false;
  194. wdev->dev = &pdev->dev;
  195. wdev->wdt_trgr_pattern = 0x1234;
  196. mutex_init(&wdev->lock);
  197. /* reserve static register mappings */
  198. wdev->base = devm_platform_ioremap_resource(pdev, 0);
  199. if (IS_ERR(wdev->base))
  200. return PTR_ERR(wdev->base);
  201. wdev->wdog.info = &omap_wdt_info;
  202. wdev->wdog.ops = &omap_wdt_ops;
  203. wdev->wdog.min_timeout = TIMER_MARGIN_MIN;
  204. wdev->wdog.max_timeout = TIMER_MARGIN_MAX;
  205. wdev->wdog.timeout = TIMER_MARGIN_DEFAULT;
  206. wdev->wdog.parent = &pdev->dev;
  207. watchdog_init_timeout(&wdev->wdog, timer_margin, &pdev->dev);
  208. watchdog_set_nowayout(&wdev->wdog, nowayout);
  209. platform_set_drvdata(pdev, wdev);
  210. pm_runtime_enable(wdev->dev);
  211. pm_runtime_get_sync(wdev->dev);
  212. if (pdata && pdata->read_reset_sources) {
  213. u32 rs = pdata->read_reset_sources();
  214. if (rs & (1 << OMAP_MPU_WD_RST_SRC_ID_SHIFT))
  215. wdev->wdog.bootstatus = WDIOF_CARDRESET;
  216. }
  217. if (early_enable) {
  218. omap_wdt_start(&wdev->wdog);
  219. set_bit(WDOG_HW_RUNNING, &wdev->wdog.status);
  220. } else {
  221. omap_wdt_disable(wdev);
  222. }
  223. ret = watchdog_register_device(&wdev->wdog);
  224. if (ret) {
  225. pm_runtime_put(wdev->dev);
  226. pm_runtime_disable(wdev->dev);
  227. return ret;
  228. }
  229. pr_info("OMAP Watchdog Timer Rev 0x%02x: initial timeout %d sec\n",
  230. readl_relaxed(wdev->base + OMAP_WATCHDOG_REV) & 0xFF,
  231. wdev->wdog.timeout);
  232. if (early_enable)
  233. omap_wdt_start(&wdev->wdog);
  234. pm_runtime_put(wdev->dev);
  235. return 0;
  236. }
  237. static void omap_wdt_shutdown(struct platform_device *pdev)
  238. {
  239. struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
  240. mutex_lock(&wdev->lock);
  241. if (wdev->omap_wdt_users) {
  242. omap_wdt_disable(wdev);
  243. pm_runtime_put_sync(wdev->dev);
  244. }
  245. mutex_unlock(&wdev->lock);
  246. }
  247. static int omap_wdt_remove(struct platform_device *pdev)
  248. {
  249. struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
  250. pm_runtime_disable(wdev->dev);
  251. watchdog_unregister_device(&wdev->wdog);
  252. return 0;
  253. }
  254. #ifdef CONFIG_PM
  255. /* REVISIT ... not clear this is the best way to handle system suspend; and
  256. * it's very inappropriate for selective device suspend (e.g. suspending this
  257. * through sysfs rather than by stopping the watchdog daemon). Also, this
  258. * may not play well enough with NOWAYOUT...
  259. */
  260. static int omap_wdt_suspend(struct platform_device *pdev, pm_message_t state)
  261. {
  262. struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
  263. mutex_lock(&wdev->lock);
  264. if (wdev->omap_wdt_users) {
  265. omap_wdt_disable(wdev);
  266. pm_runtime_put_sync(wdev->dev);
  267. }
  268. mutex_unlock(&wdev->lock);
  269. return 0;
  270. }
  271. static int omap_wdt_resume(struct platform_device *pdev)
  272. {
  273. struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
  274. mutex_lock(&wdev->lock);
  275. if (wdev->omap_wdt_users) {
  276. pm_runtime_get_sync(wdev->dev);
  277. omap_wdt_enable(wdev);
  278. omap_wdt_reload(wdev);
  279. }
  280. mutex_unlock(&wdev->lock);
  281. return 0;
  282. }
  283. #else
  284. #define omap_wdt_suspend NULL
  285. #define omap_wdt_resume NULL
  286. #endif
  287. static const struct of_device_id omap_wdt_of_match[] = {
  288. { .compatible = "ti,omap3-wdt", },
  289. {},
  290. };
  291. MODULE_DEVICE_TABLE(of, omap_wdt_of_match);
  292. static struct platform_driver omap_wdt_driver = {
  293. .probe = omap_wdt_probe,
  294. .remove = omap_wdt_remove,
  295. .shutdown = omap_wdt_shutdown,
  296. .suspend = omap_wdt_suspend,
  297. .resume = omap_wdt_resume,
  298. .driver = {
  299. .name = "omap_wdt",
  300. .of_match_table = omap_wdt_of_match,
  301. },
  302. };
  303. module_platform_driver(omap_wdt_driver);
  304. MODULE_AUTHOR("George G. Davis");
  305. MODULE_LICENSE("GPL");
  306. MODULE_ALIAS("platform:omap_wdt");