of_xilinx_wdt.c 7.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Watchdog Device Driver for Xilinx axi/xps_timebase_wdt
  4. *
  5. * (C) Copyright 2013 - 2014 Xilinx, Inc.
  6. * (C) Copyright 2011 (Alejandro Cabrera <aldaya@gmail.com>)
  7. */
  8. #include <linux/clk.h>
  9. #include <linux/err.h>
  10. #include <linux/module.h>
  11. #include <linux/types.h>
  12. #include <linux/kernel.h>
  13. #include <linux/ioport.h>
  14. #include <linux/watchdog.h>
  15. #include <linux/io.h>
  16. #include <linux/of.h>
  17. #include <linux/of_device.h>
  18. #include <linux/of_address.h>
  19. /* Register offsets for the Wdt device */
  20. #define XWT_TWCSR0_OFFSET 0x0 /* Control/Status Register0 */
  21. #define XWT_TWCSR1_OFFSET 0x4 /* Control/Status Register1 */
  22. #define XWT_TBR_OFFSET 0x8 /* Timebase Register Offset */
  23. /* Control/Status Register Masks */
  24. #define XWT_CSR0_WRS_MASK 0x00000008 /* Reset status */
  25. #define XWT_CSR0_WDS_MASK 0x00000004 /* Timer state */
  26. #define XWT_CSR0_EWDT1_MASK 0x00000002 /* Enable bit 1 */
  27. /* Control/Status Register 0/1 bits */
  28. #define XWT_CSRX_EWDT2_MASK 0x00000001 /* Enable bit 2 */
  29. /* SelfTest constants */
  30. #define XWT_MAX_SELFTEST_LOOP_COUNT 0x00010000
  31. #define XWT_TIMER_FAILED 0xFFFFFFFF
  32. #define WATCHDOG_NAME "Xilinx Watchdog"
  33. struct xwdt_device {
  34. void __iomem *base;
  35. u32 wdt_interval;
  36. spinlock_t spinlock;
  37. struct watchdog_device xilinx_wdt_wdd;
  38. struct clk *clk;
  39. };
  40. static int xilinx_wdt_start(struct watchdog_device *wdd)
  41. {
  42. int ret;
  43. u32 control_status_reg;
  44. struct xwdt_device *xdev = watchdog_get_drvdata(wdd);
  45. ret = clk_enable(xdev->clk);
  46. if (ret) {
  47. dev_err(wdd->parent, "Failed to enable clock\n");
  48. return ret;
  49. }
  50. spin_lock(&xdev->spinlock);
  51. /* Clean previous status and enable the watchdog timer */
  52. control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET);
  53. control_status_reg |= (XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK);
  54. iowrite32((control_status_reg | XWT_CSR0_EWDT1_MASK),
  55. xdev->base + XWT_TWCSR0_OFFSET);
  56. iowrite32(XWT_CSRX_EWDT2_MASK, xdev->base + XWT_TWCSR1_OFFSET);
  57. spin_unlock(&xdev->spinlock);
  58. return 0;
  59. }
  60. static int xilinx_wdt_stop(struct watchdog_device *wdd)
  61. {
  62. u32 control_status_reg;
  63. struct xwdt_device *xdev = watchdog_get_drvdata(wdd);
  64. spin_lock(&xdev->spinlock);
  65. control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET);
  66. iowrite32((control_status_reg & ~XWT_CSR0_EWDT1_MASK),
  67. xdev->base + XWT_TWCSR0_OFFSET);
  68. iowrite32(0, xdev->base + XWT_TWCSR1_OFFSET);
  69. spin_unlock(&xdev->spinlock);
  70. clk_disable(xdev->clk);
  71. pr_info("Stopped!\n");
  72. return 0;
  73. }
  74. static int xilinx_wdt_keepalive(struct watchdog_device *wdd)
  75. {
  76. u32 control_status_reg;
  77. struct xwdt_device *xdev = watchdog_get_drvdata(wdd);
  78. spin_lock(&xdev->spinlock);
  79. control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET);
  80. control_status_reg |= (XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK);
  81. iowrite32(control_status_reg, xdev->base + XWT_TWCSR0_OFFSET);
  82. spin_unlock(&xdev->spinlock);
  83. return 0;
  84. }
  85. static const struct watchdog_info xilinx_wdt_ident = {
  86. .options = WDIOF_MAGICCLOSE |
  87. WDIOF_KEEPALIVEPING,
  88. .firmware_version = 1,
  89. .identity = WATCHDOG_NAME,
  90. };
  91. static const struct watchdog_ops xilinx_wdt_ops = {
  92. .owner = THIS_MODULE,
  93. .start = xilinx_wdt_start,
  94. .stop = xilinx_wdt_stop,
  95. .ping = xilinx_wdt_keepalive,
  96. };
  97. static u32 xwdt_selftest(struct xwdt_device *xdev)
  98. {
  99. int i;
  100. u32 timer_value1;
  101. u32 timer_value2;
  102. spin_lock(&xdev->spinlock);
  103. timer_value1 = ioread32(xdev->base + XWT_TBR_OFFSET);
  104. timer_value2 = ioread32(xdev->base + XWT_TBR_OFFSET);
  105. for (i = 0;
  106. ((i <= XWT_MAX_SELFTEST_LOOP_COUNT) &&
  107. (timer_value2 == timer_value1)); i++) {
  108. timer_value2 = ioread32(xdev->base + XWT_TBR_OFFSET);
  109. }
  110. spin_unlock(&xdev->spinlock);
  111. if (timer_value2 != timer_value1)
  112. return ~XWT_TIMER_FAILED;
  113. else
  114. return XWT_TIMER_FAILED;
  115. }
  116. static void xwdt_clk_disable_unprepare(void *data)
  117. {
  118. clk_disable_unprepare(data);
  119. }
  120. static int xwdt_probe(struct platform_device *pdev)
  121. {
  122. struct device *dev = &pdev->dev;
  123. int rc;
  124. u32 pfreq = 0, enable_once = 0;
  125. struct xwdt_device *xdev;
  126. struct watchdog_device *xilinx_wdt_wdd;
  127. xdev = devm_kzalloc(dev, sizeof(*xdev), GFP_KERNEL);
  128. if (!xdev)
  129. return -ENOMEM;
  130. xilinx_wdt_wdd = &xdev->xilinx_wdt_wdd;
  131. xilinx_wdt_wdd->info = &xilinx_wdt_ident;
  132. xilinx_wdt_wdd->ops = &xilinx_wdt_ops;
  133. xilinx_wdt_wdd->parent = dev;
  134. xdev->base = devm_platform_ioremap_resource(pdev, 0);
  135. if (IS_ERR(xdev->base))
  136. return PTR_ERR(xdev->base);
  137. rc = of_property_read_u32(dev->of_node, "xlnx,wdt-interval",
  138. &xdev->wdt_interval);
  139. if (rc)
  140. dev_warn(dev, "Parameter \"xlnx,wdt-interval\" not found\n");
  141. rc = of_property_read_u32(dev->of_node, "xlnx,wdt-enable-once",
  142. &enable_once);
  143. if (rc)
  144. dev_warn(dev,
  145. "Parameter \"xlnx,wdt-enable-once\" not found\n");
  146. watchdog_set_nowayout(xilinx_wdt_wdd, enable_once);
  147. xdev->clk = devm_clk_get(dev, NULL);
  148. if (IS_ERR(xdev->clk)) {
  149. if (PTR_ERR(xdev->clk) != -ENOENT)
  150. return PTR_ERR(xdev->clk);
  151. /*
  152. * Clock framework support is optional, continue on
  153. * anyways if we don't find a matching clock.
  154. */
  155. xdev->clk = NULL;
  156. rc = of_property_read_u32(dev->of_node, "clock-frequency",
  157. &pfreq);
  158. if (rc)
  159. dev_warn(dev,
  160. "The watchdog clock freq cannot be obtained\n");
  161. } else {
  162. pfreq = clk_get_rate(xdev->clk);
  163. }
  164. /*
  165. * Twice of the 2^wdt_interval / freq because the first wdt overflow is
  166. * ignored (interrupt), reset is only generated at second wdt overflow
  167. */
  168. if (pfreq && xdev->wdt_interval)
  169. xilinx_wdt_wdd->timeout = 2 * ((1 << xdev->wdt_interval) /
  170. pfreq);
  171. spin_lock_init(&xdev->spinlock);
  172. watchdog_set_drvdata(xilinx_wdt_wdd, xdev);
  173. rc = clk_prepare_enable(xdev->clk);
  174. if (rc) {
  175. dev_err(dev, "unable to enable clock\n");
  176. return rc;
  177. }
  178. rc = devm_add_action_or_reset(dev, xwdt_clk_disable_unprepare,
  179. xdev->clk);
  180. if (rc)
  181. return rc;
  182. rc = xwdt_selftest(xdev);
  183. if (rc == XWT_TIMER_FAILED) {
  184. dev_err(dev, "SelfTest routine error\n");
  185. return rc;
  186. }
  187. rc = devm_watchdog_register_device(dev, xilinx_wdt_wdd);
  188. if (rc)
  189. return rc;
  190. clk_disable(xdev->clk);
  191. dev_info(dev, "Xilinx Watchdog Timer at %p with timeout %ds\n",
  192. xdev->base, xilinx_wdt_wdd->timeout);
  193. platform_set_drvdata(pdev, xdev);
  194. return 0;
  195. }
  196. /**
  197. * xwdt_suspend - Suspend the device.
  198. *
  199. * @dev: handle to the device structure.
  200. * Return: 0 always.
  201. */
  202. static int __maybe_unused xwdt_suspend(struct device *dev)
  203. {
  204. struct xwdt_device *xdev = dev_get_drvdata(dev);
  205. if (watchdog_active(&xdev->xilinx_wdt_wdd))
  206. xilinx_wdt_stop(&xdev->xilinx_wdt_wdd);
  207. return 0;
  208. }
  209. /**
  210. * xwdt_resume - Resume the device.
  211. *
  212. * @dev: handle to the device structure.
  213. * Return: 0 on success, errno otherwise.
  214. */
  215. static int __maybe_unused xwdt_resume(struct device *dev)
  216. {
  217. struct xwdt_device *xdev = dev_get_drvdata(dev);
  218. int ret = 0;
  219. if (watchdog_active(&xdev->xilinx_wdt_wdd))
  220. ret = xilinx_wdt_start(&xdev->xilinx_wdt_wdd);
  221. return ret;
  222. }
  223. static SIMPLE_DEV_PM_OPS(xwdt_pm_ops, xwdt_suspend, xwdt_resume);
  224. /* Match table for of_platform binding */
  225. static const struct of_device_id xwdt_of_match[] = {
  226. { .compatible = "xlnx,xps-timebase-wdt-1.00.a", },
  227. { .compatible = "xlnx,xps-timebase-wdt-1.01.a", },
  228. {},
  229. };
  230. MODULE_DEVICE_TABLE(of, xwdt_of_match);
  231. static struct platform_driver xwdt_driver = {
  232. .probe = xwdt_probe,
  233. .driver = {
  234. .name = WATCHDOG_NAME,
  235. .of_match_table = xwdt_of_match,
  236. .pm = &xwdt_pm_ops,
  237. },
  238. };
  239. module_platform_driver(xwdt_driver);
  240. MODULE_AUTHOR("Alejandro Cabrera <aldaya@gmail.com>");
  241. MODULE_DESCRIPTION("Xilinx Watchdog driver");
  242. MODULE_LICENSE("GPL");