nv_tco.c 12 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515
  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * nv_tco 0.01: TCO timer driver for NV chipsets
  4. *
  5. * (c) Copyright 2005 Google Inc., All Rights Reserved.
  6. *
  7. * Based off i8xx_tco.c:
  8. * (c) Copyright 2000 kernel concepts <nils@kernelconcepts.de>, All Rights
  9. * Reserved.
  10. * https://www.kernelconcepts.de
  11. *
  12. * TCO timer driver for NV chipsets
  13. * based on softdog.c by Alan Cox <alan@redhat.com>
  14. */
  15. /*
  16. * Includes, defines, variables, module parameters, ...
  17. */
  18. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  19. #include <linux/module.h>
  20. #include <linux/moduleparam.h>
  21. #include <linux/types.h>
  22. #include <linux/miscdevice.h>
  23. #include <linux/watchdog.h>
  24. #include <linux/init.h>
  25. #include <linux/fs.h>
  26. #include <linux/pci.h>
  27. #include <linux/ioport.h>
  28. #include <linux/jiffies.h>
  29. #include <linux/platform_device.h>
  30. #include <linux/uaccess.h>
  31. #include <linux/io.h>
  32. #include "nv_tco.h"
  33. /* Module and version information */
  34. #define TCO_VERSION "0.01"
  35. #define TCO_MODULE_NAME "NV_TCO"
  36. #define TCO_DRIVER_NAME TCO_MODULE_NAME ", v" TCO_VERSION
  37. /* internal variables */
  38. static unsigned int tcobase;
  39. static DEFINE_SPINLOCK(tco_lock); /* Guards the hardware */
  40. static unsigned long timer_alive;
  41. static char tco_expect_close;
  42. static struct pci_dev *tco_pci;
  43. /* the watchdog platform device */
  44. static struct platform_device *nv_tco_platform_device;
  45. /* module parameters */
  46. #define WATCHDOG_HEARTBEAT 30 /* 30 sec default heartbeat (2<heartbeat<39) */
  47. static int heartbeat = WATCHDOG_HEARTBEAT; /* in seconds */
  48. module_param(heartbeat, int, 0);
  49. MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds. (2<heartbeat<39, "
  50. "default=" __MODULE_STRING(WATCHDOG_HEARTBEAT) ")");
  51. static bool nowayout = WATCHDOG_NOWAYOUT;
  52. module_param(nowayout, bool, 0);
  53. MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started"
  54. " (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  55. /*
  56. * Some TCO specific functions
  57. */
  58. static inline unsigned char seconds_to_ticks(int seconds)
  59. {
  60. /* the internal timer is stored as ticks which decrement
  61. * every 0.6 seconds */
  62. return (seconds * 10) / 6;
  63. }
  64. static void tco_timer_start(void)
  65. {
  66. u32 val;
  67. unsigned long flags;
  68. spin_lock_irqsave(&tco_lock, flags);
  69. val = inl(TCO_CNT(tcobase));
  70. val &= ~TCO_CNT_TCOHALT;
  71. outl(val, TCO_CNT(tcobase));
  72. spin_unlock_irqrestore(&tco_lock, flags);
  73. }
  74. static void tco_timer_stop(void)
  75. {
  76. u32 val;
  77. unsigned long flags;
  78. spin_lock_irqsave(&tco_lock, flags);
  79. val = inl(TCO_CNT(tcobase));
  80. val |= TCO_CNT_TCOHALT;
  81. outl(val, TCO_CNT(tcobase));
  82. spin_unlock_irqrestore(&tco_lock, flags);
  83. }
  84. static void tco_timer_keepalive(void)
  85. {
  86. unsigned long flags;
  87. spin_lock_irqsave(&tco_lock, flags);
  88. outb(0x01, TCO_RLD(tcobase));
  89. spin_unlock_irqrestore(&tco_lock, flags);
  90. }
  91. static int tco_timer_set_heartbeat(int t)
  92. {
  93. int ret = 0;
  94. unsigned char tmrval;
  95. unsigned long flags;
  96. u8 val;
  97. /*
  98. * note seconds_to_ticks(t) > t, so if t > 0x3f, so is
  99. * tmrval=seconds_to_ticks(t). Check that the count in seconds isn't
  100. * out of range on it's own (to avoid overflow in tmrval).
  101. */
  102. if (t < 0 || t > 0x3f)
  103. return -EINVAL;
  104. tmrval = seconds_to_ticks(t);
  105. /* "Values of 0h-3h are ignored and should not be attempted" */
  106. if (tmrval > 0x3f || tmrval < 0x04)
  107. return -EINVAL;
  108. /* Write new heartbeat to watchdog */
  109. spin_lock_irqsave(&tco_lock, flags);
  110. val = inb(TCO_TMR(tcobase));
  111. val &= 0xc0;
  112. val |= tmrval;
  113. outb(val, TCO_TMR(tcobase));
  114. val = inb(TCO_TMR(tcobase));
  115. if ((val & 0x3f) != tmrval)
  116. ret = -EINVAL;
  117. spin_unlock_irqrestore(&tco_lock, flags);
  118. if (ret)
  119. return ret;
  120. heartbeat = t;
  121. return 0;
  122. }
  123. /*
  124. * /dev/watchdog handling
  125. */
  126. static int nv_tco_open(struct inode *inode, struct file *file)
  127. {
  128. /* /dev/watchdog can only be opened once */
  129. if (test_and_set_bit(0, &timer_alive))
  130. return -EBUSY;
  131. /* Reload and activate timer */
  132. tco_timer_keepalive();
  133. tco_timer_start();
  134. return stream_open(inode, file);
  135. }
  136. static int nv_tco_release(struct inode *inode, struct file *file)
  137. {
  138. /* Shut off the timer */
  139. if (tco_expect_close == 42) {
  140. tco_timer_stop();
  141. } else {
  142. pr_crit("Unexpected close, not stopping watchdog!\n");
  143. tco_timer_keepalive();
  144. }
  145. clear_bit(0, &timer_alive);
  146. tco_expect_close = 0;
  147. return 0;
  148. }
  149. static ssize_t nv_tco_write(struct file *file, const char __user *data,
  150. size_t len, loff_t *ppos)
  151. {
  152. /* See if we got the magic character 'V' and reload the timer */
  153. if (len) {
  154. if (!nowayout) {
  155. size_t i;
  156. /*
  157. * note: just in case someone wrote the magic character
  158. * five months ago...
  159. */
  160. tco_expect_close = 0;
  161. /*
  162. * scan to see whether or not we got the magic
  163. * character
  164. */
  165. for (i = 0; i != len; i++) {
  166. char c;
  167. if (get_user(c, data + i))
  168. return -EFAULT;
  169. if (c == 'V')
  170. tco_expect_close = 42;
  171. }
  172. }
  173. /* someone wrote to us, we should reload the timer */
  174. tco_timer_keepalive();
  175. }
  176. return len;
  177. }
  178. static long nv_tco_ioctl(struct file *file, unsigned int cmd,
  179. unsigned long arg)
  180. {
  181. int new_options, retval = -EINVAL;
  182. int new_heartbeat;
  183. void __user *argp = (void __user *)arg;
  184. int __user *p = argp;
  185. static const struct watchdog_info ident = {
  186. .options = WDIOF_SETTIMEOUT |
  187. WDIOF_KEEPALIVEPING |
  188. WDIOF_MAGICCLOSE,
  189. .firmware_version = 0,
  190. .identity = TCO_MODULE_NAME,
  191. };
  192. switch (cmd) {
  193. case WDIOC_GETSUPPORT:
  194. return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0;
  195. case WDIOC_GETSTATUS:
  196. case WDIOC_GETBOOTSTATUS:
  197. return put_user(0, p);
  198. case WDIOC_SETOPTIONS:
  199. if (get_user(new_options, p))
  200. return -EFAULT;
  201. if (new_options & WDIOS_DISABLECARD) {
  202. tco_timer_stop();
  203. retval = 0;
  204. }
  205. if (new_options & WDIOS_ENABLECARD) {
  206. tco_timer_keepalive();
  207. tco_timer_start();
  208. retval = 0;
  209. }
  210. return retval;
  211. case WDIOC_KEEPALIVE:
  212. tco_timer_keepalive();
  213. return 0;
  214. case WDIOC_SETTIMEOUT:
  215. if (get_user(new_heartbeat, p))
  216. return -EFAULT;
  217. if (tco_timer_set_heartbeat(new_heartbeat))
  218. return -EINVAL;
  219. tco_timer_keepalive();
  220. fallthrough;
  221. case WDIOC_GETTIMEOUT:
  222. return put_user(heartbeat, p);
  223. default:
  224. return -ENOTTY;
  225. }
  226. }
  227. /*
  228. * Kernel Interfaces
  229. */
  230. static const struct file_operations nv_tco_fops = {
  231. .owner = THIS_MODULE,
  232. .llseek = no_llseek,
  233. .write = nv_tco_write,
  234. .unlocked_ioctl = nv_tco_ioctl,
  235. .compat_ioctl = compat_ptr_ioctl,
  236. .open = nv_tco_open,
  237. .release = nv_tco_release,
  238. };
  239. static struct miscdevice nv_tco_miscdev = {
  240. .minor = WATCHDOG_MINOR,
  241. .name = "watchdog",
  242. .fops = &nv_tco_fops,
  243. };
  244. /*
  245. * Data for PCI driver interface
  246. *
  247. * This data only exists for exporting the supported
  248. * PCI ids via MODULE_DEVICE_TABLE. We do not actually
  249. * register a pci_driver, because someone else might one day
  250. * want to register another driver on the same PCI id.
  251. */
  252. static const struct pci_device_id tco_pci_tbl[] = {
  253. { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SMBUS,
  254. PCI_ANY_ID, PCI_ANY_ID, },
  255. { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SMBUS,
  256. PCI_ANY_ID, PCI_ANY_ID, },
  257. { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP78S_SMBUS,
  258. PCI_ANY_ID, PCI_ANY_ID, },
  259. { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP79_SMBUS,
  260. PCI_ANY_ID, PCI_ANY_ID, },
  261. { 0, }, /* End of list */
  262. };
  263. MODULE_DEVICE_TABLE(pci, tco_pci_tbl);
  264. /*
  265. * Init & exit routines
  266. */
  267. static unsigned char nv_tco_getdevice(void)
  268. {
  269. struct pci_dev *dev = NULL;
  270. u32 val;
  271. /* Find the PCI device */
  272. for_each_pci_dev(dev) {
  273. if (pci_match_id(tco_pci_tbl, dev) != NULL) {
  274. tco_pci = dev;
  275. break;
  276. }
  277. }
  278. if (!tco_pci)
  279. return 0;
  280. /* Find the base io port */
  281. pci_read_config_dword(tco_pci, 0x64, &val);
  282. val &= 0xffff;
  283. if (val == 0x0001 || val == 0x0000) {
  284. /* Something is wrong here, bar isn't setup */
  285. pr_err("failed to get tcobase address\n");
  286. return 0;
  287. }
  288. val &= 0xff00;
  289. tcobase = val + 0x40;
  290. if (!request_region(tcobase, 0x10, "NV TCO")) {
  291. pr_err("I/O address 0x%04x already in use\n", tcobase);
  292. return 0;
  293. }
  294. /* Set a reasonable heartbeat before we stop the timer */
  295. tco_timer_set_heartbeat(30);
  296. /*
  297. * Stop the TCO before we change anything so we don't race with
  298. * a zeroed timer.
  299. */
  300. tco_timer_keepalive();
  301. tco_timer_stop();
  302. /* Disable SMI caused by TCO */
  303. if (!request_region(MCP51_SMI_EN(tcobase), 4, "NV TCO")) {
  304. pr_err("I/O address 0x%04x already in use\n",
  305. MCP51_SMI_EN(tcobase));
  306. goto out;
  307. }
  308. val = inl(MCP51_SMI_EN(tcobase));
  309. val &= ~MCP51_SMI_EN_TCO;
  310. outl(val, MCP51_SMI_EN(tcobase));
  311. val = inl(MCP51_SMI_EN(tcobase));
  312. release_region(MCP51_SMI_EN(tcobase), 4);
  313. if (val & MCP51_SMI_EN_TCO) {
  314. pr_err("Could not disable SMI caused by TCO\n");
  315. goto out;
  316. }
  317. /* Check chipset's NO_REBOOT bit */
  318. pci_read_config_dword(tco_pci, MCP51_SMBUS_SETUP_B, &val);
  319. val |= MCP51_SMBUS_SETUP_B_TCO_REBOOT;
  320. pci_write_config_dword(tco_pci, MCP51_SMBUS_SETUP_B, val);
  321. pci_read_config_dword(tco_pci, MCP51_SMBUS_SETUP_B, &val);
  322. if (!(val & MCP51_SMBUS_SETUP_B_TCO_REBOOT)) {
  323. pr_err("failed to reset NO_REBOOT flag, reboot disabled by hardware\n");
  324. goto out;
  325. }
  326. return 1;
  327. out:
  328. release_region(tcobase, 0x10);
  329. return 0;
  330. }
  331. static int nv_tco_init(struct platform_device *dev)
  332. {
  333. int ret;
  334. /* Check whether or not the hardware watchdog is there */
  335. if (!nv_tco_getdevice())
  336. return -ENODEV;
  337. /* Check to see if last reboot was due to watchdog timeout */
  338. pr_info("Watchdog reboot %sdetected\n",
  339. inl(TCO_STS(tcobase)) & TCO_STS_TCO2TO_STS ? "" : "not ");
  340. /* Clear out the old status */
  341. outl(TCO_STS_RESET, TCO_STS(tcobase));
  342. /*
  343. * Check that the heartbeat value is within it's range.
  344. * If not, reset to the default.
  345. */
  346. if (tco_timer_set_heartbeat(heartbeat)) {
  347. heartbeat = WATCHDOG_HEARTBEAT;
  348. tco_timer_set_heartbeat(heartbeat);
  349. pr_info("heartbeat value must be 2<heartbeat<39, using %d\n",
  350. heartbeat);
  351. }
  352. ret = misc_register(&nv_tco_miscdev);
  353. if (ret != 0) {
  354. pr_err("cannot register miscdev on minor=%d (err=%d)\n",
  355. WATCHDOG_MINOR, ret);
  356. goto unreg_region;
  357. }
  358. clear_bit(0, &timer_alive);
  359. tco_timer_stop();
  360. pr_info("initialized (0x%04x). heartbeat=%d sec (nowayout=%d)\n",
  361. tcobase, heartbeat, nowayout);
  362. return 0;
  363. unreg_region:
  364. release_region(tcobase, 0x10);
  365. return ret;
  366. }
  367. static void nv_tco_cleanup(void)
  368. {
  369. u32 val;
  370. /* Stop the timer before we leave */
  371. if (!nowayout)
  372. tco_timer_stop();
  373. /* Set the NO_REBOOT bit to prevent later reboots, just for sure */
  374. pci_read_config_dword(tco_pci, MCP51_SMBUS_SETUP_B, &val);
  375. val &= ~MCP51_SMBUS_SETUP_B_TCO_REBOOT;
  376. pci_write_config_dword(tco_pci, MCP51_SMBUS_SETUP_B, val);
  377. pci_read_config_dword(tco_pci, MCP51_SMBUS_SETUP_B, &val);
  378. if (val & MCP51_SMBUS_SETUP_B_TCO_REBOOT) {
  379. pr_crit("Couldn't unset REBOOT bit. Machine may soon reset\n");
  380. }
  381. /* Deregister */
  382. misc_deregister(&nv_tco_miscdev);
  383. release_region(tcobase, 0x10);
  384. }
  385. static int nv_tco_remove(struct platform_device *dev)
  386. {
  387. if (tcobase)
  388. nv_tco_cleanup();
  389. return 0;
  390. }
  391. static void nv_tco_shutdown(struct platform_device *dev)
  392. {
  393. u32 val;
  394. tco_timer_stop();
  395. /* Some BIOSes fail the POST (once) if the NO_REBOOT flag is not
  396. * unset during shutdown. */
  397. pci_read_config_dword(tco_pci, MCP51_SMBUS_SETUP_B, &val);
  398. val &= ~MCP51_SMBUS_SETUP_B_TCO_REBOOT;
  399. pci_write_config_dword(tco_pci, MCP51_SMBUS_SETUP_B, val);
  400. }
  401. static struct platform_driver nv_tco_driver = {
  402. .probe = nv_tco_init,
  403. .remove = nv_tco_remove,
  404. .shutdown = nv_tco_shutdown,
  405. .driver = {
  406. .name = TCO_MODULE_NAME,
  407. },
  408. };
  409. static int __init nv_tco_init_module(void)
  410. {
  411. int err;
  412. pr_info("NV TCO WatchDog Timer Driver v%s\n", TCO_VERSION);
  413. err = platform_driver_register(&nv_tco_driver);
  414. if (err)
  415. return err;
  416. nv_tco_platform_device = platform_device_register_simple(
  417. TCO_MODULE_NAME, -1, NULL, 0);
  418. if (IS_ERR(nv_tco_platform_device)) {
  419. err = PTR_ERR(nv_tco_platform_device);
  420. goto unreg_platform_driver;
  421. }
  422. return 0;
  423. unreg_platform_driver:
  424. platform_driver_unregister(&nv_tco_driver);
  425. return err;
  426. }
  427. static void __exit nv_tco_cleanup_module(void)
  428. {
  429. platform_device_unregister(nv_tco_platform_device);
  430. platform_driver_unregister(&nv_tco_driver);
  431. pr_info("NV TCO Watchdog Module Unloaded\n");
  432. }
  433. module_init(nv_tco_init_module);
  434. module_exit(nv_tco_cleanup_module);
  435. MODULE_AUTHOR("Mike Waychison");
  436. MODULE_DESCRIPTION("TCO timer driver for NV chipsets");
  437. MODULE_LICENSE("GPL");