mtk_wdt.c 8.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Mediatek Watchdog Driver
  4. *
  5. * Copyright (C) 2014 Matthias Brugger
  6. *
  7. * Matthias Brugger <matthias.bgg@gmail.com>
  8. *
  9. * Based on sunxi_wdt.c
  10. */
  11. #include <dt-bindings/reset-controller/mt2712-resets.h>
  12. #include <dt-bindings/reset-controller/mt8183-resets.h>
  13. #include <linux/delay.h>
  14. #include <linux/err.h>
  15. #include <linux/init.h>
  16. #include <linux/io.h>
  17. #include <linux/kernel.h>
  18. #include <linux/module.h>
  19. #include <linux/moduleparam.h>
  20. #include <linux/of.h>
  21. #include <linux/of_device.h>
  22. #include <linux/platform_device.h>
  23. #include <linux/reset-controller.h>
  24. #include <linux/types.h>
  25. #include <linux/watchdog.h>
  26. #define WDT_MAX_TIMEOUT 31
  27. #define WDT_MIN_TIMEOUT 1
  28. #define WDT_LENGTH_TIMEOUT(n) ((n) << 5)
  29. #define WDT_LENGTH 0x04
  30. #define WDT_LENGTH_KEY 0x8
  31. #define WDT_RST 0x08
  32. #define WDT_RST_RELOAD 0x1971
  33. #define WDT_MODE 0x00
  34. #define WDT_MODE_EN (1 << 0)
  35. #define WDT_MODE_EXT_POL_LOW (0 << 1)
  36. #define WDT_MODE_EXT_POL_HIGH (1 << 1)
  37. #define WDT_MODE_EXRST_EN (1 << 2)
  38. #define WDT_MODE_IRQ_EN (1 << 3)
  39. #define WDT_MODE_AUTO_START (1 << 4)
  40. #define WDT_MODE_DUAL_EN (1 << 6)
  41. #define WDT_MODE_KEY 0x22000000
  42. #define WDT_SWRST 0x14
  43. #define WDT_SWRST_KEY 0x1209
  44. #define WDT_SWSYSRST 0x18U
  45. #define WDT_SWSYS_RST_KEY 0x88000000
  46. #define DRV_NAME "mtk-wdt"
  47. #define DRV_VERSION "1.0"
  48. static bool nowayout = WATCHDOG_NOWAYOUT;
  49. static unsigned int timeout;
  50. struct mtk_wdt_dev {
  51. struct watchdog_device wdt_dev;
  52. void __iomem *wdt_base;
  53. spinlock_t lock; /* protects WDT_SWSYSRST reg */
  54. struct reset_controller_dev rcdev;
  55. };
  56. struct mtk_wdt_data {
  57. int toprgu_sw_rst_num;
  58. };
  59. static const struct mtk_wdt_data mt2712_data = {
  60. .toprgu_sw_rst_num = MT2712_TOPRGU_SW_RST_NUM,
  61. };
  62. static const struct mtk_wdt_data mt8183_data = {
  63. .toprgu_sw_rst_num = MT8183_TOPRGU_SW_RST_NUM,
  64. };
  65. static int toprgu_reset_update(struct reset_controller_dev *rcdev,
  66. unsigned long id, bool assert)
  67. {
  68. unsigned int tmp;
  69. unsigned long flags;
  70. struct mtk_wdt_dev *data =
  71. container_of(rcdev, struct mtk_wdt_dev, rcdev);
  72. spin_lock_irqsave(&data->lock, flags);
  73. tmp = readl(data->wdt_base + WDT_SWSYSRST);
  74. if (assert)
  75. tmp |= BIT(id);
  76. else
  77. tmp &= ~BIT(id);
  78. tmp |= WDT_SWSYS_RST_KEY;
  79. writel(tmp, data->wdt_base + WDT_SWSYSRST);
  80. spin_unlock_irqrestore(&data->lock, flags);
  81. return 0;
  82. }
  83. static int toprgu_reset_assert(struct reset_controller_dev *rcdev,
  84. unsigned long id)
  85. {
  86. return toprgu_reset_update(rcdev, id, true);
  87. }
  88. static int toprgu_reset_deassert(struct reset_controller_dev *rcdev,
  89. unsigned long id)
  90. {
  91. return toprgu_reset_update(rcdev, id, false);
  92. }
  93. static int toprgu_reset(struct reset_controller_dev *rcdev,
  94. unsigned long id)
  95. {
  96. int ret;
  97. ret = toprgu_reset_assert(rcdev, id);
  98. if (ret)
  99. return ret;
  100. return toprgu_reset_deassert(rcdev, id);
  101. }
  102. static const struct reset_control_ops toprgu_reset_ops = {
  103. .assert = toprgu_reset_assert,
  104. .deassert = toprgu_reset_deassert,
  105. .reset = toprgu_reset,
  106. };
  107. static int toprgu_register_reset_controller(struct platform_device *pdev,
  108. int rst_num)
  109. {
  110. int ret;
  111. struct mtk_wdt_dev *mtk_wdt = platform_get_drvdata(pdev);
  112. spin_lock_init(&mtk_wdt->lock);
  113. mtk_wdt->rcdev.owner = THIS_MODULE;
  114. mtk_wdt->rcdev.nr_resets = rst_num;
  115. mtk_wdt->rcdev.ops = &toprgu_reset_ops;
  116. mtk_wdt->rcdev.of_node = pdev->dev.of_node;
  117. ret = devm_reset_controller_register(&pdev->dev, &mtk_wdt->rcdev);
  118. if (ret != 0)
  119. dev_err(&pdev->dev,
  120. "couldn't register wdt reset controller: %d\n", ret);
  121. return ret;
  122. }
  123. static int mtk_wdt_restart(struct watchdog_device *wdt_dev,
  124. unsigned long action, void *data)
  125. {
  126. struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
  127. void __iomem *wdt_base;
  128. wdt_base = mtk_wdt->wdt_base;
  129. while (1) {
  130. writel(WDT_SWRST_KEY, wdt_base + WDT_SWRST);
  131. mdelay(5);
  132. }
  133. return 0;
  134. }
  135. static int mtk_wdt_ping(struct watchdog_device *wdt_dev)
  136. {
  137. struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
  138. void __iomem *wdt_base = mtk_wdt->wdt_base;
  139. iowrite32(WDT_RST_RELOAD, wdt_base + WDT_RST);
  140. return 0;
  141. }
  142. static int mtk_wdt_set_timeout(struct watchdog_device *wdt_dev,
  143. unsigned int timeout)
  144. {
  145. struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
  146. void __iomem *wdt_base = mtk_wdt->wdt_base;
  147. u32 reg;
  148. wdt_dev->timeout = timeout;
  149. /*
  150. * One bit is the value of 512 ticks
  151. * The clock has 32 KHz
  152. */
  153. reg = WDT_LENGTH_TIMEOUT(timeout << 6) | WDT_LENGTH_KEY;
  154. iowrite32(reg, wdt_base + WDT_LENGTH);
  155. mtk_wdt_ping(wdt_dev);
  156. return 0;
  157. }
  158. static int mtk_wdt_stop(struct watchdog_device *wdt_dev)
  159. {
  160. struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
  161. void __iomem *wdt_base = mtk_wdt->wdt_base;
  162. u32 reg;
  163. reg = readl(wdt_base + WDT_MODE);
  164. reg &= ~WDT_MODE_EN;
  165. reg |= WDT_MODE_KEY;
  166. iowrite32(reg, wdt_base + WDT_MODE);
  167. return 0;
  168. }
  169. static int mtk_wdt_start(struct watchdog_device *wdt_dev)
  170. {
  171. u32 reg;
  172. struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
  173. void __iomem *wdt_base = mtk_wdt->wdt_base;
  174. int ret;
  175. ret = mtk_wdt_set_timeout(wdt_dev, wdt_dev->timeout);
  176. if (ret < 0)
  177. return ret;
  178. reg = ioread32(wdt_base + WDT_MODE);
  179. reg &= ~(WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN);
  180. reg |= (WDT_MODE_EN | WDT_MODE_KEY);
  181. iowrite32(reg, wdt_base + WDT_MODE);
  182. return 0;
  183. }
  184. static const struct watchdog_info mtk_wdt_info = {
  185. .identity = DRV_NAME,
  186. .options = WDIOF_SETTIMEOUT |
  187. WDIOF_KEEPALIVEPING |
  188. WDIOF_MAGICCLOSE,
  189. };
  190. static const struct watchdog_ops mtk_wdt_ops = {
  191. .owner = THIS_MODULE,
  192. .start = mtk_wdt_start,
  193. .stop = mtk_wdt_stop,
  194. .ping = mtk_wdt_ping,
  195. .set_timeout = mtk_wdt_set_timeout,
  196. .restart = mtk_wdt_restart,
  197. };
  198. static int mtk_wdt_probe(struct platform_device *pdev)
  199. {
  200. struct device *dev = &pdev->dev;
  201. struct mtk_wdt_dev *mtk_wdt;
  202. const struct mtk_wdt_data *wdt_data;
  203. int err;
  204. mtk_wdt = devm_kzalloc(dev, sizeof(*mtk_wdt), GFP_KERNEL);
  205. if (!mtk_wdt)
  206. return -ENOMEM;
  207. platform_set_drvdata(pdev, mtk_wdt);
  208. mtk_wdt->wdt_base = devm_platform_ioremap_resource(pdev, 0);
  209. if (IS_ERR(mtk_wdt->wdt_base))
  210. return PTR_ERR(mtk_wdt->wdt_base);
  211. mtk_wdt->wdt_dev.info = &mtk_wdt_info;
  212. mtk_wdt->wdt_dev.ops = &mtk_wdt_ops;
  213. mtk_wdt->wdt_dev.timeout = WDT_MAX_TIMEOUT;
  214. mtk_wdt->wdt_dev.max_timeout = WDT_MAX_TIMEOUT;
  215. mtk_wdt->wdt_dev.min_timeout = WDT_MIN_TIMEOUT;
  216. mtk_wdt->wdt_dev.parent = dev;
  217. watchdog_init_timeout(&mtk_wdt->wdt_dev, timeout, dev);
  218. watchdog_set_nowayout(&mtk_wdt->wdt_dev, nowayout);
  219. watchdog_set_restart_priority(&mtk_wdt->wdt_dev, 128);
  220. watchdog_set_drvdata(&mtk_wdt->wdt_dev, mtk_wdt);
  221. mtk_wdt_stop(&mtk_wdt->wdt_dev);
  222. watchdog_stop_on_reboot(&mtk_wdt->wdt_dev);
  223. err = devm_watchdog_register_device(dev, &mtk_wdt->wdt_dev);
  224. if (unlikely(err))
  225. return err;
  226. dev_info(dev, "Watchdog enabled (timeout=%d sec, nowayout=%d)\n",
  227. mtk_wdt->wdt_dev.timeout, nowayout);
  228. wdt_data = of_device_get_match_data(dev);
  229. if (wdt_data) {
  230. err = toprgu_register_reset_controller(pdev,
  231. wdt_data->toprgu_sw_rst_num);
  232. if (err)
  233. return err;
  234. }
  235. return 0;
  236. }
  237. #ifdef CONFIG_PM_SLEEP
  238. static int mtk_wdt_suspend(struct device *dev)
  239. {
  240. struct mtk_wdt_dev *mtk_wdt = dev_get_drvdata(dev);
  241. if (watchdog_active(&mtk_wdt->wdt_dev))
  242. mtk_wdt_stop(&mtk_wdt->wdt_dev);
  243. return 0;
  244. }
  245. static int mtk_wdt_resume(struct device *dev)
  246. {
  247. struct mtk_wdt_dev *mtk_wdt = dev_get_drvdata(dev);
  248. if (watchdog_active(&mtk_wdt->wdt_dev)) {
  249. mtk_wdt_start(&mtk_wdt->wdt_dev);
  250. mtk_wdt_ping(&mtk_wdt->wdt_dev);
  251. }
  252. return 0;
  253. }
  254. #endif
  255. static const struct of_device_id mtk_wdt_dt_ids[] = {
  256. { .compatible = "mediatek,mt2712-wdt", .data = &mt2712_data },
  257. { .compatible = "mediatek,mt6589-wdt" },
  258. { .compatible = "mediatek,mt8183-wdt", .data = &mt8183_data },
  259. { /* sentinel */ }
  260. };
  261. MODULE_DEVICE_TABLE(of, mtk_wdt_dt_ids);
  262. static const struct dev_pm_ops mtk_wdt_pm_ops = {
  263. SET_SYSTEM_SLEEP_PM_OPS(mtk_wdt_suspend,
  264. mtk_wdt_resume)
  265. };
  266. static struct platform_driver mtk_wdt_driver = {
  267. .probe = mtk_wdt_probe,
  268. .driver = {
  269. .name = DRV_NAME,
  270. .pm = &mtk_wdt_pm_ops,
  271. .of_match_table = mtk_wdt_dt_ids,
  272. },
  273. };
  274. module_platform_driver(mtk_wdt_driver);
  275. module_param(timeout, uint, 0);
  276. MODULE_PARM_DESC(timeout, "Watchdog heartbeat in seconds");
  277. module_param(nowayout, bool, 0);
  278. MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
  279. __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  280. MODULE_LICENSE("GPL");
  281. MODULE_AUTHOR("Matthias Brugger <matthias.bgg@gmail.com>");
  282. MODULE_DESCRIPTION("Mediatek WatchDog Timer Driver");
  283. MODULE_VERSION(DRV_VERSION);