mt7621_wdt.c 4.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Ralink MT7621/MT7628 built-in hardware watchdog timer
  4. *
  5. * Copyright (C) 2014 John Crispin <john@phrozen.org>
  6. *
  7. * This driver was based on: drivers/watchdog/rt2880_wdt.c
  8. */
  9. #include <linux/clk.h>
  10. #include <linux/reset.h>
  11. #include <linux/module.h>
  12. #include <linux/kernel.h>
  13. #include <linux/watchdog.h>
  14. #include <linux/moduleparam.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/mod_devicetable.h>
  17. #include <asm/mach-ralink/ralink_regs.h>
  18. #define SYSC_RSTSTAT 0x38
  19. #define WDT_RST_CAUSE BIT(1)
  20. #define RALINK_WDT_TIMEOUT 30
  21. #define TIMER_REG_TMRSTAT 0x00
  22. #define TIMER_REG_TMR1LOAD 0x24
  23. #define TIMER_REG_TMR1CTL 0x20
  24. #define TMR1CTL_ENABLE BIT(7)
  25. #define TMR1CTL_RESTART BIT(9)
  26. #define TMR1CTL_PRESCALE_SHIFT 16
  27. static void __iomem *mt7621_wdt_base;
  28. static struct reset_control *mt7621_wdt_reset;
  29. static bool nowayout = WATCHDOG_NOWAYOUT;
  30. module_param(nowayout, bool, 0);
  31. MODULE_PARM_DESC(nowayout,
  32. "Watchdog cannot be stopped once started (default="
  33. __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  34. static inline void rt_wdt_w32(unsigned reg, u32 val)
  35. {
  36. iowrite32(val, mt7621_wdt_base + reg);
  37. }
  38. static inline u32 rt_wdt_r32(unsigned reg)
  39. {
  40. return ioread32(mt7621_wdt_base + reg);
  41. }
  42. static int mt7621_wdt_ping(struct watchdog_device *w)
  43. {
  44. rt_wdt_w32(TIMER_REG_TMRSTAT, TMR1CTL_RESTART);
  45. return 0;
  46. }
  47. static int mt7621_wdt_set_timeout(struct watchdog_device *w, unsigned int t)
  48. {
  49. w->timeout = t;
  50. rt_wdt_w32(TIMER_REG_TMR1LOAD, t * 1000);
  51. mt7621_wdt_ping(w);
  52. return 0;
  53. }
  54. static int mt7621_wdt_start(struct watchdog_device *w)
  55. {
  56. u32 t;
  57. /* set the prescaler to 1ms == 1000us */
  58. rt_wdt_w32(TIMER_REG_TMR1CTL, 1000 << TMR1CTL_PRESCALE_SHIFT);
  59. mt7621_wdt_set_timeout(w, w->timeout);
  60. t = rt_wdt_r32(TIMER_REG_TMR1CTL);
  61. t |= TMR1CTL_ENABLE;
  62. rt_wdt_w32(TIMER_REG_TMR1CTL, t);
  63. return 0;
  64. }
  65. static int mt7621_wdt_stop(struct watchdog_device *w)
  66. {
  67. u32 t;
  68. mt7621_wdt_ping(w);
  69. t = rt_wdt_r32(TIMER_REG_TMR1CTL);
  70. t &= ~TMR1CTL_ENABLE;
  71. rt_wdt_w32(TIMER_REG_TMR1CTL, t);
  72. return 0;
  73. }
  74. static int mt7621_wdt_bootcause(void)
  75. {
  76. if (rt_sysc_r32(SYSC_RSTSTAT) & WDT_RST_CAUSE)
  77. return WDIOF_CARDRESET;
  78. return 0;
  79. }
  80. static int mt7621_wdt_is_running(struct watchdog_device *w)
  81. {
  82. return !!(rt_wdt_r32(TIMER_REG_TMR1CTL) & TMR1CTL_ENABLE);
  83. }
  84. static const struct watchdog_info mt7621_wdt_info = {
  85. .identity = "Mediatek Watchdog",
  86. .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
  87. };
  88. static const struct watchdog_ops mt7621_wdt_ops = {
  89. .owner = THIS_MODULE,
  90. .start = mt7621_wdt_start,
  91. .stop = mt7621_wdt_stop,
  92. .ping = mt7621_wdt_ping,
  93. .set_timeout = mt7621_wdt_set_timeout,
  94. };
  95. static struct watchdog_device mt7621_wdt_dev = {
  96. .info = &mt7621_wdt_info,
  97. .ops = &mt7621_wdt_ops,
  98. .min_timeout = 1,
  99. .max_timeout = 0xfffful / 1000,
  100. };
  101. static int mt7621_wdt_probe(struct platform_device *pdev)
  102. {
  103. struct device *dev = &pdev->dev;
  104. mt7621_wdt_base = devm_platform_ioremap_resource(pdev, 0);
  105. if (IS_ERR(mt7621_wdt_base))
  106. return PTR_ERR(mt7621_wdt_base);
  107. mt7621_wdt_reset = devm_reset_control_get_exclusive(dev, NULL);
  108. if (!IS_ERR(mt7621_wdt_reset))
  109. reset_control_deassert(mt7621_wdt_reset);
  110. mt7621_wdt_dev.bootstatus = mt7621_wdt_bootcause();
  111. watchdog_init_timeout(&mt7621_wdt_dev, mt7621_wdt_dev.max_timeout,
  112. dev);
  113. watchdog_set_nowayout(&mt7621_wdt_dev, nowayout);
  114. if (mt7621_wdt_is_running(&mt7621_wdt_dev)) {
  115. /*
  116. * Make sure to apply timeout from watchdog core, taking
  117. * the prescaler of this driver here into account (the
  118. * boot loader might be using a different prescaler).
  119. *
  120. * To avoid spurious resets because of different scaling,
  121. * we first disable the watchdog, set the new prescaler
  122. * and timeout, and then re-enable the watchdog.
  123. */
  124. mt7621_wdt_stop(&mt7621_wdt_dev);
  125. mt7621_wdt_start(&mt7621_wdt_dev);
  126. set_bit(WDOG_HW_RUNNING, &mt7621_wdt_dev.status);
  127. }
  128. return devm_watchdog_register_device(dev, &mt7621_wdt_dev);
  129. }
  130. static void mt7621_wdt_shutdown(struct platform_device *pdev)
  131. {
  132. mt7621_wdt_stop(&mt7621_wdt_dev);
  133. }
  134. static const struct of_device_id mt7621_wdt_match[] = {
  135. { .compatible = "mediatek,mt7621-wdt" },
  136. {},
  137. };
  138. MODULE_DEVICE_TABLE(of, mt7621_wdt_match);
  139. static struct platform_driver mt7621_wdt_driver = {
  140. .probe = mt7621_wdt_probe,
  141. .shutdown = mt7621_wdt_shutdown,
  142. .driver = {
  143. .name = KBUILD_MODNAME,
  144. .of_match_table = mt7621_wdt_match,
  145. },
  146. };
  147. module_platform_driver(mt7621_wdt_driver);
  148. MODULE_DESCRIPTION("MediaTek MT762x hardware watchdog driver");
  149. MODULE_AUTHOR("John Crispin <john@phrozen.org");
  150. MODULE_LICENSE("GPL v2");